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2024-09-09 08:52:07 +00:00
commit f9cc65cfda
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bootable/bootloader/lk/dev/panel/msm/lcdc_truly.h
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/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of The Linux Foundation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _LCDC_TRULY_H_
#define _LCDC_TRULY_H_
#define DISPLAY_RESET 90
#define BACKLIGHT_EN 89
#define SPI_MOSI 19
#define SPI_SCLK 20
#define SPI_CS 21
#define LCD_LDO_2V8 35
#define LCD_LDO_1V8 58
#endif
bootable/bootloader/lk/dev/panel/msm/lcdc_truly_hvga.c
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/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of The Linux Foundation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <msm_panel.h>
#include <platform/gpio.h>
#include <debug.h>
#include <err.h>
#include "lcdc_truly.h"
extern void spi_bit_bang_write(uint8_t, uint8_t, uint8_t, uint8_t);
static char data1[] = { 0xff, 0x83, 0x57, };
static char data2[] = { 0x03, };
static char data3[] = { 0x00, 0x13, 0x1C, 0x1C, 0x83, 0x48, };
static char data4[] = { 0x43, 0x06, 0x06, 0x06, };
static char data5[] = { 0x53, };
static char data6[] = { 0x02, 0x40, 0x00, 0x2a, 0x2a, 0x0d, 0x3f, };
static char data7[] = { 0x70, 0x50, 0x01, 0x3c, 0xe8, 0x08, };
static char data8[] = { 0x17, 0x0f, };
static char data9[] = { 0x60};
static char data10[] = { 0x00, 0x13, 0x1a, 0x29, 0x2d, 0x41, 0x49,
0x52, 0x48, 0x41, 0x3c, 0x33, 0x30, 0x1c,
0x19, 0x03, 0x00, 0x13, 0x1a, 0x29, 0x2d,
0x41, 0x49, 0x52, 0x48, 0x41, 0x3c, 0x33,
0x31, 0x1c, 0x19, 0x03, 0x00, 0x01,
};
static char data11[] = { 0x40, };
static void lcdc_truly_panel_power(int on)
{
uint32_t func = 0;
uint32_t pull = 0;
uint32_t drv = 0;
uint32_t dir = 0;
dprintf(SPEW, "lcdc_truly_panel_power on = %d\n", on);
if (on) {
func = 0;
dir = GPIO_OUTPUT;
pull = GPIO_NO_PULL;
drv = GPIO_2MA;
/* config SPI, RESET and Backlight */
gpio_tlmm_config(GPIO_CFG(SPI_MOSI, func, dir, pull, drv), 0);
gpio_tlmm_config(GPIO_CFG(SPI_SCLK, func, dir, pull, drv), 0);
gpio_tlmm_config(GPIO_CFG(SPI_CS, func, dir, pull, drv), 0);
gpio_tlmm_config(GPIO_CFG(BACKLIGHT_EN, func, dir, pull, drv), 0);
gpio_tlmm_config(GPIO_CFG(DISPLAY_RESET, func, dir, pull, drv), 0);
gpio_tlmm_config(GPIO_CFG(LCD_LDO_2V8, func, dir, pull, drv), 0);
gpio_tlmm_config(GPIO_CFG(LCD_LDO_1V8, func, dir, pull, drv), 0);
gpio_config(SPI_MOSI, GPIO_OUTPUT);
gpio_config(SPI_SCLK, GPIO_OUTPUT);
gpio_config(SPI_CS, GPIO_OUTPUT);
gpio_config(BACKLIGHT_EN, GPIO_OUTPUT);
gpio_config(DISPLAY_RESET, GPIO_OUTPUT);
gpio_config(LCD_LDO_2V8, GPIO_OUTPUT);
gpio_config(LCD_LDO_1V8, GPIO_OUTPUT);
/* turn on backlight */
gpio_set(BACKLIGHT_EN, 1);
/* turn on power */
gpio_set(LCD_LDO_1V8, 1);
gpio_set(LCD_LDO_2V8, 1);
/* reset */
gpio_set(DISPLAY_RESET, 1);
/*
* H/w requires delay between toggle
* reset pin
*/
mdelay(20);
gpio_set(DISPLAY_RESET, 0);
mdelay(20);
gpio_set(DISPLAY_RESET, 1);
mdelay(20);
} else {
/* turn off backlight */
gpio_set(BACKLIGHT_EN, 0);
gpio_set(DISPLAY_RESET, 0);
/* turn off power */
gpio_set(LCD_LDO_1V8, 0);
gpio_set(LCD_LDO_2V8, 0);
}
return;
}
static int truly_spi_write(char cmd, char *data, int num)
{
int i;
gpio_set(SPI_CS, 0); /* cs low */
/* command byte first */
spi_bit_bang_write(SPI_SCLK, SPI_MOSI, 0, cmd);
/* followed by parameter bytes */
for(i = 0; i < num; i++) {
if(data)
spi_bit_bang_write(SPI_SCLK, SPI_MOSI, 1, data[i]);
}
gpio_set(SPI_MOSI, 1); /* mosi high */
gpio_set(SPI_CS, 1); /* cs high */
/*
* H/W needs delay for gpio's to turn high
*/
udelay(10);
return 0;
}
void lcdc_truly_disp_on(void)
{
int i;
dprintf(SPEW, "lcdc_truly_disp_on\n");
gpio_set(SPI_CS, 1); /* cs high */
/*
* This function uses delays as defined by the panel
* vendor before writing to registers
*/
truly_spi_write(0xb9, data1, sizeof(data1));
mdelay(20);
truly_spi_write(0xcc, data2, sizeof(data2));
truly_spi_write(0xb1, data3, sizeof(data3));
truly_spi_write(0xb3, data4, sizeof(data4));
truly_spi_write(0xb6, data5, sizeof(data5));
truly_spi_write(0xb4, data6, sizeof(data6));
truly_spi_write(0xc0, data7, sizeof(data7));
truly_spi_write(0xe3, data8, sizeof(data8));
truly_spi_write(0x3a, data9, sizeof(data9));
truly_spi_write(0xe0, data10, sizeof(data10));
truly_spi_write(0x36, data11, sizeof(data11));
truly_spi_write(0x11, NULL, 0);
mdelay(150);
truly_spi_write(0x29, NULL, 0);
mdelay(25);
}
void lcdc_truly_disp_off(void)
{
dprintf(SPEW, "lcdc_truly_disp_off\n");
truly_spi_write(0x28, NULL, 0);
mdelay(5);
truly_spi_write(0x10, NULL, 0);
}
int lcdc_truly_panel_on(int on)
{
dprintf(SPEW, "lcdc_truly_panel_on\n");
if (on) {
lcdc_truly_panel_power(1);
lcdc_truly_disp_on();
} else {
lcdc_truly_panel_power(0);
lcdc_truly_disp_off();
}
return NO_ERROR;
}
int lcdc_truly_hvga_on()
{
return NO_ERROR;
}
int lcdc_truly_hvga_off()
{
return NO_ERROR;
}
void lcdc_truly_hvga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = 320;
pinfo->yres = 480;
pinfo->type = LCDC_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 16;
pinfo->clk_rate = 10240000;
pinfo->lcdc.h_pulse_width = 8;
pinfo->lcdc.h_back_porch = 16;
pinfo->lcdc.h_front_porch = 4;
pinfo->lcdc.hsync_skew = 0;
pinfo->lcdc.v_pulse_width = 1;
pinfo->lcdc.v_back_porch = 7;
pinfo->lcdc.v_front_porch = 3;
pinfo->on = lcdc_truly_hvga_on;
pinfo->off = lcdc_truly_hvga_off;
return;
}
bootable/bootloader/lk/dev/panel/msm/lvds_chimei_wxga.c
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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <err.h>
int lvds_chimei_wxga_config(void *pdata)
{
return NO_ERROR;
}
int lvds_chimei_wxga_on()
{
return NO_ERROR;
}
int lvds_chimei_wxga_off()
{
return NO_ERROR;
}
void lvds_chimei_wxga_init(struct msm_panel_info *pinfo)
{
pinfo->xres = 1364;
pinfo->yres = 768;
pinfo->type = LVDS_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->clk_rate = 75000000;
pinfo->lcdc.h_back_porch = 0;
pinfo->lcdc.h_front_porch = 194;
pinfo->lcdc.h_pulse_width = 40;
pinfo->lcdc.v_back_porch = 0;
pinfo->lcdc.v_front_porch = 38;
pinfo->lcdc.v_pulse_width = 20;
pinfo->lcdc.underflow_clr = 0xff;
pinfo->lcdc.hsync_skew = 0;
pinfo->lvds.channel_mode = LVDS_SINGLE_CHANNEL_MODE;
/* Set border color, padding only for reducing active display region */
pinfo->lcdc.border_clr = 0x0;
pinfo->lcdc.xres_pad = 0;
pinfo->lcdc.yres_pad = 0;
pinfo->on = lvds_chimei_wxga_on;
pinfo->off = lvds_chimei_wxga_off;
pinfo->config = lvds_chimei_wxga_config;
}
bootable/bootloader/lk/dev/panel/msm/mipi_chimei_video_wxga.c
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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <debug.h>
#include <platform/iomap.h>
#include <mdp4.h>
#include <clock.h>
#include "mipi_tc358764_dsi2lvds.h"
int mipi_chimei_video_wxga_early_config(void *pdata)
{
uint32_t tmp;
uint32_t reg = DSI_LANE_CTRL;
struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata;
/* Force DSI-clock ON */
tmp = readl_relaxed(reg);
tmp |= (1<<28);
writel_relaxed(tmp, reg);
mipi_d2l_dsi_init_sequence(pinfo);
}
int mipi_chimei_video_wxga_config(void *pdata)
{
int ret = NO_ERROR;
struct lcdc_panel_info *lcdc = NULL;
struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata;
unsigned char lane_en = 0x0F; /* 4 Lanes */
unsigned long low_pwr_stop_mode = 0;
unsigned char eof_bllp_pwr = 0;
unsigned char interleav = 0;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
ret = mipi_dsi_video_mode_config((pinfo->xres + lcdc->xres_pad),
(pinfo->yres + lcdc->yres_pad),
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
(lcdc->h_back_porch + lcdc->h_pulse_width),
(lcdc->v_front_porch),
(lcdc->v_back_porch + lcdc->v_pulse_width),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_en,
low_pwr_stop_mode,
eof_bllp_pwr,
interleav);
return ret;
}
int mipi_chimei_video_wxga_on(void)
{
int ret = 0;
return ret;
}
int mipi_chimei_video_wxga_off(void)
{
int ret = 0;
return ret;
}
static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* DSIPHY_REGULATOR_CTRL */
.regulator = {0x03, 0x0a, 0x04, 0x00, 0x20}, /* common 8960 */
/* DSIPHY_CTRL */
.ctrl = {0x5f, 0x00, 0x00, 0x10}, /* common 8960 */
/* DSIPHY_STRENGTH_CTRL */
.strength = {0xff, 0x00, 0x06, 0x00}, /* common 8960 */
/* DSIPHY_TIMING_CTRL */
.timing = { 0xB6, 0x8D, 0x1E, /* panel specific */
0, /* DSIPHY_TIMING_CTRL_3 = 0 */
0x21, 0x95, 0x21, 0x8F, 0x21, 0x03, 0x04}, /* panel specific */
/* DSIPHY_PLL_CTRL */
.pll = { 0x01, /* common 8960 */
/* VCO */
0xD8, 0x01, 0x1A, /* panel specific */
0x00, 0x50, 0x48, 0x63,
0x71, 0x0F, 0x03, /* Clocks dividers */
0x00, 0x14, 0x03, 0x00, 0x02, /* common 8960 */
0x00, 0x20, 0x00, 0x01 }, /* common 8960 */
};
void mipi_chimei_video_wxga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
dprintf(INFO, "mipi-dsi chimei wxga (1366x768) driver ver 1.0.\n");
/* Landscape */
pinfo->xres = 1366;
pinfo->yres = 768;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24; /* RGB888 = 24 bits-per-pixel */
/* bitclk */
pinfo->clk_rate = 473400000; /* 473.4 MHZ Calculated */
/*
* this panel is operated by DE,
* vsycn and hsync are ignored
*/
pinfo->lcdc.h_front_porch = 96+2;/* thfp */
pinfo->lcdc.h_back_porch = 88; /* thb */
pinfo->lcdc.h_pulse_width = 40; /* thpw */
pinfo->lcdc.v_front_porch = 15; /* tvfp */
pinfo->lcdc.v_back_porch = 23; /* tvb */
pinfo->lcdc.v_pulse_width = 20; /* tvpw */
pinfo->lcdc.border_clr = 0; /* black */
pinfo->lcdc.underflow_clr = 0xff; /* blue */
pinfo->lcdc.hsync_skew = 0;
/* mipi - general */
pinfo->mipi.vc = 0; /* virtual channel */
pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo->mipi.tx_eot_append = true;
pinfo->mipi.t_clk_post = 34; /* Calculated */
pinfo->mipi.t_clk_pre = 64; /* Calculated */
pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db;
/* Four lanes are recomended for 1366x768 at 60 frames per second */
pinfo->mipi.frame_rate = 60; /* 60 frames per second */
pinfo->mipi.data_lane0 = true;
pinfo->mipi.data_lane1 = true;
pinfo->mipi.data_lane2 = true;
pinfo->mipi.data_lane3 = true;
pinfo->mipi.mode = DSI_VIDEO_MODE;
/*
* Note: The CMI panel input is RGB888,
* thus the DSI-to-LVDS bridge output is RGB888.
* This parameter selects the DSI-Core output to the bridge.
*/
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
/* mipi - video mode */
pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
pinfo->mipi.pulse_mode_hsa_he = false; /* sync mode */
pinfo->mipi.hfp_power_stop = false;
pinfo->mipi.hbp_power_stop = false;
pinfo->mipi.hsa_power_stop = false;
pinfo->mipi.eof_bllp_power_stop = false;
pinfo->mipi.bllp_power_stop = false;
/* mipi - command mode */
pinfo->mipi.te_sel = 1; /* TE from vsycn gpio */
pinfo->mipi.interleave_max = 1;
/* The bridge supports only Generic Read/Write commands */
pinfo->mipi.insert_dcs_cmd = false;
pinfo->mipi.wr_mem_continue = 0;
pinfo->mipi.wr_mem_start = 0;
pinfo->mipi.stream = false; /* dma_p */
pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
/*
* toshiba d2l chip does not need max_pkt_szie dcs cmd
* client reply len is directly configure through
* RDPKTLN register (0x0404)
*/
pinfo->mipi.no_max_pkt_size = 1;
pinfo->mipi.force_clk_lane_hs = 1;
pinfo->mipi.num_of_lanes = 4;
pinfo->mipi.panel_cmds = NULL; /* use in mipi_dsi_panel_initialize() */
pinfo->mipi.num_of_panel_cmds = 0;
/* Provide config/on/off callbacks */
pinfo->on = mipi_chimei_video_wxga_on;
pinfo->off = mipi_chimei_video_wxga_off;
pinfo->config = mipi_chimei_video_wxga_config;
pinfo->early_config = mipi_chimei_video_wxga_early_config;
return;
}
bootable/bootloader/lk/dev/panel/msm/mipi_nt35510.c
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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <debug.h>
#include <target/display.h>
#include <dev/gpio.h>
int mipi_nt35510_panel_dsi_config(int on)
{
if (on) {
gpio_config(96, GPIO_OUTPUT);
/*
* As per the specification follow the sequence to put lcd
* backlight in one wire mode.
*/
gpio_set(96, 0x1);
udelay(190);
gpio_set(96, 0x0);
udelay(286);
gpio_set(96, 0x1);
udelay(50);
gpio_config(35, GPIO_OUTPUT);
gpio_set(35, 0x1);
gpio_config(40, GPIO_OUTPUT);
gpio_set(40, 0x1);
gpio_config(85, GPIO_OUTPUT);
gpio_set(85, 0x1);
mdelay(20);
gpio_set(85, 0x0);
mdelay(20);
gpio_set(85, 0x1);
mdelay(20);
} else {
if (!target_cont_splash_screen()) {
gpio_set(96, 0x0);
gpio_set(35, 0x0);
gpio_set(40, 0x0);
}
}
return 0;
}
bootable/bootloader/lk/dev/panel/msm/mipi_nt35510_cmd_wvga.c
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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <debug.h>
#include <target/display.h>
/* MIPI NT35510 panel commands */
static char exit_sleep[4] = {0x11, 0x00, 0x05, 0x80};
static char display_on[4] = {0x29, 0x00, 0x05, 0x80};
static char write_ram[4] = {0x2c, 0x00, 0x05, 0x80}; /* write ram */
static char cmd0[12] = {
0x06, 0x00, 0x29, 0xc0, 0xF0, 0x55, 0xAA, 0x52,
0x08, 0x01, 0xff, 0xff,
};
static char cmd1[8] = {
0x04, 0x00, 0x29, 0xc0, 0xBC, 0x00, 0xA0, 0x00,
};
static char cmd2[8] = {
0x04, 0x00, 0x29, 0xc0, 0xBD, 0x00, 0xA0, 0x00,
};
static char cmd3[8] = {
0x03, 0x00, 0x29, 0xc0, 0xBE, 0x00, 0x79, 0xff,
};
static char cmd4[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD1, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char cmd5[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD2, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char cmd6[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD3, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char cmd7[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD4, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char cmd8[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD5, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char cmd9[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD6, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char cmd10[8] = {
0x04, 0x00, 0x29, 0xc0, 0xB0, 0x0A, 0x0A, 0x0A,
};
static char cmd11[8] = {
0x04, 0x00, 0x29, 0xc0, 0xB1, 0x0A, 0x0A, 0x0A,
};
static char cmd12[8] = {
0x04, 0x00, 0x29, 0xc0, 0xBA, 0x24, 0x24, 0x24,
};
static char cmd13[8] = {
0x04, 0x00, 0x29, 0xc0, 0xB9, 0x24, 0x24, 0x24,
};
static char cmd14[8] = {
0x04, 0x00, 0x29, 0xc0, 0xB8, 0x24, 0x24, 0x24,
};
static char cmd15[12] = {
0x06, 0x00, 0x29, 0xc0, 0xF0, 0x55, 0xAA, 0x52,
0x08, 0x00, 0xff, 0xff,
};
static char cmd16[8] = {
0x02, 0x00, 0x29, 0xc0, 0xB3, 0x00, 0xff, 0xff,
};
static char cmd17[8] = {
0x02, 0x00, 0x29, 0xc0, 0xB4, 0x10, 0xff, 0xff,
};
static char cmd18[8] = {
0x02, 0x00, 0x29, 0xc0, 0xB6, 0x02, 0xff, 0xff,
};
static char cmd19[8] = {
0x03, 0x00, 0x29, 0xc0, 0xB1, 0xEC, 0x00, 0xff,
};
static char cmd19_rotate[8] = {
0x03, 0x00, 0x29, 0xc0, 0xB1, 0xEC, 0x06, 0xff,
};
static char cmd20[8] = {
0x04, 0x00, 0x29, 0xc0, 0xBC, 0x05, 0x05, 0x05,
};
static char cmd21[8] = {
0x03, 0x00, 0x29, 0xc0, 0xB7, 0x20, 0x20, 0xff,
};
static char cmd22[12] = {
0x05, 0x00, 0x29, 0xc0, 0xB8, 0x01, 0x03, 0x03,
0x03, 0xff, 0xff, 0xff,
};
static char cmd23[24] = {
0x13, 0x00, 0x29, 0xc0, 0xC8, 0x01, 0x00, 0x78,
0x50, 0x78, 0x50, 0x78,
0x50, 0x78, 0x50, 0xC8,
0x3C, 0x3C, 0xC8, 0xC8,
0x3C, 0x3C, 0xC8, 0xff,
};
static char cmd24[12] = {
0x06, 0x00, 0x29, 0xc0, 0xBD, 0x01, 0x84, 0x07,
0x31, 0x00, 0xff, 0xff,
};
static char cmd25[12] = {
0x06, 0x00, 0x29, 0xc0, 0xBE, 0x01, 0x84, 0x07,
0x31, 0x00, 0xff, 0xff,
};
static char cmd26[12] = {
0x06, 0x00, 0x29, 0xc0, 0xBF, 0x01, 0x84, 0x07,
0x31, 0x00, 0xff, 0xff,
};
static char cmd27[8] = {
0x02, 0x00, 0x29, 0xc0, 0x35, 0x00, 0xff, 0xff,
};
static char config_MADCTL[4] = {0x36, 0x00, 0x15, 0x80};
static struct mipi_dsi_cmd nt35510_panel_cmd_mode_cmds[] = {
{sizeof(cmd0), cmd0},
{sizeof(cmd1), cmd1},
{sizeof(cmd2), cmd2},
{sizeof(cmd3), cmd3},
{sizeof(cmd4), cmd4},
{sizeof(cmd5), cmd5},
{sizeof(cmd6), cmd6},
{sizeof(cmd7), cmd7},
{sizeof(cmd8), cmd8},
{sizeof(cmd9), cmd9},
{sizeof(cmd10), cmd10},
{sizeof(cmd11), cmd11},
{sizeof(cmd12), cmd12},
{sizeof(cmd13), cmd13},
{sizeof(cmd14), cmd14},
{sizeof(cmd15), cmd15},
{sizeof(cmd16), cmd16},
{sizeof(cmd17), cmd17},
{sizeof(cmd18), cmd18},
{sizeof(cmd19), cmd19},
{sizeof(cmd20), cmd20},
{sizeof(cmd21), cmd21},
{sizeof(cmd22), cmd22},
{sizeof(cmd23), cmd23},
{sizeof(cmd24), cmd24},
{sizeof(cmd25), cmd25},
{sizeof(cmd26), cmd26},
{sizeof(cmd27), cmd27},
{sizeof(exit_sleep), exit_sleep},
{sizeof(display_on), display_on},
{sizeof(config_MADCTL), config_MADCTL},
{sizeof(write_ram), write_ram},
};
static struct mipi_dsi_cmd nt35510_cmd_rotate_cmds[] = {
{sizeof(cmd19_rotate), cmd19_rotate},
};
int mipi_nt35510_cmd_wvga_on()
{
int ret = NO_ERROR;
return ret;
}
int mipi_nt35510_cmd_wvga_off()
{
int ret = NO_ERROR;
return ret;
}
int mipi_nt35510_cmd_wvga_rotate()
{
int ret = NO_ERROR;
ret = mipi_dsi_cmds_tx(nt35510_cmd_rotate_cmds, ARRAY_SIZE(nt35510_cmd_rotate_cmds));
return ret;
}
int mipi_nt35510_cmd_wvga_config(void *pdata)
{
int ret = NO_ERROR;
struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
ret = mipi_dsi_cmd_mode_config((pinfo->xres),
(pinfo->yres),
(pinfo->xres),
(pinfo->yres),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode);
return ret;
}
struct mipi_dsi_phy_ctrl dsi_cmd_mode_phy_db = {
/* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
{0x03, 0x01, 0x01, 0x00}, /* regulator */
/* timing */
{0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22,
0x90, 0x18, 0x03, 0x04},
{0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
{0xbb, 0x02, 0x06, 0x00}, /* strength */
/* pll control */
{0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62,
0x01, 0x0f, 0x07, /* --> Two lane configuration */
0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0},
};
void mipi_nt35510_cmd_wvga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = NT35510_MIPI_FB_WIDTH;
pinfo->yres = NT35510_MIPI_FB_HEIGHT;
pinfo->mipi.num_of_lanes = 2;
pinfo->type = MIPI_CMD_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->clk_rate = 499000000;
pinfo->mipi.mode = DSI_CMD_MODE;
pinfo->mipi.traffic_mode = 0;
pinfo->mipi.dst_format = 0;
pinfo->mipi.dsi_phy_db = &dsi_cmd_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.lane_swap = 1;
pinfo->mipi.panel_cmds = nt35510_panel_cmd_mode_cmds;
pinfo->mipi.num_of_panel_cmds = \
ARRAY_SIZE(nt35510_panel_cmd_mode_cmds);
pinfo->on = mipi_nt35510_cmd_wvga_on;
pinfo->off = mipi_nt35510_cmd_wvga_off;
pinfo->config = mipi_nt35510_cmd_wvga_config;
pinfo->rotate = mipi_nt35510_cmd_wvga_rotate;
return;
}
bootable/bootloader/lk/dev/panel/msm/mipi_nt35510_video_wvga.c
+372
View File
@@ -0,0 +1,372 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <debug.h>
#include <platform/iomap.h>
#include <target/display.h>
#include <dev/gpio.h>
/* MIPI NT35510 panel commands */
static char exit_sleep[4] = {0x11, 0x00, 0x09, 0x80};
static char display_on[4] = {0x29, 0x00, 0x05, 0x80};
static char video0[12] = {
0x06, 0x00, 0x29, 0xc0, 0xF0, 0x55, 0xAA, 0x52,
0x08, 0x01, 0xff, 0xff,
};
static char video1[8] = {
0x04, 0x00, 0x29, 0xc0, 0xBC, 0x00, 0xA0, 0x00,
};
static char video2[8] = {
0x04, 0x00, 0x29, 0xc0, 0xBD, 0x00, 0xA0, 0x00,
};
static char video3[8] = {
0x03, 0x00, 0x29, 0xc0, 0xBE, 0x00, 0x79, 0xff,
};
static char video4[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD1, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char video5[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD2, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff
};
static char video6[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD3, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char video7[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD4, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char video8[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD5, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char video9[60] = {
0x35, 0x00, 0x29, 0xc0, 0xD6, 0x00, 0x00, 0x00,
0x14, 0x00, 0x32, 0x00,
0x4F, 0x00, 0x65, 0x00,
0x8B, 0x00, 0xA8, 0x00,
0xD5, 0x00, 0xF7, 0x01,
0x2B, 0x01, 0x54, 0x01,
0x8E, 0x01, 0xBB, 0x01,
0xBC, 0x01, 0xE3, 0x02,
0x08, 0x02, 0x1C, 0x02,
0x39, 0x02, 0x4F, 0x02,
0x76, 0x02, 0xA3, 0x02,
0xE3, 0x03, 0x12, 0x03,
0x4C, 0x03, 0x66, 0x03,
0x9A, 0xff, 0xff, 0xff,
};
static char video10[8] = {
0x04, 0x00, 0x29, 0xc0, 0xB0, 0x0A, 0x0A, 0x0A,
};
static char video11[8] = {
0x04, 0x00, 0x29, 0xc0, 0xB1, 0x0A, 0x0A, 0x0A,
};
static char video12[8] = {
0x04, 0x00, 0x29, 0xc0, 0xBA, 0x24, 0x24, 0x24,
};
static char video13[8] = {
0x04, 0x00, 0x29, 0xc0, 0xB9, 0x24, 0x24, 0x24,
};
static char video14[8] = {
0x04, 0x00, 0x29, 0xc0, 0xB8, 0x24, 0x24, 0x24,
};
static char video15[12] = {
0x06, 0x00, 0x29, 0xc0, 0xF0, 0x55, 0xAA, 0x52,
0x08, 0x00, 0xff, 0xff,
};
static char video16[8] = {
0x02, 0x00, 0x29, 0xc0, 0xB3, 0x00, 0xff, 0xff,
};
static char video17[8] = {
0x02, 0x00, 0x29, 0xc0, 0xB4, 0x10, 0xff, 0xff,
};
static char video18[8] = {
0x02, 0x00, 0x29, 0xc0, 0xB6, 0x02, 0xff, 0xff,
};
static char video19[8] = {
0x03, 0x00, 0x29, 0xc0, 0xB1, 0xFC, 0x00, 0xff,
};
static char video19_rotate[8] = {
0x03, 0x00, 0x29, 0xc0, 0xB1, 0xFC, 0x06, 0xff,
};
static char video20[8] = {
0x04, 0x00, 0x29, 0xc0, 0xBC, 0x05, 0x05, 0x05,
};
static char video21[8] = {
0x03, 0x00, 0x29, 0xc0, 0xB7, 0x20, 0x20, 0xff,
};
static char video22[12] = {
0x05, 0x00, 0x29, 0xc0, 0xB8, 0x01, 0x03, 0x03,
0x03, 0xff, 0xff, 0xff,
};
static char video23[24] = {
0x13, 0x00, 0x29, 0xc0, 0xC8, 0x01, 0x00, 0x78,
0x50, 0x78, 0x50, 0x78,
0x50, 0x78, 0x50, 0xC8,
0x3C, 0x3C, 0xC8, 0xC8,
0x3C, 0x3C, 0xC8, 0xff,
};
static char video24[12] = {
0x06, 0x00, 0x29, 0xc0, 0xBD, 0x01, 0x84, 0x07,
0x31, 0x00, 0xff, 0xff,
};
static char video25[12] = {
0x06, 0x00, 0x29, 0xc0, 0xBE, 0x01, 0x84, 0x07,
0x31, 0x00, 0xff, 0xff,
};
static char video26[12] = {
0x06, 0x00, 0x29, 0xc0, 0xBF, 0x01, 0x84, 0x07,
0x31, 0x00, 0xff, 0xff
};
static char video27[8] = {
0x02, 0x00, 0x29, 0xc0, 0x35, 0x00, 0xff, 0xff,
};
static struct mipi_dsi_cmd nt35510_panel_video_mode_cmds[] = {
{sizeof(video0), video0},
{sizeof(video1), video1},
{sizeof(video2), video2},
{sizeof(video3), video3},
{sizeof(video4), video4},
{sizeof(video5), video5},
{sizeof(video6), video6},
{sizeof(video7), video7},
{sizeof(video8), video8},
{sizeof(video9), video9},
{sizeof(video10), video10},
{sizeof(video11), video11},
{sizeof(video12), video12},
{sizeof(video13), video13},
{sizeof(video14), video14},
{sizeof(video15), video15},
{sizeof(video16), video16},
{sizeof(video17), video17},
{sizeof(video18), video18},
{sizeof(video19), video19},
{sizeof(video20), video20},
{sizeof(video21), video21},
{sizeof(video22), video22},
{sizeof(video23), video23},
{sizeof(video24), video24},
{sizeof(video25), video25},
{sizeof(video26), video26},
{sizeof(video27), video27},
{sizeof(exit_sleep), exit_sleep},
{sizeof(display_on), display_on},
};
static struct mipi_dsi_cmd nt35510_video_rotate_cmds[] = {
{sizeof(video19_rotate), video19_rotate},
};
int mipi_nt35510_video_wvga_config(void *pdata)
{
int ret = NO_ERROR;
/* 3 Lanes -- Enables Data Lane0, 1, 2 */
unsigned char lane_en = 3;
unsigned long low_pwr_stop_mode = 1;
/* Needed or else will have blank line at top of display */
unsigned char eof_bllp_pwr = 0x9;
unsigned char interleav = 0;
struct lcdc_panel_info *lcdc = NULL;
struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
ret = mipi_dsi_video_mode_config((pinfo->xres),
(pinfo->yres),
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
(lcdc->h_back_porch),
(lcdc->v_front_porch),
(lcdc->v_back_porch),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_en,
low_pwr_stop_mode,
eof_bllp_pwr,
interleav);
return ret;
}
int mipi_nt35510_video_wvga_on()
{
int ret = NO_ERROR;
return ret;
}
int mipi_nt35510_video_wvga_off()
{
int ret = NO_ERROR;
return ret;
}
int mipi_nt35510_video_wvga_rotate()
{
int ret = NO_ERROR;
ret = mipi_dsi_cmds_tx(nt35510_video_rotate_cmds, ARRAY_SIZE(nt35510_video_rotate_cmds));
return ret;
}
static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
{0x03, 0x01, 0x01, 0x00}, /* regulator */
/* timing */
{0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22,
0x90, 0x18, 0x03, 0x04},
{0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
{0xbb, 0x02, 0x06, 0x00}, /* strength */
/* pll control */
{0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62,
0x01, 0x0f, 0x07, /* --> Two lane configuration */
0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0},
};
void mipi_nt35510_video_wvga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = NT35510_MIPI_FB_WIDTH;
pinfo->yres = NT35510_MIPI_FB_HEIGHT;
pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK;
pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK;
pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH;
pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES;
pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES;
pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH;
pinfo->mipi.num_of_lanes = 2;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->clk_rate = 499000000;
pinfo->mipi.mode = DSI_VIDEO_MODE;
pinfo->mipi.traffic_mode = 2;
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.lane_swap = 1;
pinfo->mipi.panel_cmds = nt35510_panel_video_mode_cmds;
pinfo->mipi.num_of_panel_cmds = \
ARRAY_SIZE(nt35510_panel_video_mode_cmds);
pinfo->on = mipi_nt35510_video_wvga_on;
pinfo->off = mipi_nt35510_video_wvga_off;
pinfo->config = mipi_nt35510_video_wvga_config;
pinfo->rotate = mipi_nt35510_video_wvga_rotate;
return;
}
bootable/bootloader/lk/dev/panel/msm/mipi_renesas.c
+51
View File
@@ -0,0 +1,51 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "mipi_renesas.h"
/* Toggle RESET pin of the DSI Client before sending
* panel init commands
*/
int mipi_renesas_panel_dsi_config(int on)
{
if (on) {
gpio_set(128, 0x1);
mdelay(5);
gpio_set(128, 0x0);
gpio_set(129, 0x1);
gpio_config(129, GPIO_OUTPUT);
gpio_set(129, 0x0);
gpio_set(129, 0x1);
mdelay(10);
} else {
gpio_set(128, 0x1);
}
return 0;
}
bootable/bootloader/lk/dev/panel/msm/mipi_renesas.h
+737
View File
@@ -0,0 +1,737 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _MIPI_RENESAS_H_
#define _MIPI_RENESAS_H_
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <debug.h>
#include <target/display.h>
#include <dev/gpio.h>
/* Renesas Tremelo-M panel: List of commands */
static char config_sleep_out[4] = { 0x11, 0x00, 0x05, 0x80 };
static char config_CMD_MODE[4] = { 0x40, 0x01, 0x15, 0x80 };
static char config_WRTXHT[12] = {
0x07, 0x00, 0x39, 0xC0, 0x92, 0x16, 0x08, 0x08, 0x00, 0x01, 0xe0, 0xff };
static char config_WRTXVT[12] = {
0x07, 0x00, 0x39, 0xC0, 0x8b, 0x02, 0x02, 0x02, 0x00, 0x03, 0x60, 0xff };
static char config_PLL2NR[4] = { 0xa0, 0x24, 0x15, 0x80 };
static char config_PLL2NF1[4] = { 0xa2, 0xd0, 0x15, 0x80 };
static char config_PLL2NF2[4] = { 0xa4, 0x00, 0x15, 0x80 };
static char config_PLL2BWADJ1[4] = { 0xa6, 0xd0, 0x15, 0x80 };
static char config_PLL2BWADJ2[4] = { 0xa8, 0x00, 0x15, 0x80 };
static char config_PLL2CTL[4] = { 0xaa, 0x00, 0x15, 0x80 };
static char config_DBICBR[4] = { 0x48, 0x03, 0x15, 0x80 };
static char config_DBICTYPE[4] = { 0x49, 0x00, 0x15, 0x80 };
static char config_DBICSET1[4] = { 0x4a, 0x1c, 0x15, 0x80 };
static char config_DBICADD[4] = { 0x4b, 0x00, 0x15, 0x80 };
static char config_DBICCTL[4] = { 0x4e, 0x01, 0x15, 0x80 };
/* static char config_COLMOD_565[4] = {0x3a, 0x05, 0x15, 0x80}; */
/* static char config_COLMOD_666PACK[4] = {0x3a, 0x06, 0x15, 0x80}; */
static char config_COLMOD_888[4] = { 0x3a, 0x07, 0x15, 0x80 };
static char config_MADCTL[4] = { 0x36, 0x00, 0x15, 0x80 };
static char config_DBIOC[4] = { 0x82, 0x40, 0x15, 0x80 };
static char config_CASET[12] = {
0x07, 0x00, 0x39, 0xC0, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdf, 0xff };
static char config_PASET[12] = {
0x07, 0x00, 0x39, 0xC0, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x03, 0x5f, 0xff };
static char config_TXON[4] = { 0x81, 0x00, 0x05, 0x80 };
static char config_BLSET_TM[4] = { 0xff, 0x6c, 0x15, 0x80 };
static char config_AGCPSCTL_TM[4] = { 0x56, 0x08, 0x15, 0x80 };
static char config_DBICADD70[4] = { 0x4b, 0x70, 0x15, 0x80 };
static char config_DBICSET_15[4] = { 0x4a, 0x15, 0x15, 0x80 };
static char config_DBICADD72[4] = { 0x4b, 0x72, 0x15, 0x80 };
static char config_Power_Ctrl_2a_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff };
static char config_Auto_Sequencer_Setting_a_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char Driver_Output_Ctrl_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x01, 0xff };
static char Driver_Output_Ctrl_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x10, 0xff };
static char config_LCD_drive_AC_Ctrl_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff };
static char config_LCD_drive_AC_Ctrl_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x00, 0xff };
static char config_Entry_Mode_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x03, 0xff };
static char config_Entry_Mode_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char config_Display_Ctrl_1_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x07, 0xff };
static char config_Display_Ctrl_1_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char config_Display_Ctrl_2_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x08, 0xff };
static char config_Display_Ctrl_2_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x04, 0xff };
static char config_Display_Ctrl_3_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x09, 0xff };
static char config_Display_Ctrl_3_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0c, 0xff };
static char config_Display_IF_Ctrl_1_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0c, 0xff };
static char config_Display_IF_Ctrl_1_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff };
static char config_Display_IF_Ctrl_2_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x0e, 0xff };
static char config_Display_IF_Ctrl_2_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char config_Panel_IF_Ctrl_1_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x20, 0xff };
static char config_Panel_IF_Ctrl_1_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x3f, 0xff };
static char config_Panel_IF_Ctrl_3_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x22, 0xff };
static char config_Panel_IF_Ctrl_3_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x76, 0x00, 0xff };
static char config_Panel_IF_Ctrl_4_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x23, 0xff };
static char config_Panel_IF_Ctrl_4_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x0a, 0xff };
static char config_Panel_IF_Ctrl_5_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x24, 0xff };
static char config_Panel_IF_Ctrl_5_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x2c, 0xff };
static char config_Panel_IF_Ctrl_6_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x25, 0xff };
static char config_Panel_IF_Ctrl_6_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x1c, 0x4e, 0xff };
static char config_Panel_IF_Ctrl_8_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x27, 0xff };
static char config_Panel_IF_Ctrl_8_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char config_Panel_IF_Ctrl_9_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x28, 0xff };
static char config_Panel_IF_Ctrl_9_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x76, 0x0c, 0xff };
static char config_gam_adjust_00_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x00, 0xff };
static char config_gam_adjust_00_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char config_gam_adjust_01_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x01, 0xff };
static char config_gam_adjust_01_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x02, 0xff };
static char config_gam_adjust_02_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x02, 0xff };
static char config_gam_adjust_02_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x05, 0xff };
static char config_gam_adjust_03_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x03, 0xff };
static char config_gam_adjust_03_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char config_gam_adjust_04_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff };
static char config_gam_adjust_04_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x00, 0xff };
static char config_gam_adjust_05_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x05, 0xff };
static char config_gam_adjust_05_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff };
static char config_gam_adjust_06_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x06, 0xff };
static char config_gam_adjust_06_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x10, 0x10, 0xff };
static char config_gam_adjust_07_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x07, 0xff };
static char config_gam_adjust_07_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x02, 0xff };
static char config_gam_adjust_08_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x08, 0xff };
static char config_gam_adjust_08_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x04, 0xff };
static char config_gam_adjust_09_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x09, 0xff };
static char config_gam_adjust_09_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff };
static char config_gam_adjust_0A_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0a, 0xff };
static char config_gam_adjust_0A_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char config_gam_adjust_0B_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0b, 0xff };
static char config_gam_adjust_0B_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x00, 0xff };
static char config_gam_adjust_0C_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0c, 0xff };
static char config_gam_adjust_0C_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff };
static char config_gam_adjust_0D_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x0d, 0xff };
static char config_gam_adjust_0D_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x10, 0x10, 0xff };
static char config_gam_adjust_10_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x10, 0xff };
static char config_gam_adjust_10_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x04, 0xff };
static char config_gam_adjust_11_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x11, 0xff };
static char config_gam_adjust_11_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x03, 0xff };
static char config_gam_adjust_12_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x12, 0xff };
static char config_gam_adjust_12_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff };
static char config_gam_adjust_15_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x15, 0xff };
static char config_gam_adjust_15_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x04, 0xff };
static char config_gam_adjust_16_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x16, 0xff };
static char config_gam_adjust_16_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1c, 0xff };
static char config_gam_adjust_17_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x17, 0xff };
static char config_gam_adjust_17_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x04, 0xff };
static char config_gam_adjust_18_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x18, 0xff };
static char config_gam_adjust_18_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x04, 0x02, 0xff };
static char config_gam_adjust_19_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x19, 0xff };
static char config_gam_adjust_19_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x05, 0xff };
static char config_gam_adjust_1C_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1c, 0xff };
static char config_gam_adjust_1C_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x07, 0x07, 0xff };
static char config_gam_adjust_1D_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x1D, 0xff };
static char config_gam_adjust_1D_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x1f, 0xff };
static char config_gam_adjust_20_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x20, 0xff };
static char config_gam_adjust_20_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x05, 0x07, 0xff };
static char config_gam_adjust_21_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x21, 0xff };
static char config_gam_adjust_21_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x06, 0x04, 0xff };
static char config_gam_adjust_22_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x22, 0xff };
static char config_gam_adjust_22_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x04, 0x05, 0xff };
static char config_gam_adjust_27_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x27, 0xff };
static char config_gam_adjust_27_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x02, 0x03, 0xff };
static char config_gam_adjust_28_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x28, 0xff };
static char config_gam_adjust_28_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x00, 0xff };
static char config_gam_adjust_29_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0x29, 0xff };
static char config_gam_adjust_29_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff };
static char config_Power_Ctrl_1_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x00, 0xff };
static char config_Power_Ctrl_1b_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x36, 0x3c, 0xff };
static char config_Power_Ctrl_2_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x01, 0xff };
static char config_Power_Ctrl_2b_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x03, 0xff };
static char config_Power_Ctrl_3_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x02, 0xff };
static char config_Power_Ctrl_3a_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x01, 0xff };
static char config_Power_Ctrl_4_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x03, 0xff };
static char config_Power_Ctrl_4a_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x3c, 0x58, 0xff };
static char config_Power_Ctrl_6_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x0c, 0xff };
static char config_Power_Ctrl_6a_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x35, 0xff };
static char config_Auto_Sequencer_Setting_b_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x02, 0xff };
static char config_Panel_IF_Ctrl_10_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x29, 0xff };
static char config_Panel_IF_Ctrl_10a_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x03, 0xbf, 0xff };
static char config_Auto_Sequencer_Setting_indx[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x01, 0x06, 0xff };
static char config_Auto_Sequencer_Setting_c_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x00, 0x03, 0xff };
static char config_Power_Ctrl_2c_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4c, 0x40, 0x10, 0xff };
static char config_VIDEO[4] = { 0x40, 0x00, 0x15, 0x80 };
static char config_COMMAND[4] = { 0x40, 0x01, 0x15, 0x80 };
static char config_Panel_IF_Ctrl_10_indx_off[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4C, 0x00, 0x29, 0xff };
static char config_Panel_IF_Ctrl_10b_cmd_off[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4C, 0x00, 0x02, 0xff };
static char config_Power_Ctrl_1a_cmd[8] = {
0x03, 0x00, 0x39, 0xC0, 0x4C, 0x30, 0x00, 0xff };
static struct mipi_dsi_cmd renesas_panel_video_mode_cmds[] = {
{sizeof(config_sleep_out), config_sleep_out},
{sizeof(config_CMD_MODE), config_CMD_MODE},
{sizeof(config_WRTXHT), config_WRTXHT},
{sizeof(config_WRTXVT), config_WRTXVT},
{sizeof(config_PLL2NR), config_PLL2NR},
{sizeof(config_PLL2NF1), config_PLL2NF1},
{sizeof(config_PLL2NF2), config_PLL2NF2},
{sizeof(config_PLL2BWADJ1), config_PLL2BWADJ1},
{sizeof(config_PLL2BWADJ2), config_PLL2BWADJ2},
{sizeof(config_PLL2CTL), config_PLL2CTL},
{sizeof(config_DBICBR), config_DBICBR},
{sizeof(config_DBICTYPE), config_DBICTYPE},
{sizeof(config_DBICSET1), config_DBICSET1},
{sizeof(config_DBICADD), config_DBICADD},
{sizeof(config_DBICCTL), config_DBICCTL},
{sizeof(config_COLMOD_888), config_COLMOD_888},
/* Choose config_COLMOD_565 or config_COLMOD_666PACK for other modes */
{sizeof(config_MADCTL), config_MADCTL},
{sizeof(config_DBIOC), config_DBIOC},
{sizeof(config_CASET), config_CASET},
{sizeof(config_PASET), config_PASET},
{sizeof(config_TXON), config_TXON},
{sizeof(config_BLSET_TM), config_BLSET_TM},
{sizeof(config_AGCPSCTL_TM), config_AGCPSCTL_TM},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Power_Ctrl_1_indx), config_Power_Ctrl_1_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Power_Ctrl_1a_cmd), config_Power_Ctrl_1a_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Power_Ctrl_2_indx), config_Power_Ctrl_2_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Power_Ctrl_2a_cmd), config_Power_Ctrl_2a_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Auto_Sequencer_Setting_indx),
config_Auto_Sequencer_Setting_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Auto_Sequencer_Setting_a_cmd),
config_Auto_Sequencer_Setting_a_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(Driver_Output_Ctrl_indx), Driver_Output_Ctrl_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(Driver_Output_Ctrl_cmd),
Driver_Output_Ctrl_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_LCD_drive_AC_Ctrl_indx),
config_LCD_drive_AC_Ctrl_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_LCD_drive_AC_Ctrl_cmd),
config_LCD_drive_AC_Ctrl_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Entry_Mode_indx),
config_Entry_Mode_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Entry_Mode_cmd),
config_Entry_Mode_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Display_Ctrl_1_indx),
config_Display_Ctrl_1_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Display_Ctrl_1_cmd),
config_Display_Ctrl_1_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Display_Ctrl_2_indx),
config_Display_Ctrl_2_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Display_Ctrl_2_cmd),
config_Display_Ctrl_2_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Display_Ctrl_3_indx),
config_Display_Ctrl_3_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Display_Ctrl_3_cmd),
config_Display_Ctrl_3_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Display_IF_Ctrl_1_indx),
config_Display_IF_Ctrl_1_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Display_IF_Ctrl_1_cmd),
config_Display_IF_Ctrl_1_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Display_IF_Ctrl_2_indx),
config_Display_IF_Ctrl_2_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Display_IF_Ctrl_2_cmd),
config_Display_IF_Ctrl_2_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Panel_IF_Ctrl_1_indx),
config_Panel_IF_Ctrl_1_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Panel_IF_Ctrl_1_cmd),
config_Panel_IF_Ctrl_1_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Panel_IF_Ctrl_3_indx),
config_Panel_IF_Ctrl_3_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Panel_IF_Ctrl_3_cmd),
config_Panel_IF_Ctrl_3_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Panel_IF_Ctrl_4_indx),
config_Panel_IF_Ctrl_4_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Panel_IF_Ctrl_4_cmd),
config_Panel_IF_Ctrl_4_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Panel_IF_Ctrl_5_indx),
config_Panel_IF_Ctrl_5_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Panel_IF_Ctrl_5_cmd),
config_Panel_IF_Ctrl_5_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Panel_IF_Ctrl_6_indx),
config_Panel_IF_Ctrl_6_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Panel_IF_Ctrl_6_cmd),
config_Panel_IF_Ctrl_6_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Panel_IF_Ctrl_8_indx),
config_Panel_IF_Ctrl_8_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Panel_IF_Ctrl_8_cmd),
config_Panel_IF_Ctrl_8_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Panel_IF_Ctrl_9_indx),
config_Panel_IF_Ctrl_9_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Panel_IF_Ctrl_9_cmd),
config_Panel_IF_Ctrl_9_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_00_indx),
config_gam_adjust_00_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_00_cmd),
config_gam_adjust_00_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_01_indx),
config_gam_adjust_01_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_01_cmd),
config_gam_adjust_01_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_02_indx),
config_gam_adjust_02_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_02_cmd),
config_gam_adjust_02_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_03_indx),
config_gam_adjust_03_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_03_cmd),
config_gam_adjust_03_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_04_indx), config_gam_adjust_04_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_04_cmd), config_gam_adjust_04_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_05_indx), config_gam_adjust_05_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_05_cmd), config_gam_adjust_05_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_06_indx), config_gam_adjust_06_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_06_cmd), config_gam_adjust_06_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_07_indx), config_gam_adjust_07_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_07_cmd), config_gam_adjust_07_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_08_indx), config_gam_adjust_08_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_08_cmd), config_gam_adjust_08_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_09_indx), config_gam_adjust_09_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_09_cmd), config_gam_adjust_09_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_0A_indx), config_gam_adjust_0A_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_0A_cmd), config_gam_adjust_0A_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_0B_indx), config_gam_adjust_0B_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_0B_cmd), config_gam_adjust_0B_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_0C_indx), config_gam_adjust_0C_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_0C_cmd), config_gam_adjust_0C_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_0D_indx), config_gam_adjust_0D_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_0D_cmd), config_gam_adjust_0D_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_10_indx), config_gam_adjust_10_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_10_cmd), config_gam_adjust_10_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_11_indx), config_gam_adjust_11_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_11_cmd), config_gam_adjust_11_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_12_indx), config_gam_adjust_12_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_12_cmd), config_gam_adjust_12_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_15_indx), config_gam_adjust_15_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_15_cmd), config_gam_adjust_15_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_16_indx), config_gam_adjust_16_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_16_cmd), config_gam_adjust_16_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_17_indx), config_gam_adjust_17_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_17_cmd), config_gam_adjust_17_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_18_indx), config_gam_adjust_18_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_18_cmd), config_gam_adjust_18_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_19_indx), config_gam_adjust_19_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_19_cmd), config_gam_adjust_19_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_1C_indx), config_gam_adjust_1C_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_1C_cmd), config_gam_adjust_1C_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_1D_indx), config_gam_adjust_1D_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_1D_cmd), config_gam_adjust_1D_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_20_indx), config_gam_adjust_20_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_20_cmd), config_gam_adjust_20_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_21_indx), config_gam_adjust_21_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_21_cmd), config_gam_adjust_21_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_22_indx), config_gam_adjust_22_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_22_cmd), config_gam_adjust_22_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_27_indx), config_gam_adjust_27_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_27_cmd), config_gam_adjust_27_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_28_indx), config_gam_adjust_28_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_28_cmd), config_gam_adjust_28_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_gam_adjust_29_indx), config_gam_adjust_29_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_gam_adjust_29_cmd), config_gam_adjust_29_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Power_Ctrl_1_indx), config_Power_Ctrl_1_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Power_Ctrl_1b_cmd), config_Power_Ctrl_1b_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Power_Ctrl_2_indx), config_Power_Ctrl_2_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Power_Ctrl_2b_cmd), config_Power_Ctrl_2b_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Power_Ctrl_3_indx), config_Power_Ctrl_3_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Power_Ctrl_3a_cmd), config_Power_Ctrl_3a_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Power_Ctrl_4_indx), config_Power_Ctrl_4_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Power_Ctrl_4a_cmd), config_Power_Ctrl_4a_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Power_Ctrl_6_indx), config_Power_Ctrl_6_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Power_Ctrl_6a_cmd), config_Power_Ctrl_6a_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Auto_Sequencer_Setting_indx),
config_Auto_Sequencer_Setting_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Auto_Sequencer_Setting_b_cmd),
config_Auto_Sequencer_Setting_b_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Panel_IF_Ctrl_10_indx),
config_Panel_IF_Ctrl_10_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Panel_IF_Ctrl_10a_cmd),
config_Panel_IF_Ctrl_10a_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Auto_Sequencer_Setting_indx),
config_Auto_Sequencer_Setting_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Auto_Sequencer_Setting_c_cmd),
config_Auto_Sequencer_Setting_c_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD70), config_DBICADD70},
{sizeof(config_Power_Ctrl_2_indx),
config_Power_Ctrl_2_indx},
{sizeof(config_DBICSET_15), config_DBICSET_15},
{sizeof(config_DBICADD72), config_DBICADD72},
{sizeof(config_Power_Ctrl_2c_cmd),
config_Power_Ctrl_2c_cmd},
{sizeof(config_DBICSET_15), config_DBICSET_15},
/* Change this command to config_VIDEO for video mode */
{sizeof(config_COMMAND), config_COMMAND},
};
/* Toggle RESET pin of the DSI Client before sending
* panel init commands
*/
int mipi_renesas_panel_dsi_config(int on);
#endif /* _MIPI_RENESAS_H_ */
bootable/bootloader/lk/dev/panel/msm/mipi_renesas_cmd_fwvga.c
+135
View File
@@ -0,0 +1,135 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "mipi_renesas.h"
int mipi_renesas_cmd_fwvga_config(void *pdata)
{
int ret = NO_ERROR;
struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
ret = mipi_dsi_cmd_mode_config((pinfo->xres),
(pinfo->yres),
(pinfo->xres),
(pinfo->yres),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode);
return ret;
}
int mipi_renesas_cmd_fwvga_on()
{
int ret = NO_ERROR;
return ret;
}
int mipi_renesas_cmd_fwvga_off()
{
int ret = NO_ERROR;
return ret;
}
static struct mipi_dsi_phy_ctrl dsi_cmd_mode_phy_db = {
/* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
{0x03, 0x01, 0x01, 0x00}, /* regulator */
/* timing */
{0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22,
0x90, 0x18, 0x03, 0x04},
{0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
{0xbb, 0x02, 0x06, 0x00}, /* strength */
/* pll control */
{0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62,
0x01, 0x0f, 0x07, /* --> Two lane configuration */
0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0},
};
void mipi_renesas_cmd_fwvga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = REN_MIPI_FB_WIDTH;
pinfo->yres = REN_MIPI_FB_HEIGHT;
pinfo->mipi.num_of_lanes = 2;
pinfo->type = MIPI_CMD_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->mipi.mode = DSI_CMD_MODE;
pinfo->mipi.traffic_mode = 0;
pinfo->mipi.dst_format = 0;
pinfo->mipi.dsi_phy_db = &dsi_cmd_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.lane_swap = 1;
pinfo->mipi.panel_cmds = renesas_panel_video_mode_cmds;
pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(renesas_panel_video_mode_cmds);
pinfo->on = mipi_renesas_cmd_fwvga_on;
pinfo->off = mipi_renesas_cmd_fwvga_off;
pinfo->config = mipi_renesas_cmd_fwvga_config;
return;
}
void mipi_renesas_cmd_hvga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = REN_MIPI_FB_WIDTH_HVGA;
pinfo->yres = REN_MIPI_FB_HEIGHT_HVGA;
pinfo->mipi.num_of_lanes = 1;
pinfo->type = MIPI_CMD_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->clk_rate = 499000000;
pinfo->mipi.mode = DSI_CMD_MODE;
pinfo->mipi.traffic_mode = 0;
pinfo->mipi.dst_format = 0;
pinfo->mipi.dsi_phy_db = &dsi_cmd_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.lane_swap = 1;
pinfo->mipi.panel_cmds = renesas_panel_video_mode_cmds;
pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(renesas_panel_video_mode_cmds);
pinfo->on = mipi_renesas_cmd_fwvga_on;
pinfo->off = mipi_renesas_cmd_fwvga_off;
pinfo->config = mipi_renesas_cmd_fwvga_config;
return;
}
bootable/bootloader/lk/dev/panel/msm/mipi_renesas_video_fwvga.c
+169
View File
@@ -0,0 +1,169 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "mipi_renesas.h"
int mipi_renesas_video_fwvga_config(void *pdata)
{
int ret = NO_ERROR;
/* 3 Lanes -- Enables Data Lane0, 1, 2 */
unsigned char lane_en = 3;
unsigned long low_pwr_stop_mode = 1;
/* Needed or else will have blank line at top of display */
unsigned char eof_bllp_pwr = 0x9;
unsigned char interleav = 0;
struct lcdc_panel_info *lcdc = NULL;
struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
ret = mipi_dsi_video_mode_config((pinfo->xres),
(pinfo->yres),
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
(lcdc->h_back_porch),
(lcdc->v_front_porch),
(lcdc->v_back_porch),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_en,
low_pwr_stop_mode,
eof_bllp_pwr,
interleav);
return ret;
}
int mipi_renesas_video_fwvga_on()
{
int ret = NO_ERROR;
return ret;
}
int mipi_renesas_video_fwvga_off()
{
int ret = NO_ERROR;
return ret;
}
static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
{0x03, 0x01, 0x01, 0x00}, /* regulator */
/* timing */
{0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22,
0x90, 0x18, 0x03, 0x04},
{0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
{0xbb, 0x02, 0x06, 0x00}, /* strength */
/* pll control */
{0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62,
0x01, 0x0f, 0x07, /* --> Two lane configuration */
0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0},
};
void mipi_renesas_video_fwvga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = REN_MIPI_FB_WIDTH;
pinfo->yres = REN_MIPI_FB_HEIGHT;
pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK;
pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK;
pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH;
pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES;
pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES;
pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH;
pinfo->mipi.num_of_lanes = 2;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->clk_rate = 499000000;
pinfo->mipi.mode = DSI_VIDEO_MODE;
pinfo->mipi.traffic_mode = 2;
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.lane_swap = 1;
pinfo->mipi.panel_cmds = renesas_panel_video_mode_cmds;
pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(renesas_panel_video_mode_cmds);
pinfo->on = mipi_renesas_video_fwvga_on;
pinfo->off = mipi_renesas_video_fwvga_off;
pinfo->config = mipi_renesas_video_fwvga_config;
return;
}
void mipi_renesas_video_hvga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = REN_MIPI_FB_WIDTH_HVGA;
pinfo->yres = REN_MIPI_FB_HEIGHT_HVGA;
pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK_HVGA;
pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK_HVGA;
pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES_HVGA;
pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES_HVGA;
pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH_HVGA;
pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH_HVGA;
pinfo->mipi.num_of_lanes = 1;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->mipi.mode = DSI_VIDEO_MODE;
pinfo->mipi.traffic_mode = 2;
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.lane_swap = 1;
pinfo->mipi.panel_cmds = renesas_panel_video_mode_cmds;
pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(renesas_panel_video_mode_cmds);
pinfo->on = mipi_renesas_video_fwvga_on;
pinfo->off = mipi_renesas_video_fwvga_off;
pinfo->config = mipi_renesas_video_fwvga_config;
return;
}
bootable/bootloader/lk/dev/panel/msm/mipi_sharp_video_qhd.c
+163
View File
@@ -0,0 +1,163 @@
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <mdp4.h>
int mipi_sharp_video_qhd_config(void *pdata)
{
int ret = NO_ERROR;
/* 2 Lanes -- Enables Data Lane0, 1 */
uint8_t lane_en = 0x3;
uint64_t low_pwr_stop_mode = 0;
/* Needed or else will have blank line at top of display */
uint8_t eof_bllp_pwr = 0x9;
uint8_t interleav = 0;
struct lcdc_panel_info *lcdc = NULL;
struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata;
if (!pinfo)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (!lcdc)
return ERR_INVALID_ARGS;
ret = mipi_dsi_video_mode_config((pinfo->xres + lcdc->xres_pad),
(pinfo->yres + lcdc->yres_pad),
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
(lcdc->h_back_porch + lcdc->h_pulse_width),
(lcdc->v_front_porch),
(lcdc->v_back_porch + lcdc->v_pulse_width),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_en,
low_pwr_stop_mode,
eof_bllp_pwr,
interleav);
return ret;
}
int mipi_sharp_video_qhd_on()
{
return NO_ERROR;
}
int mipi_sharp_video_qhd_off()
{
return NO_ERROR;
}
static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* 540x960, RGB888, 2 Lane 60 fps video mode */
/* regulator */
{0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01},
/* timing */
{0x46, 0x1d, 0x20, 0x00, 0x39, 0x3a, 0x21, 0x21,
0x32, 0x03, 0x04, 0x00},
/* phy ctrl */
{0x5f, 0x00, 0x00, 0x10},
/* strength */
{0xff, 0x06},
/* bist control */
{0x00, 0x00, 0xb1, 0xff, 0x00, 0x00},
/* lanes config */
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb},
};
void mipi_sharp_video_qhd_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = 540;
pinfo->yres = 960;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->lcdc.h_back_porch = 80;
pinfo->lcdc.h_front_porch = 48;
pinfo->lcdc.h_pulse_width = 32;
pinfo->lcdc.v_back_porch = 15;
pinfo->lcdc.v_front_porch = 3;
pinfo->lcdc.v_pulse_width = 10;
pinfo->lcdc.border_clr = 0; /* blk */
pinfo->lcdc.underflow_clr = 0xff; /* blue */
pinfo->lcdc.hsync_skew = 0;
pinfo->clk_rate = 500000000;
pinfo->mipi.mode = DSI_VIDEO_MODE;
pinfo->mipi.pulse_mode_hsa_he = FALSE;
pinfo->mipi.hfp_power_stop = FALSE;
pinfo->mipi.hbp_power_stop = FALSE;
pinfo->mipi.hsa_power_stop = FALSE;
pinfo->mipi.eof_bllp_power_stop = FALSE;
pinfo->mipi.bllp_power_stop = FALSE;
pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_PULSE;
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
pinfo->mipi.vc = 0;
pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo->mipi.data_lane0 = TRUE;
pinfo->mipi.data_lane1 = TRUE;
pinfo->mipi.data_lane2 = FALSE;
pinfo->mipi.data_lane3 = FALSE;
pinfo->mipi.t_clk_post = 0x04;
pinfo->mipi.t_clk_pre = 0x1c;
pinfo->mipi.stream = 0; /* dma_p */
pinfo->mipi.mdp_trigger = 0;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
pinfo->mipi.frame_rate = 60;
pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.num_of_lanes = 2;
pinfo->mipi.panel_cmds = sharp_qhd_video_mode_cmds;
pinfo->mipi.num_of_panel_cmds =
ARRAY_SIZE(sharp_qhd_video_mode_cmds);
pinfo->on = mipi_sharp_video_qhd_on;
pinfo->off = mipi_sharp_video_qhd_off;
pinfo->config = mipi_sharp_video_qhd_config;
}
bootable/bootloader/lk/dev/panel/msm/mipi_tc358764_dsi2lvds.c
+455
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@@ -0,0 +1,455 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* Toshiba MIPI-DSI-to-LVDS Bridge driver.
* Device Model TC358764XBG/65XBG.
* Reference document: TC358764XBG_65XBG_V119.pdf
*
* The Host sends a DSI Generic Long Write packet (Data ID = 0x29) over the
* DSI link for each write access transaction to the chip configuration
* registers.
* Payload of this packet is 16-bit register address and 32-bit data.
* Multiple data values are allowed for sequential addresses.
*
* The Host sends a DSI Generic Read packet (Data ID = 0x24) over the DSI
* link for each read request transaction to the chip configuration
* registers. Payload of this packet is further defined as follows:
* 16-bit address followed by a 32-bit value (Generic Long Read Response
* packet).
*
* The bridge supports 5 GPIO lines controlled via the GPC register.
*
* The bridge support I2C Master/Slave.
* The I2C slave can be used for read/write to the bridge register instead of
* using the DSI interface.
* I2C slave address is 0x0F (read/write 0x1F/0x1E).
* The I2C Master can be used for communication with the panel if
* it has an I2C slave.
*
* NOTE: The I2C interface is not used in this driver.
* Only the DSI interface is used for read/write the bridge registers.
*
* Pixel data can be transmitted in non-burst or burst fashion.
* Non-burst refers to pixel data packet transmission time on DSI link
* being roughly the same (to account for packet overhead time)
* as active video line time on LVDS output (i.e. DE = 1).
* And burst refers to pixel data packet transmission time on DSI link
* being less than the active video line time on LVDS output.
* Video mode transmission is further differentiated by the types of
* timing events being transmitted.
* Video pulse mode refers to the case where both sync start and sync end
* events (for frame and line) are transmitted.
* Video event mode refers to the case where only sync start events
* are transmitted.
* This is configured via register bit VPCTRL.EVTMODE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <debug.h>
#include <platform/iomap.h>
#include <platform/timer.h>
#include <target/display.h>
#include <dev/gpio.h>
#include <dev/pm8921.h>
#include <dev/pm8921_pwm.h>
#ifndef u32
#define u32 uint32_t
#endif
#ifndef u16
#define u16 uint16_t
#endif
/* Registers definition */
/* DSI D-PHY Layer Registers */
#define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
#define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
#define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
#define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
#define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
#define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
#define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
#define CLW_CNTRL 0x0040 /* Clock Lane Control */
#define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
#define D1W_CNTRL 0x0048 /* Data Lane 1 Control */
#define D2W_CNTRL 0x004C /* Data Lane 2 Control */
#define D3W_CNTRL 0x0050 /* Data Lane 3 Control */
#define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
/* DSI PPI Layer Registers */
#define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
#define PPI_BUSYPPI 0x0108
#define PPI_LINEINITCNT 0x0110 /* Line Initialization Wait Counter */
#define PPI_LPTXTIMECNT 0x0114
#define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */
#define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
/* Analog timer function enable */
#define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */
#define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */
#define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */
#define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */
#define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */
#define PPI_D0S_CLRSIPOCOUNT 0x0164
#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */
#define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */
#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */
#define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
#define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
#define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
#define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
#define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */
#define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */
#define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */
#define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */
#define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */
#define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */
#define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */
#define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */
#define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */
#define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */
#define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */
#define PPI_CLRFLG 0x01E0 /* PRE Counters has reached set values */
#define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
#define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */
#define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */
#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
#define DSI_BUSYDSI 0x0208
#define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */
#define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
#define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */
#define DSI_INTSTATUS 0x0220 /* Interrupt Status */
#define DSI_INTMASK 0x0224 /* Interrupt Mask */
#define DSI_INTCLR 0x0228 /* Interrupt Clear */
#define DSI_LPTXTO 0x0230 /* Low Power Tx Time Out Counter */
#define DSIERRCNT 0x0300 /* DSI Error Count */
#define APLCTRL 0x0400 /* Application Layer Control */
#define RDPKTLN 0x0404 /* Command Read Packet Length */
#define VPCTRL 0x0450 /* Video Path Control */
#define HTIM1 0x0454 /* Horizontal Timing Control 1 */
#define HTIM2 0x0458 /* Horizontal Timing Control 2 */
#define VTIM1 0x045C /* Vertical Timing Control 1 */
#define VTIM2 0x0460 /* Vertical Timing Control 2 */
#define VFUEN 0x0464 /* Video Frame Timing Update Enable */
/* Mux Input Select for LVDS LINK Input */
#define LVMX0003 0x0480 /* Bit 0 to 3 */
#define LVMX0407 0x0484 /* Bit 4 to 7 */
#define LVMX0811 0x0488 /* Bit 8 to 11 */
#define LVMX1215 0x048C /* Bit 12 to 15 */
#define LVMX1619 0x0490 /* Bit 16 to 19 */
#define LVMX2023 0x0494 /* Bit 20 to 23 */
#define LVMX2427 0x0498 /* Bit 24 to 27 */
#define LVCFG 0x049C /* LVDS Configuration */
#define LVPHY0 0x04A0 /* LVDS PHY 0 */
#define LVPHY1 0x04A4 /* LVDS PHY 1 */
#define SYSSTAT 0x0500 /* System Status */
#define SYSRST 0x0504 /* System Reset */
/* GPIO Registers */
#define GPIOC 0x0520 /* GPIO Control */
#define GPIOO 0x0524 /* GPIO Output */
#define GPIOI 0x0528 /* GPIO Input */
/* I2C Registers */
#define I2CTIMCTRL 0x0540 /* I2C IF Timing and Enable Control */
#define I2CMADDR 0x0544 /* I2C Master Addressing */
#define WDATAQ 0x0548 /* Write Data Queue */
#define RDATAQ 0x054C /* Read Data Queue */
/* Chip ID and Revision ID Register */
#define IDREG 0x0580
#define TC358764XBG_ID 0x00006500
/* Debug Registers */
#define DEBUG00 0x05A0 /* Debug */
#define DEBUG01 0x05A4 /* LVDS Data */
/* PWM */
static u32 d2l_pwm_freq_hz = (3.921*1000);
#define PWM_FREQ_HZ (d2l_pwm_freq_hz)
#define PWM_PERIOD_USEC (USEC_PER_SEC / PWM_FREQ_HZ)
#define PWM_DUTY_LEVEL (PWM_PERIOD_USEC / PWM_LEVEL)
#define CMD_DELAY 100
#define DSI_MAX_LANES 4
#define KHZ 1000
#define MHZ (1000*1000)
#define BIT(bit) (1 << (bit))
#define DSI_HOST_HDR_SIZE 4
#define DSI_HDR_LAST BIT(31)
#define DSI_HDR_LONG_PKT BIT(30)
#define DSI_HDR_BTA BIT(29)
#define DSI_HDR_VC(vc) (((vc) & 0x03) << 22)
#define DSI_HDR_DTYPE(dtype) (((dtype) & 0x03f) << 16)
#define DSI_HDR_DATA2(data) (((data) & 0x0ff) << 8)
#define DSI_HDR_DATA1(data) ((data) & 0x0ff)
#define DSI_HDR_WC(wc) ((wc) & 0x0ffff)
#define DTYPE_GEN_LWRITE 0x29 /* long write */
#define DTYPE_GEN_READ2 0x24 /* long read, 2 parameter */
/**
* Command payload for DTYPE_GEN_LWRITE (0x29) / DTYPE_GEN_READ2 (0x24).
*/
struct wr_cmd_payload {
u32 dsi_hdr;
u16 addr;
u16 data0;
u16 data1;
u16 align32;
} __packed;
static u32 mipi_d2l_read_reg(u16 reg)
{
int ret = 0;
char buf[24];
char *rp = buf;
u32 data;
int len = 4; /* return data size */
u32 dsi_hdr;
struct mipi_dsi_cmd mipi_cmd;
mipi_cmd.size = sizeof(dsi_hdr);
mipi_cmd.payload = (char *) &dsi_hdr;
dsi_hdr = 0;
dsi_hdr |= DSI_HDR_DTYPE(DTYPE_GEN_READ2);
dsi_hdr |= DSI_HDR_WC(0);
dsi_hdr |= DSI_HDR_VC(0); /* Virtual Channel */
dsi_hdr |= DSI_HDR_DATA1((reg & 0xFF));
dsi_hdr |= DSI_HDR_DATA2((reg >> 8));
dsi_hdr |= DSI_HDR_LAST;
dsi_hdr |= DSI_HDR_BTA;
/* mutex had been acquired at mipi_dsi_on */
ret = mipi_dsi_cmds_tx(&mipi_cmd, 1);
len = mipi_dsi_cmds_rx(&rp, len);
data = *(u32 *)buf;
dprintf(SPEW, "%s: reg=0x%x.data=0x%08x.\n", __func__, reg, data);
return data;
}
/**
* Write a bridge register
*
* @param reg
* @param data
*
* @return int
*/
static int mipi_d2l_write_reg(u16 reg, u32 data)
{
struct wr_cmd_payload payload;
struct mipi_dsi_cmd mipi_cmd;
int dlen = sizeof(reg) + sizeof(data);
mipi_cmd.size = sizeof(payload);
mipi_cmd.payload = (char *) &payload;
payload.addr = reg;
payload.dsi_hdr = 0;
payload.dsi_hdr |= DSI_HDR_DTYPE(DTYPE_GEN_LWRITE);
payload.dsi_hdr |= DSI_HDR_WC(dlen);
payload.dsi_hdr |= DSI_HDR_VC(0); /* Virtual Channel */
payload.dsi_hdr |= DSI_HDR_LONG_PKT;
payload.dsi_hdr |= DSI_HDR_LAST;
payload.align32 = 0xFFFF;
payload.data0 = data & 0xFFFF;
payload.data1 = data >> 16;
mipi_dsi_cmds_tx(&mipi_cmd, 1);
dprintf(SPEW, "%s: reg=0x%x. data=0x%x.\n", __func__, reg, data);
return 0;
}
static int mipi_d2l_read_chip_id(void)
{
u32 chip_id = 0;
int retry = 0;
while (chip_id != TC358764XBG_ID) {
chip_id = mipi_d2l_read_reg(IDREG);
dprintf(SPEW, "%s: chip_id=0x%x.\n", __func__, chip_id);
mdelay(100);
if (retry++ >= 2)
return ERR_IO;
}
return chip_id;
}
/**
* Init the D2L bridge via the DSI interface for Video.
*
* VPCTRL.EVTMODE (0x20) configuration bit is needed to determine whether
* video timing information is delivered in pulse mode or event mode.
* In pulse mode, both Sync Start and End packets are required.
* In event mode, only Sync Start packets are required.
*
* @param pinfo
*
* @return int
*/
int mipi_d2l_dsi_init_sequence(struct msm_panel_info *pinfo)
{
u32 lanes_enable;
u32 vpctrl;
u32 htime1;
u32 vtime1;
u32 htime2;
u32 vtime2;
u32 ppi_tx_rx_ta; /* BTA Bus-Turn-Around */
u32 lvcfg;
u32 hbpr; /* Horizontal Back Porch */
u32 hpw; /* Horizontal Pulse Width */
u32 vbpr; /* Vertical Back Porch */
u32 vpw; /* Vertical Pulse Width */
u32 hfpr; /* Horizontal Front Porch */
u32 hsize; /* Horizontal Active size */
u32 vfpr; /* Vertical Front Porch */
u32 vsize; /* Vertical Active size */
bool vesa_rgb888 = false;
lanes_enable = 0x01F; /* clock-lane enable + 4 data lanes */
vpctrl = 0x01000120; /* DSI_NON_BURST_SYNCH_EVENT */
dprintf(SPEW, "%s.xres=%d.yres=%d.fps=%d.dst_format=%d.\n",
__func__,
pinfo->xres,
pinfo->yres,
pinfo->mipi.frame_rate,
pinfo->mipi.dst_format);
hbpr = pinfo->lcdc.h_back_porch;
hpw = pinfo->lcdc.h_pulse_width;
vbpr = pinfo->lcdc.v_back_porch;
vpw = pinfo->lcdc.v_pulse_width;
htime1 = (hbpr << 16) + hpw;
vtime1 = (vbpr << 16) + vpw;
hfpr = pinfo->lcdc.h_front_porch;
hsize = pinfo->xres;
vfpr = pinfo->lcdc.v_front_porch;
vsize = pinfo->yres;
htime2 = (hfpr << 16) + hsize;
vtime2 = (vfpr << 16) + vsize;
lvcfg = 0x0003; /* PCLK=DCLK/3, Dual Link, LVEN */
vpctrl = 0x01000120; /* Output RGB888 , Event-Mode , */
ppi_tx_rx_ta = 0x00040004;
if (pinfo->xres == 1366) {
ppi_tx_rx_ta = 0x00040004;
lvcfg = 0x01; /* LVEN */
vesa_rgb888 = true;
}
if (pinfo->xres == 1200) {
lvcfg = 0x0103; /* PCLK=DCLK/4, Dual Link, LVEN */
vesa_rgb888 = true;
}
dprintf(SPEW, "%s.htime1=0x%x.\n", __func__, htime1);
dprintf(SPEW, "%s.vtime1=0x%x.\n", __func__, vtime1);
dprintf(SPEW, "%s.vpctrl=0x%x.\n", __func__, vpctrl);
dprintf(SPEW, "%s.lvcfg=0x%x.\n", __func__, lvcfg);
mipi_d2l_write_reg(SYSRST, 0xFF);
mdelay(30);
if (vesa_rgb888) {
/* VESA format instead of JEIDA format for RGB888 */
mipi_d2l_write_reg(LVMX0003, 0x03020100);
mipi_d2l_write_reg(LVMX0407, 0x08050704);
mipi_d2l_write_reg(LVMX0811, 0x0F0E0A09);
mipi_d2l_write_reg(LVMX1215, 0x100D0C0B);
mipi_d2l_write_reg(LVMX1619, 0x12111716);
mipi_d2l_write_reg(LVMX2023, 0x1B151413);
mipi_d2l_write_reg(LVMX2427, 0x061A1918);
}
mipi_d2l_write_reg(PPI_TX_RX_TA, ppi_tx_rx_ta); /* BTA */
mipi_d2l_write_reg(PPI_LPTXTIMECNT, 0x00000004);
mipi_d2l_write_reg(PPI_D0S_CLRSIPOCOUNT, 0x00000003);
mipi_d2l_write_reg(PPI_D1S_CLRSIPOCOUNT, 0x00000003);
mipi_d2l_write_reg(PPI_D2S_CLRSIPOCOUNT, 0x00000003);
mipi_d2l_write_reg(PPI_D3S_CLRSIPOCOUNT, 0x00000003);
mipi_d2l_write_reg(PPI_LANEENABLE, lanes_enable);
mipi_d2l_write_reg(DSI_LANEENABLE, lanes_enable);
mipi_d2l_write_reg(PPI_STARTPPI, 0x00000001);
mipi_d2l_write_reg(DSI_STARTDSI, 0x00000001);
mipi_d2l_write_reg(VPCTRL, vpctrl); /* RGB888 + Event mode */
mipi_d2l_write_reg(HTIM1, htime1);
mipi_d2l_write_reg(VTIM1, vtime1);
mipi_d2l_write_reg(HTIM2, htime2);
mipi_d2l_write_reg(VTIM2, vtime2);
mipi_d2l_write_reg(VFUEN, 0x00000001);
mipi_d2l_write_reg(LVCFG, lvcfg); /* Enables LVDS tx */
mipi_d2l_write_reg(GPIOC, 0x1F);
/* Set gpio#4=U/D=0, gpio#3=L/R=1 , gpio#2,1=CABC=0, gpio#0=NA. */
mipi_d2l_write_reg(GPIOO, 0x08);
mipi_d2l_read_chip_id();
return 0;
}
bootable/bootloader/lk/dev/panel/msm/mipi_tc358764_dsi2lvds.h
+35
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@@ -0,0 +1,35 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MIPI_TC358764_DSI2LVDS_H
#define MIPI_TC358764_DSI2LVDS_H
int mipi_d2l_dsi_init_sequence(struct msm_panel_info *pinfo);
#endif /* MIPI_TC358764_DSI2LVDS_H */
bootable/bootloader/lk/dev/panel/msm/mipi_toshiba_video_720p.c
+175
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@@ -0,0 +1,175 @@
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <mdp4.h>
int mipi_toshiba_video_720p_config(void *pdata)
{
int ret = NO_ERROR;
/* 3 Lanes -- Enables Data Lane0, 1, 2 */
uint8_t lane_en = 0xf;
uint64_t low_pwr_stop_mode = 0;
/* Needed or else will have blank line at top of display
Enable LP during EOF to send DCS commands during blanking */
uint8_t eof_bllp_pwr = 0x9;
uint8_t interleav = 0;
struct lcdc_panel_info *lcdc = NULL;
struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
ret = mipi_dsi_video_mode_config((pinfo->xres + lcdc->xres_pad),
(pinfo->yres + lcdc->yres_pad),
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
(lcdc->h_back_porch + lcdc->h_pulse_width),
(lcdc->v_front_porch),
(lcdc->v_back_porch + lcdc->v_pulse_width),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_en,
low_pwr_stop_mode,
eof_bllp_pwr,
interleav);
return ret;
}
int mipi_toshiba_video_720p_on()
{
int ret = NO_ERROR;
return ret;
}
int mipi_toshiba_video_720p_off()
{
int ret = NO_ERROR;
return ret;
}
static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* 720x1280, RGB888, 4 Lane 60 fps video mode */
/* regulator */
{0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01},
/* timing */
{0xb0, 0x23, 0x1b, 0x00, 0x94, 0x93, 0x1e, 0x25,
0x15, 0x03, 0x04, 0x00},
/* phy ctrl */
{0x5f, 0x00, 0x00, 0x10},
/* strength */
{0xff, 0x06},
/* bist control */
{0x00, 0x00, 0xb1, 0xff, 0x00, 0x00},
/* lanes config */
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb},
};
void mipi_toshiba_video_720p_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = 720;
pinfo->yres = 1280;
/*
*
* Panel's Horizontal input timing requirement is to
* include dummy(pad) data of 200 clk in addition to
* width and porch/sync width values
*/
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->lcdc.h_back_porch = 32;
pinfo->lcdc.h_front_porch = 144;
pinfo->lcdc.h_pulse_width = 12;
pinfo->lcdc.v_back_porch = 3;
pinfo->lcdc.v_front_porch = 9;
pinfo->lcdc.v_pulse_width = 4;
pinfo->lcdc.border_clr = 0; /* blk */
pinfo->lcdc.underflow_clr = 0xff; /* blue */
pinfo->lcdc.hsync_skew = 0;
pinfo->clk_rate = 424000000;
pinfo->mipi.mode = DSI_VIDEO_MODE;
pinfo->mipi.pulse_mode_hsa_he = FALSE;
pinfo->mipi.hfp_power_stop = FALSE;
pinfo->mipi.hbp_power_stop = FALSE;
pinfo->mipi.hsa_power_stop = FALSE;
pinfo->mipi.eof_bllp_power_stop = FALSE;
pinfo->mipi.bllp_power_stop = FALSE;
pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
pinfo->mipi.vc = 0;
pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo->mipi.data_lane0 = TRUE;
pinfo->mipi.data_lane1 = TRUE;
pinfo->mipi.data_lane2 = TRUE;
pinfo->mipi.data_lane3 = TRUE;
pinfo->mipi.t_clk_post = 0x04;
pinfo->mipi.t_clk_pre = 0x1b;
pinfo->mipi.stream = 0; /* dma_p */
pinfo->mipi.mdp_trigger = 0;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
pinfo->mipi.frame_rate = 60;
pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.num_of_lanes = 4;
pinfo->mipi.panel_cmds = toshiba_mdv24_video_mode_cmds;
pinfo->mipi.num_of_panel_cmds =
ARRAY_SIZE(toshiba_mdv24_video_mode_cmds);
pinfo->on = mipi_toshiba_video_720p_on;
pinfo->off = mipi_toshiba_video_720p_off;
pinfo->config = mipi_toshiba_video_720p_config;
return;
}
bootable/bootloader/lk/dev/panel/msm/mipi_toshiba_video_wsvga.c
+172
View File
@@ -0,0 +1,172 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <stdint.h>
#include <msm_panel.h>
#include <mipi_dsi.h>
#include <sys/types.h>
#include <err.h>
#include <reg.h>
#include <platform/iomap.h>
#include <mdp4.h>
int mipi_toshiba_video_wsvga_config(void *pdata)
{
int ret = NO_ERROR;
/* 3 Lanes -- Enables Data Lane0, 1, 2 */
unsigned char lane_en = 7;
unsigned long low_pwr_stop_mode = 0;
/* Needed or else will have blank line at top of display */
unsigned char eof_bllp_pwr = 0x8;
unsigned char interleav = 0;
struct lcdc_panel_info *lcdc = NULL;
struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
ret = mipi_dsi_video_mode_config((pinfo->xres + lcdc->xres_pad),
(pinfo->yres + lcdc->yres_pad),
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
(lcdc->h_back_porch + lcdc->h_pulse_width),
(lcdc->v_front_porch),
(lcdc->v_back_porch + lcdc->v_pulse_width),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_en,
low_pwr_stop_mode,
eof_bllp_pwr,
interleav);
return ret;
}
int mipi_toshiba_video_wsvga_on()
{
int ret = NO_ERROR;
return ret;
}
int mipi_toshiba_video_wsvga_off()
{
int ret = NO_ERROR;
return ret;
}
static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* 600*1024, RGB888, 3 Lane 55 fps video mode */
/* regulator */
{0x03, 0x0a, 0x04, 0x00, 0x20},
/* timing */
{0xab, 0x8a, 0x18, 0x00, 0x92, 0x97, 0x1b, 0x8c,
0x0c, 0x03, 0x04, 0xa0},
/* phy ctrl */
{0x5f, 0x00, 0x00, 0x10},
/* strength */
{0xff, 0x00, 0x06, 0x00},
/* pll control */
{0x0, 0x7f, 0x31, 0xda, 0x00, 0x50, 0x48, 0x63,
0x41, 0x0f, 0x01,
0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 },
};
void mipi_toshiba_video_wsvga_init(struct msm_panel_info *pinfo)
{
if (!pinfo)
return;
pinfo->xres = 600;
pinfo->yres = 1024;
/*
*
* Panel's Horizontal input timing requirement is to
* include dummy(pad) data of 200 clk in addition to
* width and porch/sync width values
*/
pinfo->lcdc.xres_pad = 200;
pinfo->lcdc.yres_pad = 0;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->lcdc.h_back_porch = 16;
pinfo->lcdc.h_front_porch = 23;
pinfo->lcdc.h_pulse_width = 8;
pinfo->lcdc.v_back_porch = 2;
pinfo->lcdc.v_front_porch = 7;
pinfo->lcdc.v_pulse_width = 2;
pinfo->lcdc.border_clr = 0; /* blk */
pinfo->lcdc.underflow_clr = 0xff; /* blue */
pinfo->lcdc.hsync_skew = 0;
pinfo->clk_rate = 384000000;
pinfo->mipi.mode = DSI_VIDEO_MODE;
pinfo->mipi.pulse_mode_hsa_he = FALSE;
pinfo->mipi.hfp_power_stop = FALSE;
pinfo->mipi.hbp_power_stop = FALSE;
pinfo->mipi.hsa_power_stop = FALSE;
pinfo->mipi.eof_bllp_power_stop = FALSE;
pinfo->mipi.bllp_power_stop = FALSE;
pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
pinfo->mipi.vc = 0;
pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo->mipi.data_lane0 = TRUE;
pinfo->mipi.data_lane1 = TRUE;
pinfo->mipi.data_lane2 = TRUE;
pinfo->mipi.t_clk_post = 0x20;
pinfo->mipi.t_clk_pre = 0x2d;
pinfo->mipi.stream = 0; /* dma_p */
pinfo->mipi.mdp_trigger = 0;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
pinfo->mipi.frame_rate = 55;
pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db;
pinfo->mipi.tx_eot_append = TRUE;
pinfo->mipi.num_of_lanes = 3;
pinfo->mipi.panel_cmds = toshiba_mdt61_video_mode_cmds;
pinfo->mipi.num_of_panel_cmds =
ARRAY_SIZE(toshiba_mdt61_video_mode_cmds);
pinfo->on = mipi_toshiba_video_wsvga_on;
pinfo->off = mipi_toshiba_video_wsvga_off;
pinfo->config = mipi_toshiba_video_wsvga_config;
return;
}
bootable/bootloader/lk/dev/panel/msm/rules.mk
+28
View File
@@ -0,0 +1,28 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include
ifeq ($(PLATFORM),msm8960)
OBJS += \
$(LOCAL_DIR)/lvds_chimei_wxga.o \
$(LOCAL_DIR)/mipi_tc358764_dsi2lvds.o \
$(LOCAL_DIR)/mipi_chimei_video_wxga.o \
$(LOCAL_DIR)/mipi_toshiba_video_wsvga.o
endif
ifeq ($(PLATFORM),msm7x27a)
OBJS += \
$(LOCAL_DIR)/mipi_renesas.o \
$(LOCAL_DIR)/mipi_renesas_video_fwvga.o \
$(LOCAL_DIR)/mipi_renesas_cmd_fwvga.o \
$(LOCAL_DIR)/mipi_nt35510.o \
$(LOCAL_DIR)/mipi_nt35510_video_wvga.o \
$(LOCAL_DIR)/mipi_nt35510_cmd_wvga.o \
$(LOCAL_DIR)/lcdc_truly_hvga.o
endif
ifeq ($(PLATFORM),msm8974)
OBJS += \
$(LOCAL_DIR)/mipi_toshiba_video_720p.o \
$(LOCAL_DIR)/mipi_sharp_video_qhd.o
endif