From 801e6d2ad8005335413fc75ec2d874055ffb04b4 Mon Sep 17 00:00:00 2001 From: T Date: Mon, 9 Sep 2024 08:54:06 +0000 Subject: [PATCH] M7350v2_en_gpl --- .../drivers/net/wireless/ath/ath6kl/txrx.c | 6 +- .../drivers/net/wireless/ath/ath6kl/usb.c | 23 +- external/hostap/hostapd/Makefile | 30 + .../hostapd/config/tp-ath6kl-ap-all.conf | 2 +- .../config/tp-bcm-ap-all-7350-series.conf | 15 + .../config/tp-bcm-ap-all-7350-series.deny | 0 .../hostap/hostapd/config/tp-bcm-ap-all.conf | 13 + external/hostap/src/ap/ieee802_11_ht.c | 6 +- .../dts/m7350-un-v3/am3517_mt_ventoux.dts | 27 + .../arm/boot/dts/m7350-un-v3/apq8026-mtp.dts | 22 + .../arm/boot/dts/m7350-un-v3/apq8026-xpm.dts | 22 + .../arm/boot/dts/m7350-un-v3/apq8026.dtsi | 24 + .../dts/m7350-un-v3/apq8074-dragonboard.dtsi | 654 ++++++ .../arm/boot/dts/m7350-un-v3/apq8074-v1.dtsi | 48 + .../m7350-un-v3/apq8074-v2-dragonboard.dts | 22 + .../dts/m7350-un-v3/apq8074-v2-liquid.dts | 34 + .../arm/boot/dts/m7350-un-v3/apq8074-v2.dtsi | 52 + .../arm/boot/dts/m7350-un-v3/apq8084-ion.dtsi | 31 + .../dts/m7350-un-v3/apq8084-regulator.dtsi | 377 ++++ .../arm/boot/dts/m7350-un-v3/apq8084-sim.dts | 173 ++ .../boot/dts/m7350-un-v3/apq8084-smp2p.dtsi | 82 + .../arm/boot/dts/m7350-un-v3/apq8084.dtsi | 276 +++ .../arm/boot/dts/m7350-un-v3/at91sam9g20.dtsi | 238 +++ .../boot/dts/m7350-un-v3/at91sam9g25ek.dts | 49 + .../arm/boot/dts/m7350-un-v3/at91sam9g45.dtsi | 247 +++ .../boot/dts/m7350-un-v3/at91sam9m10g45ek.dts | 156 ++ .../arm/boot/dts/m7350-un-v3/at91sam9x5.dtsi | 263 +++ .../boot/dts/m7350-un-v3/at91sam9x5cm.dtsi | 74 + .../arch/arm/boot/dts/m7350-un-v3/db8500.dtsi | 274 +++ .../dsi-panel-nt35590-720p-cmd.dtsi | 530 +++++ .../dsi-panel-nt35590-720p-video.dtsi | 524 +++++ .../dsi-panel-orise-720p-video.dtsi | 60 + .../dsi-panel-sharp-qhd-video.dtsi | 67 + .../dts/m7350-un-v3/dsi-panel-sim-video.dtsi | 46 + .../dsi-panel-toshiba-720p-video.dtsi | 124 ++ .../dsi-v2-panel-hx8379a-wvga-video.dtsi | 117 ++ .../dsi-v2-panel-truly-wvga-video.dtsi | 120 ++ .../dts/m7350-un-v3/exynos4210-origen.dts | 137 ++ .../dts/m7350-un-v3/exynos4210-smdkv310.dts | 182 ++ .../arm/boot/dts/m7350-un-v3/exynos4210.dtsi | 398 ++++ .../dts/m7350-un-v3/exynos5250-smdk5250.dts | 26 + .../arm/boot/dts/m7350-un-v3/exynos5250.dtsi | 413 ++++ .../arm/boot/dts/m7350-un-v3/fsm9900-rumi.dts | 31 + .../arm/boot/dts/m7350-un-v3/fsm9900-sim.dts | 32 + .../arm/boot/dts/m7350-un-v3/fsm9900.dtsi | 94 + .../arm/boot/dts/m7350-un-v3/highbank.dts | 209 ++ .../dts/m7350-un-v3/imx27-phytec-phycore.dts | 76 + .../arch/arm/boot/dts/m7350-un-v3/imx27.dtsi | 217 ++ .../boot/dts/m7350-un-v3/imx51-babbage.dts | 221 +++ .../arch/arm/boot/dts/m7350-un-v3/imx51.dtsi | 246 +++ .../arm/boot/dts/m7350-un-v3/imx53-ard.dts | 113 ++ .../arm/boot/dts/m7350-un-v3/imx53-evk.dts | 119 ++ .../arm/boot/dts/m7350-un-v3/imx53-qsb.dts | 125 ++ .../arm/boot/dts/m7350-un-v3/imx53-smd.dts | 168 ++ .../arch/arm/boot/dts/m7350-un-v3/imx53.dtsi | 301 +++ .../arm/boot/dts/m7350-un-v3/imx6q-arm2.dts | 76 + .../boot/dts/m7350-un-v3/imx6q-sabrelite.dts | 83 + .../arch/arm/boot/dts/m7350-un-v3/imx6q.dtsi | 575 ++++++ .../dts/m7350-un-v3/kirkwood-dreamplug.dts | 24 + .../arm/boot/dts/m7350-un-v3/kirkwood.dtsi | 36 + .../boot/dts/m7350-un-v3/mpq8092-iommu.dtsi | 40 + .../arm/boot/dts/m7350-un-v3/mpq8092-ion.dtsi | 33 + .../dts/m7350-un-v3/mpq8092-regulator.dtsi | 324 +++ .../arm/boot/dts/m7350-un-v3/mpq8092-rumi.dts | 28 + .../boot/dts/m7350-un-v3/mpq8092-rumi.dtsi | 134 ++ .../arm/boot/dts/m7350-un-v3/mpq8092-sim.dts | 125 ++ .../arm/boot/dts/m7350-un-v3/mpq8092.dtsi | 240 +++ .../arm/boot/dts/m7350-un-v3/msm-gdsc.dtsi | 63 + .../boot/dts/m7350-un-v3/msm-iommu-v0.dtsi | 333 ++++ .../boot/dts/m7350-un-v3/msm-iommu-v1.dtsi | 514 +++++ .../m7350-un-v3/msm-pm8019-rpm-regulator.dtsi | 301 +++ .../arm/boot/dts/m7350-un-v3/msm-pm8019.dtsi | 415 ++++ .../m7350-un-v3/msm-pm8110-rpm-regulator.dtsi | 381 ++++ .../arm/boot/dts/m7350-un-v3/msm-pm8110.dtsi | 608 ++++++ .../m7350-un-v3/msm-pm8226-rpm-regulator.dtsi | 492 +++++ .../arm/boot/dts/m7350-un-v3/msm-pm8226.dtsi | 833 ++++++++ .../arm/boot/dts/m7350-un-v3/msm-pm8841.dtsi | 242 +++ .../arm/boot/dts/m7350-un-v3/msm-pm8941.dtsi | 1384 +++++++++++++ .../m7350-un-v3/msm-pm8x41-rpm-regulator.dtsi | 585 ++++++ .../arm/boot/dts/m7350-un-v3/msm-pma8084.dtsi | 666 +++++++ .../arm/boot/dts/m7350-un-v3/msm8226-bus.dtsi | 1128 +++++++++++ .../msm8226-camera-sensor-cdp.dtsi | 108 + .../msm8226-camera-sensor-mtp.dtsi | 108 + .../msm8226-camera-sensor-qrd.dtsi | 108 + .../boot/dts/m7350-un-v3/msm8226-camera.dtsi | 139 ++ .../arm/boot/dts/m7350-un-v3/msm8226-cdp.dtsi | 393 ++++ .../dts/m7350-un-v3/msm8226-coresight.dtsi | 377 ++++ .../boot/dts/m7350-un-v3/msm8226-fluid.dts | 33 + .../arm/boot/dts/m7350-un-v3/msm8226-gpu.dtsi | 161 ++ .../m7350-un-v3/msm8226-iommu-domains.dtsi | 31 + .../boot/dts/m7350-un-v3/msm8226-iommu.dtsi | 237 +++ .../arm/boot/dts/m7350-un-v3/msm8226-ion.dtsi | 66 + .../boot/dts/m7350-un-v3/msm8226-mdss.dtsi | 80 + .../arm/boot/dts/m7350-un-v3/msm8226-mtp.dtsi | 445 +++++ .../arm/boot/dts/m7350-un-v3/msm8226-pm.dtsi | 389 ++++ .../arm/boot/dts/m7350-un-v3/msm8226-qrd.dtsi | 406 ++++ .../dts/m7350-un-v3/msm8226-regulator.dtsi | 460 +++++ .../arm/boot/dts/m7350-un-v3/msm8226-sim.dts | 135 ++ .../boot/dts/m7350-un-v3/msm8226-smp2p.dtsi | 225 +++ .../boot/dts/m7350-un-v3/msm8226-v1-cdp.dts | 25 + .../boot/dts/m7350-un-v3/msm8226-v1-mtp.dts | 25 + .../boot/dts/m7350-un-v3/msm8226-v1-qrd.dts | 25 + .../arm/boot/dts/m7350-un-v3/msm8226-v1.dtsi | 19 + .../boot/dts/m7350-un-v3/msm8226-v2-cdp.dts | 25 + .../boot/dts/m7350-un-v3/msm8226-v2-mtp.dts | 25 + .../boot/dts/m7350-un-v3/msm8226-v2-qrd.dts | 25 + .../arm/boot/dts/m7350-un-v3/msm8226-v2.dtsi | 19 + .../arm/boot/dts/m7350-un-v3/msm8226.dtsi | 1248 ++++++++++++ .../arm/boot/dts/m7350-un-v3/msm8610-bus.dtsi | 1014 ++++++++++ .../msm8610-camera-sensor-cdp-mtp.dtsi | 116 ++ .../boot/dts/m7350-un-v3/msm8610-camera.dtsi | 80 + .../arm/boot/dts/m7350-un-v3/msm8610-cdp.dts | 396 ++++ .../dts/m7350-un-v3/msm8610-coresight.dtsi | 357 ++++ .../arm/boot/dts/m7350-un-v3/msm8610-gpu.dtsi | 167 ++ .../m7350-un-v3/msm8610-iommu-domains.dtsi | 36 + .../arm/boot/dts/m7350-un-v3/msm8610-ion.dtsi | 38 + .../boot/dts/m7350-un-v3/msm8610-mdss.dtsi | 37 + .../arm/boot/dts/m7350-un-v3/msm8610-mtp.dts | 354 ++++ .../arm/boot/dts/m7350-un-v3/msm8610-pm.dtsi | 391 ++++ .../arm/boot/dts/m7350-un-v3/msm8610-qrd.dts | 267 +++ .../dts/m7350-un-v3/msm8610-regulator.dtsi | 358 ++++ .../arm/boot/dts/m7350-un-v3/msm8610-rumi.dts | 31 + .../arm/boot/dts/m7350-un-v3/msm8610-sim.dts | 72 + .../boot/dts/m7350-un-v3/msm8610-smp2p.dtsi | 225 +++ .../arm/boot/dts/m7350-un-v3/msm8610.dtsi | 1075 ++++++++++ .../arm/boot/dts/m7350-un-v3/msm8660-surf.dts | 24 + .../arm/boot/dts/m7350-un-v3/msm8926-cdp.dts | 22 + .../arm/boot/dts/m7350-un-v3/msm8926-mtp.dts | 22 + .../arm/boot/dts/m7350-un-v3/msm8926-qrd.dts | 21 + .../arm/boot/dts/m7350-un-v3/msm8926.dtsi | 30 + .../arm/boot/dts/m7350-un-v3/msm8974-bus.dtsi | 1411 +++++++++++++ .../msm8974-camera-sensor-cdp.dtsi | 189 ++ .../msm8974-camera-sensor-dragonboard.dtsi | 174 ++ .../msm8974-camera-sensor-fluid.dtsi | 190 ++ .../msm8974-camera-sensor-liquid.dtsi | 190 ++ .../msm8974-camera-sensor-mtp.dtsi | 191 ++ .../boot/dts/m7350-un-v3/msm8974-camera.dtsi | 215 ++ .../arm/boot/dts/m7350-un-v3/msm8974-cdp.dtsi | 729 +++++++ .../boot/dts/m7350-un-v3/msm8974-clock.dtsi | 27 + .../dts/m7350-un-v3/msm8974-coresight.dtsi | 381 ++++ .../boot/dts/m7350-un-v3/msm8974-fluid.dtsi | 667 +++++++ .../arm/boot/dts/m7350-un-v3/msm8974-gpu.dtsi | 185 ++ .../arm/boot/dts/m7350-un-v3/msm8974-ion.dtsi | 59 + .../boot/dts/m7350-un-v3/msm8974-leds.dtsi | 129 ++ .../boot/dts/m7350-un-v3/msm8974-liquid.dtsi | 893 +++++++++ .../boot/dts/m7350-un-v3/msm8974-mdss.dtsi | 148 ++ .../arm/boot/dts/m7350-un-v3/msm8974-mtp.dtsi | 705 +++++++ .../dts/m7350-un-v3/msm8974-regulator.dtsi | 568 ++++++ .../boot/dts/m7350-un-v3/msm8974-rumi.dtsi | 146 ++ .../arm/boot/dts/m7350-un-v3/msm8974-sim.dtsi | 93 + .../boot/dts/m7350-un-v3/msm8974-smp2p.dtsi | 225 +++ .../boot/dts/m7350-un-v3/msm8974-v1-cdp.dts | 33 + .../boot/dts/m7350-un-v3/msm8974-v1-fluid.dts | 33 + .../m7350-un-v3/msm8974-v1-iommu-domains.dtsi | 31 + .../dts/m7350-un-v3/msm8974-v1-iommu.dtsi | 40 + .../dts/m7350-un-v3/msm8974-v1-liquid.dts | 24 + .../boot/dts/m7350-un-v3/msm8974-v1-mtp.dts | 28 + .../boot/dts/m7350-un-v3/msm8974-v1-pm.dtsi | 456 +++++ .../boot/dts/m7350-un-v3/msm8974-v1-rumi.dts | 24 + .../boot/dts/m7350-un-v3/msm8974-v1-sim.dts | 24 + .../arm/boot/dts/m7350-un-v3/msm8974-v1.dtsi | 134 ++ .../boot/dts/m7350-un-v3/msm8974-v2-cdp.dts | 36 + .../boot/dts/m7350-un-v3/msm8974-v2-fluid.dts | 36 + .../m7350-un-v3/msm8974-v2-iommu-domains.dtsi | 45 + .../dts/m7350-un-v3/msm8974-v2-iommu.dtsi | 256 +++ .../dts/m7350-un-v3/msm8974-v2-liquid.dts | 36 + .../boot/dts/m7350-un-v3/msm8974-v2-mtp.dts | 40 + .../boot/dts/m7350-un-v3/msm8974-v2-pm.dtsi | 452 +++++ .../arm/boot/dts/m7350-un-v3/msm8974-v2.dtsi | 138 ++ .../arm/boot/dts/m7350-un-v3/msm8974.dtsi | 1745 +++++++++++++++++ .../arm/boot/dts/m7350-un-v3/msm9625-cdp.dtsi | 100 + .../dts/m7350-un-v3/msm9625-coresight.dtsi | 259 +++ .../boot/dts/m7350-un-v3/msm9625-display.dtsi | 20 + .../arm/boot/dts/m7350-un-v3/msm9625-ion.dtsi | 35 + .../arm/boot/dts/m7350-un-v3/msm9625-mtp.dtsi | 111 ++ .../arm/boot/dts/m7350-un-v3/msm9625-pm.dtsi | 299 +++ .../dts/m7350-un-v3/msm9625-regulator.dtsi | 284 +++ .../boot/dts/m7350-un-v3/msm9625-smp2p.dtsi | 142 ++ .../boot/dts/m7350-un-v3/msm9625-v1-cdp.dts | 24 + .../boot/dts/m7350-un-v3/msm9625-v1-mtp.dts | 24 + .../boot/dts/m7350-un-v3/msm9625-v1-rumi.dts | 26 + .../arm/boot/dts/m7350-un-v3/msm9625-v1.dtsi | 67 + .../boot/dts/m7350-un-v3/msm9625-v2-cdp.dts | 24 + .../boot/dts/m7350-un-v3/msm9625-v2-mtp.dts | 122 ++ .../boot/dts/m7350-un-v3/msm9625-v2.1-cdp.dts | 24 + .../boot/dts/m7350-un-v3/msm9625-v2.1-mtp.dts | 24 + .../boot/dts/m7350-un-v3/msm9625-v2.1.dtsi | 40 + .../arm/boot/dts/m7350-un-v3/msm9625-v2.dtsi | 54 + .../arm/boot/dts/m7350-un-v3/msm9625.dtsi | 895 +++++++++ .../boot/dts/m7350-un-v3/msmkrypton-sim.dts | 25 + .../arm/boot/dts/m7350-un-v3/msmkrypton.dtsi | 120 ++ .../boot/dts/m7350-un-v3/msmsamarium-ion.dtsi | 31 + .../boot/dts/m7350-un-v3/msmsamarium-rumi.dts | 25 + .../boot/dts/m7350-un-v3/msmsamarium-sim.dts | 55 + .../arm/boot/dts/m7350-un-v3/msmsamarium.dtsi | 90 + .../arch/arm/boot/dts/m7350-un-v3/omap2.dtsi | 67 + .../arm/boot/dts/m7350-un-v3/omap3-beagle.dts | 20 + .../arm/boot/dts/m7350-un-v3/omap3-evm.dts | 20 + .../arch/arm/boot/dts/m7350-un-v3/omap3.dtsi | 117 ++ .../arm/boot/dts/m7350-un-v3/omap4-panda.dts | 20 + .../arm/boot/dts/m7350-un-v3/omap4-sdp.dts | 20 + .../arch/arm/boot/dts/m7350-un-v3/omap4.dtsi | 159 ++ .../boot/dts/m7350-un-v3/picoxcell-pc3x2.dtsi | 249 +++ .../boot/dts/m7350-un-v3/picoxcell-pc3x3.dtsi | 365 ++++ .../m7350-un-v3/picoxcell-pc7302-pc3x2.dts | 86 + .../m7350-un-v3/picoxcell-pc7302-pc3x3.dts | 92 + .../arm/boot/dts/m7350-un-v3/prima2-cb.dts | 424 ++++ .../boot/dts/m7350-un-v3/pxa168-aspenite.dts | 38 + .../arch/arm/boot/dts/m7350-un-v3/pxa168.dtsi | 98 + .../dts/m7350-un-v3/qpic-panel-ili-qvga.dtsi | 27 + .../arm/boot/dts/m7350-un-v3/skeleton.dtsi | 18 + .../arm/boot/dts/m7350-un-v3/skeleton64.dtsi | 18 + .../arm/boot/dts/m7350-un-v3/snowball.dts | 139 ++ .../arm/boot/dts/m7350-un-v3/spear600-evb.dts | 47 + .../arm/boot/dts/m7350-un-v3/spear600.dtsi | 174 ++ .../arm/boot/dts/m7350-un-v3/tegra-cardhu.dts | 70 + .../boot/dts/m7350-un-v3/tegra-harmony.dts | 115 ++ .../arm/boot/dts/m7350-un-v3/tegra-paz00.dts | 134 ++ .../boot/dts/m7350-un-v3/tegra-seaboard.dts | 175 ++ .../boot/dts/m7350-un-v3/tegra-trimslice.dts | 77 + .../boot/dts/m7350-un-v3/tegra-ventana.dts | 108 + .../arm/boot/dts/m7350-un-v3/tegra20.dtsi | 210 ++ .../arm/boot/dts/m7350-un-v3/tegra30.dtsi | 186 ++ .../m7350-un-v3/testcases/tests-phandle.dtsi | 39 + .../boot/dts/m7350-un-v3/testcases/tests.dtsi | 1 + .../dts/m7350-un-v3/usb_a9g20-dab-mmx.dtsi | 96 + .../arm/boot/dts/m7350-un-v3/usb_a9g20.dts | 130 ++ .../arm/boot/dts/m7350-un-v3/versatile-ab.dts | 192 ++ .../arm/boot/dts/m7350-un-v3/versatile-pb.dts | 50 + .../dts/m7350-un-v3/vexpress-v2m-rs1.dtsi | 201 ++ .../boot/dts/m7350-un-v3/vexpress-v2m.dtsi | 200 ++ .../dts/m7350-un-v3/vexpress-v2p-ca15-tc1.dts | 157 ++ .../dts/m7350-un-v3/vexpress-v2p-ca5s.dts | 162 ++ .../boot/dts/m7350-un-v3/vexpress-v2p-ca9.dts | 192 ++ .../arm/boot/dts/m7350-un-v3/zynq-ep107.dts | 52 + kernel/arch/arm/boot/dts/msm9625.dtsi | 2 +- .../dts/tr961-5200l-v2/am3517_mt_ventoux.dts | 27 + .../boot/dts/tr961-5200l-v2/apq8026-mtp.dts | 22 + .../boot/dts/tr961-5200l-v2/apq8026-xpm.dts | 22 + .../arm/boot/dts/tr961-5200l-v2/apq8026.dtsi | 24 + .../tr961-5200l-v2/apq8074-dragonboard.dtsi | 654 ++++++ .../boot/dts/tr961-5200l-v2/apq8074-v1.dtsi | 48 + .../tr961-5200l-v2/apq8074-v2-dragonboard.dts | 22 + .../dts/tr961-5200l-v2/apq8074-v2-liquid.dts | 34 + .../boot/dts/tr961-5200l-v2/apq8074-v2.dtsi | 52 + .../boot/dts/tr961-5200l-v2/apq8084-ion.dtsi | 31 + .../dts/tr961-5200l-v2/apq8084-regulator.dtsi | 377 ++++ .../boot/dts/tr961-5200l-v2/apq8084-sim.dts | 173 ++ .../dts/tr961-5200l-v2/apq8084-smp2p.dtsi | 82 + .../arm/boot/dts/tr961-5200l-v2/apq8084.dtsi | 276 +++ .../boot/dts/tr961-5200l-v2/at91sam9g20.dtsi | 238 +++ .../boot/dts/tr961-5200l-v2/at91sam9g25ek.dts | 49 + .../boot/dts/tr961-5200l-v2/at91sam9g45.dtsi | 247 +++ .../dts/tr961-5200l-v2/at91sam9m10g45ek.dts | 156 ++ .../boot/dts/tr961-5200l-v2/at91sam9x5.dtsi | 263 +++ .../boot/dts/tr961-5200l-v2/at91sam9x5cm.dtsi | 74 + .../arm/boot/dts/tr961-5200l-v2/db8500.dtsi | 274 +++ .../dsi-panel-nt35590-720p-cmd.dtsi | 530 +++++ .../dsi-panel-nt35590-720p-video.dtsi | 524 +++++ .../dsi-panel-orise-720p-video.dtsi | 60 + .../dsi-panel-sharp-qhd-video.dtsi | 67 + .../tr961-5200l-v2/dsi-panel-sim-video.dtsi | 46 + .../dsi-panel-toshiba-720p-video.dtsi | 124 ++ .../dsi-v2-panel-hx8379a-wvga-video.dtsi | 117 ++ .../dsi-v2-panel-truly-wvga-video.dtsi | 120 ++ .../dts/tr961-5200l-v2/exynos4210-origen.dts | 137 ++ .../tr961-5200l-v2/exynos4210-smdkv310.dts | 182 ++ .../boot/dts/tr961-5200l-v2/exynos4210.dtsi | 398 ++++ .../tr961-5200l-v2/exynos5250-smdk5250.dts | 26 + .../boot/dts/tr961-5200l-v2/exynos5250.dtsi | 413 ++++ .../boot/dts/tr961-5200l-v2/fsm9900-rumi.dts | 31 + .../boot/dts/tr961-5200l-v2/fsm9900-sim.dts | 32 + .../arm/boot/dts/tr961-5200l-v2/fsm9900.dtsi | 94 + .../arm/boot/dts/tr961-5200l-v2/highbank.dts | 209 ++ .../tr961-5200l-v2/imx27-phytec-phycore.dts | 76 + .../arm/boot/dts/tr961-5200l-v2/imx27.dtsi | 217 ++ .../boot/dts/tr961-5200l-v2/imx51-babbage.dts | 221 +++ .../arm/boot/dts/tr961-5200l-v2/imx51.dtsi | 246 +++ .../arm/boot/dts/tr961-5200l-v2/imx53-ard.dts | 113 ++ .../arm/boot/dts/tr961-5200l-v2/imx53-evk.dts | 119 ++ .../arm/boot/dts/tr961-5200l-v2/imx53-qsb.dts | 125 ++ .../arm/boot/dts/tr961-5200l-v2/imx53-smd.dts | 168 ++ .../arm/boot/dts/tr961-5200l-v2/imx53.dtsi | 301 +++ .../boot/dts/tr961-5200l-v2/imx6q-arm2.dts | 76 + .../dts/tr961-5200l-v2/imx6q-sabrelite.dts | 83 + .../arm/boot/dts/tr961-5200l-v2/imx6q.dtsi | 575 ++++++ .../dts/tr961-5200l-v2/kirkwood-dreamplug.dts | 24 + .../arm/boot/dts/tr961-5200l-v2/kirkwood.dtsi | 36 + .../dts/tr961-5200l-v2/mpq8092-iommu.dtsi | 40 + .../boot/dts/tr961-5200l-v2/mpq8092-ion.dtsi | 33 + .../dts/tr961-5200l-v2/mpq8092-regulator.dtsi | 324 +++ .../boot/dts/tr961-5200l-v2/mpq8092-rumi.dts | 28 + .../boot/dts/tr961-5200l-v2/mpq8092-rumi.dtsi | 134 ++ .../boot/dts/tr961-5200l-v2/mpq8092-sim.dts | 125 ++ .../arm/boot/dts/tr961-5200l-v2/mpq8092.dtsi | 240 +++ .../arm/boot/dts/tr961-5200l-v2/msm-gdsc.dtsi | 63 + .../boot/dts/tr961-5200l-v2/msm-iommu-v0.dtsi | 333 ++++ .../boot/dts/tr961-5200l-v2/msm-iommu-v1.dtsi | 514 +++++ .../msm-pm8019-rpm-regulator.dtsi | 301 +++ .../boot/dts/tr961-5200l-v2/msm-pm8019.dtsi | 415 ++++ .../msm-pm8110-rpm-regulator.dtsi | 381 ++++ .../boot/dts/tr961-5200l-v2/msm-pm8110.dtsi | 608 ++++++ .../msm-pm8226-rpm-regulator.dtsi | 492 +++++ .../boot/dts/tr961-5200l-v2/msm-pm8226.dtsi | 833 ++++++++ .../boot/dts/tr961-5200l-v2/msm-pm8841.dtsi | 242 +++ .../boot/dts/tr961-5200l-v2/msm-pm8941.dtsi | 1384 +++++++++++++ .../msm-pm8x41-rpm-regulator.dtsi | 585 ++++++ .../boot/dts/tr961-5200l-v2/msm-pma8084.dtsi | 666 +++++++ .../boot/dts/tr961-5200l-v2/msm8226-bus.dtsi | 1128 +++++++++++ .../msm8226-camera-sensor-cdp.dtsi | 108 + .../msm8226-camera-sensor-mtp.dtsi | 108 + .../msm8226-camera-sensor-qrd.dtsi | 108 + .../dts/tr961-5200l-v2/msm8226-camera.dtsi | 139 ++ .../boot/dts/tr961-5200l-v2/msm8226-cdp.dtsi | 393 ++++ .../dts/tr961-5200l-v2/msm8226-coresight.dtsi | 377 ++++ .../boot/dts/tr961-5200l-v2/msm8226-fluid.dts | 33 + .../boot/dts/tr961-5200l-v2/msm8226-gpu.dtsi | 161 ++ .../tr961-5200l-v2/msm8226-iommu-domains.dtsi | 31 + .../dts/tr961-5200l-v2/msm8226-iommu.dtsi | 237 +++ .../boot/dts/tr961-5200l-v2/msm8226-ion.dtsi | 66 + .../boot/dts/tr961-5200l-v2/msm8226-mdss.dtsi | 80 + .../boot/dts/tr961-5200l-v2/msm8226-mtp.dtsi | 445 +++++ .../boot/dts/tr961-5200l-v2/msm8226-pm.dtsi | 389 ++++ .../boot/dts/tr961-5200l-v2/msm8226-qrd.dtsi | 406 ++++ .../dts/tr961-5200l-v2/msm8226-regulator.dtsi | 460 +++++ .../boot/dts/tr961-5200l-v2/msm8226-sim.dts | 135 ++ .../dts/tr961-5200l-v2/msm8226-smp2p.dtsi | 225 +++ .../dts/tr961-5200l-v2/msm8226-v1-cdp.dts | 25 + .../dts/tr961-5200l-v2/msm8226-v1-mtp.dts | 25 + .../dts/tr961-5200l-v2/msm8226-v1-qrd.dts | 25 + .../boot/dts/tr961-5200l-v2/msm8226-v1.dtsi | 19 + .../dts/tr961-5200l-v2/msm8226-v2-cdp.dts | 25 + .../dts/tr961-5200l-v2/msm8226-v2-mtp.dts | 25 + .../dts/tr961-5200l-v2/msm8226-v2-qrd.dts | 25 + .../boot/dts/tr961-5200l-v2/msm8226-v2.dtsi | 19 + .../arm/boot/dts/tr961-5200l-v2/msm8226.dtsi | 1248 ++++++++++++ .../boot/dts/tr961-5200l-v2/msm8610-bus.dtsi | 1014 ++++++++++ .../msm8610-camera-sensor-cdp-mtp.dtsi | 116 ++ .../dts/tr961-5200l-v2/msm8610-camera.dtsi | 80 + .../boot/dts/tr961-5200l-v2/msm8610-cdp.dts | 396 ++++ .../dts/tr961-5200l-v2/msm8610-coresight.dtsi | 357 ++++ .../boot/dts/tr961-5200l-v2/msm8610-gpu.dtsi | 167 ++ .../tr961-5200l-v2/msm8610-iommu-domains.dtsi | 36 + .../boot/dts/tr961-5200l-v2/msm8610-ion.dtsi | 38 + .../boot/dts/tr961-5200l-v2/msm8610-mdss.dtsi | 37 + .../boot/dts/tr961-5200l-v2/msm8610-mtp.dts | 354 ++++ .../boot/dts/tr961-5200l-v2/msm8610-pm.dtsi | 391 ++++ .../boot/dts/tr961-5200l-v2/msm8610-qrd.dts | 267 +++ .../dts/tr961-5200l-v2/msm8610-regulator.dtsi | 358 ++++ .../boot/dts/tr961-5200l-v2/msm8610-rumi.dts | 31 + .../boot/dts/tr961-5200l-v2/msm8610-sim.dts | 72 + .../dts/tr961-5200l-v2/msm8610-smp2p.dtsi | 225 +++ .../arm/boot/dts/tr961-5200l-v2/msm8610.dtsi | 1075 ++++++++++ .../boot/dts/tr961-5200l-v2/msm8660-surf.dts | 24 + .../boot/dts/tr961-5200l-v2/msm8926-cdp.dts | 22 + .../boot/dts/tr961-5200l-v2/msm8926-mtp.dts | 22 + .../boot/dts/tr961-5200l-v2/msm8926-qrd.dts | 21 + .../arm/boot/dts/tr961-5200l-v2/msm8926.dtsi | 30 + .../boot/dts/tr961-5200l-v2/msm8974-bus.dtsi | 1411 +++++++++++++ .../msm8974-camera-sensor-cdp.dtsi | 189 ++ .../msm8974-camera-sensor-dragonboard.dtsi | 174 ++ .../msm8974-camera-sensor-fluid.dtsi | 190 ++ .../msm8974-camera-sensor-liquid.dtsi | 190 ++ .../msm8974-camera-sensor-mtp.dtsi | 191 ++ .../dts/tr961-5200l-v2/msm8974-camera.dtsi | 215 ++ .../boot/dts/tr961-5200l-v2/msm8974-cdp.dtsi | 729 +++++++ .../dts/tr961-5200l-v2/msm8974-clock.dtsi | 27 + .../dts/tr961-5200l-v2/msm8974-coresight.dtsi | 381 ++++ .../dts/tr961-5200l-v2/msm8974-fluid.dtsi | 667 +++++++ .../boot/dts/tr961-5200l-v2/msm8974-gpu.dtsi | 185 ++ .../boot/dts/tr961-5200l-v2/msm8974-ion.dtsi | 59 + .../boot/dts/tr961-5200l-v2/msm8974-leds.dtsi | 129 ++ .../dts/tr961-5200l-v2/msm8974-liquid.dtsi | 893 +++++++++ .../boot/dts/tr961-5200l-v2/msm8974-mdss.dtsi | 148 ++ .../boot/dts/tr961-5200l-v2/msm8974-mtp.dtsi | 705 +++++++ .../dts/tr961-5200l-v2/msm8974-regulator.dtsi | 568 ++++++ .../boot/dts/tr961-5200l-v2/msm8974-rumi.dtsi | 146 ++ .../boot/dts/tr961-5200l-v2/msm8974-sim.dtsi | 93 + .../dts/tr961-5200l-v2/msm8974-smp2p.dtsi | 225 +++ .../dts/tr961-5200l-v2/msm8974-v1-cdp.dts | 33 + .../dts/tr961-5200l-v2/msm8974-v1-fluid.dts | 33 + .../msm8974-v1-iommu-domains.dtsi | 31 + .../dts/tr961-5200l-v2/msm8974-v1-iommu.dtsi | 40 + .../dts/tr961-5200l-v2/msm8974-v1-liquid.dts | 24 + .../dts/tr961-5200l-v2/msm8974-v1-mtp.dts | 28 + .../dts/tr961-5200l-v2/msm8974-v1-pm.dtsi | 456 +++++ .../dts/tr961-5200l-v2/msm8974-v1-rumi.dts | 24 + .../dts/tr961-5200l-v2/msm8974-v1-sim.dts | 24 + .../boot/dts/tr961-5200l-v2/msm8974-v1.dtsi | 134 ++ .../dts/tr961-5200l-v2/msm8974-v2-cdp.dts | 36 + .../dts/tr961-5200l-v2/msm8974-v2-fluid.dts | 36 + .../msm8974-v2-iommu-domains.dtsi | 45 + .../dts/tr961-5200l-v2/msm8974-v2-iommu.dtsi | 256 +++ .../dts/tr961-5200l-v2/msm8974-v2-liquid.dts | 36 + .../dts/tr961-5200l-v2/msm8974-v2-mtp.dts | 40 + .../dts/tr961-5200l-v2/msm8974-v2-pm.dtsi | 452 +++++ .../boot/dts/tr961-5200l-v2/msm8974-v2.dtsi | 138 ++ .../arm/boot/dts/tr961-5200l-v2/msm8974.dtsi | 1745 +++++++++++++++++ .../boot/dts/tr961-5200l-v2/msm9625-cdp.dtsi | 100 + .../dts/tr961-5200l-v2/msm9625-coresight.dtsi | 259 +++ .../dts/tr961-5200l-v2/msm9625-display.dtsi | 20 + .../boot/dts/tr961-5200l-v2/msm9625-ion.dtsi | 35 + .../boot/dts/tr961-5200l-v2/msm9625-mtp.dtsi | 138 ++ .../boot/dts/tr961-5200l-v2/msm9625-pm.dtsi | 299 +++ .../dts/tr961-5200l-v2/msm9625-regulator.dtsi | 284 +++ .../dts/tr961-5200l-v2/msm9625-smp2p.dtsi | 142 ++ .../dts/tr961-5200l-v2/msm9625-v1-cdp.dts | 24 + .../dts/tr961-5200l-v2/msm9625-v1-mtp.dts | 24 + .../dts/tr961-5200l-v2/msm9625-v1-rumi.dts | 26 + .../boot/dts/tr961-5200l-v2/msm9625-v1.dtsi | 67 + .../dts/tr961-5200l-v2/msm9625-v2-cdp.dts | 24 + .../dts/tr961-5200l-v2/msm9625-v2-mtp.dts | 122 ++ .../dts/tr961-5200l-v2/msm9625-v2.1-cdp.dts | 24 + .../dts/tr961-5200l-v2/msm9625-v2.1-mtp.dts | 24 + .../boot/dts/tr961-5200l-v2/msm9625-v2.1.dtsi | 41 + .../boot/dts/tr961-5200l-v2/msm9625-v2.dtsi | 54 + .../arm/boot/dts/tr961-5200l-v2/msm9625.dtsi | 864 ++++++++ .../dts/tr961-5200l-v2/msmkrypton-sim.dts | 25 + .../boot/dts/tr961-5200l-v2/msmkrypton.dtsi | 120 ++ .../dts/tr961-5200l-v2/msmsamarium-ion.dtsi | 31 + .../dts/tr961-5200l-v2/msmsamarium-rumi.dts | 25 + .../dts/tr961-5200l-v2/msmsamarium-sim.dts | 55 + .../boot/dts/tr961-5200l-v2/msmsamarium.dtsi | 90 + .../arm/boot/dts/tr961-5200l-v2/omap2.dtsi | 67 + .../boot/dts/tr961-5200l-v2/omap3-beagle.dts | 20 + .../arm/boot/dts/tr961-5200l-v2/omap3-evm.dts | 20 + .../arm/boot/dts/tr961-5200l-v2/omap3.dtsi | 117 ++ .../boot/dts/tr961-5200l-v2/omap4-panda.dts | 20 + .../arm/boot/dts/tr961-5200l-v2/omap4-sdp.dts | 20 + .../arm/boot/dts/tr961-5200l-v2/omap4.dtsi | 159 ++ .../dts/tr961-5200l-v2/picoxcell-pc3x2.dtsi | 249 +++ .../dts/tr961-5200l-v2/picoxcell-pc3x3.dtsi | 365 ++++ .../tr961-5200l-v2/picoxcell-pc7302-pc3x2.dts | 86 + .../tr961-5200l-v2/picoxcell-pc7302-pc3x3.dts | 92 + .../arm/boot/dts/tr961-5200l-v2/prima2-cb.dts | 424 ++++ .../dts/tr961-5200l-v2/pxa168-aspenite.dts | 38 + .../arm/boot/dts/tr961-5200l-v2/pxa168.dtsi | 98 + .../tr961-5200l-v2/qpic-panel-ili-qvga.dtsi | 27 + .../arm/boot/dts/tr961-5200l-v2/skeleton.dtsi | 18 + .../boot/dts/tr961-5200l-v2/skeleton64.dtsi | 18 + .../arm/boot/dts/tr961-5200l-v2/snowball.dts | 139 ++ .../boot/dts/tr961-5200l-v2/spear600-evb.dts | 47 + .../arm/boot/dts/tr961-5200l-v2/spear600.dtsi | 174 ++ .../boot/dts/tr961-5200l-v2/tegra-cardhu.dts | 70 + .../boot/dts/tr961-5200l-v2/tegra-harmony.dts | 115 ++ .../boot/dts/tr961-5200l-v2/tegra-paz00.dts | 134 ++ .../dts/tr961-5200l-v2/tegra-seaboard.dts | 175 ++ .../dts/tr961-5200l-v2/tegra-trimslice.dts | 77 + .../boot/dts/tr961-5200l-v2/tegra-ventana.dts | 108 + .../arm/boot/dts/tr961-5200l-v2/tegra20.dtsi | 210 ++ .../arm/boot/dts/tr961-5200l-v2/tegra30.dtsi | 186 ++ .../testcases/tests-phandle.dtsi | 39 + .../dts/tr961-5200l-v2/testcases/tests.dtsi | 1 + .../dts/tr961-5200l-v2/usb_a9g20-dab-mmx.dtsi | 96 + .../arm/boot/dts/tr961-5200l-v2/usb_a9g20.dts | 130 ++ .../boot/dts/tr961-5200l-v2/versatile-ab.dts | 192 ++ .../boot/dts/tr961-5200l-v2/versatile-pb.dts | 50 + .../dts/tr961-5200l-v2/vexpress-v2m-rs1.dtsi | 201 ++ .../boot/dts/tr961-5200l-v2/vexpress-v2m.dtsi | 200 ++ .../tr961-5200l-v2/vexpress-v2p-ca15-tc1.dts | 157 ++ .../dts/tr961-5200l-v2/vexpress-v2p-ca5s.dts | 162 ++ .../dts/tr961-5200l-v2/vexpress-v2p-ca9.dts | 192 ++ .../boot/dts/tr961-5200l-v2/zynq-ep107.dts | 52 + ...-un-v2_defconfig => m7350-un-v1_defconfig} | 2 +- .../arm/configs/m7350-un-v3-perf_defconfig | 339 ++++ kernel/arch/arm/configs/m7350-un-v3_defconfig | 351 ++++ kernel/arch/arm/configs/msm9625_defconfig | 2 +- ...r961-2500l-mobile-unicom-v1-perf_defconfig | 1 + .../tr961-2500l-mobile-unicom-v1_defconfig | 1 + .../arm/configs/tr961-5200l-v2-perf_defconfig | 344 ++++ .../arch/arm/configs/tr961-5200l-v2_defconfig | 356 ++++ kernel/arch/arm/mach-msm/Kconfig | 8 + kernel/arch/arm/mach-msm/Makefile | 8 + .../arm/mach-msm/board-m7350-un-v3-gpiomux.c | 381 ++++ .../mach-msm/board-tr961-5200l-v2-gpiomux.c | 354 ++++ kernel/arch/arm/mach-msm/gpiomux.c | 34 + kernel/arch/microblaze/boot/dts/system.dts | 368 +--- kernel/drivers/mtd/devices/Kconfig | 4 + kernel/drivers/mtd/devices/msm_qpic_nand.c | 22 +- kernel/drivers/mtd/nand/nand_ids.c | 7 + kernel/drivers/usb/core/driver.c | 16 +- kernel/drivers/usb/host/ehci-msm-hsic.c | 74 +- kernel/drivers/usb/host/hbm.c | 22 +- kernel/include/linux/mtd/nand.h | 10 + oe-core/bitbake/lib/bb/COW.pyc | Bin 9954 -> 9867 bytes oe-core/bitbake/lib/bb/__init__.pyc | Bin 6733 -> 6679 bytes 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kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4-panda.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4-sdp.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc3x2.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc3x3.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc7302-pc3x2.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc7302-pc3x3.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/prima2-cb.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/pxa168-aspenite.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/pxa168.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/qpic-panel-ili-qvga.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/skeleton.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/skeleton64.dtsi create mode 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100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/usb_a9g20-dab-mmx.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/usb_a9g20.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/versatile-ab.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/versatile-pb.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2m-rs1.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2m.dtsi create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca15-tc1.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca5s.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca9.dts create mode 100644 kernel/arch/arm/boot/dts/tr961-5200l-v2/zynq-ep107.dts rename kernel/arch/arm/configs/{m7350-un-v2_defconfig => m7350-un-v1_defconfig} (99%) mode change 100755 => 100644 create mode 100755 kernel/arch/arm/configs/m7350-un-v3-perf_defconfig create mode 100755 kernel/arch/arm/configs/m7350-un-v3_defconfig mode change 100644 => 100755 kernel/arch/arm/configs/msm9625_defconfig create mode 100644 kernel/arch/arm/configs/tr961-5200l-v2-perf_defconfig create mode 100644 kernel/arch/arm/configs/tr961-5200l-v2_defconfig create mode 100755 kernel/arch/arm/mach-msm/board-m7350-un-v3-gpiomux.c create mode 100755 kernel/arch/arm/mach-msm/board-tr961-5200l-v2-gpiomux.c mode change 100644 => 120000 kernel/arch/microblaze/boot/dts/system.dts create mode 100644 oe-core/build/downloads/tp-domain.bb create mode 100644 oe-core/build/downloads/tp-domain.bb.done mode change 100644 => 100755 oe-core/meta-msm/recipes/hostap-daemon/hostap-daemon-ath6kl_git.bb diff --git a/external/compat-wireless/drivers/net/wireless/ath/ath6kl/txrx.c b/external/compat-wireless/drivers/net/wireless/ath/ath6kl/txrx.c index 86b6a6409..0ffee9f5b 100644 --- a/external/compat-wireless/drivers/net/wireless/ath/ath6kl/txrx.c +++ b/external/compat-wireless/drivers/net/wireless/ath/ath6kl/txrx.c @@ -1030,8 +1030,10 @@ int ath6kl_send_msg_ipa(struct ath6kl_vif *vif, enum ipa_wlan_event type, "IPA-CM: AP mode Adding Partial hdr: %s, %pM\n", vif->ndev->name, vif->ndev->dev_addr); /* Add partial header with IPA for this interface */ - ath6kl_ipa_add_header_info(vif->ar, 1, vif->fw_vif_idx, - vif->ndev->name, vif->ndev->dev_addr); + if (!(test_bit(CONNECTED, &vif->flags))) { + ath6kl_ipa_add_header_info(vif->ar, 1, vif->fw_vif_idx, + vif->ndev->name, vif->ndev->dev_addr); + } break; case WLAN_AP_DISCONNECT: diff --git a/external/compat-wireless/drivers/net/wireless/ath/ath6kl/usb.c b/external/compat-wireless/drivers/net/wireless/ath/ath6kl/usb.c index e67b04492..c1fc0a7be 100644 --- a/external/compat-wireless/drivers/net/wireless/ath/ath6kl/usb.c +++ b/external/compat-wireless/drivers/net/wireless/ath/ath6kl/usb.c @@ -1182,6 +1182,25 @@ static void ath6kl_usb_flush_all(struct ath6kl_usb *ar_usb) #endif } +static void ath6kl_usb_suspend_flush_all(struct ath6kl_usb *ar_usb) +{ + int i; + struct ath6kl_usb_pipe *pipe; + + for (i = 0; i < ATH6KL_USB_PIPE_MAX; i++) { + pipe = &ar_usb->pipes[i].ar_usb->pipes[i]; + if (!pipe->ar_usb) + continue; + flush_work(&pipe->tx_io_complete_work); + flush_work(&pipe->rx_io_complete_work); + usb_kill_anchored_urbs(&pipe->urb_submitted); + + } +#ifdef CONFIG_ATH6KL_AUTO_PM + flush_work(&ar_usb->pm_resume_work); +#endif +} + static void ath6kl_usb_start_recv_pipes(struct ath6kl_usb *ar_usb) { /* @@ -1421,6 +1440,7 @@ static void ath6kl_usb_destroy(struct ath6kl_usb *ar_usb) ath6kl_usb_flush_all(ar_usb); #ifdef CONFIG_ATH6KL_AUTO_PM + spin_lock_bh(&ar_usb->pm_lock); while (!list_empty(&ar_usb->pm_q)) { struct ath6kl_urb_context *urb_context; @@ -1430,6 +1450,7 @@ static void ath6kl_usb_destroy(struct ath6kl_usb *ar_usb) list_del(&urb_context->link); ath6kl_usb_cleanup_urb_context(urb_context); } + spin_unlock_bh(&ar_usb->pm_lock); #endif ath6kl_usb_cleanup_pipe_resources(ar_usb); @@ -2463,7 +2484,7 @@ end: return ret; } - ath6kl_usb_flush_all(ar_usb); + ath6kl_usb_suspend_flush_all(ar_usb); #ifdef CONFIG_ATH6KL_AUTO_PM atomic_set(&ar_usb->autopm_state, ATH6KL_USB_AUTOPM_STATE_SUSPENDED); diff --git a/external/hostap/hostapd/Makefile b/external/hostap/hostapd/Makefile old mode 100644 new mode 100755 index a3720bd57..ce6027b09 --- a/external/hostap/hostapd/Makefile +++ b/external/hostap/hostapd/Makefile @@ -862,14 +862,42 @@ verify_config: fi install: all +ifndef CONFIG_TP_WLAN_MODULE_BCM mkdir -p $(DESTDIR)/usr/bin for i in $(ALL); do cp -f $$i $(DESTDIR)/usr/bin/$$i; done +endif mkdir -p $(DESTDIR)/etc ifdef CONFIG_DRIVER_AR6000 install -m 0644 config/ar6k-ap-all.conf $(DESTDIR)/etc/AR6003_hostapd.conf install -m 0644 config/ar6k-ap1-all.conf $(DESTDIR)/etc/AR6003_AP1_hostapd.conf endif + +ifdef CONFIG_TP_WLAN_MODULE_BCM + +ifdef CONFIG_WIRELESS_ACL_TYPE_BLACK + #[liyuan start] M7350 series enable acl deny list in default + install -m 0644 -d $(DESTDIR)/etc/config + install -m 0644 config/tp-bcm-ap-all-7350-series.conf $(DESTDIR)/etc/AR6004_hostapd.conf + install -m 0644 config/tp-bcm-ap-all-7350-series.deny $(DESTDIR)/etc/config/hostapd.deny + ln -s /etc/AR6004_hostapd.conf $(DESTDIR)/etc/hostapd.conf + + install -m 0644 -d $(DESTDIR)/etc/default_config + install -m 0644 config/tp-bcm-ap-all-7350-series.conf $(DESTDIR)/etc/default_config/AR6004_hostapd.conf + install -m 0644 config/tp-bcm-ap-all-7350-series.deny $(DESTDIR)/etc/default_config/hostapd.deny + #[liyuan end] +else + #[lixiangkui start] install wifi default config + install -m 0644 config/tp-bcm-ap-all.conf $(DESTDIR)/etc/AR6004_hostapd.conf + ln -s /etc/AR6004_hostapd.conf $(DESTDIR)/etc/hostapd.conf + + install -m 0644 -d $(DESTDIR)/etc/default_config + install -m 0644 config/tp-bcm-ap-all.conf $(DESTDIR)/etc/default_config/AR6004_hostapd.conf + #[lixiangkui end] +endif + +else + ifdef CONFIG_DRIVER_NL80211 ifdef CONFIG_WIRELESS_ACL_TYPE_BLACK #[liyuan start] M7350 series enable acl deny list in default @@ -896,6 +924,8 @@ else endif endif +endif + ../src/drivers/build.hostapd: @if [ -f ../src/drivers/build.wpa_supplicant ]; then \ $(MAKE) -C ../src/wps clean; \ diff --git a/external/hostap/hostapd/config/tp-ath6kl-ap-all.conf b/external/hostap/hostapd/config/tp-ath6kl-ap-all.conf index 3e12fc6c6..ec60fd246 100644 --- a/external/hostap/hostapd/config/tp-ath6kl-ap-all.conf +++ b/external/hostap/hostapd/config/tp-ath6kl-ap-all.conf @@ -10,4 +10,4 @@ ignore_broadcast_ssid=0 ieee80211n=1 ht_capab=[HT40-][SHORT-GI-20][SHORT-GI-40] require_ht=0 -max_num_sta=15 \ No newline at end of file +max_num_sta=15 diff --git a/external/hostap/hostapd/config/tp-bcm-ap-all-7350-series.conf b/external/hostap/hostapd/config/tp-bcm-ap-all-7350-series.conf new file mode 100644 index 000000000..25bb50212 --- /dev/null +++ b/external/hostap/hostapd/config/tp-bcm-ap-all-7350-series.conf @@ -0,0 +1,15 @@ +interface=wlan0 +bridge=br0 +driver=nl80211 +ctrl_interface=/var/run/hostapd +wmode=2 +channel=0 +auto_chan_select=2 +auth_algs=1 +ignore_broadcast_ssid=0 +ieee80211n=1 +ht_capab=[HT40-][SHORT-GI-20][SHORT-GI-40] +require_ht=0 +max_num_sta=15 +macaddr_acl=3 +deny_mac_file=/etc/config/hostapd.deny diff --git a/external/hostap/hostapd/config/tp-bcm-ap-all-7350-series.deny b/external/hostap/hostapd/config/tp-bcm-ap-all-7350-series.deny new file mode 100644 index 000000000..e69de29bb diff --git a/external/hostap/hostapd/config/tp-bcm-ap-all.conf b/external/hostap/hostapd/config/tp-bcm-ap-all.conf new file mode 100644 index 000000000..7903c70ec --- /dev/null +++ b/external/hostap/hostapd/config/tp-bcm-ap-all.conf @@ -0,0 +1,13 @@ +interface=wlan0 +bridge=br0 +driver=nl80211 +ctrl_interface=/var/run/hostapd +wmode=2 +channel=0 +auto_chan_select=2 +auth_algs=1 +ignore_broadcast_ssid=0 +ieee80211n=1 +ht_capab=[HT40-][SHORT-GI-20][SHORT-GI-40] +require_ht=0 +max_num_sta=15 diff --git a/external/hostap/src/ap/ieee802_11_ht.c b/external/hostap/src/ap/ieee802_11_ht.c index ce9117540..f094e9814 100644 --- a/external/hostap/src/ap/ieee802_11_ht.c +++ b/external/hostap/src/ap/ieee802_11_ht.c @@ -308,6 +308,8 @@ static int is_40_allowed(struct hostapd_iface *iface, int channel) void ap_ht2040_timeout(void *eloop_data, void *user_data) { +//[lixiangkui 20150417] Fix Bug#74496, don't switch to 40MHz +#if 0 struct hostapd_data *hapd = eloop_data; wpa_printf(MSG_INFO, "Switching to 40MHz operation"); @@ -316,7 +318,9 @@ void ap_ht2040_timeout(void *eloop_data, void *user_data) HT_OPMODE_SWITCH_TO_40); hapd->ht_40 = TRUE; hapd->iconf->secondary_channel = hapd->secondary_ch; - +#else + wpa_printf(MSG_INFO, "Don't switching to 40MHz!"); +#endif } void hostapd_2040_coex_action(struct hostapd_data *hapd, const struct ieee80211_mgmt *mgmt, size_t len) diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/am3517_mt_ventoux.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/am3517_mt_ventoux.dts new file mode 100644 index 000000000..5eb26d7d9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/am3517_mt_ventoux.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011 Ilya Yanok, EmCraft Systems + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TeeJet Mt.Ventoux"; + compatible = "teejet,mt_ventoux", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* AM35xx doesn't have IVA */ + soc { + iva { + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026-mtp.dts new file mode 100644 index 000000000..e14a68568 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/include/ "apq8026.dtsi" +/include/ "msm8226-mtp.dtsi" + +/ { + model = "Qualcomm APQ 8026 MTP"; + compatible = "qcom,apq8026-mtp", "qcom,apq8026", "qcom,mtp"; + qcom,msm-id = <199 8 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026-xpm.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026-xpm.dts new file mode 100644 index 000000000..67152af2d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026-xpm.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/include/ "apq8026.dtsi" +/include/ "msm8226-cdp.dtsi" + +/ { + model = "Qualcomm APQ 8026 XPM"; + compatible = "qcom,apq8026-xpm", "qcom,apq8026", "qcom,xpm"; + qcom,msm-id = <199 14 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026.dtsi new file mode 100644 index 000000000..db6576a0d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8026.dtsi @@ -0,0 +1,24 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Only 8026-specific property overrides should be placed inside this + * file. Device definitions should be placed inside the msm8226.dtsi + * file. + */ + +/include/ "msm8226.dtsi" + +/ { + model = "Qualcomm APQ 8026"; + compatible = "qcom,apq8026"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-dragonboard.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-dragonboard.dtsi new file mode 100644 index 000000000..6b4d1d339 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-dragonboard.dtsi @@ -0,0 +1,654 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-sharp-qhd-video.dtsi" +/include/ "msm8974-camera-sensor-dragonboard.dtsi" +/include/ "msm8974-leds.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_dsi_sharp_qhd_video { + status = "ok"; + }; + + qcom,hdmi_tx@fd922100 { + status = "ok"; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + general { + label = "general"; + gpios = <&pm8941_gpios 23 0x1>; + linux,input-type = <1>; + linux,code = <102>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + bt_ar3002 { + compatible = "qca,ar3002"; + qca,bt-reset-gpio = <&pm8941_gpios 34 0>; + }; + + hsic_hub { + compatible = "qcom,hsic-smsc-hub"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + smsc,reset-gpio = <&pm8941_gpios 8 0x00>; + + hsic_host: hsic@f9a00000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a00000 0x400>; + #address-cells = <0>; + interrupt-parent = <&hsic_host>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 136 0 + 1 &intc 0 148 0 + 2 &msmgpio 144 0x8>; + interrupt-names = "core_irq", "async_irq", "wakeup"; + HSIC_VDDCX-supply = <&pm8841_s2>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + hsic,strobe-gpio = <&msmgpio 144 0x00>; + hsic,data-gpio = <&msmgpio 145 0x00>; + hsic,ignore-cal-pad-config; + hsic,strobe-pad-offset = <0x2050>; + hsic,data-pad-offset = <0x2054>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>; + }; + }; + + i2c@f9923000 { + status = "ok"; + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l18>; + vcc_i2c-supply = <&pm8941_s3>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 566 1067>; + atmel,display-coords = <0 0 540 960>; + atmel,i2c-pull-up; + atmel,cfg_1 { + atmel,family-id = <0x81>; + atmel,variant-id = <0x19>; + atmel,version = <0x10>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 38, Instance = 0 */ + 0F 02 00 17 04 0C 00 00 + /* Object 7, Instance = 0 */ + 30 FF 19 + /* Object 8, Instance = 0 */ + 1B 00 05 01 00 00 08 08 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 13 0B 00 10 23 01 03 + 0A 0F 01 0B 04 05 28 0A 2B 04 + 36 02 00 00 00 00 8F 28 8F 50 + 12 0F 32 32 02 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 + /* Object 23, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 00 00 00 00 + /* Object 42, Instance = 0 */ + 00 00 00 00 00 00 00 00 + /* Object 46, Instance = 0 */ + 00 03 10 30 00 00 01 00 00 + /* Object 47, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + /* Object 48, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <540>; + qcom,disp-maxy = <960>; + qcom,panel-maxx = <566>; + qcom,panel-maxy = <1067>; + qcom,key-codes = <158 139 102 217>; + }; + + sound { + qcom,model = "apq8074-taiko-db-snd-card"; + qcom,hdmi-audio-rx; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "AMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic4", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic6", + "AMIC6", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic7", + "DMIC1", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic1", + "DMIC2", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic2", + "DMIC3", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4", + "DMIC5", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic5", + "DMIC6", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic6"; + }; + + qcom,pronto@fb21b000 { + status = "disabled"; + }; + + qcom,iris-fm { + status = "disabled"; + }; + + qcom,wcnss-wlan@fb000000 { + status = "disabled"; + }; + + qcom,smd-wcnss { + status = "disabled"; + }; + + qcom,smsm-wcnss { + status = "disabled"; + }; +}; + +&mdss_fb0 { + qcom,memory-reservation-size = <0x1000000>; /* size 16MB */ +}; + +&sdcc3 { + qcom,sup-voltages = <2000 2000>; + status = "ok"; +}; + +&pm8941_l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + regulator-always-on; +}; + +&pm8941_l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + regulator-always-on; +}; + +&uart7 { + status = "ok"; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; +}; + +&usb_otg { + status = "ok"; + qcom,hsusb-otg-otg-control = <2>; + qcom,hsusb-otg-mode = <3>; + vbus_otg-supply = <&pm8941_mvs1>; + qcom,usb2-enable-hsphy2; + qcom,dp-manual-pullup; + + #address-cells = <0>; + interrupt-parent = <&usb_otg>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 134 0 + 1 &intc 0 140 0 + 2 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "core_irq", "async_irq", "pmic_id_irq"; +}; + +&usb3 { + qcom,charging-disabled; + vbus_dwc3-supply = <0>; + dwc3@f9200000 { + host-only-mode; + }; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias2-ext-cap; + qcom,cdc-micbias3-ext-cap; + }; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c500 { /* GPIO 6 */ + /* TUSB3_HUB-RESET */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <0>; /* QPNP_PIN_PULL_30 */ + qcom,vin-sel = <0>; /* QPNP_PIN_VIN0 VPH */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; /* Keep it out of reset */ + qcom,master-en = <1>; + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + /* HSIC_HUB-RESET */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,pull = <5>; /* PULL_NO */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,master-en = <1>; + }; + + gpio@c800 { /* GPIO 9 */ + /* GbE_RST_N */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <0>; /* QPNP_PIN_PULL_30 */ + qcom,vin-sel = <0>; /* QPNP_PIN_VIN0 VPH */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; /* Keep it out of reset */ + qcom,master-en = <1>; + }; + + gpio@c900 { /* GPIO 10 */ + /* SATA_RST_N */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <0>; /* QPNP_PIN_PULL_30 */ + qcom,vin-sel = <0>; /* QPNP_PIN_VIN0 VPH */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; /* Keep it out of reset */ + qcom,master-en = <1>; + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; + + gpio@d600 { /* GPIO 23 */ + }; + + gpio@d700 { /* GPIO 24 */ + }; + + gpio@d800 { /* GPIO 25 */ + }; + + gpio@d900 { /* GPIO 26 */ + }; + + gpio@da00 { /* GPIO 27 */ + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,pull = <0>; /* set to default pull */ + qcom,master-en = <1>; + qcom,vin-sel = <2>; /* select 1.8 V source */ + }; + + gpio@dd00 { /* GPIO 30 */ + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + }; + + gpio@e000 { /* GPIO 33 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; + qcom,master-en = <1>; + }; + + gpio@e100 { /* GPIO 34 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <0>; + qcom,master-en = <1>; + }; + + gpio@e200 { /* GPIO 35 */ + }; + + gpio@e300 { /* GPIO 36 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <3>; /* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */ + qcom,master-en = <1>; + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3*/ + }; + + mpp@a300 { /* MPP 4*/ + }; +}; + +&spi_epm { + epm-adc@0 { + compatible = "cy,epm-adc-cy8c5568lti-114"; + reg = <0>; + interrupt-parent = <&msmgpio>; + spi-max-frequency = <960000>; + qcom,channels = <31>; + qcom,gain = <50 50 50 50 50 100 50 50 50 50 + 50 50 50 50 100 50 50 50 50 100 + 50 50 50 100 50 50 50 1 1 1 + 1>; + qcom,rsense = <40 10 10 25 10 1000 75 25 10 25 + 33 500 200 10 500 100 33 200 25 100 + 75 500 50 200 5 5 3 1 1 1 + 1>; + qcom,channel-type = <0xf0000000>; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d000 { + qcom,rgb_2 { + status = "ok"; + qcom,default-state = "on"; + qcom,turn-off-delay-ms = <1000>; + }; + }; + + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <20>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <1>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + }; +}; + +&pm8941_chg { + status = "ok"; + + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v1.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v1.dtsi new file mode 100644 index 000000000..c4e7b7c3c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v1.dtsi @@ -0,0 +1,48 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8974.dtsi file. + */ + +/include/ "msm8974-v1.dtsi" + +&soc { + qcom,qseecom@a700000 { + compatible = "qcom,qseecom"; + reg = <0x0a700000 0x500000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <1>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; +}; + +&memory_hole { + qcom,memblock-remove = <0x0a700000 0x5800000>; /* Address and size of the hole */ +}; + +&qseecom { + status = "disabled"; +}; + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2-dragonboard.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2-dragonboard.dts new file mode 100644 index 000000000..5a6f5f3bf --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2-dragonboard.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "apq8074-v2.dtsi" +/include/ "apq8074-dragonboard.dtsi" + +/ { + model = "Qualcomm APQ 8074v2 DRAGONBOARD"; + compatible = "qcom,apq8074-dragonboard", "qcom,apq8074", "qcom,dragonboard"; + qcom,msm-id = <184 10 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2-liquid.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2-liquid.dts new file mode 100644 index 000000000..4ec1cdd17 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2-liquid.dts @@ -0,0 +1,34 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "apq8074-v2.dtsi" +/include/ "msm8974-liquid.dtsi" + +/ { + model = "Qualcomm APQ 8074v2 LIQUID"; + compatible = "qcom,apq8074-liquid", "qcom,apq8074", "qcom,liquid"; + qcom,msm-id = <184 9 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2.dtsi new file mode 100644 index 000000000..76eb14b96 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8074-v2.dtsi @@ -0,0 +1,52 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8974.dtsi file. + */ + +/include/ "msm8974-v2.dtsi" + +&soc { + qcom,qseecom@a700000 { + compatible = "qcom,qseecom"; + reg = <0x0a700000 0x500000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <1>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; + + sound { + compatible = "qcom,apq8074-audio-taiko"; + }; +}; + +&memory_hole { + qcom,memblock-remove = <0x0a700000 0x5800000>; /* Address and size of the hole */ +}; + +&qseecom { + status = "disabled"; +}; + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-ion.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-ion.dtsi new file mode 100644 index 000000000..ea954b89c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-ion.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-regulator.dtsi new file mode 100644 index 000000000..998b46906 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-regulator.dtsi @@ -0,0 +1,377 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* QPNP controlled regulators: */ + +&spmi_bus { + qcom,pma8084@1 { + pma8084_s1: regulator@1400 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + /* PMA8084 S2 + S12 = 2 phase VDD_CX supply */ + pma8084_s2: regulator@1700 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s3: regulator@1a00 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s4: regulator@1d00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s5: regulator@2000 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + /* PMA8084 S6 + S7 = 2 phase VDD_GFX supply */ + pma8084_s6: regulator@2300 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + /* PMA8084 S8 + S9 + S10 + S11 = 4 phase VDD_APC supply */ + pma8084_s8: regulator@2900 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + /* Output of PMA8084 L1 and L11 is tied together. */ + pma8084_l1: regulator@4000 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <10000>; + status = "okay"; + }; + + pma8084_l2: regulator@4100 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l3: regulator@4200 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l4: regulator@4300 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l6: regulator@4500 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l8: regulator@4700 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l9: regulator@4800 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l10: regulator@4900 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l12: regulator@4b00 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l13: regulator@4c00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l14: regulator@4d00 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l15: regulator@4e00 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l16: regulator@4f00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l17: regulator@5000 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l18: regulator@5100 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l19: regulator@5200 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l20: regulator@5300 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l21: regulator@5400 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l22: regulator@5500 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l23: regulator@5600 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l24: regulator@5700 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l25: regulator@5800 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l26: regulator@5900 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l27: regulator@5a00 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs1: regulator@8000 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs2: regulator@8100 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs3: regulator@8200 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs4: regulator@8300 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_mvs1: regulator@8400 { + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + }; +}; + +&rpm_bus { + rpm-regulator-smpb1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + + pma8084_s1_ao: regulator-s1-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8084_s1_ao"; + qcom,set = <1>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + }; + + rpm-regulator-smpb2 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + + pma8084_s2_corner_ao: regulator-s2-corner-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8084_s2_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + + pma8084_l12_ao: regulator-l12-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8084_l12_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-sim.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-sim.dts new file mode 100644 index 000000000..e206d4dd0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-sim.dts @@ -0,0 +1,173 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "apq8084.dtsi" + +/ { + model = "Qualcomm APQ 8084 Simulator"; + compatible = "qcom,apq8084-sim", "qcom,apq8084", "qcom,sim"; + qcom,msm-id = <178 0 0>; + + aliases { + serial0 = &uart0; + }; +}; + +&soc { + uart0: serial@f991f000 { + status = "ok"; + }; +}; + +&sdcc1 { + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdcc2 { + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + qcom,vdd-io-lpm-sup; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + status = "ok"; +}; + +&pma8084_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + }; + + gpio@cf00 { /* GPIO 16 */ + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; +}; + +&pma8084_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&usb3 { + qcom,skip-charger-detection; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-smp2p.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-smp2p.dtsi new file mode 100644 index 000000000..b1d21ffd7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084-smp2p.dtsi @@ -0,0 +1,82 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084.dtsi new file mode 100644 index 000000000..b39f5690a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/apq8084.dtsi @@ -0,0 +1,276 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton64.dtsi" + +/ { + model = "Qualcomm APQ 8084"; + compatible = "qcom,apq8084"; + interrupt-parent = <&intc>; + soc: soc { }; +}; + +/include/ "apq8084-ion.dtsi" +/include/ "apq8084-smp2p.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <146>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + qcom,cache_erp { + compatible = "qcom,cache_erp"; + interrupts = <1 9 0>, <0 2 0>; + interrupt-names = "l1_irq", "l2_irq"; + }; + + qcom,cache_dump { + compatible = "qcom,cache_dump"; + qcom,l1-dump-size = <0x100000>; + qcom,l2-dump-size = <0x500000>; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x600000>; /* 6M EBI1 buffer */ + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + rpm-standalone; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>; + reg-names = "core_mem"; + interrupts = <0 123 0>; + interrupt-names = "core_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>; + reg-names = "core_mem"; + interrupts = <0 125 0>; + interrupt-names = "core_irq"; + + + qcom,bus-width = <4>; + status = "disabled"; + }; + + qcom,sps@f9980000 { + compatible = "qcom,msm_sps"; + reg = <0xf9984000 0x15000>, + <0xf9999000 0xb000>; + interrupts = <0 94 0>; + qcom,pipe-attr-ee; + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0>, <0 187 0>; + qcom,not-wakeup; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + i2c_0: i2c@f9925000 { /* BLSP1 QUP3 */ + cell-index = <0>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9925000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 97 0>; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <50000000>; + qcom,sda-gpio = <&msmgpio 10 0>; + qcom,scl-gpio = <&msmgpio 11 0>; + }; + + usb3: qcom,ssusb@f9200000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xf9200000 0xfc000>, + <0xfd4ab000 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupts = <0 133 0>; + interrupt-names = "hs_phy_irq"; + ssusb_vdd_dig-supply = <&pma8084_s1>; + SSUSB_1p8-supply = <&pma8084_l6>; + hsusb_vdd_dig-supply = <&pma8084_s1>; + HSUSB_1p8-supply = <&pma8084_l6>; + HSUSB_3p3-supply = <&pma8084_l24>; + qcom,dwc-usb3-msm-dbm-eps = <4>; + qcom,vdd-voltage-level = <0 900000 1050000>; + + dwc3@f9200000 { + compatible = "synopsys,dwc3"; + reg = <0xf9200000 0xfc000>; + interrupt-parent = <&intc>; + interrupts = <0 131 0>, <0 179 0>; + interrupt-names = "irq", "otg_irq"; + tx-fifo-resize; + }; + }; + + android_usb { + compatible = "qcom,android-usb"; + }; + + qcom,ocmem@fdd00000 { + compatible = "qcom,msm-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfdd02000 0x2000>, + <0xfe039000 0x400>, + <0xfec00000 0x200000>; + reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical"; + interrupts = <0 76 0 0 77 0>; + interrupt-names = "ocmem_irq", "dm_irq"; + qcom,ocmem-num-regions = <0x4>; + qcom,ocmem-num-macros = <0x20>; + qcom,resource-type = <0x706d636f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfec00000 0x200000>; + + partition@0 { + reg = <0x0 0x180000>; + qcom,ocmem-part-name = "graphics"; + qcom,ocmem-part-min = <0x80000>; + }; + + partition@80000 { + reg = <0x180000 0x80000>; + qcom,ocmem-part-name = "lp_audio"; + qcom,ocmem-part-min = <0x80000>; + }; + + partition@100000 { + reg = <0x180000 0x80000>; + qcom,ocmem-part-name = "video"; + qcom,ocmem-part-min = <0x55000>; + }; + + }; + + memory_hole: qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x0dc00000 0x2000000>; /* Address and Size of Hole */ + }; + + qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + qcom,smem@fa00000 { + compatible = "qcom,smem"; + reg = <0xfa00000 0x200000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; +}; + +/include/ "msm-pma8084.dtsi" +/include/ "apq8084-regulator.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g20.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g20.dtsi new file mode 100644 index 000000000..773ef4840 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g20.dtsi @@ -0,0 +1,238 @@ +/* + * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre , + * 2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Atmel AT91SAM9G20 family SoC"; + compatible = "atmel,at91sam9g20"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + serial5 = &usart4; + serial6 = &usart5; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + reg = <0x20000000 0x08000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <2>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 4>; + }; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffa0000 0x100>; + interrupts = <17 4 18 4 19 4>; + }; + + tcb1: timer@fffdc000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffdc000 0x100>; + interrupts = <26 4 27 4 28 4>; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <4 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 4>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + interrupts = <6 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + interrupts = <7 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart2: serial@fffb8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + interrupts = <8 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart3: serial@fffd0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd0000 0x200>; + interrupts = <23 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart4: serial@fffd4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd4000 0x200>; + interrupts = <24 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart5: serial@fffd8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd8000 0x200>; + interrupts = <25 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + macb0: ethernet@fffc4000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffc4000 0x100>; + interrupts = <21 4>; + status = "disabled"; + }; + + usb1: gadget@fffa4000 { + compatible = "atmel,at91rm9200-udc"; + reg = <0xfffa4000 0x4000>; + interrupts = <10 4>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe800 0x200 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + gpios = <&pioC 13 0 + &pioC 14 0 + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <20 4>; + status = "disabled"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioA 23 0 /* sda */ + &pioA 24 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g25ek.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g25ek.dts new file mode 100644 index 000000000..7829a4d0c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g25ek.dts @@ -0,0 +1,49 @@ +/* + * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "at91sam9x5.dtsi" +/include/ "at91sam9x5cm.dtsi" + +/ { + model = "Atmel AT91SAM9G25-EK"; + compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@f801c000 { + status = "okay"; + }; + + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + }; + + usb0: ohci@00600000 { + status = "okay"; + num-ports = <2>; + atmel,vbus-gpio = <&pioD 19 1 + &pioD 20 1 + >; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g45.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g45.dtsi new file mode 100644 index 000000000..c8042147e --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9g45.dtsi @@ -0,0 +1,247 @@ +/* + * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC + * applies to AT91SAM9G45, AT91SAM9M10, + * AT91SAM9G46, AT91SAM9M11 SoC + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Atmel AT91SAM9G45 family SoC"; + compatible = "atmel,at91sam9g45"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + reg = <0x70000000 0x10000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <2>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + }; + + ramc0: ramc@ffffe400 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe400 0x200 + 0xffffe600 0x200>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffd00 0x10>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 4>; + }; + + + shdwc@fffffd10 { + compatible = "atmel,at91sam9rl-shdwc"; + reg = <0xfffffd10 0x10>; + }; + + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfff7c000 0x100>; + interrupts = <18 4>; + }; + + tcb1: timer@fffd4000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffd4000 0x100>; + interrupts = <18 4>; + }; + + dma: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <21 4>; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <4 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <5 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <5 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; + interrupts = <1 4>; + status = "disabled"; + }; + + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x200>; + interrupts = <7 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart1: serial@fff90000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff90000 0x200>; + interrupts = <8 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart2: serial@fff94000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff94000 0x200>; + interrupts = <9 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart3: serial@fff98000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff98000 0x200>; + interrupts = <10 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + macb0: ethernet@fffbc000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; + interrupts = <25 4>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe200 0x200 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + gpios = <&pioC 8 0 + &pioC 14 0 + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00700000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00700000 0x100000>; + interrupts = <22 4>; + status = "disabled"; + }; + + usb1: ehci@00800000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00800000 0x100000>; + interrupts = <22 4>; + status = "disabled"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioA 20 0 /* sda */ + &pioA 21 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <5>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9m10g45ek.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9m10g45ek.dts new file mode 100644 index 000000000..a3633bd13 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9m10g45ek.dts @@ -0,0 +1,156 @@ +/* + * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "at91sam9g45.dtsi" + +/ { + model = "Atmel AT91SAM9M10G45-EK"; + compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2"; + }; + + memory { + reg = <0x70000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + usart1: serial@fff90000 { + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + boot@0 { + label = "bootstrap/uboot/kernel"; + reg = <0x0 0x400000>; + }; + + rootfs@400000 { + label = "rootfs"; + reg = <0x400000 0x3C00000>; + }; + + data@4000000 { + label = "data"; + reg = <0x4000000 0xC000000>; + }; + }; + + usb0: ohci@00700000 { + status = "okay"; + num-ports = <2>; + atmel,vbus-gpio = <&pioD 1 1 + &pioD 3 1>; + }; + + usb1: ehci@00800000 { + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + d8 { + label = "d8"; + gpios = <&pioD 30 0>; + linux,default-trigger = "heartbeat"; + }; + + d6 { + label = "d6"; + gpios = <&pioD 0 1>; + linux,default-trigger = "nand-disk"; + }; + + d7 { + label = "d7"; + gpios = <&pioD 31 1>; + linux,default-trigger = "mmc0"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + left_click { + label = "left_click"; + gpios = <&pioB 6 1>; + linux,code = <272>; + gpio-key,wakeup; + }; + + right_click { + label = "right_click"; + gpios = <&pioB 7 1>; + linux,code = <273>; + gpio-key,wakeup; + }; + + left { + label = "Joystick Left"; + gpios = <&pioB 14 1>; + linux,code = <105>; + }; + + right { + label = "Joystick Right"; + gpios = <&pioB 15 1>; + linux,code = <106>; + }; + + up { + label = "Joystick Up"; + gpios = <&pioB 16 1>; + linux,code = <103>; + }; + + down { + label = "Joystick Down"; + gpios = <&pioB 17 1>; + linux,code = <108>; + }; + + enter { + label = "Joystick Press"; + gpios = <&pioB 18 1>; + linux,code = <28>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9x5.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9x5.dtsi new file mode 100644 index 000000000..dd4ed7484 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9x5.dtsi @@ -0,0 +1,263 @@ +/* + * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC + * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, + * AT91SAM9X25, AT91SAM9X35 SoC + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Atmel AT91SAM9x5 family SoC"; + compatible = "atmel,at91sam9x5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <2>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + }; + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + + rstc@fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + }; + + shdwc@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <1 4>; + }; + + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8008000 0x100>; + interrupts = <17 4>; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; + interrupts = <17 4>; + }; + + dma0: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <20 4>; + }; + + dma1: dma-controller@ffffee00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffee00 0x200>; + interrupts = <21 4>; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 4>; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x200>; + interrupts = <5 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x200>; + interrupts = <6 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x200>; + interrupts = <7 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + macb0: ethernet@f802c000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <24 4>; + status = "disabled"; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf8030000 0x100>; + interrupts = <27 4>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + gpios = <&pioD 5 0 + &pioD 4 0 + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <22 4>; + status = "disabled"; + }; + + usb1: ehci@00700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <22 4>; + status = "disabled"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioA 30 0 /* sda */ + &pioA 31 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@1 { + compatible = "i2c-gpio"; + gpios = <&pioC 0 0 /* sda */ + &pioC 1 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@2 { + compatible = "i2c-gpio"; + gpios = <&pioB 4 0 /* sda */ + &pioB 5 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9x5cm.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9x5cm.dtsi new file mode 100644 index 000000000..31e7be237 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/at91sam9x5cm.dtsi @@ -0,0 +1,74 @@ +/* + * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/ { + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pb18 { + label = "pb18"; + gpios = <&pioB 18 1>; + linux,default-trigger = "heartbeat"; + }; + + pd21 { + label = "pd21"; + gpios = <&pioD 21 0>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/db8500.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/db8500.dtsi new file mode 100644 index 000000000..14bc30705 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/db8500.dtsi @@ -0,0 +1,274 @@ +/* + * Copyright 2012 Linaro Ltd + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + soc-u9500 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500"; + interrupt-parent = <&intc>; + ranges; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = <0 13 4>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 7 0x4>; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = <1 13 0x304>; + }; + + rtc@80154000 { + compatible = "stericsson,db8500-rtc"; + reg = <0x80154000 0x1000>; + interrupts = <0 18 0x4>; + }; + + gpio0: gpio@8012e000 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8012e000 0x80>; + interrupts = <0 119 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio1: gpio@8012e080 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8012e080 0x80>; + interrupts = <0 120 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio2: gpio@8000e000 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8000e000 0x80>; + interrupts = <0 121 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio3: gpio@8000e080 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8000e080 0x80>; + interrupts = <0 122 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio4: gpio@8000e100 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8000e100 0x80>; + interrupts = <0 123 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio5: gpio@8000e180 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8000e180 0x80>; + interrupts = <0 124 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio6: gpio@8011e000 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8011e000 0x80>; + interrupts = <0 125 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio7: gpio@8011e080 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8011e080 0x80>; + interrupts = <0 126 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio8: gpio@a03fe000 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0xa03fe000 0x80>; + interrupts = <0 127 0x4>; + supports-sleepmode; + gpio-controller; + }; + + usb@a03e0000 { + compatible = "stericsson,db8500-musb", + "mentor,musb"; + reg = <0xa03e0000 0x10000>; + interrupts = <0 23 0x4>; + }; + + dma-controller@801C0000 { + compatible = "stericsson,db8500-dma40", + "stericsson,dma40"; + reg = <0x801C0000 0x1000 0x40010000 0x800>; + interrupts = <0 25 0x4>; + }; + + prcmu@80157000 { + compatible = "stericsson,db8500-prcmu"; + reg = <0x80157000 0x1000>; + interrupts = <46 47>; + #address-cells = <1>; + #size-cells = <0>; + + ab8500@5 { + compatible = "stericsson,ab8500"; + reg = <5>; /* mailbox 5 is i2c */ + interrupts = <0 40 0x4>; + }; + }; + + i2c@80004000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x80004000 0x1000>; + interrupts = <0 21 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80122000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x80122000 0x1000>; + interrupts = <0 22 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80128000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x80128000 0x1000>; + interrupts = <0 55 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80110000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x80110000 0x1000>; + interrupts = <0 12 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@8012a000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x8012a000 0x1000>; + interrupts = <0 51 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + ssp@80002000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <80002000 0x1000>; + interrupts = <0 14 0x4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + // Add one of these for each child device + cs-gpios = <&gpio0 31 &gpio4 14 &gpio4 16 &gpio6 22 &gpio7 0>; + + }; + + uart@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <0 11 0x4>; + status = "disabled"; + }; + uart@80121000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80121000 0x1000>; + interrupts = <0 19 0x4>; + status = "disabled"; + }; + uart@80007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80007000 0x1000>; + interrupts = <0 26 0x4>; + status = "disabled"; + }; + + sdi@80126000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80126000 0x1000>; + interrupts = <0 60 0x4>; + status = "disabled"; + }; + sdi@80118000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80118000 0x1000>; + interrupts = <0 50 0x4>; + status = "disabled"; + }; + sdi@80005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80005000 0x1000>; + interrupts = <0 41 0x4>; + status = "disabled"; + }; + sdi@80119000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80119000 0x1000>; + interrupts = <0 59 0x4>; + status = "disabled"; + }; + sdi@80114000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = <0 99 0x4>; + status = "disabled"; + }; + sdi@80008000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = <0 100 0x4>; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-nt35590-720p-cmd.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-nt35590-720p-cmd.dtsi new file mode 100644 index 000000000..7942567cc --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-nt35590-720p-cmd.dtsi @@ -0,0 +1,530 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + qcom,mdss_dsi_nt35590_720p_cmd { + compatible = "qcom,mdss-dsi-panel"; + label = "nt35590 720p command mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,rst-gpio = <&msmgpio 25 0>; + qcom,te-gpio = <&msmgpio 24 0>; + qcom,mdss-pan-res = <720 1280>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <164 8 140 1 1 6>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-bl-levels = <1 4095>; + qcom,mdss-pan-dsi-mode = <1>; + qcom,mdss-vsync-enable = <1>; + qcom,mdss-hw-vsync-mode = <1>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <2>; + qcom,mdss-pan-dsi-dst-format = <8>; + qcom,mdss-pan-insert-dcs-cmd = <1>; + qcom,mdss-pan-wr-mem-continue = <0x3c>; + qcom,mdss-pan-wr-mem-start = <0x2c>; + qcom,mdss-pan-te-sel = <1>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 1 1>; /* 4 lanes */ + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x2c 0x20>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [07 09 03 00 /* Regualotor settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 00 00 00 00 00 00 01 97 /* lane0 config */ + 00 00 00 00 05 00 00 01 97 /* lane1 config */ + 00 00 00 00 0a 00 00 01 97 /* lane2 config */ + 00 00 00 00 0f 00 00 01 97 /* lane3 config */ + 00 c0 00 00 00 00 00 01 bb]; /* Clk ln config */ + qcom,panel-on-cmds = [29 01 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02 6A 60 + 29 01 00 00 00 02 FF 00 + 29 01 00 00 78 02 29 00]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 32 02 28 00 + 05 01 00 00 78 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_HS_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-nt35590-720p-video.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-nt35590-720p-video.dtsi new file mode 100644 index 000000000..7bc748d59 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-nt35590-720p-video.dtsi @@ -0,0 +1,524 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_dsi_nt35590_720p_video { + compatible = "qcom,mdss-dsi-panel"; + label = "nt35590 720p video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,rst-gpio = <&msmgpio 25 0>; + qcom,mdss-pan-res = <720 1280>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <164 8 140 1 1 6>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-bl-levels = <1 4095>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <2>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 1 1>; /* 4 lanes */ + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x2c 0x20>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [07 09 03 00 /* Regualotor settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 00 00 00 00 00 00 01 97 /* lane0 config */ + 00 00 00 00 05 00 00 01 97 /* lane1 config */ + 00 00 00 00 0a 00 00 01 97 /* lane2 config */ + 00 00 00 00 0f 00 00 01 97 /* lane3 config */ + 00 c0 00 00 00 00 00 01 bb]; /* Clk ln config */ + qcom,panel-on-cmds = [29 01 00 00 00 00 02 FF EE + 29 01 00 00 00 00 02 26 08 + 29 01 00 00 00 00 02 26 00 + 29 01 00 00 10 00 02 FF 00 + 29 01 00 00 00 00 02 BA 03 + 29 01 00 00 00 00 02 C2 03 + 29 01 00 00 00 00 02 FF 01 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 00 4A + 29 01 00 00 00 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29 01 00 00 00 00 02 AE CB + 29 01 00 00 00 00 02 AF 00 + 29 01 00 00 00 00 02 B0 19 + 29 01 00 00 00 00 02 B1 00 + 29 01 00 00 00 00 02 B2 36 + 29 01 00 00 00 00 02 B3 00 + 29 01 00 00 00 00 02 B4 55 + 29 01 00 00 00 00 02 B5 00 + 29 01 00 00 00 00 02 B6 70 + 29 01 00 00 00 00 02 B7 00 + 29 01 00 00 00 00 02 B8 83 + 29 01 00 00 00 00 02 B9 00 + 29 01 00 00 00 00 02 BA 99 + 29 01 00 00 00 00 02 BB 00 + 29 01 00 00 00 00 02 BC A8 + 29 01 00 00 00 00 02 BD 00 + 29 01 00 00 00 00 02 BE B7 + 29 01 00 00 00 00 02 BF 00 + 29 01 00 00 00 00 02 C0 C5 + 29 01 00 00 00 00 02 C1 00 + 29 01 00 00 00 00 02 C2 F7 + 29 01 00 00 00 00 02 C3 01 + 29 01 00 00 00 00 02 C4 1E + 29 01 00 00 00 00 02 C5 01 + 29 01 00 00 00 00 02 C6 60 + 29 01 00 00 00 00 02 C7 01 + 29 01 00 00 00 00 02 C8 95 + 29 01 00 00 00 00 02 C9 01 + 29 01 00 00 00 00 02 CA E1 + 29 01 00 00 00 00 02 CB 02 + 29 01 00 00 00 00 02 CC 20 + 29 01 00 00 00 00 02 CD 02 + 29 01 00 00 00 00 02 CE 23 + 29 01 00 00 00 00 02 CF 02 + 29 01 00 00 00 00 02 D0 59 + 29 01 00 00 00 00 02 D1 02 + 29 01 00 00 00 00 02 D2 94 + 29 01 00 00 00 00 02 D3 02 + 29 01 00 00 00 00 02 D4 B4 + 29 01 00 00 00 00 02 D5 02 + 29 01 00 00 00 00 02 D6 E1 + 29 01 00 00 00 00 02 D7 03 + 29 01 00 00 00 00 02 D8 01 + 29 01 00 00 00 00 02 D9 03 + 29 01 00 00 00 00 02 DA 28 + 29 01 00 00 00 00 02 DB 03 + 29 01 00 00 00 00 02 DC 30 + 29 01 00 00 00 00 02 DD 03 + 29 01 00 00 00 00 02 DE 37 + 29 01 00 00 00 00 02 DF 03 + 29 01 00 00 00 00 02 E0 3B + 29 01 00 00 00 00 02 E1 03 + 29 01 00 00 00 00 02 E2 40 + 29 01 00 00 00 00 02 E3 03 + 29 01 00 00 00 00 02 E4 50 + 29 01 00 00 00 00 02 E5 03 + 29 01 00 00 00 00 02 E6 6D + 29 01 00 00 00 00 02 E7 03 + 29 01 00 00 00 00 02 E8 80 + 29 01 00 00 00 00 02 E9 03 + 29 01 00 00 00 00 02 EA CB + 29 01 00 00 00 00 02 FF 01 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 FF 02 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 FF 04 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 FF 00 + 29 01 00 00 64 00 02 11 00 + 29 01 00 00 00 00 02 FF EE + 29 01 00 00 00 00 02 12 50 + 29 01 00 00 00 00 02 13 02 + 29 01 00 00 00 00 02 6A 60 + 29 01 00 00 00 00 02 FF 00 + 29 01 00 00 78 00 02 29 00]; + + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_HS_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-orise-720p-video.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-orise-720p-video.dtsi new file mode 100644 index 000000000..478541fb1 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-orise-720p-video.dtsi @@ -0,0 +1,60 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_dsi_orise_720p_video { + compatible = "qcom,mdss-dsi-panel"; + label = "orise 720p video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi1>; + qcom,mdss-pan-res = <720 1280>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_2"; + qcom,mdss-pan-porch-values = <32 12 144 3 4 9>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-levels = <1 255>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <0>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <1>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 1 1>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [03 01 01 00 /* Regualotor settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [69 29 1f 00 55 55 + 19 2a 2a 03 04 00]; + qcom,panel-phy-strengthCtrl = [77 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 c2 45 00 00 00 00 01 75 /* lane0 config */ + 00 c2 45 00 00 00 00 01 75 /* lane1 config */ + 00 c2 45 00 00 00 00 01 75 /* lane2 config */ + 00 c2 45 00 00 00 00 01 75 /* lane3 config */ + 00 02 45 00 00 00 00 01 97]; /* Clk ln config */ + + qcom,panel-on-cmds = [05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_LP_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-sharp-qhd-video.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-sharp-qhd-video.dtsi new file mode 100644 index 000000000..45d396cdc --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-sharp-qhd-video.dtsi @@ -0,0 +1,67 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_dsi_sharp_qhd_video { + compatible = "qcom,mdss-dsi-panel"; + label = "sharp QHD LS043T1LE01 video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,enable-gpio = <&msmgpio 58 0>; + qcom,rst-gpio = <&pm8941_gpios 19 0>; + qcom,mdss-pan-res = <540 960>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <80 32 48 15 10 3>; /* HBP, HPW, HFP, VBP, VPW, VFP */ + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-bl-levels = <1 4095>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <0>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <2>; + qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x1c 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x04>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [07 09 03 00 /* Regulator settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [46 1d 20 00 39 3a + 21 21 32 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 00 00 00 00 00 00 01 97 /* lane0 config */ + 00 00 00 00 05 00 00 01 97 /* lane1 config */ + 00 00 00 00 0a 00 00 01 97 /* lane2 config */ + 00 00 00 00 0f 00 00 01 97 /* lane3 config */ + 00 c0 00 00 00 00 00 01 bb]; /* Clk ln config */ + qcom,panel-on-cmds = [05 01 00 00 32 00 02 01 00 /* sw reset */ + 05 01 00 00 0a 00 02 11 00 /* exit sleep */ + 15 01 00 00 0a 00 02 53 2c /* backlight on */ + 15 01 00 00 0a 00 02 51 ff /* brightness max */ + 05 01 00 00 0a 00 02 29 00 /* display on */ + 15 01 00 00 0a 00 02 ae 03 /* set num of lanes */ + 15 01 00 00 0a 00 02 3a 77 /* rgb_888 */]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 0a 00 02 28 00 /* display off */ + 05 01 00 00 78 00 02 10 00 /* enter sleep */]; + qcom,off-cmds-dsi-state = "DSI_HS_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-sim-video.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-sim-video.dtsi new file mode 100644 index 000000000..271e37316 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-sim-video.dtsi @@ -0,0 +1,46 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + qcom,mdss_dsi_sim_video { + compatible = "qcom,mdss-dsi-panel"; + label = "simulator video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,mdss-pan-res = <640 480>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <6 2 6 6 2 6>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-levels = <1 15>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <1 1 1>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <0>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x24 0x03>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x04>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-on-cmds = [32 01 00 00 00 00 02 00 00]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [22 01 00 00 00 00 02 00 00]; + qcom,off-cmds-dsi-state = "DSI_LP_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-toshiba-720p-video.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-toshiba-720p-video.dtsi new file mode 100644 index 000000000..5c37cf8dc --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-panel-toshiba-720p-video.dtsi @@ -0,0 +1,124 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + qcom,mdss_dsi_toshiba_720p_video { + compatible = "qcom,mdss-dsi-panel"; + label = "toshiba 720p video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,enable-gpio = <&msmgpio 58 0>; + qcom,rst-gpio = <&pm8941_gpios 19 0>; + qcom,mdss-pan-res = <720 1280>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <32 12 144 3 4 9>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-bl-levels = <1 4095>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <0>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <1>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 1 1>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [07 09 03 00 /* Regualotor settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [b0 23 1b 00 94 93 + 1e 25 15 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 00 00 00 00 00 00 01 97 /* lane0 config */ + 00 00 00 00 05 00 00 01 97 /* lane1 config */ + 00 00 00 00 0a 00 00 01 97 /* lane2 config */ + 00 00 00 00 0f 00 00 01 97 /* lane3 config */ + 00 c0 00 00 00 00 00 01 bb]; /* Clk ln config */ + + qcom,panel-on-cmds = [23 01 00 00 0a 00 02 b0 00 + 23 01 00 00 0a 00 02 b2 00 + 23 01 00 00 0a 00 02 b3 0c + 23 01 00 00 0a 00 02 b4 02 + 29 01 00 00 00 00 06 + c0 40 02 7f c8 08 + 29 01 00 00 00 00 10 + c1 00 a8 00 00 00 + 00 00 9d 08 27 00 + 00 00 00 00 + 29 01 00 00 00 00 06 + c2 00 00 09 00 00 + 23 01 00 00 0a 00 02 c3 04 + 29 01 00 00 00 00 04 + c4 4d 83 00 + 29 01 00 00 00 00 0b + c6 12 00 08 71 00 + 00 00 80 00 04 + 23 01 00 00 0a 00 02 c7 22 + 29 01 00 00 00 00 05 + c8 4c 0c 0c 0c + 29 01 00 00 00 00 0e + c9 00 40 00 16 32 + 2e 3a 43 3e 3c 45 + 79 3f + 29 01 00 00 00 00 0e + ca 00 46 1a 23 21 + 1c 25 31 2d 49 5f + 7f 3f + 29 01 00 00 00 00 0e + cb 00 4c 20 3a 42 + 40 47 4b 42 3e 46 + 7e 3f + 29 01 00 00 00 00 0e + cc 00 41 19 21 1d + 14 18 1f 1d 25 3f + 73 3f + 29 01 00 00 00 00 0e + cd 23 79 5a 5f 57 + 4c 51 51 45 3f 4b + 7f 3f + 29 01 00 00 00 00 0e + ce 00 40 14 20 1a + 0e 0e 13 08 00 05 + 46 1c + 29 01 00 00 00 00 04 + d0 6a 64 01 + 29 01 00 00 00 00 03 d1 77 d4 + 23 01 00 00 0a 00 02 d3 33 + 29 01 00 00 00 00 03 d5 0f 0f + 29 01 00 00 00 00 07 + d8 34 64 23 25 62 + 32 + 29 01 00 00 00 00 0c + de 10 7b 11 0a 00 + 00 00 00 00 00 00 + 29 01 00 00 00 00 09 + fd 04 55 53 00 70 + ff 10 73 + 23 01 00 00 0a 00 02 e2 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_HS_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-v2-panel-hx8379a-wvga-video.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-v2-panel-hx8379a-wvga-video.dtsi new file mode 100644 index 000000000..b9ed0506a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-v2-panel-hx8379a-wvga-video.dtsi @@ -0,0 +1,117 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + qcom,dsi_v2_hx8379a_wvga_video { + compatible = "qcom,dsi-panel-v2"; + label = "HX8379A WVGA video mode dsi panel"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,rst-gpio = <&msmgpio 41 0>; + vdda-supply = <&pm8110_l19>; + vddio-supply=<&pm8110_l14>; + qcom,mdss-pan-res = <480 800>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <90 17 90 2 3 11>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-levels = <1 255>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <2>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>; + qcom,mdss-pan-dsi-dlane-swap = <1>; + qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>;/*todo*/ + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings =[09 08 05 00 20 03]; + qcom,panel-phy-timingSettings = [5D 12 0C 00 33 39 + 10 16 15 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [03 03 00 00 0f 00]; + qcom,panel-phy-laneConfig = + [80 45 00 00 01 66 /*lane0**/ + 80 45 00 00 01 66 /*lane1*/ + 80 45 00 00 01 66 /*lane2*/ + 80 45 00 00 01 66 /*lane3*/ + 40 67 00 00 01 88]; /*Clk*/ + + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-on-cmds = [ + 29 01 00 00 01 04 + B9 FF 83 79 + 23 01 00 00 01 02 + BA 51 + 29 01 00 00 01 14 + B1 00 50 44 + EA 8D 08 11 + 0F 0F 24 2C + 9A 1A 42 0B + 6E F1 00 E6 + 29 01 00 00 01 0e + B2 00 00 3C + 08 04 19 22 + 00 FF 08 04 + 19 20 + 29 01 00 00 01 20 + B4 80 08 00 + 32 10 03 32 + 13 70 32 10 + 08 37 01 28 + 05 37 08 3C + 20 44 44 08 + 00 40 08 28 + 08 30 30 04 + 23 01 00 00 01 02 + cc 02 + 29 01 00 00 01 30 + D5 00 00 08 + 00 01 05 00 + 03 00 88 88 + 88 88 23 01 + 67 45 02 13 + 88 88 88 88 + 88 88 88 88 + 88 88 54 76 + 10 32 31 20 + 88 88 88 88 + 88 88 00 00 + 00 00 00 00 + 29 01 00 00 01 24 + E0 79 00 00 + 02 1C 1F 33 + 28 3E 07 0E + 0F 15 17 16 + 16 13 19 00 + 00 02 1C 1F + 33 28 3E 07 + 0E 0F 15 17 + 16 16 13 19 + 29 01 00 00 01 05 + B6 00 A6 00 A6 + 05 01 00 00 96 02 + 11 00 + 05 01 00 00 78 02 + 29 00 + ]; + qcom,panel-off-cmds = [05 01 00 00 32 02 28 00 + 05 01 00 00 78 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_LP_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-v2-panel-truly-wvga-video.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-v2-panel-truly-wvga-video.dtsi new file mode 100644 index 000000000..891eac3ad --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/dsi-v2-panel-truly-wvga-video.dtsi @@ -0,0 +1,120 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + qcom,dsi_v2_truly_wvga_video { + compatible = "qcom,dsi-panel-v2"; + label = "Truly WVGA video mode dsi panel"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,rst-gpio = <&msmgpio 41 0>; + qcom,mode-selection-gpio = <&msmgpio 7 0>; + vdda-supply = <&pm8110_l19>; + vddio-supply=<&pm8110_l14>; + qcom,mdss-pan-res = <480 800>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <40 8 160 10 2 12>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-levels = <1 255>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <0>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <1>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>;/*todo*/ + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings =[09 08 05 00 20 03]; + qcom,panel-phy-timingSettings = [5D 12 0C 00 33 38 + 10 16 1E 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [03 03 00 00 0f 00]; + qcom,panel-phy-laneConfig = + [80 45 00 00 01 66 /*lane0**/ + 80 45 00 00 01 66 /*lane1*/ + 80 45 00 00 01 66 /*lane2*/ + 80 45 00 00 01 66 /*lane3*/ + 40 67 00 00 01 88]; /*Clk*/ + + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-on-cmds = [ + 05 01 00 00 00 02 + 01 00 + 23 01 00 00 00 02 + b0 04 + 29 01 00 00 00 03 + b3 02 00 + 23 01 00 00 00 02 + bd 00 + 29 01 00 00 00 03 + c0 18 66 + 29 01 00 00 00 10 + c1 23 31 99 21 20 00 30 28 0c 0c + 00 00 00 21 01 + 29 01 00 00 00 07 + c2 10 06 06 01 03 00 + 29 01 00 00 00 19 + c8 04 10 18 20 2e 46 3c 28 1f 18 + 10 04 04 10 18 20 2e 46 3c 28 1f 18 10 04 + 29 01 00 00 00 19 + c9 04 10 18 20 2e 46 3c 28 1f 18 + 10 04 04 10 18 20 2e 46 3c 28 1f 18 10 04 + 29 01 00 00 00 19 + ca 04 10 18 20 2e 46 3c 28 1f 18 + 10 04 04 10 18 20 2e 46 3c 28 1f 18 10 04 + 29 01 00 00 00 11 + d0 29 03 ce a6 00 43 20 10 01 00 + 01 01 00 03 01 00 + 29 01 00 00 00 08 + d1 18 0C 23 03 75 02 50 + 23 01 00 00 00 02 + d3 11 + 29 01 00 00 00 03 + d5 2a 2a + 29 01 00 00 00 03 + de 01 41 + 23 01 00 00 00 02 + e6 51 + 23 01 00 00 00 02 + fa 03 + 23 01 00 00 64 02 + d6 28 + 39 01 00 00 00 05 + 2a 00 00 01 df + 39 01 00 00 00 05 + 2b 00 00 03 1f + 15 01 00 00 00 02 + 35 00 + 39 01 00 00 00 03 + 44 00 50 + 15 01 00 00 00 02 + 36 c1 + 15 01 00 00 00 02 + 3a 77 + 05 01 00 00 7D 02 + 11 00 + 05 01 00 00 14 02 + 29 00 + ]; + qcom,panel-off-cmds = [05 01 00 00 32 02 28 00 + 05 01 00 00 78 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_LP_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210-origen.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210-origen.dts new file mode 100644 index 000000000..b8c476384 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210-origen.dts @@ -0,0 +1,137 @@ +/* + * Samsung's Exynos4210 based Origen board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Insignal's Origen board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x40000000>; + }; + + chosen { + bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; + }; + + sdhci@12530000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; + }; + + sdhci@12510000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk0 2 2 3 3>; + gpios = <&gpk0 0 2 0 3>, + <&gpk0 1 2 0 3>, + <&gpk0 3 2 3 3>, + <&gpk0 4 2 3 3>, + <&gpk0 5 2 3 3>, + <&gpk0 6 2 3 3>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + up { + label = "Up"; + gpios = <&gpx2 0 0 0 2>; + linux,code = <103>; + }; + + down { + label = "Down"; + gpios = <&gpx2 1 0 0 2>; + linux,code = <108>; + }; + + back { + label = "Back"; + gpios = <&gpx1 7 0 0 2>; + linux,code = <158>; + }; + + home { + label = "Home"; + gpios = <&gpx1 6 0 0 2>; + linux,code = <102>; + }; + + menu { + label = "Menu"; + gpios = <&gpx1 5 0 0 2>; + linux,code = <139>; + }; + }; + + keypad@100A0000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + i2c@13860000 { + status = "disabled"; + }; + + i2c@13870000 { + status = "disabled"; + }; + + i2c@13880000 { + status = "disabled"; + }; + + i2c@13890000 { + status = "disabled"; + }; + + i2c@138A0000 { + status = "disabled"; + }; + + i2c@138B0000 { + status = "disabled"; + }; + + i2c@138C0000 { + status = "disabled"; + }; + + i2c@138D0000 { + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210-smdkv310.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210-smdkv310.dts new file mode 100644 index 000000000..27afc8e53 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210-smdkv310.dts @@ -0,0 +1,182 @@ +/* + * Samsung's Exynos4210 based SMDKV310 board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Samsung's SMDKV310 board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Samsung smdkv310 evaluation board based on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; + }; + + sdhci@12530000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; + }; + + keypad@100A0000 { + samsung,keypad-num-rows = <2>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + + row-gpios = <&gpx2 0 3 3 0>, + <&gpx2 1 3 3 0>; + + col-gpios = <&gpx1 0 3 0 0>, + <&gpx1 1 3 0 0>, + <&gpx1 2 3 0 0>, + <&gpx1 3 3 0 0>, + <&gpx1 4 3 0 0>, + <&gpx1 5 3 0 0>, + <&gpx1 6 3 0 0>, + <&gpx1 7 3 0 0>; + + key_1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = <2>; + }; + + key_2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = <3>; + }; + + key_3 { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <4>; + }; + + key_4 { + keypad,row = <0>; + keypad,column = <6>; + linux,code = <5>; + }; + + key_5 { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <6>; + }; + + key_a { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <30>; + }; + + key_b { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <48>; + }; + + key_c { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <46>; + }; + + key_d { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <32>; + }; + + key_e { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <18>; + }; + }; + + i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpd1 0 2 3 0>, + <&gpd1 1 2 3 0>; + + eeprom@50 { + compatible = "samsung,24ad0xd1"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "samsung,24ad0xd1"; + reg = <0x52>; + }; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + i2c@13870000 { + status = "disabled"; + }; + + i2c@13880000 { + status = "disabled"; + }; + + i2c@13890000 { + status = "disabled"; + }; + + i2c@138A0000 { + status = "disabled"; + }; + + i2c@138B0000 { + status = "disabled"; + }; + + i2c@138C0000 { + status = "disabled"; + }; + + i2c@138D0000 { + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210.dtsi new file mode 100644 index 000000000..a1dd2ee83 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos4210.dtsi @@ -0,0 +1,398 @@ +/* + * Samsung's Exynos4210 SoC device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,exynos4210"; + interrupt-parent = <&gic>; + + gic:interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + cpu-offset = <0x8000>; + reg = <0x10490000 0x1000>, <0x10480000 0x100>; + }; + + watchdog@10060000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x10060000 0x100>; + interrupts = <0 43 0>; + }; + + rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 44 0>, <0 45 0>; + }; + + keypad@100A0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100A0000 0x100>; + interrupts = <0 109 0>; + }; + + sdhci@12510000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12510000 0x100>; + interrupts = <0 73 0>; + }; + + sdhci@12520000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12520000 0x100>; + interrupts = <0 74 0>; + }; + + sdhci@12530000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12530000 0x100>; + interrupts = <0 75 0>; + }; + + sdhci@12540000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12540000 0x100>; + interrupts = <0 76 0>; + }; + + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 52 0>; + }; + + serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 53 0>; + }; + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 54 0>; + }; + + serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = <0 55 0>; + }; + + i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 59 0>; + }; + + i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@138A0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@138B0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@138C0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 64 0>; + }; + + i2c@138D0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 65 0>; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 35 0>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 36 0>; + }; + }; + + gpio-controllers { + #address-cells = <1>; + #size-cells = <1>; + gpio-controller; + ranges; + + gpa0: gpio-controller@11400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400000 0x20>; + #gpio-cells = <4>; + }; + + gpa1: gpio-controller@11400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400020 0x20>; + #gpio-cells = <4>; + }; + + gpb: gpio-controller@11400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400040 0x20>; + #gpio-cells = <4>; + }; + + gpc0: gpio-controller@11400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400060 0x20>; + #gpio-cells = <4>; + }; + + gpc1: gpio-controller@11400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400080 0x20>; + #gpio-cells = <4>; + }; + + gpd0: gpio-controller@114000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000A0 0x20>; + #gpio-cells = <4>; + }; + + gpd1: gpio-controller@114000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000C0 0x20>; + #gpio-cells = <4>; + }; + + gpe0: gpio-controller@114000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000E0 0x20>; + #gpio-cells = <4>; + }; + + gpe1: gpio-controller@11400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400100 0x20>; + #gpio-cells = <4>; + }; + + gpe2: gpio-controller@11400120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400120 0x20>; + #gpio-cells = <4>; + }; + + gpe3: gpio-controller@11400140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400140 0x20>; + #gpio-cells = <4>; + }; + + gpe4: gpio-controller@11400160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400160 0x20>; + #gpio-cells = <4>; + }; + + gpf0: gpio-controller@11400180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400180 0x20>; + #gpio-cells = <4>; + }; + + gpf1: gpio-controller@114001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001A0 0x20>; + #gpio-cells = <4>; + }; + + gpf2: gpio-controller@114001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001C0 0x20>; + #gpio-cells = <4>; + }; + + gpf3: gpio-controller@114001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001E0 0x20>; + #gpio-cells = <4>; + }; + + gpj0: gpio-controller@11000000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000000 0x20>; + #gpio-cells = <4>; + }; + + gpj1: gpio-controller@11000020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000020 0x20>; + #gpio-cells = <4>; + }; + + gpk0: gpio-controller@11000040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000040 0x20>; + #gpio-cells = <4>; + }; + + gpk1: gpio-controller@11000060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000060 0x20>; + #gpio-cells = <4>; + }; + + gpk2: gpio-controller@11000080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000080 0x20>; + #gpio-cells = <4>; + }; + + gpk3: gpio-controller@110000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000A0 0x20>; + #gpio-cells = <4>; + }; + + gpl0: gpio-controller@110000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000C0 0x20>; + #gpio-cells = <4>; + }; + + gpl1: gpio-controller@110000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000E0 0x20>; + #gpio-cells = <4>; + }; + + gpl2: gpio-controller@11000100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000100 0x20>; + #gpio-cells = <4>; + }; + + gpy0: gpio-controller@11000120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000120 0x20>; + #gpio-cells = <4>; + }; + + gpy1: gpio-controller@11000140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000140 0x20>; + #gpio-cells = <4>; + }; + + gpy2: gpio-controller@11000160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000160 0x20>; + #gpio-cells = <4>; + }; + + gpy3: gpio-controller@11000180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000180 0x20>; + #gpio-cells = <4>; + }; + + gpy4: gpio-controller@110001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001A0 0x20>; + #gpio-cells = <4>; + }; + + gpy5: gpio-controller@110001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001C0 0x20>; + #gpio-cells = <4>; + }; + + gpy6: gpio-controller@110001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001E0 0x20>; + #gpio-cells = <4>; + }; + + gpx0: gpio-controller@11000C00 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C00 0x20>; + #gpio-cells = <4>; + }; + + gpx1: gpio-controller@11000C20 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C20 0x20>; + #gpio-cells = <4>; + }; + + gpx2: gpio-controller@11000C40 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C40 0x20>; + #gpio-cells = <4>; + }; + + gpx3: gpio-controller@11000C60 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C60 0x20>; + #gpio-cells = <4>; + }; + + gpz: gpio-controller@03860000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x03860000 0x20>; + #gpio-cells = <4>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/exynos5250-smdk5250.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos5250-smdk5250.dts new file mode 100644 index 000000000..399d17b23 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos5250-smdk5250.dts @@ -0,0 +1,26 @@ +/* + * SAMSUNG SMDK5250 board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos5250.dtsi" + +/ { + model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; + compatible = "samsung,smdk5250", "samsung,exynos5250"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/exynos5250.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos5250.dtsi new file mode 100644 index 000000000..dfc433599 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/exynos5250.dtsi @@ -0,0 +1,413 @@ +/* + * SAMSUNG EXYNOS5250 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. + * EXYNOS5250 based board files can include this file and provide + * values for board specfic bindings. + * + * Note: This file does not include device nodes for all the controllers in + * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, + * additional nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,exynos5250"; + interrupt-parent = <&gic>; + + gic:interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10490000 0x1000>, <0x10480000 0x100>; + }; + + watchdog { + compatible = "samsung,s3c2410-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + }; + + rtc { + compatible = "samsung,s3c6410-rtc"; + reg = <0x101E0000 0x100>; + interrupts = <0 43 0>, <0 44 0>; + }; + + sdhci@12200000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12200000 0x100>; + interrupts = <0 75 0>; + }; + + sdhci@12210000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12210000 0x100>; + interrupts = <0 76 0>; + }; + + sdhci@12220000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12220000 0x100>; + interrupts = <0 77 0>; + }; + + sdhci@12230000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12230000 0x100>; + interrupts = <0 78 0>; + }; + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + }; + + serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + interrupts = <0 54 0>; + }; + + i2c@12C60000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C60000 0x100>; + interrupts = <0 56 0>; + }; + + i2c@12C70000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C70000 0x100>; + interrupts = <0 57 0>; + }; + + i2c@12C80000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C80000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@12C90000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C90000 0x100>; + interrupts = <0 59 0>; + }; + + i2c@12CA0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CA0000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@12CB0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CB0000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@12CC0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CC0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@12CD0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CD0000 0x100>; + interrupts = <0 63 0>; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@121A0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <0 34 0>; + }; + + pdma1: pdma@121B0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <0 35 0>; + }; + + mdma0: pdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <0 33 0>; + }; + + mdma1: pdma@11C10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <0 124 0>; + }; + }; + + gpio-controllers { + #address-cells = <1>; + #size-cells = <1>; + gpio-controller; + ranges; + + gpa0: gpio-controller@11400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400000 0x20>; + #gpio-cells = <4>; + }; + + gpa1: gpio-controller@11400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400020 0x20>; + #gpio-cells = <4>; + }; + + gpa2: gpio-controller@11400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400040 0x20>; + #gpio-cells = <4>; + }; + + gpb0: gpio-controller@11400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400060 0x20>; + #gpio-cells = <4>; + }; + + gpb1: gpio-controller@11400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400080 0x20>; + #gpio-cells = <4>; + }; + + gpb2: gpio-controller@114000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000A0 0x20>; + #gpio-cells = <4>; + }; + + gpb3: gpio-controller@114000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000C0 0x20>; + #gpio-cells = <4>; + }; + + gpc0: gpio-controller@114000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000E0 0x20>; + #gpio-cells = <4>; + }; + + gpc1: gpio-controller@11400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400100 0x20>; + #gpio-cells = <4>; + }; + + gpc2: gpio-controller@11400120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400120 0x20>; + #gpio-cells = <4>; + }; + + gpc3: gpio-controller@11400140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400140 0x20>; + #gpio-cells = <4>; + }; + + gpd0: gpio-controller@11400160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400160 0x20>; + #gpio-cells = <4>; + }; + + gpd1: gpio-controller@11400180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400180 0x20>; + #gpio-cells = <4>; + }; + + gpy0: gpio-controller@114001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001A0 0x20>; + #gpio-cells = <4>; + }; + + gpy1: gpio-controller@114001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001C0 0x20>; + #gpio-cells = <4>; + }; + + gpy2: gpio-controller@114001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001E0 0x20>; + #gpio-cells = <4>; + }; + + gpy3: gpio-controller@11400200 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400200 0x20>; + #gpio-cells = <4>; + }; + + gpy4: gpio-controller@11400220 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400220 0x20>; + #gpio-cells = <4>; + }; + + gpy5: gpio-controller@11400240 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400240 0x20>; + #gpio-cells = <4>; + }; + + gpy6: gpio-controller@11400260 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400260 0x20>; + #gpio-cells = <4>; + }; + + gpx0: gpio-controller@11400C00 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C00 0x20>; + #gpio-cells = <4>; + }; + + gpx1: gpio-controller@11400C20 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C20 0x20>; + #gpio-cells = <4>; + }; + + gpx2: gpio-controller@11400C40 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C40 0x20>; + #gpio-cells = <4>; + }; + + gpx3: gpio-controller@11400C60 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C60 0x20>; + #gpio-cells = <4>; + }; + + gpe0: gpio-controller@13400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400000 0x20>; + #gpio-cells = <4>; + }; + + gpe1: gpio-controller@13400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400020 0x20>; + #gpio-cells = <4>; + }; + + gpf0: gpio-controller@13400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400040 0x20>; + #gpio-cells = <4>; + }; + + gpf1: gpio-controller@13400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400060 0x20>; + #gpio-cells = <4>; + }; + + gpg0: gpio-controller@13400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400080 0x20>; + #gpio-cells = <4>; + }; + + gpg1: gpio-controller@134000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000A0 0x20>; + #gpio-cells = <4>; + }; + + gpg2: gpio-controller@134000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000C0 0x20>; + #gpio-cells = <4>; + }; + + gph0: gpio-controller@134000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000E0 0x20>; + #gpio-cells = <4>; + }; + + gph1: gpio-controller@13400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400100 0x20>; + #gpio-cells = <4>; + }; + + gpv0: gpio-controller@10D10000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10000 0x20>; + #gpio-cells = <4>; + }; + + gpv1: gpio-controller@10D10020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10020 0x20>; + #gpio-cells = <4>; + }; + + gpv2: gpio-controller@10D10040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10040 0x20>; + #gpio-cells = <4>; + }; + + gpv3: gpio-controller@10D10060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10060 0x20>; + #gpio-cells = <4>; + }; + + gpv4: gpio-controller@10D10080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10080 0x20>; + #gpio-cells = <4>; + }; + + gpz: gpio-controller@03860000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x03860000 0x20>; + #gpio-cells = <4>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900-rumi.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900-rumi.dts new file mode 100644 index 000000000..2b380c7b3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900-rumi.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "fsm9900.dtsi" + +/ { + model = "Qualcomm FSM9900 Rumi"; + compatible = "qcom,fsm9900-rumi", "qcom,fsm9900", "qcom-sim"; + qcom,msm-id = <188 0 0>; + + aliases { + serial0 = &uart0; + }; +}; + +&soc { + uart0: serial@f9960000 { + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900-sim.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900-sim.dts new file mode 100644 index 000000000..050929e60 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900-sim.dts @@ -0,0 +1,32 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "fsm9900.dtsi" + +/ { + model = "Qualcomm FSM9900 Simulator"; + compatible = "qcom,fsm9900-sim", "qcom,fsm9900", "qcom-sim"; + qcom,msm-id = <188 0 0>; + + aliases { + serial0 = &uart0; + }; +}; + +&soc { + uart0: serial@f9960000 { + interrupts = <0 116 0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900.dtsi new file mode 100644 index 000000000..766db368d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/fsm9900.dtsi @@ -0,0 +1,94 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton64.dtsi" + +/ { + model = "Qualcomm FSM9900"; + compatible = "qcom,fsm9900"; + interrupt-parent = <&intc>; + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <142>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <5>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + serial@f9960000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf9960000 0x1000>; + interrupts = <0 104 0>; + status = "disabled"; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + qcom,irq-is-percpu; + interrupts = <1 7 0xf00>; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + qcom,cache_erp { + compatible = "qcom,cache_erp"; + interrupts = <1 9 0>, <0 2 0>; + interrupt-names = "l1_irq", "l2_irq"; + }; + + qcom,cache_dump { + compatible = "qcom,cache_dump"; + qcom,l1-dump-size = <0x100000>; + qcom,l2-dump-size = <0x500000>; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x600000>; /* 6M EBI1 buffer */ + }; + + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/highbank.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/highbank.dts new file mode 100644 index 000000000..83e72294a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/highbank.dts @@ -0,0 +1,209 @@ +/* + * Copyright 2011 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/dts-v1/; + +/* First 4KB has pen for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; + +/ { + model = "Calxeda Highbank"; + compatible = "calxeda,highbank"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x00000000 0xff900000>; + }; + + chosen { + bootargs = "console=ttyAMA0"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + timer@fff10600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfff10600 0x20>; + interrupts = <1 13 0xf01>; + }; + + watchdog@fff10620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xfff10620 0x20>; + interrupts = <1 14 0xf01>; + }; + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + interrupts = <0 70 4>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; + }; + + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x10000>; + interrupts = <0 83 4>; + }; + + sdhci@ffe0e000 { + compatible = "calxeda,hb-sdhci"; + reg = <0xffe0e000 0x1000>; + interrupts = <0 90 4>; + }; + + ipc@fff20000 { + compatible = "arm,pl320", "arm,primecell"; + reg = <0xfff20000 0x1000>; + interrupts = <0 7 4>; + }; + + gpioe: gpio@fff30000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff30000 0x1000>; + interrupts = <0 14 4>; + }; + + gpiof: gpio@fff31000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff31000 0x1000>; + interrupts = <0 15 4>; + }; + + gpiog: gpio@fff32000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff32000 0x1000>; + interrupts = <0 16 4>; + }; + + gpioh: gpio@fff33000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff33000 0x1000>; + interrupts = <0 17 4>; + }; + + timer { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xfff34000 0x1000>; + interrupts = <0 18 4>; + }; + + rtc@fff35000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0xfff35000 0x1000>; + interrupts = <0 19 4>; + }; + + serial@fff36000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xfff36000 0x1000>; + interrupts = <0 20 4>; + }; + + smic@fff3a000 { + compatible = "ipmi-smic"; + device_type = "ipmi"; + reg = <0xfff3a000 0x1000>; + interrupts = <0 24 4>; + reg-size = <4>; + reg-spacing = <4>; + }; + + sregs@fff3c000 { + compatible = "calxeda,hb-sregs"; + reg = <0xfff3c000 0x1000>; + }; + + dma@fff3d000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xfff3d000 0x1000>; + interrupts = <0 92 4>; + }; + + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4 0 78 4 0 79 4>; + }; + + ethernet@fff51000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff51000 0x1000>; + interrupts = <0 80 4 0 81 4 0 82 4>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx27-phytec-phycore.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/imx27-phytec-phycore.dts new file mode 100644 index 000000000..a51a08fc2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx27-phytec-phycore.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx27.dtsi" + +/ { + model = "Phytec pcm038"; + compatible = "phytec,imx27-pcm038", "fsl,imx27"; + + memory { + reg = <0x0 0x0>; + }; + + soc { + aipi@10000000 { /* aipi */ + + wdog@10002000 { + status = "okay"; + }; + + uart@1000a000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + uart@1000b000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + uart@1000c000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + fec@1002b000 { + status = "okay"; + }; + + i2c@1001d000 { + clock-frequency = <400000>; + status = "okay"; + at24@4c { + compatible = "at,24c32"; + pagesize = <32>; + reg = <0x52>; + }; + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + lm75@4a { + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + }; + }; + + nor_flash@c0000000 { + compatible = "cfi-flash"; + bank-width = <2>; + reg = <0xc0000000 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx27.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/imx27.dtsi new file mode 100644 index 000000000..bc5e7d5dd --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx27.dtsi @@ -0,0 +1,217 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + }; + + avic: avic-interrupt-controller@e0000000 { + compatible = "fsl,imx27-avic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10040000 0x1000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc26m { + compatible = "fsl,imx-osc26m", "fixed-clock"; + clock-frequency = <26000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&avic>; + ranges; + + aipi@10000000 { /* AIPI1 */ + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10000000 0x10000000>; + ranges; + + wdog@10002000 { + compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; + reg = <0x10002000 0x4000>; + interrupts = <27>; + status = "disabled"; + }; + + uart1: uart@1000a000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000a000 0x1000>; + interrupts = <20>; + status = "disabled"; + }; + + uart2: uart@1000b000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000b000 0x1000>; + interrupts = <19>; + status = "disabled"; + }; + + uart3: uart@1000c000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000c000 0x1000>; + interrupts = <18>; + status = "disabled"; + }; + + uart4: uart@1000d000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000d000 0x1000>; + interrupts = <17>; + status = "disabled"; + }; + + cspi1: cspi@1000e000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x1000e000 0x1000>; + interrupts = <16>; + status = "disabled"; + }; + + cspi2: cspi@1000f000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x1000f000 0x1000>; + interrupts = <15>; + status = "disabled"; + }; + + i2c1: i2c@10012000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-i2c", "fsl,imx1-i2c"; + reg = <0x10012000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + + gpio1: gpio@10015000 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015000 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@10015100 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015100 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@10015200 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015200 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@10015300 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015300 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio5: gpio@10015400 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015400 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio6: gpio@10015500 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015500 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + cspi3: cspi@10017000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x10017000 0x1000>; + interrupts = <6>; + status = "disabled"; + }; + + uart5: uart@1001b000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1001b000 0x1000>; + interrupts = <49>; + status = "disabled"; + }; + + uart6: uart@1001c000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1001c000 0x1000>; + interrupts = <48>; + status = "disabled"; + }; + + i2c2: i2c@1001d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-i2c", "fsl,imx1-i2c"; + reg = <0x1001d000 0x1000>; + interrupts = <1>; + status = "disabled"; + }; + + fec: fec@1002b000 { + compatible = "fsl,imx27-fec"; + reg = <0x1002b000 0x4000>; + interrupts = <50>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx51-babbage.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/imx51-babbage.dts new file mode 100644 index 000000000..9949e6060 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx51-babbage.dts @@ -0,0 +1,221 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx51.dtsi" + +/ { + model = "Freescale i.MX51 Babbage Board"; + compatible = "fsl,imx51-babbage", "fsl,imx51"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x90000000 0x20000000>; + }; + + soc { + aips@70000000 { /* aips-1 */ + spba@70000000 { + esdhc@70004000 { /* ESDHC1 */ + fsl,cd-internal; + fsl,wp-internal; + status = "okay"; + }; + + esdhc@70008000 { /* ESDHC2 */ + cd-gpios = <&gpio1 6 0>; + wp-gpios = <&gpio1 5 0>; + status = "okay"; + }; + + uart3: uart@7000c000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + ecspi@70010000 { /* ECSPI1 */ + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; + status = "okay"; + + pmic: mc13892@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mc13892"; + spi-max-frequency = <6000000>; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8>; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + }; + + flash: at45db321d@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0x3c0000>; + }; + }; + }; + }; + + wdog@73f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@73fa8000 { + compatible = "fsl,imx51-iomuxc-babbage"; + reg = <0x73fa8000 0x4000>; + }; + + uart1: uart@73fbc000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + uart2: uart@73fc0000 { + status = "okay"; + }; + }; + + aips@80000000 { /* aips-2 */ + sdma@83fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; + }; + + i2c@83fc4000 { /* I2C2 */ + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + }; + + fec@83fec000 { + phy-mode = "mii"; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power Button"; + gpios = <&gpio2 21 0>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx51.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/imx51.dtsi new file mode 100644 index 000000000..6663986fe --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx51.dtsi @@ -0,0 +1,246 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + tzic: tz-interrupt-controller@e0000000 { + compatible = "fsl,imx51-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xe0000000 0x4000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + aips@70000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x70000000 0x10000000>; + ranges; + + spba@70000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x70000000 0x40000>; + ranges; + + esdhc@70004000 { /* ESDHC1 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70004000 0x4000>; + interrupts = <1>; + status = "disabled"; + }; + + esdhc@70008000 { /* ESDHC2 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70008000 0x4000>; + interrupts = <2>; + status = "disabled"; + }; + + uart3: uart@7000c000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x7000c000 0x4000>; + interrupts = <33>; + status = "disabled"; + }; + + ecspi@70010000 { /* ECSPI1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ecspi"; + reg = <0x70010000 0x4000>; + interrupts = <36>; + status = "disabled"; + }; + + esdhc@70020000 { /* ESDHC3 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70020000 0x4000>; + interrupts = <3>; + status = "disabled"; + }; + + esdhc@70024000 { /* ESDHC4 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70024000 0x4000>; + interrupts = <4>; + status = "disabled"; + }; + }; + + gpio1: gpio@73f84000 { + compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; + reg = <0x73f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@73f88000 { + compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; + reg = <0x73f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@73f8c000 { + compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; + reg = <0x73f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@73f90000 { + compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; + reg = <0x73f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + wdog@73f98000 { /* WDOG1 */ + compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; + reg = <0x73f98000 0x4000>; + interrupts = <58>; + status = "disabled"; + }; + + wdog@73f9c000 { /* WDOG2 */ + compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; + reg = <0x73f9c000 0x4000>; + interrupts = <59>; + status = "disabled"; + }; + + uart1: uart@73fbc000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fbc000 0x4000>; + interrupts = <31>; + status = "disabled"; + }; + + uart2: uart@73fc0000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fc0000 0x4000>; + interrupts = <32>; + status = "disabled"; + }; + }; + + aips@80000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x10000000>; + ranges; + + ecspi@83fac000 { /* ECSPI2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ecspi"; + reg = <0x83fac000 0x4000>; + interrupts = <37>; + status = "disabled"; + }; + + sdma@83fb0000 { + compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; + reg = <0x83fb0000 0x4000>; + interrupts = <6>; + }; + + cspi@83fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; + reg = <0x83fc0000 0x4000>; + interrupts = <38>; + status = "disabled"; + }; + + i2c@83fc4000 { /* I2C2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; + reg = <0x83fc4000 0x4000>; + interrupts = <63>; + status = "disabled"; + }; + + i2c@83fc8000 { /* I2C1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; + reg = <0x83fc8000 0x4000>; + interrupts = <62>; + status = "disabled"; + }; + + fec@83fec000 { + compatible = "fsl,imx51-fec", "fsl,imx27-fec"; + reg = <0x83fec000 0x4000>; + interrupts = <87>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-ard.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-ard.dts new file mode 100644 index 000000000..2dccce46e --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-ard.dts @@ -0,0 +1,113 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Automotive Reference Design Board"; + compatible = "fsl,imx53-ard", "fsl,imx53"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x70000000 0x40000000>; + }; + + soc { + aips@50000000 { /* AIPS1 */ + spba@50000000 { + esdhc@50004000 { /* ESDHC1 */ + cd-gpios = <&gpio1 1 0>; + wp-gpios = <&gpio1 9 0>; + status = "okay"; + }; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-ard"; + reg = <0x53fa8000 0x4000>; + }; + + uart1: uart@53fbc000 { + status = "okay"; + }; + }; + + aips@60000000 { /* AIPS2 */ + sdma@63fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + }; + }; + + eim-cs1@f4000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eim-bus", "simple-bus"; + reg = <0xf4000000 0x3ff0000>; + ranges; + + lan9220@f4000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0xf4000000 0x2000000>; + phy-mode = "mii"; + interrupt-parent = <&gpio2>; + interrupts = <31>; + reg-io-width = <4>; + smsc,irq-push-pull; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + home { + label = "Home"; + gpios = <&gpio5 10 0>; + linux,code = <102>; /* KEY_HOME */ + gpio-key,wakeup; + }; + + back { + label = "Back"; + gpios = <&gpio5 11 0>; + linux,code = <158>; /* KEY_BACK */ + gpio-key,wakeup; + }; + + program { + label = "Program"; + gpios = <&gpio5 12 0>; + linux,code = <362>; /* KEY_PROGRAM */ + gpio-key,wakeup; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio5 13 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 0 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-evk.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-evk.dts new file mode 100644 index 000000000..5bac4aa48 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-evk.dts @@ -0,0 +1,119 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Evaluation Kit"; + compatible = "fsl,imx53-evk", "fsl,imx53"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x70000000 0x80000000>; + }; + + soc { + aips@50000000 { /* AIPS1 */ + spba@50000000 { + esdhc@50004000 { /* ESDHC1 */ + cd-gpios = <&gpio3 13 0>; + wp-gpios = <&gpio3 14 0>; + status = "okay"; + }; + + ecspi@50010000 { /* ECSPI1 */ + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; + status = "okay"; + + flash: at45db321d@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0x3c0000>; + }; + }; + }; + + esdhc@50020000 { /* ESDHC3 */ + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; + status = "okay"; + }; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-evk"; + reg = <0x53fa8000 0x4000>; + }; + + uart1: uart@53fbc000 { + status = "okay"; + }; + }; + + aips@60000000 { /* AIPS2 */ + sdma@63fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + i2c@63fc4000 { /* I2C2 */ + status = "okay"; + + pmic: mc13892@08 { + compatible = "fsl,mc13892", "fsl,mc13xxx"; + reg = <0x08>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + }; + + fec@63fec000 { + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + green { + label = "Heartbeat"; + gpios = <&gpio7 7 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-qsb.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-qsb.dts new file mode 100644 index 000000000..5c57c8672 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-qsb.dts @@ -0,0 +1,125 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Quick Start Board"; + compatible = "fsl,imx53-qsb", "fsl,imx53"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x70000000 0x40000000>; + }; + + soc { + aips@50000000 { /* AIPS1 */ + spba@50000000 { + esdhc@50004000 { /* ESDHC1 */ + cd-gpios = <&gpio3 13 0>; + status = "okay"; + }; + + esdhc@50020000 { /* ESDHC3 */ + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; + status = "okay"; + }; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-qsb"; + reg = <0x53fa8000 0x4000>; + }; + + uart1: uart@53fbc000 { + status = "okay"; + }; + }; + + aips@60000000 { /* AIPS2 */ + sdma@63fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + i2c@63fc4000 { /* I2C2 */ + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + }; + + i2c@63fc8000 { /* I2C1 */ + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + pmic: dialog@48 { + compatible = "dialog,da9053", "dialog,da9052"; + reg = <0x48>; + }; + }; + + fec@63fec000 { + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power Button"; + gpios = <&gpio1 8 0>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 14 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio2 15 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio7 7 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-smd.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-smd.dts new file mode 100644 index 000000000..c7ee86c2d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53-smd.dts @@ -0,0 +1,168 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Smart Mobile Reference Design Board"; + compatible = "fsl,imx53-smd", "fsl,imx53"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x70000000 0x40000000>; + }; + + soc { + aips@50000000 { /* AIPS1 */ + spba@50000000 { + esdhc@50004000 { /* ESDHC1 */ + cd-gpios = <&gpio3 13 0>; + wp-gpios = <&gpio4 11 0>; + status = "okay"; + }; + + esdhc@50008000 { /* ESDHC2 */ + fsl,card-wired; + status = "okay"; + }; + + uart3: uart@5000c000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + ecspi@50010000 { /* ECSPI1 */ + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; + status = "okay"; + + zigbee: mc1323@0 { + compatible = "fsl,mc1323"; + spi-max-frequency = <8000000>; + reg = <0>; + }; + + flash: m25p32@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "st,m25p"; + spi-max-frequency = <20000000>; + reg = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0x3c0000>; + }; + }; + }; + + esdhc@50020000 { /* ESDHC3 */ + fsl,card-wired; + status = "okay"; + }; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-smd"; + reg = <0x53fa8000 0x4000>; + }; + + uart1: uart@53fbc000 { + status = "okay"; + }; + + uart2: uart@53fc0000 { + status = "okay"; + }; + }; + + aips@60000000 { /* AIPS2 */ + sdma@63fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + i2c@63fc4000 { /* I2C2 */ + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + + magnetometer: mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + }; + + touchkey: mpr121@5a { + compatible = "fsl,mpr121"; + reg = <0x5a>; + }; + }; + + i2c@63fc8000 { /* I2C1 */ + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + camera: ov5642@3c { + compatible = "ovti,ov5642"; + reg = <0x3c>; + }; + + pmic: dialog@48 { + compatible = "dialog,da9053", "dialog,da9052"; + reg = <0x48>; + }; + }; + + fec@63fec000 { + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 14 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio2 15 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx53.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53.dtsi new file mode 100644 index 000000000..5dd91b942 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx53.dtsi @@ -0,0 +1,301 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + tzic: tz-interrupt-controller@0fffc000 { + compatible = "fsl,imx53-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x0fffc000 0x4000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + aips@50000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x10000000>; + ranges; + + spba@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x40000>; + ranges; + + esdhc@50004000 { /* ESDHC1 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50004000 0x4000>; + interrupts = <1>; + status = "disabled"; + }; + + esdhc@50008000 { /* ESDHC2 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50008000 0x4000>; + interrupts = <2>; + status = "disabled"; + }; + + uart3: uart@5000c000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + status = "disabled"; + }; + + ecspi@50010000 { /* ECSPI1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + status = "disabled"; + }; + + esdhc@50020000 { /* ESDHC3 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50020000 0x4000>; + interrupts = <3>; + status = "disabled"; + }; + + esdhc@50024000 { /* ESDHC4 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50024000 0x4000>; + interrupts = <4>; + status = "disabled"; + }; + }; + + gpio1: gpio@53f84000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@53f88000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@53f8c000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@53f90000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + wdog@53f98000 { /* WDOG1 */ + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + status = "disabled"; + }; + + wdog@53f9c000 { /* WDOG2 */ + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f9c000 0x4000>; + interrupts = <59>; + status = "disabled"; + }; + + uart1: uart@53fbc000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + status = "disabled"; + }; + + uart2: uart@53fc0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + status = "disabled"; + }; + + gpio5: gpio@53fdc000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fdc000 0x4000>; + interrupts = <103 104>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio6: gpio@53fe0000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fe0000 0x4000>; + interrupts = <105 106>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio7: gpio@53fe4000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fe4000 0x4000>; + interrupts = <107 108>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + i2c@53fec000 { /* I2C3 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x53fec000 0x4000>; + interrupts = <64>; + status = "disabled"; + }; + + uart4: uart@53ff0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + status = "disabled"; + }; + }; + + aips@60000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x60000000 0x10000000>; + ranges; + + uart5: uart@63f90000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + status = "disabled"; + }; + + ecspi@63fac000 { /* ECSPI2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + status = "disabled"; + }; + + sdma@63fb0000 { + compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; + reg = <0x63fb0000 0x4000>; + interrupts = <6>; + }; + + cspi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + status = "disabled"; + }; + + i2c@63fc4000 { /* I2C2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x63fc4000 0x4000>; + interrupts = <63>; + status = "disabled"; + }; + + i2c@63fc8000 { /* I2C1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x63fc8000 0x4000>; + interrupts = <62>; + status = "disabled"; + }; + + fec@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q-arm2.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q-arm2.dts new file mode 100644 index 000000000..ce1c8238c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q-arm2.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait"; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + soc { + aips-bus@02100000 { /* AIPS2 */ + enet@02188000 { + phy-mode = "rgmii"; + local-mac-address = [00 04 9F 01 1B 61]; + status = "okay"; + }; + + usdhc@02198000 { /* uSDHC3 */ + cd-gpios = <&gpio6 11 0>; + wp-gpios = <&gpio6 14 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + usdhc@0219c000 { /* uSDHC4 */ + fsl,card-wired; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + uart4: uart@021f0000 { + status = "okay"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + leds { + compatible = "gpio-leds"; + + debug-led { + label = "Heartbeat"; + gpios = <&gpio3 25 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q-sabrelite.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q-sabrelite.dts new file mode 100644 index 000000000..4663a4e5a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q-sabrelite.dts @@ -0,0 +1,83 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Lite Board"; + compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + soc { + aips-bus@02100000 { /* AIPS2 */ + enet@02188000 { + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; + status = "okay"; + }; + + usdhc@02198000 { /* uSDHC3 */ + cd-gpios = <&gpio7 0 0>; + wp-gpios = <&gpio7 1 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + usdhc@0219c000 { /* uSDHC4 */ + cd-gpios = <&gpio2 6 0>; + wp-gpios = <&gpio2 7 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + uart2: uart@021e8000 { + status = "okay"; + }; + + i2c@021a0000 { /* I2C1 */ + status = "okay"; + clock-frequency = <100000>; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q.dtsi new file mode 100644 index 000000000..4905f51a1 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/imx6q.dtsi @@ -0,0 +1,575 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + timer@00a00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x00a00600 0x20>; + interrupts = <1 13 0xf01>; + }; + + L2: l2-cache@00a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = <0 92 0x04>; + cache-unified; + cache-level = <2>; + }; + + aips-bus@02000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif@02004000 { + reg = <0x02004000 0x4000>; + interrupts = <0 52 0x04>; + }; + + ecspi@02008000 { /* eCSPI1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <0 31 0x04>; + status = "disabled"; + }; + + ecspi@0200c000 { /* eCSPI2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <0 32 0x04>; + status = "disabled"; + }; + + ecspi@02010000 { /* eCSPI3 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <0 33 0x04>; + status = "disabled"; + }; + + ecspi@02014000 { /* eCSPI4 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <0 34 0x04>; + status = "disabled"; + }; + + ecspi@02018000 { /* eCSPI5 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02018000 0x4000>; + interrupts = <0 35 0x04>; + status = "disabled"; + }; + + uart1: uart@02020000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <0 26 0x04>; + status = "disabled"; + }; + + esai@02024000 { + reg = <0x02024000 0x4000>; + interrupts = <0 51 0x04>; + }; + + ssi@02028000 { /* SSI1 */ + reg = <0x02028000 0x4000>; + interrupts = <0 46 0x04>; + }; + + ssi@0202c000 { /* SSI2 */ + reg = <0x0202c000 0x4000>; + interrupts = <0 47 0x04>; + }; + + ssi@02030000 { /* SSI3 */ + reg = <0x02030000 0x4000>; + interrupts = <0 48 0x04>; + }; + + asrc@02034000 { + reg = <0x02034000 0x4000>; + interrupts = <0 50 0x04>; + }; + + spba@0203c000 { + reg = <0x0203c000 0x4000>; + }; + }; + + vpu@02040000 { + reg = <0x02040000 0x3c000>; + interrupts = <0 3 0x04 0 12 0x04>; + }; + + aipstz@0207c000 { /* AIPSTZ1 */ + reg = <0x0207c000 0x4000>; + }; + + pwm@02080000 { /* PWM1 */ + reg = <0x02080000 0x4000>; + interrupts = <0 83 0x04>; + }; + + pwm@02084000 { /* PWM2 */ + reg = <0x02084000 0x4000>; + interrupts = <0 84 0x04>; + }; + + pwm@02088000 { /* PWM3 */ + reg = <0x02088000 0x4000>; + interrupts = <0 85 0x04>; + }; + + pwm@0208c000 { /* PWM4 */ + reg = <0x0208c000 0x4000>; + interrupts = <0 86 0x04>; + }; + + flexcan@02090000 { /* CAN1 */ + reg = <0x02090000 0x4000>; + interrupts = <0 110 0x04>; + }; + + flexcan@02094000 { /* CAN2 */ + reg = <0x02094000 0x4000>; + interrupts = <0 111 0x04>; + }; + + gpt@02098000 { + compatible = "fsl,imx6q-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <0 55 0x04>; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <0 66 0x04 0 67 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <0 68 0x04 0 69 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <0 70 0x04 0 71 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <0 72 0x04 0 73 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <0 74 0x04 0 75 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio6: gpio@020b0000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = <0 76 0x04 0 77 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio7: gpio@020b4000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020b4000 0x4000>; + interrupts = <0 78 0x04 0 79 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + kpp@020b8000 { + reg = <0x020b8000 0x4000>; + interrupts = <0 82 0x04>; + }; + + wdog@020bc000 { /* WDOG1 */ + compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <0 80 0x04>; + status = "disabled"; + }; + + wdog@020c0000 { /* WDOG2 */ + compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <0 81 0x04>; + status = "disabled"; + }; + + ccm@020c4000 { + compatible = "fsl,imx6q-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 0x04 0 88 0x04>; + }; + + anatop@020c8000 { + compatible = "fsl,imx6q-anatop"; + reg = <0x020c8000 0x1000>; + interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; + }; + + usbphy@020c9000 { /* USBPHY1 */ + reg = <0x020c9000 0x1000>; + interrupts = <0 44 0x04>; + }; + + usbphy@020ca000 { /* USBPHY2 */ + reg = <0x020ca000 0x1000>; + interrupts = <0 45 0x04>; + }; + + snvs@020cc000 { + reg = <0x020cc000 0x4000>; + interrupts = <0 19 0x04 0 20 0x04>; + }; + + epit@020d0000 { /* EPIT1 */ + reg = <0x020d0000 0x4000>; + interrupts = <0 56 0x04>; + }; + + epit@020d4000 { /* EPIT2 */ + reg = <0x020d4000 0x4000>; + interrupts = <0 57 0x04>; + }; + + src@020d8000 { + compatible = "fsl,imx6q-src"; + reg = <0x020d8000 0x4000>; + interrupts = <0 91 0x04 0 96 0x04>; + }; + + gpc@020dc000 { + compatible = "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = <0 89 0x04 0 90 0x04>; + }; + + iomuxc@020e0000 { + reg = <0x020e0000 0x4000>; + }; + + dcic@020e4000 { /* DCIC1 */ + reg = <0x020e4000 0x4000>; + interrupts = <0 124 0x04>; + }; + + dcic@020e8000 { /* DCIC2 */ + reg = <0x020e8000 0x4000>; + interrupts = <0 125 0x04>; + }; + + sdma@020ec000 { + compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = <0 2 0x04>; + }; + }; + + aips-bus@02100000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + caam@02100000 { + reg = <0x02100000 0x40000>; + interrupts = <0 105 0x04 0 106 0x04>; + }; + + aipstz@0217c000 { /* AIPSTZ2 */ + reg = <0x0217c000 0x4000>; + }; + + enet@02188000 { + compatible = "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupts = <0 118 0x04 0 119 0x04>; + status = "disabled"; + }; + + mlb@0218c000 { + reg = <0x0218c000 0x4000>; + interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; + }; + + usdhc@02190000 { /* uSDHC1 */ + compatible = "fsl,imx6q-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <0 22 0x04>; + status = "disabled"; + }; + + usdhc@02194000 { /* uSDHC2 */ + compatible = "fsl,imx6q-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <0 23 0x04>; + status = "disabled"; + }; + + usdhc@02198000 { /* uSDHC3 */ + compatible = "fsl,imx6q-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = <0 24 0x04>; + status = "disabled"; + }; + + usdhc@0219c000 { /* uSDHC4 */ + compatible = "fsl,imx6q-usdhc"; + reg = <0x0219c000 0x4000>; + interrupts = <0 25 0x04>; + status = "disabled"; + }; + + i2c@021a0000 { /* I2C1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <0 36 0x04>; + status = "disabled"; + }; + + i2c@021a4000 { /* I2C2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <0 37 0x04>; + status = "disabled"; + }; + + i2c@021a8000 { /* I2C3 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <0 38 0x04>; + status = "disabled"; + }; + + romcp@021ac000 { + reg = <0x021ac000 0x4000>; + }; + + mmdc@021b0000 { /* MMDC0 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + mmdc@021b4000 { /* MMDC1 */ + reg = <0x021b4000 0x4000>; + }; + + weim@021b8000 { + reg = <0x021b8000 0x4000>; + interrupts = <0 14 0x04>; + }; + + ocotp@021bc000 { + reg = <0x021bc000 0x4000>; + }; + + ocotp@021c0000 { + reg = <0x021c0000 0x4000>; + interrupts = <0 21 0x04>; + }; + + tzasc@021d0000 { /* TZASC1 */ + reg = <0x021d0000 0x4000>; + interrupts = <0 108 0x04>; + }; + + tzasc@021d4000 { /* TZASC2 */ + reg = <0x021d4000 0x4000>; + interrupts = <0 109 0x04>; + }; + + audmux@021d8000 { + reg = <0x021d8000 0x4000>; + }; + + mipi@021dc000 { /* MIPI-CSI */ + reg = <0x021dc000 0x4000>; + }; + + mipi@021e0000 { /* MIPI-DSI */ + reg = <0x021e0000 0x4000>; + }; + + vdoa@021e4000 { + reg = <0x021e4000 0x4000>; + interrupts = <0 18 0x04>; + }; + + uart2: uart@021e8000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = <0 27 0x04>; + status = "disabled"; + }; + + uart3: uart@021ec000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = <0 28 0x04>; + status = "disabled"; + }; + + uart4: uart@021f0000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = <0 29 0x04>; + status = "disabled"; + }; + + uart5: uart@021f4000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = <0 30 0x04>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/kirkwood-dreamplug.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/kirkwood-dreamplug.dts new file mode 100644 index 000000000..a5376b842 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/kirkwood-dreamplug.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +/include/ "kirkwood.dtsi" + +/ { + model = "Globalscale Technologies Dreamplug"; + compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + serial@12000 { + clock-frequency = <200000000>; + status = "ok"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/kirkwood.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/kirkwood.dtsi new file mode 100644 index 000000000..3474ef890 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/kirkwood.dtsi @@ -0,0 +1,36 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "mrvl,kirkwood"; + + ocp@f1000000 { + compatible = "simple-bus"; + ranges = <0 0xf1000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <33>; + /* set clock-frequency in board dts */ + status = "disabled"; + }; + + serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <34>; + /* set clock-frequency in board dts */ + status = "disabled"; + }; + + rtc@10300 { + compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-iommu.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-iommu.dtsi new file mode 100644 index 000000000..56369dce3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-iommu.dtsi @@ -0,0 +1,40 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm-iommu-v1.dtsi" + +&jpeg_iommu { + status = "ok"; + vdd-supply = <&gdsc_jpeg>; +}; + +&mdp_iommu { + status = "ok"; + vdd-supply = <&gdsc_mdss>; +}; + +&venus_iommu { + status = "ok"; + vdd-supply = <&gdsc_venus>; +}; + +&kgsl_iommu { + status = "ok"; + qcom,needs-alt-core-clk; + vdd-supply = <&gdsc_oxili_cx>; + qcom,alt-vdd-supply = <&gdsc_oxili_gx>; +}; + +&vfe_iommu { + status = "ok"; + vdd-supply = <&gdsc_vfe>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-ion.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-ion.dtsi new file mode 100644 index 000000000..f9f59850a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-ion.dtsi @@ -0,0 +1,33 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + }; +}; + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-regulator.dtsi new file mode 100644 index 000000000..63896e922 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-regulator.dtsi @@ -0,0 +1,324 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* QPNP controlled regulators: */ + +&spmi_bus { + + qcom,pma8084@1 { + pma8084_s1: regulator@1400 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s3: regulator@1a00 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s4: regulator@1d00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s5: regulator@2000 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_s6: regulator@2300 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_s8: regulator@2900 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_s12: regulator@3500 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_l1: regulator@4000 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <10000>; + status = "okay"; + }; + + pma8084_l2: regulator@4100 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l3: regulator@4200 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l4: regulator@4300 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l6: regulator@4500 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l9: regulator@4800 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l10: regulator@4900 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l11: regulator@4a00 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l12: regulator@4b00 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l13: regulator@4c00 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l14: regulator@4d00 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l15: regulator@4e00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l16: regulator@4f00 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l17: regulator@5000 { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_l18: regulator@5100 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l19: regulator@5200 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l20: regulator@5300 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l21: regulator@5400 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l22: regulator@5500 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l23: regulator@5600 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l24: regulator@5700 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l25: regulator@5800 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + pma8084_l26: regulator@5900 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + pma8084_l27: regulator@5A00 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs1: regulator@8000 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs2: regulator@8100 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs3: regulator@8200 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs4: regulator@8300 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_mvs1: regulator@8400 { + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + }; +}; + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-rumi.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-rumi.dts new file mode 100644 index 000000000..1abaf5596 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-rumi.dts @@ -0,0 +1,28 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "mpq8092.dtsi" +/include/ "mpq8092-rumi.dtsi" + +/ { + model = "Qualcomm MPQ8092 RUMI"; + compatible = "qcom,mpq8092-rumi", "qcom,mpq8092", "qcom,rumi"; + qcom,msm-id = <146 16 0>; +}; + +&soc { + serial@f9922000 { + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-rumi.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-rumi.dtsi new file mode 100644 index 000000000..201699882 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-rumi.dtsi @@ -0,0 +1,134 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + timer { + clock-frequency = <5000000>; + }; + + timer@f9020000 { + clock-frequency = <5000000>; + }; + + usb@f9a55000 { + status = "disable"; + }; + + qcom,sdcc@f9824000 { + status = "disabled"; + qcom,clk-rates = <400000 19200000>; + }; + + qcom,sdcc@f98a4000 { + status = "disabled"; + qcom,clk-rates = <400000 19200000>; + }; + + qcom,sps@f998000 { + status = "disable"; + }; + + spi@f9924000 { + status = "disable"; + }; + + spi@f9923000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 0>; + spi-max-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 3 0>, /* CLK */ + <&msmgpio 1 0>, /* MISO */ + <&msmgpio 0 0>; /* MOSI */ + cs-gpios = <&msmgpio 9 0>; + + ethernet-switch@2 { + compatible = "simtec,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <90 0>; + spi-max-frequency = <5000000>; + }; + }; + + i2c@f9966000 { + status = "disable"; + }; + + i2c@f9967000 { + status = "disable"; + cell-index = <0>; + compatible = "qcom,i2c-qup"; + reg = <0Xf9967000 0x1000>; + reg-names = "qup_phys_addr"; + interrupts = <0 105 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + gpios = <&msmgpio 83 0>,/* DAT */ + <&msmgpio 84 0>;/* CLK */ + }; + + slim@fe12f000 { + status = "disable"; + }; + + qcom,mdss_dsi@fd922800 { + status = "disable"; + }; + + qcom,spmi@fc4c0000 { + status = "disable"; + }; + + qcom,ssusb@F9200000 { + status = "disable"; + }; + + qcom,lpass@fe200000 { + status = "disable"; + }; + + qcom,pronto@fb21b000 { + status = "disable"; + }; + + qcom,mss@fc880000 { + status = "disable"; + }; + + qcom,kgsl-3d0@fdb00000 { + status = "disabled"; + }; +}; + +&gdsc_venus { + status = "disabled"; +}; + +&gdsc_jpeg { + status = "disabled"; +}; + +&gdsc_oxili_gx { + status = "disabled"; +}; + +&gdsc_oxili_cx { + status = "disabled"; +}; + +&gdsc_usb_hsic { + status = "disabled"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-sim.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-sim.dts new file mode 100644 index 000000000..676ef3b17 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092-sim.dts @@ -0,0 +1,125 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "mpq8092.dtsi" + +/ { + model = "Qualcomm MPQ8092 Simulator"; + compatible = "qcom,mpq8092-sim", "qcom,mpq8092", "qcom,sim"; + qcom,msm-id = <126 16 0>; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; + + serial@f995e000 { + status = "ok"; + }; +}; + +&pma8084_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + }; + + gpio@cf00 { /* GPIO 16 */ + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; +}; + +&pma8084_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092.dtsi new file mode 100644 index 000000000..e8674a055 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/mpq8092.dtsi @@ -0,0 +1,240 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MPQ8092"; + compatible = "qcom,mpq8092"; + interrupt-parent = <&intc>; + + soc: soc { }; +}; + +/include/ "mpq8092-iommu.dtsi" +/include/ "msm-gdsc.dtsi" +/include/ "mpq8092-ion.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <146>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0>, <1 3 0>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + serial@f9922000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf9922000 0x1000>; + interrupts = <0 112 0>; + status = "disabled"; + }; + + serial@f995e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf995e000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0 0 187 0>; + qcom,not-wakeup; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>; + reg-names = "core_mem"; + interrupts = <0 123 0>; + interrupt-names = "core_irq"; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <8>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>; + reg-names = "core_mem"; + interrupts = <0 125 0>; + interrupt-names = "core_irq"; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <4>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + }; + + sata: sata@fc580000 { + compatible = "qcom,msm-ahci"; + reg = <0xfc580000 0x17c>; + interrupts = <0 243 0>; + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + }; +}; + +&gdsc_venus { + status = "ok"; +}; + +&gdsc_mdss { + status = "ok"; +}; + +&gdsc_jpeg { + status = "ok"; +}; + +&gdsc_oxili_gx { + status = "ok"; +}; + +&gdsc_oxili_cx { + status = "ok"; +}; + +&gdsc_usb_hsic { + status = "ok"; +}; + +/include/ "msm-pma8084.dtsi" +/include/ "mpq8092-regulator.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-gdsc.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-gdsc.dtsi new file mode 100644 index 000000000..78234e858 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-gdsc.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + gdsc_venus: qcom,gdsc@fd8c1024 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus"; + reg = <0xfd8c1024 0x4>; + status = "disabled"; + }; + + gdsc_mdss: qcom,gdsc@fd8c2304 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_mdss"; + reg = <0xfd8c2304 0x4>; + status = "disabled"; + }; + + gdsc_jpeg: qcom,gdsc@fd8c35a4 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_jpeg"; + reg = <0xfd8c35a4 0x4>; + status = "disabled"; + }; + + gdsc_vfe: qcom,gdsc@fd8c36a4 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe"; + reg = <0xfd8c36a4 0x4>; + status = "disabled"; + }; + + gdsc_oxili_gx: qcom,gdsc@fd8c4024 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_gx"; + reg = <0xfd8c4024 0x4>; + status = "disabled"; + }; + + gdsc_oxili_cx: qcom,gdsc@fd8c4034 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_cx"; + reg = <0xfd8c4034 0x4>; + status = "disabled"; + }; + + gdsc_usb_hsic: qcom,gdsc@fc400404 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_usb_hsic"; + reg = <0xfc400404 0x4>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-iommu-v0.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-iommu-v0.dtsi new file mode 100644 index 000000000..2cfc5cf07 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-iommu-v0.dtsi @@ -0,0 +1,333 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + lpass_iommu: qcom,iommu@fd000000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd000000 0x10000>; + interrupts = <0 248 0>; + qcom,glb-offset = <0xF000>; + label = "lpass_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "lpass_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <11 512 0 0>, + <11 512 0 1000>; + status = "disabled"; + + lpass_q6_fw: qcom,iommu-ctx@fd000000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd000000 0x1000>; + interrupts = <0 250 0>; + qcom,iommu-ctx-mids = <0 15>; + label = "q6_fw"; + }; + + lpass_audio_shared: qcom,iommu-ctx@fd001000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd001000 0x1000>; + interrupts = <0 250 0>; + qcom,iommu-ctx-mids = <1>; + label = "audio_shared"; + }; + + lpass_video_shared: qcom,iommu-ctx@fd002000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd002000 0x1000>; + interrupts = <0 250 0>; + qcom,iommu-ctx-mids = <2>; + label = "video_shared"; + }; + + lpass_q6_spare: qcom,iommu-ctx@fd003000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd003000 0x1000>; + interrupts = <0 250 0>; + qcom,iommu-ctx-mids = <3 4 5 6 7 8 9 10 11 12 13 14>; + label = "q6_spare"; + }; + }; + + copss_iommu: qcom,iommu@fd010000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd010000 0x10000>; + interrupts = <0 252 0>; + qcom,glb-offset = <0xF000>; + label = "copss_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "copss_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <88 512 0 0>, + <88 512 0 1000>; + + status = "disabled"; + + qcom,iommu-ctx@fd010000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd010000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <0>; + label = "copss_0"; + }; + + qcom,iommu-ctx@fd011000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd011000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <1>; + label = "copss_1"; + }; + + qcom,iommu-ctx@fd012000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd012000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <2>; + label = "copss_2"; + }; + + qcom,iommu-ctx@fd013000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd013000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <3>; + label = "copss_3"; + }; + + qcom,iommu-ctx@fd014000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd014000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <4>; + label = "copss_4"; + }; + + qcom,iommu-ctx@fd015000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd015000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <5>; + label = "copss_5"; + }; + + qcom,iommu-ctx@fd016000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd016000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <6>; + label = "copss_6"; + }; + + qcom,iommu-ctx@fd017000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd017000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <7>; + label = "copss_7"; + }; + }; + + mdpe_iommu: qcom,iommu@fd860000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd860000 0x10000>; + interrupts = <0 245 0>; + qcom,glb-offset = <0xF000>; + label = "mdpe_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "mdpe_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <92 512 0 0>, + <92 512 0 1000>; + status = "disabled"; + + qcom,iommu-ctx@fd860000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd860000 0x1000>; + interrupts = <0 247 0>; + qcom,iommu-ctx-mids = <0 1 3>; + label = "mdpe_0"; + }; + + qcom,iommu-ctx@fd861000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd861000 0x1000>; + interrupts = <0 247 0>; + qcom,iommu-ctx-mids = <2>; + label = "mdpe_1"; + }; + }; + + mdps_iommu: qcom,iommu@fd870000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd870000 0x10000>; + interrupts = <0 73 0>; + qcom,glb-offset = <0xF000>; + label = "mdps_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "mdps_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + status = "disabled"; + + qcom,iommu-ctx@fd870000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd870000 0x1000>; + interrupts = <0 47 0>; + qcom,iommu-ctx-mids = <0>; + label = "mdps_0"; + }; + + qcom,iommu-ctx@fd871000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd871000 0x1000>; + interrupts = <0 47 0>; + qcom,iommu-ctx-mids = <1>; + label = "mdps_1"; + }; + }; + + gfx_iommu: qcom,iommu@fd880000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd880000 0x10000>; + interrupts = <0 38 0>; + qcom,glb-offset = <0xF000>; + qcom,needs-alt-core-clk; + label = "gfx_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "gfx_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 1000>; + status = "disabled"; + + qcom,iommu-ctx@fd880000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd880000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-mids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 + 14 15>; + label = "gfx3d_user"; + }; + + qcom,iommu-ctx@fd881000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd881000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-mids = <16 17 18 19 20 21 22 23 24 25 + 26 27 28 29 30 31>; + label = "gfx3d_priv"; + }; + + qcom,iommu-ctx@fd882000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd882000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-mids = <>; + label = "gfx3d_spare"; + }; + }; + + vfe_iommu: qcom,iommu@fd890000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd890000 0x10000>; + interrupts = <0 62 0>; + qcom,glb-offset = <0xF000>; + label = "vfe_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "vfe_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 0 1000>; + status = "disabled"; + + qcom,iommu-ctx@fd890000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd890000 0x1000>; + interrupts = <0 65 0>; + qcom,iommu-ctx-mids = <0 1 2 3 4 5 6 7 8 9>; + label = "vfe0"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-iommu-v1.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-iommu-v1.dtsi new file mode 100644 index 000000000..44920778e --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-iommu-v1.dtsi @@ -0,0 +1,514 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + jpeg_iommu: qcom,iommu@fda64000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfda64000 0x10000>; + reg-names = "iommu_base"; + interrupts = <0 67 0>; + qcom,needs-alt-core-clk; + label = "jpeg_iommu"; + status = "disabled"; + qcom,msm-bus,name = "jpeg_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <62 512 0 0>, + <62 512 0 1000>; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014>; + + qcom,iommu-bfb-data = <0x0000ffff + 0x0 + 0x4 + 0x4 + 0x0 + 0x0 + 0x10 + 0x50 + 0x0 + 0x10 + 0x20 + 0x0 + 0x0 + 0x0 + 0x0>; + + qcom,iommu-ctx@fda6c000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda6c000 0x1000>; + interrupts = <0 70 0>; + qcom,iommu-ctx-sids = <0>; + label = "jpeg_enc0"; + }; + + qcom,iommu-ctx@fda6d000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda6d000 0x1000>; + interrupts = <0 70 0>; + qcom,iommu-ctx-sids = <1>; + label = "jpeg_enc1"; + }; + + qcom,iommu-ctx@fda6e000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda6e000 0x1000>; + interrupts = <0 70 0>; + qcom,iommu-ctx-sids = <2>; + label = "jpeg_dec"; + }; + }; + + mdp_iommu: qcom,iommu@fd928000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd928000 0x10000>; + reg-names = "iommu_base"; + interrupts = <0 73 0>; + qcom,iommu-secure-id = <1>; + label = "mdp_iommu"; + qcom,msm-bus,name = "mdp_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + status = "disabled"; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x0 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000034 + 0x00000044 + 0x0 + 0x34 + 0x74 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; + + qcom,iommu-ctx@fd930000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfd930000 0x1000>; + interrupts = <0 47 0>; + qcom,iommu-ctx-sids = <0>; + label = "mdp_0"; + }; + + qcom,iommu-ctx@fd931000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfd931000 0x1000>; + interrupts = <0 47 0>, <0 46 0>; + qcom,iommu-ctx-sids = <1>; + label = "mdp_1"; + qcom,secure-context; + }; + + qcom,iommu-ctx@fd932000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfd932000 0x1000>; + interrupts = <0 47 0>, <0 46 0>; + qcom,iommu-ctx-sids = <>; + label = "mdp_2"; + qcom,secure-context; + }; + }; + + venus_iommu: qcom,iommu@fdc84000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfdc84000 0x10000 + 0xfdce0004 0x4>; + reg-names = "iommu_base", "clk_base"; + interrupts = <0 45 0>; + qcom,iommu-secure-id = <0>; + qcom,needs-alt-core-clk; + label = "venus_iommu"; + qcom,msm-bus,name = "venus_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 1000>; + status = "disabled"; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020 + 0x2024 + 0x2028 + 0x202c + 0x2030 + 0x2034 + 0x2038>; + + qcom,iommu-bfb-data = <0xffffffff + 0xffffffff + 0x00000004 + 0x00000008 + 0x00000000 + 0x00000000 + 0x00000094 + 0x000000b4 + 0x0 + 0x94 + 0x114 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; + + venus_ns: qcom,iommu-ctx@fdc8c000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc8c000 0x1000>; + interrupts = <0 42 0>; + qcom,iommu-ctx-sids = <0 1 2 3 4 5>; + label = "venus_ns"; + }; + + venus_cp: qcom,iommu-ctx@fdc8d000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc8d000 0x1000>; + interrupts = <0 42 0>, <0 43 0>; + qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84 0x85>; + label = "venus_cp"; + qcom,secure-context; + }; + + venus_fw: qcom,iommu-ctx@fdc8e000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc8e000 0x1000>; + interrupts = <0 42 0>, <0 43 0>; + qcom,iommu-ctx-sids = <0xc0 0xc6>; + label = "venus_fw"; + qcom,secure-context; + }; + }; + + kgsl_iommu: qcom,iommu@fdb10000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfdb10000 0x10000>; + reg-names = "iommu_base"; + interrupts = <0 38 0>; + label = "kgsl_iommu"; + qcom,msm-bus,name = "kgsl_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 1000>; + status = "disabled"; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008>; + + qcom,iommu-bfb-data = <0x00000003 + 0x0 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000021 + 0x0 + 0x1 + 0x81 + 0x0>; + + qcom,iommu-ctx@fdb18000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdb18000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-sids = <0>; + label = "gfx3d_user"; + }; + + qcom,iommu-ctx@fdb19000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdb19000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-sids = <1>; + label = "gfx3d_priv"; + }; + }; + + vfe_iommu: qcom,iommu@fda44000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfda44000 0x10000>; + reg-names = "iommu_base"; + interrupts = <0 62 0>; + qcom,needs-alt-core-clk; + label = "vfe_iommu"; + qcom,msm-bus,name = "vfe_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 0 1000>; + status = "disabled"; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x00000000 + 0x4 + 0x8 + 0x0 + 0x0 + 0x20 + 0x78 + 0x0 + 0x20 + 0x36 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; + + qcom,iommu-ctx@fda4c000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda4c000 0x1000>; + interrupts = <0 65 0>; + qcom,iommu-ctx-sids = <0>; + label = "vfe0"; + }; + + qcom,iommu-ctx@fda4d000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda4d000 0x1000>; + interrupts = <0 65 0>; + qcom,iommu-ctx-sids = <1>; + label = "vfe1"; + }; + + qcom,iommu-ctx@fda4e000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda4e000 0x1000>; + interrupts = <0 65 0>; + qcom,iommu-ctx-sids = <2>; + label = "cpp"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8019-rpm-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8019-rpm-regulator.dtsi new file mode 100644 index 000000000..c48f67dca --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8019-rpm-regulator.dtsi @@ -0,0 +1,301 @@ +/* Copyright (c) 2012, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa1 { + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s1 { + regulator-name = "8019_s1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa2 { + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s2 { + regulator-name = "8019_s2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa3 { + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s3 { + regulator-name = "8019_s3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa4 { + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s4 { + regulator-name = "8019_s4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa1 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l1 { + regulator-name = "8019_l1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa2 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l2 { + regulator-name = "8019_l2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa3 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l3 { + regulator-name = "8019_l3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa4 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l4 { + regulator-name = "8019_l4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa5 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l5 { + regulator-name = "8019_l5"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa6 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l6 { + regulator-name = "8019_l6"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa7 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l7 { + regulator-name = "8019_l7"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa8 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l8 { + regulator-name = "8019_l8"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa9 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l9 { + regulator-name = "8019_l9"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa10 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l10 { + regulator-name = "8019_l10"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa11 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l11 { + regulator-name = "8019_l11"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa12 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l12 { + regulator-name = "8019_l12"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa13 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l13 { + regulator-name = "8019_l13"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa14 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l14 { + regulator-name = "8019_l14"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8019.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8019.dtsi new file mode 100755 index 000000000..6b5edf7ea --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8019.dtsi @@ -0,0 +1,415 @@ +/* Copyright (c) 2012-2013, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8019@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power_on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x2>; + interrupt-names = "cblpwr"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + + qcom,pon_1 { + qcom,pon-type = <2>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + }; + + clkdiv@5b00 { + reg = <0x5b00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + clkdiv@5c00 { + reg = <0x5c00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + clkdiv@5d00 { + reg = <0x5d00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8019_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm8019_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + + pm8019_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8019-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + }; + }; + + pm8019_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8019-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + + mpp@a400 { + reg = <0xa400 0x100>; + qcom,pin-num = <5>; + }; + + mpp@a500 { + reg = <0xa500 0x100>; + qcom,pin-num = <6>; + }; + }; + + pm8019_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,vadc-poll-eoc; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + pm8019_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + }; + }; + + qcom,pm8019@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8019_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8019_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8019_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8019_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@4000 { + regulator-name = "8019_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8019_l2"; + reg = <0x4100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8019_l3"; + reg = <0x4200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8019_l4"; + reg = <0x4300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8019_l5"; + reg = <0x4400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8019_l6"; + reg = <0x4500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8019_l7"; + reg = <0x4600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8019_l8"; + reg = <0x4700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8019_l9"; + reg = <0x4800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8019_l10"; + reg = <0x4900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4a00 { + regulator-name = "8019_l11"; + reg = <0x4a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8019_l12"; + reg = <0x4b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4c00 { + regulator-name = "8019_l13"; + reg = <0x4c00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8019_l14"; + reg = <0x4d00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8019_ldo_xo"; + reg = <0x4e00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8019_ldo_rfclk"; + reg = <0x4f00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8110-rpm-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8110-rpm-regulator.dtsi new file mode 100644 index 000000000..0de72b0de --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8110-rpm-regulator.dtsi @@ -0,0 +1,381 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l8"; + qcom,set = <1>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8110.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8110.dtsi new file mode 100644 index 000000000..1877f40d7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8110.dtsi @@ -0,0 +1,608 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8110@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0>, + <0x0 0x8 0x1>, + <0x0 0x8 0x4>; + interrupt-names = "kpdpwr", "resin", "resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + }; + + pm8110_chg: qcom,charger { + spmi-dev-container; + compatible = "qcom,qpnp-charger"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,vddmax-mv = <4200>; + qcom,vddsafe-mv = <4230>; + qcom,vinmin-mv = <4200>; + qcom,vbatdet-mv = <4100>; + qcom,ibatmax-ma = <1500>; + qcom,ibatterm-ma = <200>; + qcom,ibatsafe-ma = <1500>; + qcom,thermal-mitigation = <1500 700 600 325>; + qcom,vbatdet-delta-mv = <350>; + qcom,tchg-mins = <150>; + + qcom,chgr@1000 { + status = "disabled"; + reg = <0x1000 0x100>; + interrupts = <0x0 0x10 0x0>, + <0x0 0x10 0x1>, + <0x0 0x10 0x2>, + <0x0 0x10 0x3>, + <0x0 0x10 0x4>, + <0x0 0x10 0x5>, + <0x0 0x10 0x6>, + <0x0 0x10 0x7>; + + interrupt-names = "vbat-det-lo", + "vbat-det-hi", + "chgwdog", + "state-change", + "trkl-chg-on", + "fast-chg-on", + "chg-failed", + "chg-done"; + }; + + qcom,buck@1100 { + status = "disabled"; + reg = <0x1100 0x100>; + interrupts = <0x0 0x11 0x0>, + <0x0 0x11 0x1>, + <0x0 0x11 0x2>, + <0x0 0x11 0x3>, + <0x0 0x11 0x4>, + <0x0 0x11 0x5>, + <0x0 0x11 0x6>; + + interrupt-names = "vbat-ov", + "vreg-ov", + "overtemp", + "vchg-loop", + "ichg-loop", + "ibat-loop", + "vdd-loop"; + }; + + qcom,bat-if@1200 { + status = "disabled"; + reg = <0x1200 0x100>; + interrupts = <0x0 0x12 0x0>, + <0x0 0x12 0x1>, + <0x0 0x12 0x2>, + <0x0 0x12 0x3>, + <0x0 0x12 0x4>; + + interrupt-names = "batt-pres", + "bat-temp-ok", + "bat-fet-on", + "vcp-on", + "psi"; + }; + + qcom,usb-chgpth@1300 { + status = "disabled"; + reg = <0x1300 0x100>; + interrupts = <0 0x13 0x0>, + <0 0x13 0x1>, + <0x0 0x13 0x2>; + + interrupt-names = "coarse-det-usb", + "usbin-valid", + "chg-gone"; + }; + + qcom,chg-misc@1600 { + status = "disabled"; + reg = <0x1600 0x100>; + }; + }; + + pm8110_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8110-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + }; + + pm8110_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8110-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + }; + + pm8110_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + iadc@3600 { + compatible = "qcom,qpnp-iadc"; + reg = <0x3600 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x36 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <16>; + qcom,adc-vdd-reference = <1800>; + + chan@0 { + label = "internal_rsense"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + pm8110_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0>; + label = "pm8110_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + }; + + pm8110_bms: qcom,bms { + spmi-dev-container; + compatible = "qcom,qpnp-bms"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,r-sense-uohm = <10000>; + qcom,v-cutoff-uv = <3400000>; + qcom,max-voltage-uv = <4200000>; + qcom,r-conn-mohm = <0>; + qcom,shutdown-soc-valid-limit = <20>; + qcom,adjust-soc-low-threshold = <15>; + qcom,ocv-voltage-high-threshold-uv = <3750000>; + qcom,ocv-voltage-low-threshold-uv = <3650000>; + qcom,low-soc-calculate-soc-threshold = <15>; + qcom,low-soc-calculate-soc-ms = <5000>; + qcom,calculate-soc-ms = <20000>; + qcom,chg-term-ua = <100000>; + qcom,batt-type = <0>; + qcom,low-voltage-threshold = <3420000>; + qcom,tm-temp-margin = <5000>; + qcom,low-ocv-correction-limit-uv = <100>; + qcom,high-ocv-correction-limit-uv = <50>; + qcom,hold-soc-est = <3>; + + qcom,bms-iadc@3800 { + reg = <0x3800 0x100>; + }; + + qcom,bms-bms@4000 { + reg = <0x4000 0x100>; + interrupts = <0x0 0x40 0x0>, + <0x0 0x40 0x1>, + <0x0 0x40 0x2>, + <0x0 0x40 0x3>, + <0x0 0x40 0x4>, + <0x0 0x40 0x5>, + <0x0 0x40 0x6>, + <0x0 0x40 0x7>; + + interrupt-names = "vsense_for_r", + "vsense_avg", + "sw_cc_thr", + "ocv_thr", + "charge_begin", + "good_ocv", + "ocv_for_r", + "cc_thr"; + }; + }; + + qcom,pm8110_rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8110_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm8110_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + + qcom,leds@a100 { + compatible = "qcom,leds-qpnp"; + reg = <0xa100 0x100>; + label = "mpp"; + }; + + qcom,leds@a200 { + compatible = "qcom,leds-qpnp"; + reg = <0xa200 0x100>; + label = "mpp"; + }; + }; + + qcom,pm8110@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@4000 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l1"; + reg = <0x4000 0x100>; + status = "disabled"; + }; + + regulator@4100 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l2"; + reg = <0x4100 0x100>; + status = "disabled"; + }; + + regulator@4200 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l3"; + reg = <0x4200 0x100>; + status = "disabled"; + }; + + regulator@4300 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l4"; + reg = <0x4300 0x100>; + status = "disabled"; + }; + + regulator@4400 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l5"; + reg = <0x4400 0x100>; + status = "disabled"; + }; + + regulator@4500 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l6"; + reg = <0x4500 0x100>; + status = "disabled"; + }; + + regulator@4600 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l7"; + reg = <0x4600 0x100>; + status = "disabled"; + }; + + regulator@4700 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l8"; + reg = <0x4700 0x100>; + status = "disabled"; + }; + + regulator@4800 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l9"; + reg = <0x4800 0x100>; + status = "disabled"; + }; + + regulator@4900 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l10"; + reg = <0x4900 0x100>; + status = "disabled"; + }; + + regulator@4b00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l12"; + reg = <0x4b00 0x100>; + status = "disabled"; + }; + + regulator@4d00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l14"; + reg = <0x4d00 0x100>; + status = "disabled"; + }; + + regulator@4e00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l15"; + reg = <0x4e00 0x100>; + status = "disabled"; + }; + + regulator@4f00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l16"; + reg = <0x4f00 0x100>; + status = "disabled"; + }; + + regulator@5000 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l17"; + reg = <0x5000 0x100>; + status = "disabled"; + }; + + regulator@5100 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l18"; + reg = <0x5100 0x100>; + status = "disabled"; + }; + + regulator@5200 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l19"; + reg = <0x5200 0x100>; + status = "disabled"; + }; + + regulator@5300 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l20"; + reg = <0x5300 0x100>; + status = "disabled"; + }; + + regulator@5400 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l21"; + reg = <0x5400 0x100>; + status = "disabled"; + }; + + regulator@5500 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l22"; + reg = <0x5500 0x100>; + status = "disabled"; + }; + + qcom,vibrator@c000 { + compatible = "qcom,qpnp-vibrator"; + reg = <0xc000 0x100>; + label = "vibrator"; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8226-rpm-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8226-rpm-regulator.dtsi new file mode 100644 index 000000000..ded949489 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8226-rpm-regulator.dtsi @@ -0,0 +1,492 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l8"; + qcom,set = <1>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa24 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l24 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l24"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa26 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <26>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l26 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l26"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa27 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <27>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l27 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l27"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa28 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <28>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l28 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l28"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-vsa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "vsa"; + qcom,resource-id = <1>; + qcom,regulator-type = <2>; + status = "disabled"; + + regulator-lvs1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_lvs1"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8226.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8226.dtsi new file mode 100644 index 000000000..d429f72b7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8226.dtsi @@ -0,0 +1,833 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8226@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0>, + <0x0 0x8 0x1>, + <0x0 0x8 0x4>; + interrupt-names = "kpdpwr", "resin", "resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <0>; + qcom,s2-timer = <2000>; + qcom,s2-type = <1>; + linux,code = <114>; + }; + }; + + pm8226_chg: qcom,charger { + spmi-dev-container; + compatible = "qcom,qpnp-charger"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,vddmax-mv = <4200>; + qcom,vddsafe-mv = <4230>; + qcom,vinmin-mv = <4200>; + qcom,vbatdet-delta-mv = <150>; + qcom,ibatmax-ma = <1500>; + qcom,ibatterm-ma = <100>; + qcom,ibatsafe-ma = <1500>; + qcom,thermal-mitigation = <1500 700 600 325>; + qcom,tchg-mins = <150>; + + qcom,chgr@1000 { + status = "disabled"; + reg = <0x1000 0x100>; + interrupts = <0x0 0x10 0x0>, + <0x0 0x10 0x1>, + <0x0 0x10 0x2>, + <0x0 0x10 0x3>, + <0x0 0x10 0x4>, + <0x0 0x10 0x5>, + <0x0 0x10 0x6>, + <0x0 0x10 0x7>; + + interrupt-names = "vbat-det-lo", + "vbat-det-hi", + "chgwdog", + "state-change", + "trkl-chg-on", + "fast-chg-on", + "chg-failed", + "chg-done"; + }; + + qcom,buck@1100 { + status = "disabled"; + reg = <0x1100 0x100>; + interrupts = <0x0 0x11 0x0>, + <0x0 0x11 0x1>, + <0x0 0x11 0x2>, + <0x0 0x11 0x3>, + <0x0 0x11 0x4>, + <0x0 0x11 0x5>, + <0x0 0x11 0x6>; + + interrupt-names = "vbat-ov", + "vreg-ov", + "overtemp", + "vchg-loop", + "ichg-loop", + "ibat-loop", + "vdd-loop"; + }; + + qcom,bat-if@1200 { + status = "disabled"; + reg = <0x1200 0x100>; + interrupts = <0x0 0x12 0x0>, + <0x0 0x12 0x1>, + <0x0 0x12 0x2>, + <0x0 0x12 0x3>, + <0x0 0x12 0x4>; + + interrupt-names = "batt-pres", + "bat-temp-ok", + "bat-fet-on", + "vcp-on", + "psi"; + + }; + + pm8226_chg_otg: qcom,usb-chgpth@1300 { + status = "disabled"; + reg = <0x1300 0x100>; + interrupts = <0 0x13 0x0>, + <0 0x13 0x1>, + <0x0 0x13 0x2>; + + interrupt-names = "coarse-det-usb", + "usbin-valid", + "chg-gone"; + }; + + pm8226_chg_boost: qcom,boost@1500 { + status = "disabled"; + reg = <0x1500 0x100>; + interrupts = <0x0 0x15 0x0>, + <0x0 0x15 0x1>; + + interrupt-names = "boost-pwr-ok", + "limit-error"; + }; + + qcom,chg-misc@1600 { + status = "disabled"; + reg = <0x1600 0x100>; + }; + }; + + pm8226_bms: qcom,bms { + spmi-dev-container; + compatible = "qcom,qpnp-bms"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,r-sense-uohm = <10000>; + qcom,v-cutoff-uv = <3400000>; + qcom,max-voltage-uv = <4200000>; + qcom,r-conn-mohm = <0>; + qcom,shutdown-soc-valid-limit = <20>; + qcom,adjust-soc-low-threshold = <15>; + qcom,ocv-voltage-high-threshold-uv = <3750000>; + qcom,ocv-voltage-low-threshold-uv = <3650000>; + qcom,low-soc-calculate-soc-threshold = <15>; + qcom,low-soc-calculate-soc-ms = <5000>; + qcom,calculate-soc-ms = <20000>; + qcom,chg-term-ua = <100000>; + qcom,batt-type = <0>; + qcom,tm-temp-margin = <5000>; + qcom,low-ocv-correction-limit-uv = <100>; + qcom,high-ocv-correction-limit-uv = <50>; + qcom,hold-soc-est = <3>; + qcom,low-voltage-threshold = <3420000>; + + qcom,bms-iadc@3800 { + reg = <0x3800 0x100>; + }; + + qcom,bms-bms@4000 { + reg = <0x4000 0x100>; + interrupts = <0x0 0x40 0x0>, + <0x0 0x40 0x1>, + <0x0 0x40 0x2>, + <0x0 0x40 0x3>, + <0x0 0x40 0x4>, + <0x0 0x40 0x5>, + <0x0 0x40 0x6>, + <0x0 0x40 0x7>; + + interrupt-names = "vsense_for_r", + "vsense_avg", + "sw_cc_thr", + "ocv_thr", + "charge_begin", + "good_ocv", + "ocv_for_r", + "cc_thr"; + }; + }; + + qcom,leds@a100 { + compatible = "qcom,leds-qpnp"; + reg = <0xa100 0x100>; + label = "mpp"; + }; + + qcom,leds@a300 { + compatible = "qcom,leds-qpnp"; + reg = <0xa300 0x100>; + label = "mpp"; + }; + + qcom,leds@a500 { + compatible = "qcom,leds-qpnp"; + reg = <0xa500 0x100>; + label = "mpp"; + }; + + pm8226_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8226-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + }; + }; + + pm8226_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8226-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + + mpp@a400 { + reg = <0xa400 0x100>; + qcom,pin-num = <5>; + }; + + mpp@a500 { + reg = <0xa500 0x100>; + qcom,pin-num = <6>; + }; + + mpp@a600 { + reg = <0xa600 0x100>; + qcom,pin-num = <7>; + }; + + mpp@a700 { + reg = <0xa700 0x100>; + qcom,pin-num = <8>; + }; + }; + + pm8226_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@c { + label = "ref_buf_625mv"; + reg = <0xc>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + iadc@3600 { + compatible = "qcom,qpnp-iadc"; + reg = <0x3600 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x36 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <16>; + qcom,adc-vdd-reference = <1800>; + + chan@0 { + label = "internal_rsense"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + pm8226_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0>; + label = "pm8226_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + }; + + qcom,pm8226_rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8226_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm8226_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + }; + + qcom,pm8226@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8226_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8226_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8226_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8226_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@2000 { + regulator-name = "8226_s5"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2000 0x300>; + status = "disabled"; + + qcom,ctl@2000 { + reg = <0x2000 0x100>; + }; + qcom,ps@2100 { + reg = <0x2100 0x100>; + }; + qcom,freq@2200 { + reg = <0x2200 0x100>; + }; + }; + + regulator@4000 { + regulator-name = "8226_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8226_l2"; + reg = <0x4100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8226_l3"; + reg = <0x4200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8226_l4"; + reg = <0x4300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8226_l5"; + reg = <0x4400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8226_l6"; + reg = <0x4500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8226_l7"; + reg = <0x4600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8226_l8"; + reg = <0x4700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8226_l9"; + reg = <0x4800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8226_l10"; + reg = <0x4900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8226_l12"; + reg = <0x4b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8226_l14"; + reg = <0x4d00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8226_l15"; + reg = <0x4e00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8226_l16"; + reg = <0x4f00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5000 { + regulator-name = "8226_l17"; + reg = <0x5000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5100 { + regulator-name = "8226_l18"; + reg = <0x5100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5200 { + regulator-name = "8226_l19"; + reg = <0x5200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5300 { + regulator-name = "8226_l20"; + reg = <0x5300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5400 { + regulator-name = "8226_l21"; + reg = <0x5400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5500 { + regulator-name = "8226_l22"; + reg = <0x5500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5600 { + regulator-name = "8226_l23"; + reg = <0x5600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5700 { + regulator-name = "8226_l24"; + reg = <0x5700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5900 { + regulator-name = "8226_l26"; + reg = <0x5900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5a00 { + regulator-name = "8226_l27"; + reg = <0x5a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5b00 { + regulator-name = "8226_l28"; + reg = <0x5b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + qcom,leds@d800 { + compatible = "qcom,leds-qpnp"; + reg = <0xd800 0x100>; + label = "wled"; + }; + + pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <0>; + }; + + pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <1>; + }; + + pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <2>; + }; + + pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <3>; + }; + + pwm@b500 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb500 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <4>; + }; + + pwm@b600 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb600 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <5>; + }; + + regulator@8000 { + regulator-name = "8226_lvs1"; + reg = <0x8000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + qcom,vibrator@c000 { + compatible = "qcom,qpnp-vibrator"; + reg = <0xc000 0x100>; + label = "vibrator"; + status = "disabled"; + }; + + qcom,leds@d300 { + compatible = "qcom,leds-qpnp"; + status = "okay"; + reg = <0xd300 0x100>; + label = "flash"; + flash_boost-supply = <&pm8226_chg_boost>; + pm8226_flash0: qcom,flash_0 { + qcom,max-current = <1000>; + qcom,default-state = "off"; + qcom,headroom = <0>; + qcom,duration = <1280>; + qcom,clamp-curr = <200>; + qcom,startup-dly = <1>; + qcom,safety-timer; + label = "flash"; + linux,default-trigger = + "flash0_trigger"; + qcom,id = <1>; + linux,name = "led:flash_0"; + qcom,current = <625>; + }; + + pm8226_flash1: qcom,flash_1 { + qcom,max-current = <1000>; + qcom,default-state = "off"; + qcom,headroom = <0>; + qcom,duration = <1280>; + qcom,clamp-curr = <200>; + qcom,startup-dly = <1>; + qcom,safety-timer; + linux,default-trigger = + "flash1_trigger"; + label = "flash"; + qcom,id = <2>; + linux,name = "led:flash_1"; + qcom,current = <625>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8841.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8841.dtsi new file mode 100644 index 000000000..a2d80ec05 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8841.dtsi @@ -0,0 +1,242 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8841@4 { + spmi-slave-container; + reg = <0x4>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,qpnp-revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x4 0x24 0x0>; + label = "pm8841_tz"; + qcom,threshold-set = <0>; + qcom,default-temp = <37000>; + }; + + pm8841_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8841-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + }; + }; + + qcom,pm8841@5 { + spmi-slave-container; + reg = <0x5>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8841_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8841_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8841_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8841_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@2000 { + regulator-name = "8841_s5"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2000 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@0 { + reg = <0x2000 0x100>; + }; + qcom,ps@100 { + reg = <0x2100 0x100>; + }; + qcom,freq@200 { + reg = <0x2200 0x100>; + }; + }; + + regulator@2300 { + regulator-name = "8841_s6"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2300 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@2300 { + reg = <0x2300 0x100>; + }; + qcom,ps@2400 { + reg = <0x2400 0x100>; + }; + qcom,freq@2500 { + reg = <0x2500 0x100>; + }; + }; + + regulator@2600 { + regulator-name = "8841_s7"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2600 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@2600 { + reg = <0x2600 0x100>; + }; + qcom,ps@2700 { + reg = <0x2700 0x100>; + }; + qcom,freq@2800 { + reg = <0x2800 0x100>; + }; + }; + + regulator@2900 { + regulator-name = "8841_s8"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2900 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@2900 { + reg = <0x2900 0x100>; + }; + qcom,ps@2a000 { + reg = <0x2a00 0x100>; + }; + qcom,freq@2b00 { + reg = <0x2b00 0x100>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8941.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8941.dtsi new file mode 100644 index 000000000..b4e557e16 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8941.dtsi @@ -0,0 +1,1384 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8941@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + pm8941_misc: qcom,misc@900 { + compatible = "qcom,qpnp-misc"; + reg = <0x900 0x100>; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0>; + label = "pm8941_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0>, + <0x0 0x8 0x1>, + <0x0 0x8 0x4>; + interrupt-names = "kpdpwr", "resin", "resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <0>; + qcom,s2-timer = <2000>; + qcom,s2-type = <1>; + linux,code = <114>; + }; + }; + + bif_ctrl: qcom,bsi@1b00 { + compatible = "qcom,qpnp-bsi"; + reg = <0x1b00 0x100>, + <0x1208 0x1>; + reg-names = "bsi-base", "batt-id-status"; + label = "pm8941-bsi"; + interrupts = <0x0 0x1b 0x0>, + <0x0 0x1b 0x1>, + <0x0 0x1b 0x2>, + <0x0 0x12 0x0>; + interrupt-names = "err", + "rx", + "tx", + "batt-present"; + qcom,channel-num = <0x31>; + qcom,pullup-ohms = <100000>; + qcom,vref-microvolts = <1800000>; + qcom,min-clock-period = <1000>; + qcom,max-clock-period = <160000>; + qcom,sample-rate = <4>; + }; + + pm8941_coincell: qcom,coincell@2800 { + compatible = "qcom,qpnp-coincell"; + reg = <0x2800 0x100>; + }; + + pm8941_bms: qcom,bms { + spmi-dev-container; + compatible = "qcom,qpnp-bms"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,r-sense-uohm = <10000>; + qcom,v-cutoff-uv = <3400000>; + qcom,max-voltage-uv = <4200000>; + qcom,r-conn-mohm = <0>; + qcom,shutdown-soc-valid-limit = <20>; + qcom,adjust-soc-low-threshold = <15>; + qcom,ocv-voltage-high-threshold-uv = <3750000>; + qcom,ocv-voltage-low-threshold-uv = <3650000>; + qcom,low-soc-calculate-soc-threshold = <15>; + qcom,low-soc-calculate-soc-ms = <5000>; + qcom,calculate-soc-ms = <20000>; + qcom,chg-term-ua = <100000>; + qcom,batt-type = <0>; + qcom,low-voltage-threshold = <3420000>; + qcom,tm-temp-margin = <5000>; + qcom,low-ocv-correction-limit-uv = <100>; + qcom,high-ocv-correction-limit-uv = <50>; + qcom,hold-soc-est = <3>; + + qcom,bms-iadc@3800 { + reg = <0x3800 0x100>; + }; + + qcom,bms-bms@4000 { + reg = <0x4000 0x100>; + interrupts = <0x0 0x40 0x0>, + <0x0 0x40 0x1>, + <0x0 0x40 0x2>, + <0x0 0x40 0x3>, + <0x0 0x40 0x4>, + <0x0 0x40 0x5>, + <0x0 0x40 0x6>, + <0x0 0x40 0x7>; + + interrupt-names = "vsense_for_r", + "vsense_avg", + "sw_cc_thr", + "ocv_thr", + "charge_begin", + "good_ocv", + "ocv_for_r", + "cc_thr"; + }; + }; + + clkdiv@5b00 { + reg = <0x5b00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + clkdiv@5c00 { + reg = <0x5c00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + clkdiv@5d00 { + reg = <0x5d00 0x1000>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + pm8941_chg: qcom,charger { + spmi-dev-container; + compatible = "qcom,qpnp-charger"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,vddmax-mv = <4200>; + qcom,vddsafe-mv = <4230>; + qcom,vinmin-mv = <4300>; + qcom,ibatmax-ma = <1500>; + qcom,ibatterm-ma = <100>; + qcom,ibatsafe-ma = <1500>; + qcom,thermal-mitigation = <1500 700 600 325>; + qcom,cool-bat-decidegc = <100>; + qcom,cool-bat-mv = <4100>; + qcom,ibatmax-warm-ma = <350>; + qcom,warm-bat-decidegc = <450>; + qcom,warm-bat-mv = <4100>; + qcom,ibatmax-cool-ma = <350>; + qcom,vbatdet-delta-mv = <100>; + qcom,tchg-mins = <150>; + + qcom,chgr@1000 { + status = "disabled"; + reg = <0x1000 0x100>; + interrupts = <0x0 0x10 0x0>, + <0x0 0x10 0x1>, + <0x0 0x10 0x2>, + <0x0 0x10 0x3>, + <0x0 0x10 0x4>, + <0x0 0x10 0x5>, + <0x0 0x10 0x6>, + <0x0 0x10 0x7>; + + interrupt-names = "vbat-det-lo", + "vbat-det-hi", + "chgwdog", + "state-change", + "trkl-chg-on", + "fast-chg-on", + "chg-failed", + "chg-done"; + }; + + qcom,buck@1100 { + status = "disabled"; + reg = <0x1100 0x100>; + interrupts = <0x0 0x11 0x0>, + <0x0 0x11 0x1>, + <0x0 0x11 0x2>, + <0x0 0x11 0x3>, + <0x0 0x11 0x4>, + <0x0 0x11 0x5>, + <0x0 0x11 0x6>; + + interrupt-names = "vbat-ov", + "vreg-ov", + "overtemp", + "vchg-loop", + "ichg-loop", + "ibat-loop", + "vdd-loop"; + }; + + qcom,bat-if@1200 { + status = "disabled"; + reg = <0x1200 0x100>; + interrupts = <0x0 0x12 0x0>, + <0x0 0x12 0x1>, + <0x0 0x12 0x2>, + <0x0 0x12 0x3>, + <0x0 0x12 0x4>; + + interrupt-names = "batt-pres", + "bat-temp-ok", + "bat-fet-on", + "vcp-on", + "psi"; + + }; + + pm8941_chg_otg: qcom,usb-chgpth@1300 { + status = "disabled"; + reg = <0x1300 0x100>; + interrupts = <0 0x13 0x0>, + <0 0x13 0x1>, + <0x0 0x13 0x2>; + + interrupt-names = "coarse-det-usb", + "usbin-valid", + "chg-gone"; + }; + + qcom,dc-chgpth@1400 { + status = "disabled"; + reg = <0x1400 0x100>; + interrupts = <0x0 0x14 0x0>, + <0x0 0x14 0x1>; + + interrupt-names = "coarse-det-dc", + "dcin-valid"; + }; + + pm8941_chg_boost: qcom,boost@1500 { + status = "disabled"; + reg = <0x1500 0x100>; + interrupts = <0x0 0x15 0x0>, + <0x0 0x15 0x1>; + + interrupt-names = "boost-pwr-ok", + "limit-error"; + }; + + qcom,chg-misc@1600 { + status = "disabled"; + reg = <0x1600 0x100>; + }; + }; + + pm8941_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8941-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + }; + + gpio@cd00 { + reg = <0xcd00 0x100>; + qcom,pin-num = <14>; + }; + + gpio@ce00 { + reg = <0xce00 0x100>; + qcom,pin-num = <15>; + }; + + gpio@cf00 { + reg = <0xcf00 0x100>; + qcom,pin-num = <16>; + }; + + gpio@d000 { + reg = <0xd000 0x100>; + qcom,pin-num = <17>; + }; + + gpio@d100 { + reg = <0xd100 0x100>; + qcom,pin-num = <18>; + }; + + gpio@d200 { + reg = <0xd200 0x100>; + qcom,pin-num = <19>; + }; + + gpio@d300 { + reg = <0xd300 0x100>; + qcom,pin-num = <20>; + }; + + gpio@d400 { + reg = <0xd400 0x100>; + qcom,pin-num = <21>; + }; + + gpio@d500 { + reg = <0xd500 0x100>; + qcom,pin-num = <22>; + }; + + gpio@d600 { + reg = <0xd600 0x100>; + qcom,pin-num = <23>; + }; + + gpio@d700 { + reg = <0xd700 0x100>; + qcom,pin-num = <24>; + }; + + gpio@d800 { + reg = <0xd800 0x100>; + qcom,pin-num = <25>; + }; + + gpio@d900 { + reg = <0xd900 0x100>; + qcom,pin-num = <26>; + }; + + gpio@da00 { + reg = <0xda00 0x100>; + qcom,pin-num = <27>; + }; + + gpio@db00 { + reg = <0xdb00 0x100>; + qcom,pin-num = <28>; + }; + + gpio@dc00 { + reg = <0xdc00 0x100>; + qcom,pin-num = <29>; + }; + + gpio@dd00 { + reg = <0xdd00 0x100>; + qcom,pin-num = <30>; + }; + + gpio@de00 { + reg = <0xde00 0x100>; + qcom,pin-num = <31>; + }; + + gpio@df00 { + reg = <0xdf00 0x100>; + qcom,pin-num = <32>; + }; + + gpio@e000 { + reg = <0xe000 0x100>; + qcom,pin-num = <33>; + }; + + gpio@e100 { + reg = <0xe100 0x100>; + qcom,pin-num = <34>; + }; + + gpio@e200 { + reg = <0xe200 0x100>; + qcom,pin-num = <35>; + }; + + gpio@e300 { + reg = <0xe300 0x100>; + qcom,pin-num = <36>; + }; + }; + + pm8941_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8941-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + + mpp@a400 { + reg = <0xa400 0x100>; + qcom,pin-num = <5>; + }; + + mpp@a500 { + reg = <0xa500 0x100>; + qcom,pin-num = <6>; + }; + + mpp@a600 { + reg = <0xa600 0x100>; + qcom,pin-num = <7>; + }; + + mpp@a700 { + reg = <0xa700 0x100>; + qcom,pin-num = <8>; + }; + }; + + qcom,pm8941_rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8941_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm8941_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + + vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + chan@0 { + label = "usb_in"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@1 { + label = "dc_in"; + reg = <1>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@2 { + label = "vchg_sns"; + reg = <2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <3>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@3 { + label = "spare1_div3"; + reg = <3>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4 { + label = "usb_id_mv"; + reg = <4>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@31 { + label = "batt_id"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b2 { + label = "xo_therm_pu2"; + reg = <0xb2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b3 { + label = "msm_therm"; + reg = <0xb3>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b4 { + label = "emmc_therm"; + reg = <0xb4>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b5 { + label = "pa_therm0"; + reg = <0xb5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b7 { + label = "pa_therm1"; + reg = <0xb7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b8 { + label = "quiet_therm"; + reg = <0xb8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b9 { + label = "usb_id"; + reg = <0xb9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@39 { + label = "usb_id_nopull"; + reg = <0x39>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + }; + + iadc@3600 { + compatible = "qcom,qpnp-iadc"; + reg = <0x3600 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x36 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <16>; + qcom,adc-vdd-reference = <1800>; + + chan@0 { + label = "internal_rsense"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + qcom,vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + /* Channel Node */ + chan@b9 { + label = "usb_id"; + reg = <0xb9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x48>; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x68>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x70>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x78>; + }; + + chan@b5 { + label = "pa_therm0"; + reg = <0xb5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x80>; + qcom,thermal-node; + }; + + chan@b7 { + label = "pa_therm1"; + reg = <0xb7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x88>; + qcom,thermal-node; + }; + + chan@b4 { + label = "emmc_therm"; + reg = <0xb4>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x90>; + qcom,thermal-node; + }; + + chan@b3 { + label = "msm_therm"; + reg = <0xb3>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x98>; + qcom,thermal-node; + }; + }; + }; + + qcom,pm8941@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8941_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8941_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8941_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@a000 { + regulator-name = "8941_boost"; + reg = <0xa000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4000 { + regulator-name = "8941_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8941_l2"; + reg = <0x4100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8941_l3"; + reg = <0x4200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8941_l4"; + reg = <0x4300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8941_l5"; + reg = <0x4400 0x100>; + compatible = "qcom,qpnp-regulator"; + qcom,force-type = <0x04 0x10>; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8941_l6"; + reg = <0x4500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8941_l7"; + reg = <0x4600 0x100>; + compatible = "qcom,qpnp-regulator"; + qcom,force-type = <0x04 0x10>; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8941_l8"; + reg = <0x4700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8941_l9"; + reg = <0x4800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8941_l10"; + reg = <0x4900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4a00 { + regulator-name = "8941_l11"; + reg = <0x4a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8941_l12"; + reg = <0x4b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4c00 { + regulator-name = "8941_l13"; + reg = <0x4c00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8941_l14"; + reg = <0x4d00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8941_l15"; + reg = <0x4e00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8941_l16"; + reg = <0x4f00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5000 { + regulator-name = "8941_l17"; + reg = <0x5000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5100 { + regulator-name = "8941_l18"; + reg = <0x5100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5200 { + regulator-name = "8941_l19"; + reg = <0x5200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5300 { + regulator-name = "8941_l20"; + reg = <0x5300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5400 { + regulator-name = "8941_l21"; + reg = <0x5400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5500 { + regulator-name = "8941_l22"; + reg = <0x5500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5600 { + regulator-name = "8941_l23"; + reg = <0x5600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5700 { + regulator-name = "8941_l24"; + reg = <0x5700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8000 { + regulator-name = "8941_lvs1"; + reg = <0x8000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8100 { + regulator-name = "8941_lvs2"; + reg = <0x8100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8200 { + regulator-name = "8941_lvs3"; + reg = <0x8200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8300 { + regulator-name = "8941_mvs1"; + reg = <0x8300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8400 { + regulator-name = "8941_mvs2"; + reg = <0x8400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + qcom,vibrator@c000 { + compatible = "qcom,qpnp-vibrator"; + reg = <0xc000 0x100>; + label = "vibrator"; + status = "disabled"; + }; + + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + }; + + qcom,leds@d100 { + compatible = "qcom,leds-qpnp"; + reg = <0xd100 0x100>; + label = "rgb"; + }; + + qcom,leds@d200 { + compatible = "qcom,leds-qpnp"; + reg = <0xd200 0x100>; + label = "rgb"; + }; + + qcom,leds@d300 { + compatible = "qcom,leds-qpnp"; + reg = <0xd300 0x100>; + label = "flash"; + flash_boost-supply = <&pm8941_chg_boost>; + }; + + qcom,leds@d400 { + compatible = "qcom,leds-qpnp"; + reg = <0xd400 0x100>; + label = "flash"; + }; + + qcom,leds@d500 { + compatible = "qcom,leds-qpnp"; + reg = <0xd500 0x100>; + label = "flash"; + }; + + qcom,leds@d600 { + compatible = "qcom,leds-qpnp"; + reg = <0xd600 0x100>; + label = "flash"; + }; + + qcom,leds@d700 { + compatible = "qcom,leds-qpnp"; + reg = <0xd700 0x100>; + label = "flash"; + }; + + qcom,leds@d800 { + compatible = "qcom,leds-qpnp"; + reg = <0xd800 0x100>; + label = "wled"; + }; + + qcom,leds@d900 { + compatible = "qcom,leds-qpnp"; + reg = <0xd900 0x100>; + label = "wled"; + }; + + qcom,leds@da00 { + compatible = "qcom,leds-qpnp"; + reg = <0xda00 0x100>; + label = "wled"; + }; + + qcom,leds@db00 { + compatible = "qcom,leds-qpnp"; + reg = <0xdb00 0x100>; + label = "wled"; + }; + + qcom,leds@dc00 { + compatible = "qcom,leds-qpnp"; + reg = <0xdc00 0x100>; + label = "wled"; + }; + + qcom,leds@dd00 { + compatible = "qcom,leds-qpnp"; + reg = <0xdd00 0x100>; + label = "wled"; + }; + + qcom,leds@de00 { + compatible = "qcom,leds-qpnp"; + reg = <0xde00 0x100>; + label = "wled"; + }; + + qcom,leds@df00 { + compatible = "qcom,leds-qpnp"; + reg = <0xdf00 0x100>; + label = "wled"; + }; + + qcom,leds@e000 { + compatible = "qcom,leds-qpnp"; + reg = <0xe000 0x100>; + label = "wled"; + }; + + qcom,leds@e100 { + compatible = "qcom,leds-qpnp"; + reg = <0xe100 0x100>; + label = "wled"; + }; + + pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <0>; + }; + + pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <1>; + }; + + pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <2>; + }; + + pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <3>; + }; + + pwm@b500 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb500 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <4>; + }; + + pwm@b600 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb600 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <5>; + }; + + pwm@b700 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb700 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <6>; + }; + + pwm@b800 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb800 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <7>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8x41-rpm-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8x41-rpm-regulator.dtsi new file mode 100644 index 000000000..6e67dd85c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pm8x41-rpm-regulator.dtsi @@ -0,0 +1,585 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpb1 { + qcom,resource-name = "smpb"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s1 { + regulator-name = "8841_s1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpb2 { + qcom,resource-name = "smpb"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s2 { + regulator-name = "8841_s2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpb3 { + qcom,resource-name = "smpb"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s3 { + regulator-name = "8841_s3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpb4 { + qcom,resource-name = "smpb"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s4 { + regulator-name = "8841_s4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa1 { + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s1 { + regulator-name = "8941_s1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa2 { + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s2 { + regulator-name = "8941_s2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa3 { + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s3 { + regulator-name = "8941_s3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa1 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l1 { + regulator-name = "8941_l1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa2 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l2 { + regulator-name = "8941_l2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa3 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l3 { + regulator-name = "8941_l3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa4 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l4 { + regulator-name = "8941_l4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa5 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l5 { + regulator-name = "8941_l5"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa6 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l6 { + regulator-name = "8941_l6"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa7 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l7 { + regulator-name = "8941_l7"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa8 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l8 { + regulator-name = "8941_l8"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa9 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l9 { + regulator-name = "8941_l9"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa10 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l10 { + regulator-name = "8941_l10"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa11 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l11 { + regulator-name = "8941_l11"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa12 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l12 { + regulator-name = "8941_l12"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa13 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l13 { + regulator-name = "8941_l13"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa14 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l14 { + regulator-name = "8941_l14"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa15 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l15 { + regulator-name = "8941_l15"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa16 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l16 { + regulator-name = "8941_l16"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa17 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l17 { + regulator-name = "8941_l17"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa18 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l18 { + regulator-name = "8941_l18"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa19 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l19 { + regulator-name = "8941_l19"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa20 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l20 { + regulator-name = "8941_l20"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa21 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l21 { + regulator-name = "8941_l21"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa22 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l22 { + regulator-name = "8941_l22"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa23 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l23 { + regulator-name = "8941_l23"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa24 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l24 { + regulator-name = "8941_l24"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + /* TODO: find out correct resource names for LVS vs MVS */ + rpm-regulator-vsa1 { + qcom,resource-name = "vsa"; + qcom,resource-id = <1>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-lvs1 { + regulator-name = "8941_lvs1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-vsa2 { + qcom,resource-name = "vsa"; + qcom,resource-id = <2>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-lvs2 { + regulator-name = "8941_lvs2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-vsa3 { + qcom,resource-name = "vsa"; + qcom,resource-id = <3>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-lvs3 { + regulator-name = "8941_lvs3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-vsa4 { + qcom,resource-name = "vsa"; + qcom,resource-id = <4>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-mvs1 { + regulator-name = "8941_mvs1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-vsa5 { + qcom,resource-name = "vsa"; + qcom,resource-id = <5>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-mvs2 { + regulator-name = "8941_mvs2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pma8084.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pma8084.dtsi new file mode 100644 index 000000000..30525aac0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm-pma8084.dtsi @@ -0,0 +1,666 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pma8084@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + pma8084_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pma8084-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + }; + + gpio@cd00 { + reg = <0xcd00 0x100>; + qcom,pin-num = <14>; + }; + + gpio@ce00 { + reg = <0xce00 0x100>; + qcom,pin-num = <15>; + }; + + gpio@cf00 { + reg = <0xcf00 0x100>; + qcom,pin-num = <16>; + }; + + gpio@d000 { + reg = <0xd000 0x100>; + qcom,pin-num = <17>; + }; + + gpio@d100 { + reg = <0xd100 0x100>; + qcom,pin-num = <18>; + }; + + gpio@d200 { + reg = <0xd200 0x100>; + qcom,pin-num = <19>; + }; + + gpio@d300 { + reg = <0xd300 0x100>; + qcom,pin-num = <20>; + }; + + gpio@d400 { + reg = <0xd400 0x100>; + qcom,pin-num = <21>; + }; + + gpio@d500 { + reg = <0xd500 0x100>; + qcom,pin-num = <22>; + }; + }; + + pma8084_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pma8084-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + + mpp@a400 { + reg = <0xa400 0x100>; + qcom,pin-num = <5>; + }; + + mpp@a500 { + reg = <0xa500 0x100>; + qcom,pin-num = <6>; + }; + + mpp@a600 { + reg = <0xa600 0x100>; + qcom,pin-num = <7>; + }; + + mpp@a700 { + reg = <0xa700 0x100>; + qcom,pin-num = <8>; + }; + }; + }; + + qcom,pma8084@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8084_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8084_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8084_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8084_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@2000 { + regulator-name = "8084_s5"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2000 0x300>; + status = "disabled"; + + qcom,ctl@2000 { + reg = <0x2000 0x100>; + }; + qcom,ps@2100 { + reg = <0x2100 0x100>; + }; + qcom,freq@2200 { + reg = <0x2200 0x100>; + }; + }; + + regulator@2300 { + regulator-name = "8084_s6"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2300 0x300>; + status = "disabled"; + + qcom,ctl@2300 { + reg = <0x2300 0x100>; + }; + qcom,ps@2400 { + reg = <0x2400 0x100>; + }; + qcom,freq@2500 { + reg = <0x2500 0x100>; + }; + }; + + regulator@2600 { + regulator-name = "8084_s7"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2600 0x300>; + status = "disabled"; + + qcom,ctl@2600 { + reg = <0x2600 0x100>; + }; + qcom,ps@2700 { + reg = <0x2700 0x100>; + }; + qcom,freq@2800 { + reg = <0x2800 0x100>; + }; + }; + + regulator@2900 { + regulator-name = "8084_s8"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2900 0x300>; + status = "disabled"; + + qcom,ctl@2900 { + reg = <0x2900 0x100>; + }; + qcom,ps@2a00 { + reg = <0x2a00 0x100>; + }; + qcom,freq@2b00 { + reg = <0x2b00 0x100>; + }; + }; + + regulator@2c00 { + regulator-name = "8084_s9"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2c00 0x300>; + status = "disabled"; + + qcom,ctl@2c00 { + reg = <0x2c00 0x100>; + }; + qcom,ps@2d00 { + reg = <0x2d00 0x100>; + }; + qcom,freq@2e00 { + reg = <0x2e00 0x100>; + }; + }; + + regulator@2f00 { + regulator-name = "8084_s10"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2f00 0x300>; + status = "disabled"; + + qcom,ctl@2f00 { + reg = <0x2f00 0x100>; + }; + qcom,ps@3000 { + reg = <0x3000 0x100>; + }; + qcom,freq@3100 { + reg = <0x3100 0x100>; + }; + }; + + regulator@3200 { + regulator-name = "8084_s11"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x3200 0x300>; + status = "disabled"; + + qcom,ctl@3200 { + reg = <0x3200 0x100>; + }; + qcom,ps@3300 { + reg = <0x3300 0x100>; + }; + qcom,freq@3400 { + reg = <0x3400 0x100>; + }; + }; + + regulator@3500 { + regulator-name = "8084_s12"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x3500 0x300>; + status = "disabled"; + + qcom,ctl@3500 { + reg = <0x3500 0x100>; + }; + qcom,ps@3600 { + reg = <0x3600 0x100>; + }; + qcom,freq@3700 { + reg = <0x3700 0x100>; + }; + }; + + regulator@4000 { + regulator-name = "8084_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8084_l2"; + reg = <0x4100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8084_l3"; + reg = <0x4200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8084_l4"; + reg = <0x4300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8084_l5"; + reg = <0x4400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8084_l6"; + reg = <0x4500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8084_l7"; + reg = <0x4600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8084_l8"; + reg = <0x4700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8084_l9"; + reg = <0x4800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8084_l10"; + reg = <0x4900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4a00 { + regulator-name = "8084_l11"; + reg = <0x4a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8084_l12"; + reg = <0x4b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4c00 { + regulator-name = "8084_l13"; + reg = <0x4c00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8084_l14"; + reg = <0x4d00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8084_l15"; + reg = <0x4e00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8084_l16"; + reg = <0x4f00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5000 { + regulator-name = "8084_l17"; + reg = <0x5000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5100 { + regulator-name = "8084_l18"; + reg = <0x5100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5200 { + regulator-name = "8084_l19"; + reg = <0x5200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5300 { + regulator-name = "8084_l20"; + reg = <0x5300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5400 { + regulator-name = "8084_l21"; + reg = <0x5400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5500 { + regulator-name = "8084_l22"; + reg = <0x5500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5600 { + regulator-name = "8084_l23"; + reg = <0x5600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5700 { + regulator-name = "8084_l24"; + reg = <0x5700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5800 { + regulator-name = "8084_l25"; + reg = <0x5800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5900 { + regulator-name = "8084_l26"; + reg = <0x5900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5a00 { + regulator-name = "8084_l27"; + reg = <0x5a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8000 { + regulator-name = "8084_lvs1"; + reg = <0x8000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8100 { + regulator-name = "8084_lvs2"; + reg = <0x8100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8200 { + regulator-name = "8084_lvs3"; + reg = <0x8200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8300 { + regulator-name = "8084_lvs4"; + reg = <0x8300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8400 { + regulator-name = "8084_mvs1"; + reg = <0x8400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-bus.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-bus.dtsi new file mode 100644 index 000000000..d87aa3ea5 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-bus.dtsi @@ -0,0 +1,1128 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm-mmss-noc@fc478000 { + compatible = "msm-bus-fabric"; + reg = <0xfc478000 0x00004000>; + cell-id = <2048>; + label = "msm_mmss_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-gfx3d { + cell-id = <26>; + label = "mas-gfx3d"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <2>; + qcom,mas-hw-id = <6>; + }; + + mas-jpeg { + cell-id = <62>; + label = "mas-jpeg"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <7>; + }; + + mas-mdp-port0 { + cell-id = <22>; + label = "mas-mdp-port0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,qport = <1>; + qcom,ws = <10000>; + qcom,mas-hw-id = <8>; + }; + + mas-video-p0 { + cell-id = <63>; + label = "mas-video-p0"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <4>; + qcom,mas-hw-id = <9>; + }; + + mas-vfe { + cell-id = <29>; + label = "mas-vfe"; + qcom,masterp = <16>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <6>; + qcom,mas-hw-id = <11>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,masterp = <0 1>; + qcom,buswidth = <16>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <4>; + }; + + fab-bimc { + cell-id = <0>; + label = "fab-bimc"; + qcom,gateway; + qcom,slavep = <16>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <16>; + }; + + slv-camera-cfg { + cell-id = <589>; + label = "slv-camera-cfg"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <3>; + }; + + slv-display-cfg { + cell-id = <590>; + label = "slv-display-cfg"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <4>; + }; + + slv-ocmem-cfg { + cell-id = <591>; + label = "slv-ocmem-cfg"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <5>; + }; + + slv-cpr-cfg { + cell-id = <592>; + label = "slv-cpr-cfg"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <6>; + }; + + slv-cpr-xpu-cfg { + cell-id = <593>; + label = "slv-cpr-xpu-cfg"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <7>; + }; + + slv-misc-cfg { + cell-id = <594>; + label = "slv-misc-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <8>; + }; + + slv-misc-xpu-cfg { + cell-id = <595>; + label = "slv-misc-xpu-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <9>; + }; + + slv-venus-cfg { + cell-id = <596>; + label = "slv-venus-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <10>; + }; + + slv-gfx3d-cfg { + cell-id = <598>; + label = "slv-gfx3d-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <11>; + }; + + slv-mmss-clk-cfg { + cell-id = <599>; + label = "slv-mmss-clk-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <12>; + }; + + slv-mmss-clk-xpu-cfg { + cell-id = <600>; + label = "slv-mmss-clk-xpu-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <13>; + }; + + slv-mnoc-mpu-cfg { + cell-id = <601>; + label = "slv-mnoc-mpu-cfg"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <14>; + }; + + slv-onoc-mpu-cfg { + cell-id = <602>; + label = "slv-onoc-mpu-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <15>; + }; + + slv-service-mnoc { + cell-id = <603>; + label = "slv-service-mnoc"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <17>; + }; + + }; + + msm-sys-noc@fc460000 { + compatible = "msm-bus-fabric"; + reg = <0xfc460000 0x00004000>; + cell-id = <1024>; + label = "msm_sys_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-lpass-ahb { + cell-id = <52>; + label = "mas-lpass-ahb"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,qport = <0>; + qcom,mas-hw-id = <18>; + qcom,mode = "Fixed"; + qcom,prio-rd = <2>; + qcom,prio-wr = <2>; + }; + + mas-qdss-bam { + cell-id = <53>; + label = "mas-qdss-bam"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <1>; + qcom,mas-hw-id = <19>; + }; + + mas-snoc-cfg { + cell-id = <54>; + label = "mas-snoc-cfg"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,mas-hw-id = <20>; + }; + + fab-bimc { + cell-id = <0>; + label= "fab-bimc"; + qcom,gateway; + qcom,slavep = <7>; + qcom,masterp = <3>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <21>; + qcom,slv-hw-id = <24>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,slavep = <8>; + qcom,masterp = <4>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <22>; + qcom,slv-hw-id = <25>; + }; + + fab-pnoc { + cell-id = <4096>; + label = "fab-pnoc"; + qcom,gateway; + qcom,slavep = <10>; + qcom,masterp = <10>; + qcom,buswidth = <8>; + qcom,qport = <8>; + qcom,mas-hw-id = <29>; + qcom,slv-hw-id = <28>; + qcom,mode = "Fixed"; + qcom,prio-rd = <2>; + qcom,prio-wr = <2>; + }; + + fab-ovnoc { + cell-id = <6144>; + label = "fab-ovnoc"; + qcom,gateway; + qcom,buswidth = <8>; + qcom,mas-hw-id = <53>; + qcom,slv-hw-id = <77>; + }; + + mas-crypto-core0 { + cell-id = <55>; + label = "mas-crypto-core0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,mode = "Fixed"; +/* qcom,qport = <2>;*/ + qcom,mas-hw-id = <23>; + qcom,hw-sel = "NoC"; + qcom,prio-rd = <1>; + qcom,prio-wr = <1>; + }; + + mas-lpass-proc { + cell-id = <11>; + label = "mas-lpass-proc"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,qport = <4>; + qcom,mas-hw-id = <25>; + qcom,mode = "Fixed"; + qcom,prio-rd = <2>; + qcom,prio-wr = <2>; + }; + + mas-mss { + cell-id = <38>; + label = "mas-mss"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,mas-hw-id = <26>; + }; + + mas-mss-nav { + cell-id = <57>; + label = "mas-mss-nav"; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,mas-hw-id = <27>; + }; + + mas-ocmem-dma { + cell-id = <58>; + label = "mas-ocmem-dma"; + qcom,masterp = <9>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <7>; + qcom,mas-hw-id = <28>; + }; + + mas-wcss { + cell-id = <59>; + label = "mas-wcss"; + qcom,masterp = <11>; + qcom,tier = <2>; + qcom,mas-hw-id = <30>; + }; + + mas-qdss-etr { + cell-id = <60>; + label = "mas-qdss-etr"; + qcom,masterp = <12>; + qcom,tier = <2>; + qcom,qport = <10>; + qcom,mode = "Fixed"; + qcom,mas-hw-id = <31>; + }; + + slv-ampss { + cell-id = <520>; + label = "slv-ampss"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <20>; + }; + + slv-lpass { + cell-id = <522>; + label = "slv-lpass"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <21>; + }; + + slv-wcss { + cell-id = <584>; + label = "slv-wcss"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <23>; + }; + + slv-ocimem { + cell-id = <585>; + label = "slv-ocimem"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <26>; + }; + + slv-service-snoc { + cell-id = <587>; + label = "slv-service-snoc"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <29>; + }; + + slv-qdss-stm { + cell-id = <588>; + label = "slv-qdss-stm"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <30>; + }; + + }; + + msm-periph-noc@fc468000 { + compatible = "msm-bus-fabric"; + reg = <0xfc468000 0x00004000>; + cell-id = <4096>; + label = "msm_periph_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-pnoc-cfg { + cell-id = <88>; + label = "mas-pnoc-cfg"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <43>; + }; + + mas-sdcc-1 { + cell-id = <78>; + label = "mas-sdcc-1"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <33>; + }; + + mas-sdcc-3 { + cell-id = <79>; + label = "mas-sdcc-3"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <34>; + }; + + mas-sdcc-2 { + cell-id = <81>; + label = "mas-sdcc-2"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <35>; + }; + + mas-bam-dma { + cell-id = <83>; + label = "mas-bam-dma"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <38>; + }; + + mas-usb-hsic { + cell-id = <85>; + label = "mas-usb-hsic"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <40>; + }; + + mas-blsp-1 { + cell-id = <86>; + label = "mas-blsp-1"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <41>; + }; + + mas-usb-hs { + cell-id = <87>; + label = "mas-usb-hs"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <42>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <12>; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <45>; + qcom,mas-hw-id = <44>; + }; + + slv-sdcc-1 { + cell-id = <606>; + label = "slv-sdcc-1"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <31>; + }; + + slv-sdcc-3 { + cell-id = <607>; + label = "slv-sdcc-3"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <32>; + }; + + slv-sdcc-2 { + cell-id = <608>; + label = "slv-sdcc-2"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <33>; + }; + + slv-bam-dma { + cell-id = <610>; + label = "slv-bam-dma"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <36>; + }; + + slv-usb-hsic { + cell-id = <612>; + label = "slv-usb-hsic"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <38>; + }; + + slv-blsp-1 { + cell-id = <613>; + label = "slv-blsp-1"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <39>; + }; + + slv-usb-hs { + cell-id = <614>; + label = "slv-usb-hs"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <40>; + }; + + slv-pdm { + cell-id = <615>; + label = "slv-pdm"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <41>; + }; + + slv-periph-apu-cfg { + cell-id = <616>; + label = "slv-periph-apu-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <42>; + }; + + slv-pnoc-mpu-cfg { + cell-id = <617>; + label = "slv-pnoc-mpu-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <43>; + }; + + slv-prng { + cell-id = <618>; + label = "slv-prng"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <44>; + }; + + slv-service-pnoc { + cell-id = <619>; + label = "slv-service-pnoc"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <46>; + }; + + }; + + msm-config-noc@fc480000 { + compatible = "msm-bus-fabric"; + reg = <0xfc480000 0x00004000>; + cell-id = <5120>; + label = "msm_config_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-rpm-inst { + cell-id = <72>; + label = "mas-rpm-inst"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <45>; + }; + + mas-rpm-data { + cell-id = <73>; + label = "mas-rpm-data"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <46>; + }; + + mas-rpm-sys { + cell-id = <74>; + label = "mas-rpm-sys"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <47>; + }; + + mas-dehr { + cell-id = <75>; + label = "mas-dehr"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <48>; + }; + + mas-qdss-dsp { + cell-id = <76>; + label = "mas-qdss-dap"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <49>; + }; + + mas-spdm { + cell-id = <36>; + label = "mas-spdm"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <50>; + }; + + mas-tic { + cell-id = <77>; + label = "mas-tic"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <51>; + }; + + slv-clk-ctl { + cell-id = <620>; + label = "slv-clk-ctl"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <47>; + }; + + slv-cnoc-mss { + cell-id = <621>; + label = "slv-cnoc-mss"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <48>; + }; + + slv-security { + cell-id = <622>; + label = "slv-security"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <49>; + }; + + slv-tcsr { + cell-id = <623>; + label = "slv-tcsr"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <50>; + }; + + slv-tlmm { + cell-id = <624>; + label = "slv-tlmm"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <51>; + }; + + slv-crypto-0-cfg { + cell-id = <625>; + label = "slv-crypto-0-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <52>; + }; + + slv-imem-cfg { + cell-id = <627>; + label = "slv-imem-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <54>; + }; + + slv-message-ram { + cell-id = <628>; + label = "slv-message-ram"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <55>; + }; + + slv-bimc-cfg { + cell-id = <629>; + label = "slv-bimc-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <56>; + }; + + slv-boot-rom { + cell-id = <630>; + label = "slv-boot-rom"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <57>; + }; + + slv-pmic-arb { + cell-id = <632>; + label = "slv-pmic-arb"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <59>; + }; + + slv-spdm-wrapper { + cell-id = <633>; + label = "slv-spdm-wrapper"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <60>; + }; + + slv-dehr-cfg { + cell-id = <634>; + label = "slv-dehr-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <61>; + }; + + slv-mpm { + cell-id = <536>; + label = "slv-mpm"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <62>; + }; + + slv-qdss-cfg { + cell-id = <635>; + label = "slv-qdss-cfg"; + qcom,slavep = <16>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <63>; + }; + + slv-rbcpr-cfg { + cell-id = <636>; + label = "slv-rbcpr-cfg"; + qcom,slavep = <17>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <64>; + }; + + slv-rbcpr-qdss-apu-cfg { + cell-id = <637>; + label = "slv-rbcpr-qdss-apu-cfg"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <65>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <26>; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <52>; + qcom,slv-hw-id = <75>; + }; + + slv-cnoc-mnoc-mmss-cfg { + cell-id = <631>; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <58>; + }; + + slv-cnoc-mnoc-cfg { + cell-id = <640>; + label = "slv-cnoc-mnoc-cfg"; + qcom,slavep = <19>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <66>; + }; + + slv-pnoc-cfg { + cell-id = <641>; + label = "slv-pnoc-cfg"; + qcom,slavep = <21>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <69>; + }; + + slv-snoc-mpu-cfg { + cell-id = <638>; + label = "slv-snoc-mpu-cfg"; + qcom,slavep = <20>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <67>; + }; + + slv-snoc-cfg { + cell-id = <642>; + label = "slv-snoc-cfg"; + qcom,slavep = <22>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <70>; + }; + + slv-phy-apu-cfg { + cell-id = <644>; + label = "slv-phy-apu-cfg"; + qcom,slavep = <23>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <72>; + }; + + slv-ebi1-phy-cfg { + cell-id = <645>; + label = "slv-ebi1-phy-cfg"; + qcom,slavep = <24>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <73>; + }; + + slv-rpm { + cell-id = <534>; + label = "slv-rpm"; + qcom,slavep = <25>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <74>; + }; + + slv-service-cnoc { + cell-id = <646>; + label = "slv-service-cnoc"; + qcom,slavep = <27>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <76>; + }; + + }; + + msm-bimc@0xfc380000 { + compatible = "msm-bus-fabric"; + reg = <0xfc380000 0x0006A000>; + cell-id = <0>; + label = "msm_bimc"; + qcom,fabclk-dual = "mem_clk"; + qcom,fabclk-active = "mem_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "BIMC"; + qcom,rpm-en; + + mas-ampss-m0 { + cell-id = <1>; + label = "mas-ampss-m0"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Fixed"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + }; + + mas-mss-proc { + cell-id = <65>; + label = "mas-mss-proc"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <1>; + }; + + fab-mmss-noc { + cell-id = <2048>; + label = "fab_mmss_noc"; + qcom,gateway; + qcom,masterp = <2>; + qcom,qport = <2>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Bypass"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <2>; + qcom,masterp = <4>; + qcom,qport = <4>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <3>; + qcom,slv-hw-id = <2>; + qcom,mode = "Bypass"; + qcom,hw-sel = "RPM"; + }; + + slv-ebi-ch0 { + cell-id = <512>; + label = "slv-ebi-ch0"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <0>; + qcom,mode = "Bypass"; + }; + + slv-ampss-l2 { + cell-id = <514>; + label = "slv-ampss-l2"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <1>; + }; + }; + + msm-ocmem-vnoc@6144 { + compatible = "msm-bus-fabric"; + reg = <0x6144 0x2>; + cell-id = <6144>; + label = "msm-ocmem-vnoc"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + qcom,virt; + + mas-v-ocmem-gfx3d { + cell-id = <89>; + label = "mas-v-ocmem-gfx3d"; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <55>; + }; + + slv-ocmem { + cell-id = <604>; + label = "slv-ocmem"; + qcom,slavep = <0 1>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,slv-hw-id = <18>; + qcom,slaveclk-dual = "ocmem_clk"; + qcom,slaveclk-active = "ocmem_a_clk"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,buswidth = <32>; + qcom,ws = <10000>; + qcom,mas-hw-id = <57>; + qcom,slv-hw-id = <80>; + }; + + fab-onoc { + cell-id = <3072>; + label = "fab-onoc"; + qcom,gateway; + qcom,buswidth = <16>; + qcom,ws = <10000>; + qcom,mas-hw-id = <56>; + qcom,slv-hw-id = <79>; + }; + + }; +}; + + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-cdp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-cdp.dtsi new file mode 100644 index 000000000..41d6b7e79 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-cdp.dtsi @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + led_flash0: qcom,camera-led-flash { + cell-index = <0>; + compatible = "qcom,camera-led-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pm8226_flash0 &pm8226_flash1>; + }; +}; + +&cci { + + actuator0: qcom,actuator@6e { + cell-index = <3>; + reg = <0x6c>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6f { + compatible = "qcom,ov8825"; + reg = <0x6f>; + qcom,slave-id = <0x6c 0x300a 0x8825>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "ov8825"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + cam_vaf-supply = <&pm8226_l15>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 36 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1f>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; + + qcom,camera@6d { + compatible = "qcom,ov9724"; + reg = <0x6d>; + qcom,slave-id = <0x20 0x0 0x9724>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <0>; + qcom,sensor-name = "ov9724"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-type = <0 1 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 28 0>, + <&msmgpio 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-mtp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-mtp.dtsi new file mode 100644 index 000000000..53860ac85 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-mtp.dtsi @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + led_flash0: qcom,camera-led-flash { + cell-index = <0>; + compatible = "qcom,camera-led-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pm8226_flash0 &pm8226_flash1>; + }; +}; + +&cci { + + actuator0: qcom,actuator@6e { + cell-index = <3>; + reg = <0x6c>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6f { + compatible = "qcom,ov8825"; + reg = <0x6f>; + qcom,slave-id = <0x6c 0x300a 0x8825>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "ov8825"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + cam_vaf-supply = <&pm8226_l15>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1f>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; + + qcom,camera@6d { + compatible = "qcom,ov9724"; + reg = <0x6d>; + qcom,slave-id = <0x20 0x0 0x9724>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <270>; + qcom,sensor-name = "ov9724"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-type = <0 1 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 28 0>, + <&msmgpio 36 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-qrd.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-qrd.dtsi new file mode 100644 index 000000000..3935dbb78 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera-sensor-qrd.dtsi @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + led_flash0: qcom,camera-led-flash { + cell-index = <0>; + compatible = "qcom,camera-led-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pm8226_flash0 &pm8226_flash1>; + }; +}; + +&cci { + + actuator0: qcom,actuator@6e { + cell-index = <3>; + reg = <0x6c>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6f { + compatible = "qcom,ov8825"; + reg = <0x6f>; + qcom,slave-id = <0x6c 0x300a 0x8825>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <270>; + qcom,sensor-name = "ov8825"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + cam_vaf-supply = <&pm8226_l15>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 36 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1f>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; + + qcom,camera@6d { + compatible = "qcom,ov9724"; + reg = <0x6d>; + qcom,slave-id = <0x20 0x0 0x9724>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <270>; + qcom,sensor-name = "ov9724"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-type = <0 1 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 28 0>, + <&msmgpio 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera.dtsi new file mode 100644 index 000000000..ec0092d43 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-camera.dtsi @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-cam@fd8c0000 { + compatible = "qcom,msm-cam"; + reg = <0xfd8c0000 0x10000>; + reg-names = "msm-cam"; + }; + + qcom,csiphy@fda0ac00 { + cell-index = <0>; + compatible = "qcom,csiphy"; + reg = <0xfda0ac00 0x200>, + <0xfda00030 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + }; + + qcom,csiphy@fda0b000 { + cell-index = <1>; + compatible = "qcom,csiphy"; + reg = <0xfda0b000 0x200>, + <0xfda00038 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + }; + + qcom,csid@fda08000 { + cell-index = <0>; + compatible = "qcom,csid"; + reg = <0xfda08000 0x100>; + reg-names = "csid"; + interrupts = <0 51 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8226_l4>; + }; + + qcom,csid@fda08400 { + cell-index = <1>; + compatible = "qcom,csid"; + reg = <0xfda08400 0x100>; + reg-names = "csid"; + interrupts = <0 52 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8226_l4>; + }; + + qcom,ispif@fda0a000 { + cell-index = <0>; + compatible = "qcom,ispif"; + reg = <0xfda0a000 0x500>, + <0xfda00020 0x10>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 55 0>; + interrupt-names = "ispif"; + }; + + qcom,vfe@fda10000 { + cell-index = <0>; + compatible = "qcom,vfe40"; + reg = <0xfda10000 0x1000>, + <0xfda40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 57 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + }; + + qcom,jpeg@fda1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0xfda1c000 0x400>; + reg-names = "jpeg"; + interrupts = <0 59 0>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + }; + + qcom,irqrouter@fda00000 { + cell-index = <0>; + compatible = "qcom,irqrouter"; + reg = <0xfda00000 0x100>; + reg-names = "irqrouter"; + }; + + qcom,cpp@fda04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xfda04000 0x100>, + <0xfda40000 0x200>, + <0xfda18000 0x008>; + reg-names = "cpp", "cpp_vbif", "cpp_hw"; + interrupts = <0 49 0>; + interrupt-names = "cpp"; + vdd-supply = <&gdsc_vfe>; + }; + + cci: qcom,cci@fda0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xfda0c000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 50 0>; + interrupt-names = "cci"; + gpios = <&msmgpio 29 0>, + <&msmgpio 30 0>; + qcom,gpio-tbl-num = <0 1>; + qcom,gpio-tbl-flags = <1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0"; + qcom,hw-thigh = <78>; + qcom,hw-tlow = <114>; + qcom,hw-tsu-sto = <28>; + qcom,hw-tsu-sta = <28>; + qcom,hw-thd-dat = <10>; + qcom,hw-thd-sta = <77>; + qcom,hw-tbuf = <118>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-cdp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-cdp.dtsi new file mode 100644 index 000000000..da9ad8c0a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-cdp.dtsi @@ -0,0 +1,393 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-nt35590-720p-video.dtsi" +/include/ "msm8226-camera-sensor-cdp.dtsi" + +&soc { + serial@f991f000 { + status = "ok"; + }; + + qcom,mdss_dsi_nt35590_720p_video { + status = "ok"; + }; + + i2c@f9927000 { /* BLSP1 QUP5 */ + synaptics@20 { + compatible = "synaptics,rmi4"; + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <17 0x2008>; + vdd-supply = <&pm8226_l19>; + vcc_i2c-supply = <&pm8226_lvs1>; + synaptics,reset-gpio = <&msmgpio 16 0x00>; + synaptics,irq-gpio = <&msmgpio 17 0x2008>; + synaptics,button-map = <139 102 158>; + synaptics,i2c-pull-up; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 108 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 107 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 106 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@3 { + compatible = "micrel,ks8851"; + reg = <3>; + interrupt-parent = <&msmgpio>; + interrupts = <0 115 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&msmgpio 114 0>; + vdd-io-supply = <&pm8226_lvs1>; + vdd-phy-supply = <&pm8226_lvs1>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "SPK_OUT", "MCLK", + "SPK_OUT", "EXT_VDD_SPKR", + "AMIC1", "MIC BIAS1 Internal1", + "MIC BIAS1 Internal1", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC5", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC2", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic2", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4"; + + qcom,cdc-mclk-gpios = <&pm8226_gpios 1 0>; + qcom,cdc-vdd-spkr-gpios = <&pm8226_gpios 2 0>; + qcom,headset-jack-type-NO; + }; +}; + +&sdcc1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdcc2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <600>; + + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "disabled"; +}; + +&sdhc_2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "ok"; +}; + +&spmi_bus { + qcom,pm8226@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "manual"; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + }; + }; + + qcom,leds@a300 { + status = "okay"; + qcom,led_mpp_4 { + label = "mpp"; + linux,name = "green"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,source-sel = <8>; + qcom,mode-ctrl = <0x60>; + qcom,pwm-channel = <0>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + + qcom,leds@a500 { + status = "okay"; + qcom,led_mpp_6 { + label = "mpp"; + linux,name = "red"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,mode-ctrl = <0x60>; + qcom,source-sel = <10>; + qcom,pwm-channel = <5>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + }; + + qcom,pm8226@1 { + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <20>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <0>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + }; +}; + +&pm8226_gpios { + gpio@c000 { /* GPIO 1 */ + /* XO_PMIC_CDC_MCLK enable for tapan codec */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS logic */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO*/ + qcom,vin-sel = <3>; /* QPNP_PIN_VIN3 */ + qcom,out-strength = <3>;/* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <3>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; +}; + +&pm8226_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&pm8226_chg { + qcom,charging-disabled; + qcom,use-default-batt-values; +}; + +&usb_otg_sw { + status = "okay"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-coresight.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-coresight.dtsi new file mode 100644 index 000000000..e11c963c6 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-coresight.dtsi @@ -0,0 +1,377 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@fc322000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc322000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + }; + + tpiu: tpiu@fc318000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc318000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + vdd-supply = <&pm8226_l18>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + }; + + replicator: replicator@fc31c000 { + compatible = "qcom,coresight-replicator"; + reg = <0xfc31c000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + }; + + tmc_etf: tmc@fc307000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc307000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + }; + + funnel_merg: funnel@fc31b000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31b000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc319000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc319000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + funnel_in1: funnel@fc31a000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31a000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <6>; + coresight-name = "coresight-funnel-in1"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <1>; + }; + + funnel_a7ss: funnel@fc345000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc345000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <7>; + coresight-name = "coresight-funnel-a7ss"; + coresight-nr-inports = <4>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <5>; + }; + + funnel_mmss: funnel@fc364000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc364000 0x1000>; + reg-names = "funnel-base"; + + + coresight-id = <8>; + coresight-name = "coresight-funnel-mmss"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <1>; + }; + + stm: stm@fc321000 { + compatible = "arm,coresight-stm"; + reg = <0xfc321000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <9>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc33c000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33c000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <10>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <0>; + + qcom,round-robin; + }; + + etm1: etm@fc33d000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33d000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <11>; + coresight-name = "coresight-etm1"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <1>; + + qcom,round-robin; + }; + + etm2: etm@fc33e000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33e000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <12>; + coresight-name = "coresight-etm2"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <2>; + + qcom,round-robin; + }; + + etm3: etm@fc33f000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33f000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <13>; + coresight-name = "coresight-etm3"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <3>; + + qcom,round-robin; + }; + + csr: csr@fc302000 { + compatible = "qcom,coresight-csr"; + reg = <0xfc302000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <14>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <1>; + }; + + cti0: cti@fc308000 { + compatible = "arm,coresight-cti"; + reg = <0xfc308000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + }; + + cti1: cti@fc309000 { + compatible = "arm,coresight-cti"; + reg = <0xfc309000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + cti2: cti@fc30a000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30a000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + }; + + cti3: cti@fc30b000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30b000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <18>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + }; + + cti4: cti@fc30c000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30c000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <19>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + }; + + cti5: cti@fc30d000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30d000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <20>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + }; + + cti6: cti@fc30e000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30e000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <21>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + }; + + cti7: cti@fc30f000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30f000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <22>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + }; + + cti8: cti@fc310000 { + compatible = "arm,coresight-cti"; + reg = <0xfc310000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <23>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + }; + + cti_l2: cti@fc340000 { + compatible = "arm,coresight-cti"; + reg = <0xfc340000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <24>; + coresight-name = "coresight-cti-l2"; + coresight-nr-inports = <0>; + }; + + cti_cpu0: cti@fc341000 { + compatible = "arm,coresight-cti"; + reg = <0xfc341000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <25>; + coresight-name = "coresight-cti-cpu0"; + coresight-nr-inports = <0>; + }; + + cti_cpu1: cti@fc342000 { + compatible = "arm,coresight-cti"; + reg = <0xfc342000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <26>; + coresight-name = "coresight-cti-cpu1"; + coresight-nr-inports = <0>; + }; + + cti_cpu2: cti@fc343000 { + compatible = "arm,coresight-cti"; + reg = <0xfc343000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <27>; + coresight-name = "coresight-cti-cpu2"; + coresight-nr-inports = <0>; + }; + + cti_cpu3: cti@fc344000 { + compatible = "arm,coresight-cti"; + reg = <0xfc344000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <28>; + coresight-name = "coresight-cti-cpu3"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@fd828018 { + compatible = "qcom,coresight-hwevent"; + reg = <0xfd828018 0x80>, + <0xf9011080 0x80>, + <0xfd4ab160 0x80>; + reg-names = "mmss-mux", "apcs-mux", "ppss-mux"; + + coresight-id = <29>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + + qcom,hwevent-clks = "core_mmss_clk"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-fluid.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-fluid.dts new file mode 100644 index 000000000..c58b43b4b --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-fluid.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226.dtsi" + +/ { + model = "Qualcomm MSM 8226 FLUID"; + compatible = "qcom,msm8226-fluid", "qcom,msm8226", "qcom,fluid"; + qcom,msm-id = <145 3 0>, + <158 3 0>, + <159 3 0>, + <198 3 0>; +}; + +&soc { + serial@f991f000 { + status = "disabled"; + }; +}; + +&pm8226_bms { + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-gpu.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-gpu.dtsi new file mode 100644 index 000000000..590f73395 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-gpu.dtsi @@ -0,0 +1,161 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + msm_gpu: qcom,kgsl-3d0@fdb00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0xfdb00000 0x10000 + 0xfdb20000 0x10000>; + reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03000510>; + + qcom,initial-pwrlevel = <1>; + + qcom,idle-timeout = <8>; // + qcom,strtstp-sleepwake; + qcom,clk-map = <0x00000016>; /* KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE */ + + /* Bus Scale Settings */ + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, <89 604 0 0>, + <26 512 0 1600000>, <89 604 0 3200000>, + <26 512 0 3200000>, <89 604 0 5120000>, + <26 512 0 4256000>, <89 604 0 6400000>; + + + /* GDSC oxili regulators */ + vddcx-supply = "\0"; + vdd-supply = <&gdsc_oxili_cx>; + + + /* IOMMU Data */ + iommu = <&kgsl_iommu>; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <450000000>; + qcom,bus-freq = <3>; + qcom,io-fraction = <0>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <1>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <19000000>; + qcom,bus-freq = <0>; + qcom,io-fraction = <0>; + }; + }; + + qcom,dcvs-core-info { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,dcvs-core-info"; + + qcom,num-cores = <1>; + qcom,sensors = <0>; + + qcom,core-core-type = <1>; + + qcom,algo-disable-pc-threshold = <0>; + qcom,algo-em-win-size-min-us = <100000>; + qcom,algo-em-win-size-max-us = <300000>; + qcom,algo-em-max-util-pct = <97>; + qcom,algo-group-id = <95>; + qcom,algo-max-freq-chg-time-us = <100000>; + qcom,algo-slack-mode-dynamic = <100000>; + qcom,algo-slack-weight-thresh-pct = <0>; + qcom,algo-slack-time-min-us = <39000>; + qcom,algo-slack-time-max-us = <39000>; + qcom,algo-ss-win-size-min-us = <1000000>; + qcom,algo-ss-win-size-max-us = <1000000>; + qcom,algo-ss-util-pct = <95>; + qcom,algo-ss-no-corr-below-freq = <0>; + + qcom,energy-active-coeff-a = <2492>; + qcom,energy-active-coeff-b = <0>; + qcom,energy-active-coeff-c = <0>; + qcom,energy-leakage-coeff-a = <11>; + qcom,energy-leakage-coeff-b = <157150>; + qcom,energy-leakage-coeff-c = <0>; + qcom,energy-leakage-coeff-d = <0>; + + qcom,power-current-temp = <25>; + qcom,power-num-freq = <4>; + + qcom,dcvs-freq@0 { + reg = <0>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@1 { + reg = <1>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@2 { + reg = <2>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@3 { + reg = <3>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <844545>; + qcom,leakage-energy-offset = <0>; + }; + }; + + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-iommu-domains.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-iommu-domains.dtsi new file mode 100644 index 000000000..25fca2a54 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-iommu-domains.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,iommu-domains { + compatible = "qcom,iommu-domains"; + + venus_domain_ns: qcom,iommu-domain1 { + label = "venus_ns"; + qcom,iommu-contexts = <&venus_ns>; + qcom,virtual-addr-pool = <0x40000000 0x3f000000 + 0x7f000000 0x1000000>; + }; + + venus_domain_cp: qcom,iommu-domain2 { + label = "venus_cp"; + qcom,iommu-contexts = <&venus_cp>; + qcom,virtual-addr-pool = <0x1000000 0x3f000000>; + qcom,secure-domain; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-iommu.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-iommu.dtsi new file mode 100644 index 000000000..ff3e0a59d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-iommu.dtsi @@ -0,0 +1,237 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm-iommu-v1.dtsi" + +&jpeg_iommu { + status = "ok"; + vdd-supply = <&gdsc_jpeg>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014>; + + qcom,iommu-bfb-data = <0x0000ffff + 0x00000000 + 0x4 + 0x4 + 0x0 + 0x0 + 0x10 + 0x50 + 0x0 + 0x10 + 0x20 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&mdp_iommu { + status = "ok"; + vdd-supply = <&gdsc_mdss>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x00000000 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000013 + 0x00000017 + 0x0 + 0x13 + 0x23 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&venus_iommu { + status = "ok"; + vdd-supply = <&gdsc_venus>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020 + 0x2024 + 0x2028 + 0x202c + 0x2030 + 0x2034 + 0x2038>; + + qcom,iommu-bfb-data = <0xffffffff + 0xffffffff + 0x00000004 + 0x00000008 + 0x00000000 + 0x00000000 + 0x00000094 + 0x000000b4 + 0x0 + 0x94 + 0x114 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&venus_ns { + qcom,iommu-ctx-sids = <0 1 2 3 4 5 7>; +}; + +&venus_cp { + qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84>; +}; + +&kgsl_iommu { + status = "ok"; + vdd-supply = <&gdsc_oxili_cx>; + qcom,alt-vdd-supply = <&gdsc_oxili_gx>; + qcom,iommu-enable-halt; + qcom,needs-alt-core-clk; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008>; + + qcom,iommu-bfb-data = <0x00000003 + 0x0 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000011 + 0x0 + 0x1 + 0x41 + 0x0>; +}; + +&vfe_iommu { + status = "ok"; + vdd-supply = <&gdsc_vfe>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x00000000 + 0x4 + 0x8 + 0x0 + 0x0 + 0x1b + 0x5b + 0x0 + 0x1b + 0x2b + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-ion.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-ion.dtsi new file mode 100644 index 000000000..dee64e538 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-ion.dtsi @@ -0,0 +1,66 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@8 { /* CP_MM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <8>; + qcom,heap-align = <0x1000>; + linux,contiguous-region = <&secure_mem>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + qcom,ion-heap@27 { /* QSECOM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <27>; + linux,contiguous-region = <&qsecom_mem>; + }; + + qcom,ion-heap@28 { /* AUDIO HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <28>; + qcom,heap-align = <0x1000>; + qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */ + qcom,memory-reservation-size = <0x314000>; + }; + qcom,ion-heap@23 { /* OTHER PIL HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <23>; + qcom,heap-align = <0x1000>; + qcom,memory-fixed = <0x06400000 0x2000000>; + }; + qcom,ion-heap@26 { /* MODEM PIL HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <26>; + qcom,heap-align = <0x1000>; + qcom,memory-fixed = <0x08400000 0x4E00000>; + + }; + + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-mdss.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-mdss.dtsi new file mode 100644 index 000000000..f58089709 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-mdss.dtsi @@ -0,0 +1,80 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_mdp@fd900000 { + compatible = "qcom,mdss_mdp"; + reg = <0xfd900000 0x22100>, + <0xfd924000 0x1000>; + reg-names = "mdp_phys", "vbif_phys"; + interrupts = <0 72 0>; + vdd-supply = <&gdsc_mdss>; + + qcom,max-clk-rate = <200000000>; + qcom,mdss-pipe-vig-off = <0x00001200>; + qcom,mdss-pipe-rgb-off = <0x00001E00>; + qcom,mdss-pipe-dma-off = <0x00002A00>; + qcom,mdss-pipe-vig-fetch-id = <1>; + qcom,mdss-pipe-rgb-fetch-id = <7>; + qcom,mdss-pipe-dma-fetch-id = <4>; + qcom,mdss-smp-data = <7 4096>; + + qcom,mdss-ctl-off = <0x00000600 0x00000700>; + qcom,mdss-mixer-intf-off = <0x00003200>; + qcom,mdss-mixer-wb-off = <0x00003E00>; + qcom,mdss-dspp-off = <0x00004600>; + qcom,mdss-pingpong-off = <0x00021B00>; + qcom,mdss-wb-off = <0x00011100 0x00013100>; + qcom,mdss-intf-off = <0x00000000 0x00021300>; + qcom,mdss-rot-block-size = <64>; + + qcom,vbif-settings = <0x004 0x00000001>, + <0x0D8 0x00000707>, + <0x124 0x00000003>; + qcom,mdp-settings = <0x02E0 0x000000A9>, + <0x02E4 0x00000055>; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x800000>; + }; + + mdss_fb1: qcom,mdss_fb_wfd { + cell-index = <1>; + compatible = "qcom,mdss-fb"; + }; + }; + + mdss_dsi0: qcom,mdss_dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0xfd922800 0x600>; + vdd-supply = <&pm8226_l15>; + vddio-supply = <&pm8226_l8>; + vdda-supply = <&pm8226_l4>; + qcom,supply-names = "vdd", "vddio", "vdda"; + qcom,supply-min-voltage-level = <2800000 1800000 1200000>; + qcom,supply-max-voltage-level = <2800000 1800000 1200000>; + qcom,supply-peak-current = <150000 100000 100000>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; + + qcom,mdss_wb_panel { + compatible = "qcom,mdss_wb"; + qcom,mdss_pan_res = <1280 720>; + qcom,mdss_pan_bpp = <24>; + qcom,mdss-fb-map = <&mdss_fb1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-mtp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-mtp.dtsi new file mode 100644 index 000000000..bcd1c41d6 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-mtp.dtsi @@ -0,0 +1,445 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-nt35590-720p-video.dtsi" +/include/ "msm8226-camera-sensor-mtp.dtsi" + +&soc { + serial@f991f000 { + status = "ok"; + }; + + qcom,mdss_dsi_nt35590_720p_video { + status = "ok"; + }; + + i2c@f9927000 { /* BLSP1 QUP5 */ + synaptics@20 { + compatible = "synaptics,rmi4"; + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <17 0x2008>; + vdd-supply = <&pm8226_l19>; + vcc_i2c-supply = <&pm8226_lvs1>; + synaptics,reset-gpio = <&msmgpio 16 0x00>; + synaptics,irq-gpio = <&msmgpio 17 0x2008>; + synaptics,button-map = <139 102 158>; + synaptics,i2c-pull-up; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 108 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 107 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 106 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@3 { + compatible = "micrel,ks8851"; + reg = <3>; + interrupt-parent = <&msmgpio>; + interrupts = <0 115 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&msmgpio 114 0>; + vdd-io-supply = <&pm8226_lvs1>; + vdd-phy-supply = <&pm8226_lvs1>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "SPK_OUT", "MCLK", + "SPK_OUT", "EXT_VDD_SPKR", + "AMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS1 External", + "MIC BIAS1 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic"; + + qcom,cdc-mclk-gpios = <&pm8226_gpios 1 0>; + qcom,cdc-vdd-spkr-gpios = <&pm8226_gpios 2 0>; + }; +}; + +&usb_otg { + #address-cells = <0>; + interrupt-parent = <&usb_otg>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 134 0 + 1 &intc 0 140 0 + 2 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "core_irq", "async_irq", "pmic_id_irq"; + + qcom,hsusb-otg-mode = <3>; + vbus_otg-supply = <&usb_otg_sw>; +}; + +&sdcc1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdcc2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <600>; #address-cells = <0>; interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "disabled"; +}; + +&sdhc_2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "ok"; +}; + +&spmi_bus { + qcom,pm8226@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "manual"; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + }; + }; + + qcom,leds@a300 { + status = "okay"; + qcom,led_mpp_4 { + label = "mpp"; + linux,name = "green"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,source-sel = <8>; + qcom,mode-ctrl = <0x60>; + qcom,pwm-channel = <0>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + + qcom,leds@a500 { + status = "okay"; + qcom,led_mpp_6 { + label = "mpp"; + linux,name = "red"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,mode-ctrl = <0x60>; + qcom,source-sel = <10>; + qcom,pwm-channel = <5>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + }; + + qcom,pm8226@1 { + qcom,leds@d300 { + status = "okay"; + }; + + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <20>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <0>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + }; +}; + +&pm8226_gpios { + gpio@c000 { /* GPIO 1 */ + /* XO_PMIC_CDC_MCLK enable for tapan codec */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS logic */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO*/ + qcom,vin-sel = <3>; /* QPNP_PIN_VIN3 */ + qcom,out-strength = <3>;/* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <3>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; +}; + +&pm8226_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + /* PA_THERM0 config */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <0>; /* AMUX 5 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + /* PA_THERM1 config */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; +}; + +&pm8226_vadc { + chan@14 { + label = "pa_therm0"; + reg = <0x14>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@17 { + label = "pa_therm1"; + reg = <0x17>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8226_bms { + status = "ok"; +}; + +&pm8226_chg { + qcom,charging-disabled; +}; + +&usb_otg_sw { + status = "okay"; +}; + +&slim_msm { + tapan_codec { + qcom,cdc-micbias1-ext-cap; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-pm.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-pm.dtsi new file mode 100644 index 000000000..3240efb75 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-pm.dtsi @@ -0,0 +1,389 @@ +/* Copyright (c) 2013 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f9099000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,core-id = <1>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f90a9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,core-id = <2>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f90b9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,core-id = <3>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f9012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9012000 0x1000>; + qcom,core-id = <0xffff>; /* L2/APCS SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-pmic-data0 = <0x02030080>; + qcom,saw2-pmic-data1 = <0x00030000>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + qcom,saw2-spm-cmd-ret = [00 03 00 7b 0f]; + qcom,saw2-spm-cmd-pc = [00 32 b0 10 e0 d0 6b c0 42 f0 + 11 07 01 b0 4e c0 d0 12 e0 6b 50 02 32 + 50 f0 7b 0f]; /*APCS_PMIC_OFF_L2RAM_OFF*/ + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x61706d73>; /* "smpa" */ + qcom,id = <0x01>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <3>; /* SVS SOC */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x616F646C>; /* "ldoa" */ + qcom,id = <0x03>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <3>; /* SVS SOC */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + + qcom,lpm-resources@3 { + reg = <0x3>; + qcom,name = "l2"; + qcom,local-resource-type; + qcom,init-value = "l2_cache_retention"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <1>; + qcom,ss-power = <784>; + qcom,energy-overhead = <190000>; + qcom,time-overhead = <100>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3000>; + qcom,ss-power = <725>; + qcom,energy-overhead = <99500>; + qcom,time-overhead = <3130>; + }; + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_retention"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <8000>; + qcom,ss-power = <138>; + qcom,energy-overhead = <1208400>; + qcom,time-overhead = <9200>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <4>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <9000>; + qcom,ss-power = <110>; + qcom,energy-overhead = <1250300>; + qcom,time-overhead = <9500>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <16300>; + qcom,ss-power = <63>; + qcom,energy-overhead = <2128000>; + qcom,time-overhead = <24200>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <4>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,latency-us = <24000>; + qcom,ss-power = <10>; + qcom,energy-overhead = <3202600>; + qcom,time-overhead = <33000>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <1>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <26000>; + qcom,ss-power = <2>; + qcom,energy-overhead = <4252000>; + qcom,time-overhead = <38000>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <47 172>, /* usb2_hsic_async_wakeup_irq */ + <53 104>, /* mdss_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <2 216>, /* tsens_upper_lower_int */ + <0xff 56>, /* q6_wdog_expired_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 61>, /* mss_a2_bam_irq */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_low */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr + <0xff 181>, /* o_wcss_apss_wdog_bite_and_reset_rdy */ + <0xff 188>, /* lpass_irq_out_apcs(0) */ + <0xff 189>, /* lpass_irq_out_apcs(1) */ + <0xff 190>, /* lpass_irq_out_apcs(2) */ + <0xff 191>, /* lpass_irq_out_apcs(3) */ + <0xff 192>, /* lpass_irq_out_apcs(4) */ + <0xff 194>, /* lpass_irq_out_apcs[6] */ + <0xff 195>, /* lpass_irq_out_apcs[7] */ + <0xff 196>, /* lpass_irq_out_apcs[8] */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 258>, /* rpm_ipc(28) */ + <0xff 259>, /* rpm_ipc(29) */ + <0xff 275>, /* rpm_ipc(30) */ + <0xff 276>, /* rpm_ipc(31) */ + <0xff 269>, /* rpm_wdog_expired_irq */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <3 1>, + <4 4 >, + <5 5 >, + <6 9 >, + <7 13>, + <8 17>, + <9 21>, + <10 27>, + <11 29>, + <12 31>, + <13 33>, + <14 35>, + <15 37>, + <16 38>, + <17 39>, + <18 41>, + <19 46>, + <20 48>, + <21 49>, + <22 50>, + <23 51>, + <24 52>, + <25 54>, + <26 62>, + <27 63>, + <28 64>, + <29 65>, + <30 66>, + <31 67>, + <32 68>, + <33 69>, + <34 71>, + <35 72>, + <36 106>, + <37 107>, + <38 108>, + <39 109>, + <40 110>, + <54 111>, + <55 113>; + }; + + qcom,pm-8x60@fe805664 { + compatible = "qcom,pm-8x60"; + reg = <0xfe805664 0x40>; + qcom,pc-mode = "tz_l2_int"; + qcom,use-sync-timer; + qcom,pc-resets-timer; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-qrd.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-qrd.dtsi new file mode 100644 index 000000000..fc9d9f9b9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-qrd.dtsi @@ -0,0 +1,406 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-nt35590-720p-video.dtsi" +/include/ "msm8226-camera-sensor-qrd.dtsi" + +&soc { + serial@f991f000 { + status = "ok"; + }; + + qcom,mdss_dsi_nt35590_720p_video { + status = "ok"; + }; + + i2c@f9927000 { /* BLSP1 QUP5 */ + synaptics@20 { + compatible = "synaptics,rmi4"; + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <17 0x2008>; + vdd-supply = <&pm8226_l19>; + vcc_i2c-supply = <&pm8226_lvs1>; + synaptics,reset-gpio = <&msmgpio 16 0x00>; + synaptics,irq-gpio = <&msmgpio 17 0x2008>; + synaptics,button-map = <139 102 158>; + synaptics,i2c-pull-up; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 108 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 107 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 106 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@3 { + compatible = "micrel,ks8851"; + reg = <3>; + interrupt-parent = <&msmgpio>; + interrupts = <0 115 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&msmgpio 114 0>; + vdd-io-supply = <&pm8226_lvs1>; + vdd-phy-supply = <&pm8226_lvs1>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "SPK_OUT", "MCLK", + "SPK_OUT", "EXT_VDD_SPKR", + "AMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS1 External", + "MIC BIAS1 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic"; + + qcom,cdc-mclk-gpios = <&pm8226_gpios 1 0>; + qcom,cdc-vdd-spkr-gpios = <&pm8226_gpios 2 0>; + qcom,cdc-us-euro-gpios = <&msmgpio 69 0>; + }; +}; + +&sdcc1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdcc2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <600>; + + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "disabled"; +}; + +&sdhc_2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "ok"; +}; + +&spmi_bus { + qcom,pm8226@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "manual"; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + }; + }; + + qcom,leds@a300 { + status = "okay"; + qcom,led_mpp_4 { + label = "mpp"; + linux,name = "green"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,source-sel = <8>; + qcom,mode-ctrl = <0x60>; + qcom,pwm-channel = <0>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + + qcom,leds@a500 { + status = "okay"; + qcom,led_mpp_6 { + label = "mpp"; + linux,name = "red"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,mode-ctrl = <0x60>; + qcom,source-sel = <10>; + qcom,pwm-channel = <5>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + }; + + qcom,pm8226@1 { + qcom,leds@d300 { + status = "okay"; + }; + + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <20>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <0>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + + qcom,vibrator@c000 { + status = "okay"; + qcom,vib-timeout-ms = <15000>; + qcom,vib-vtg-level-mV = <3100>; + }; + + }; +}; + +&pm8226_bms { + status = "okay"; + qcom,batt-type = <4>; + qcom,max-voltage-uv = <4350000>; +}; + +&pm8226_chg { + status = "okay"; + qcom,chg-vddmax-mv = <4350>; + qcom,chg-vddsafe-mv = <4350>; +}; + +&pm8226_gpios { + gpio@c000 { /* GPIO 1 */ + /* XO_PMIC_CDC_MCLK enable for tapan codec */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS logic */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO*/ + qcom,vin-sel = <3>; /* QPNP_PIN_VIN3 */ + qcom,out-strength = <3>;/* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <3>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; +}; + +&pm8226_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&slim_msm { + tapan_codec { + qcom,cdc-micbias1-ext-cap; + }; + +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-regulator.dtsi new file mode 100644 index 000000000..3254d17c8 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-regulator.dtsi @@ -0,0 +1,460 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SPM controlled regulators: */ + +&spmi_bus { + qcom,pm8226@1 { + pm8226_s2: spm-regulator@1700 { + compatible = "qcom,spm-regulator"; + regulator-name = "8226_s2"; + reg = <0x1700 0x100>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1275000>; + }; + }; +}; + +/* CPR controlled regulator */ + +&soc { + apc_vreg_corner: regulator@f9018000 { + status = "okay"; + compatible = "qcom,cpr-regulator"; + reg = <0xf9018000 0x1000>, <0xf9011064 4>, <0xfc4b80b0 8>, + <0xfc4bc450 16>; + reg-names = "rbcpr", "rbcpr_clk", "pvs_efuse", "cpr_efuse"; + interrupts = <0 15 0>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + qcom,num-efuse-bits = <5>; + qcom,pvs-bin-process = <0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 2 + 2 2 2 2 3 3 3 3 3 3 3 3 0 0 0 0>; + qcom,pvs-corner-ceiling-slow = <1155000 1160000 1275000>; + qcom,pvs-corner-ceiling-nom = <975000 1075000 1200000>; + qcom,pvs-corner-ceiling-fast = <900000 1000000 1140000>; + vdd-apc-supply = <&pm8226_s2>; + + vdd-mx-supply = <&pm8226_l3_ao>; + qcom,vdd-mx-vmax = <1350000>; + qcom,vdd-mx-vmin-method = <1>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <1>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <15>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <5>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <5000>; + }; +}; + +/* RPM controlled regulators: */ + +&rpm_bus { + rpm-regulator-smpa1 { + status = "okay"; + pm8226_s1: regulator-s1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + pm8226_s1_corner: regulator-s1-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s1_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + qcom,consumer-supplies = "vdd_dig", ""; + }; + pm8226_s1_corner_ao: regulator-s1-corner-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s1_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + qcom,consumer-supplies = "vdd_sr2_dig", ""; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8226_s3: regulator-s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8226_s4: regulator-s4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + qcom,init-voltage = <2100000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa5 { + status = "okay"; + pm8226_s5: regulator-s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <1150000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8226_l1: regulator-l1 { + regulator-name = "8226_l1"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8226_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8226_l3: regulator-l3 { + regulator-name = "8226_l3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + pm8226_l3_ao: regulator-3-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l3_ao"; + qcom,set = <1>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + pm8226_l3_so: regulator-l3-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l3_so"; + qcom,set = <2>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + qcom,init-voltage = <750000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8226_l4: regulator-l4 { + regulator-name = "8226_l4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8226_l5: regulator-l5 { + regulator-name = "8226_l5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8226_l6: regulator-l6 { + regulator-name = "8226_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8226_l7: regulator-l7 { + regulator-name = "8226_l7"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + qcom,init-voltage = <1850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8226_l8: regulator-l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8226_l8_ao: regulator-l8-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l8_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,consumer-supplies = "vdd_sr2_pll", ""; + }; + + pm8226_l8_so: regulator-l8-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l8_so"; + qcom,set = <2>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-enable = <0>; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8226_l9: regulator-l9 { + regulator-name = "8226_l9"; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8226_l10: regulator-l10 { + regulator-name = "8226_l10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8226_l12: regulator-l12 { + regulator-name = "8226_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8226_l14: regulator-l14 { + regulator-name = "8226_l14"; + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + qcom,init-voltage = <2750000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8226_l15: regulator-l15 { + regulator-name = "8226_l15"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8226_l16: regulator-l16 { + regulator-name = "8226_l16"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8226_l17: regulator-l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8226_l18: regulator-l18 { + regulator-name = "8226_l18"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8226_l19: regulator-l19 { + regulator-name = "8226_l19"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + pm8226_l20: regulator-l20 { + regulator-name = "8226_l20"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + pm8226_l21: regulator-l21 { + regulator-name = "8226_l21"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8226_l22: regulator-l22 { + regulator-name = "8226_l22"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + pm8226_l23: regulator-l23 { + regulator-name = "8226_l23"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + pm8226_l24: regulator-l24 { + regulator-name = "8226_l24"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa26 { + status = "okay"; + pm8226_l26: regulator-l26 { + regulator-name = "8226_l26"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa27 { + status = "okay"; + pm8226_l27: regulator-l27 { + regulator-name = "8226_l27"; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa28 { + status = "okay"; + pm8226_l28: regulator-l28 { + regulator-name = "8226_l28"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-vsa1 { + status = "okay"; + pm8226_lvs1: regulator-lvs1 { + status = "okay"; + }; + }; +}; + +&pm8226_chg_boost { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "8226_smbbp_boost"; +}; + +&soc { + usb_otg_sw: regulator-ncp380 { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_sw"; + gpio = <&msmgpio 67 0>; + parent-supply = <&pm8226_chg_boost>; + startup-delay-us = <4000>; + enable-active-high; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-sim.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-sim.dts new file mode 100644 index 000000000..240564632 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-sim.dts @@ -0,0 +1,135 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226.dtsi" +/include/ "msm8226-camera.dtsi" + +/ { + model = "Qualcomm MSM 8226 Simulator"; + compatible = "qcom,msm8226-sim", "qcom,msm8226", "qcom,sim"; + qcom,msm-id = <145 16 0>, + <158 16 0>, + <159 16 0>, + <198 16 0>; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; +}; + +&sdcc1 { + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + vdd-supply = <&pm8226_l17>; + vdd-io-supply = <&pm8226_l6>; + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + status = "ok"; +}; + +&sdcc2 { + vdd-supply = <&pm8226_l18>; + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + status = "ok"; +}; + +&pm8226_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; +}; + +&pm8226_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-smp2p.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-smp2p.dtsi new file mode 100644 index 000000000..3921a686a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-smp2p.dtsi @@ -0,0 +1,225 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-wcnss { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <4>; + qcom,irq-bitmask = <0x40000>; + interrupts = <0 143 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + /* SMP2P SSR Driver for inbound entry from lpass. */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* SMP2P SSR Driver for outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_4_in: qcom,smp2pgpio-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_in { + compatible = "qcom,smp2pgpio_test_smp2p_4_in"; + gpios = <&smp2pgpio_smp2p_4_in 0 0>; + }; + + smp2pgpio_smp2p_4_out: qcom,smp2pgpio-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_in: qcom,smp2pgpio-ssr-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_out: qcom,smp2pgpio-ssr-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_out { + compatible = "qcom,smp2pgpio_test_smp2p_4_out"; + gpios = <&smp2pgpio_smp2p_4_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-cdp.dts new file mode 100644 index 000000000..9c49840d9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v1.dtsi" +/include/ "msm8226-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8226 CDP"; + compatible = "qcom,msm8226-cdp", "qcom,msm8226", "qcom,cdp"; + qcom,msm-id = <145 1 0>, + <158 1 0>, + <159 1 0>, + <198 1 0>, + <205 1 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-mtp.dts new file mode 100644 index 000000000..b1d46b1c4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v1.dtsi" +/include/ "msm8226-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8226 MTP"; + compatible = "qcom,msm8226-mtp", "qcom,msm8226", "qcom,mtp"; + qcom,msm-id = <145 8 0>, + <158 8 0>, + <159 8 0>, + <198 8 0>, + <205 8 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-qrd.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-qrd.dts new file mode 100644 index 000000000..d2aabac0c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1-qrd.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v1.dtsi" +/include/ "msm8226-qrd.dtsi" + +/ { + model = "Qualcomm MSM 8226 QRD"; + compatible = "qcom,msm8226-qrd", "qcom,msm8226", "qcom,qrd"; + qcom,msm-id = <145 11 0>, + <158 11 0>, + <159 11 0>, + <198 11 0>, + <205 11 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1.dtsi new file mode 100644 index 000000000..d471bece9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v1.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8226.dtsi file. + */ + +/include/ "msm8226.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-cdp.dts new file mode 100644 index 000000000..2b18491d9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v2.dtsi" +/include/ "msm8226-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8226v2 CDP"; + compatible = "qcom,msm8226-cdp", "qcom,msm8226", "qcom,cdp"; + qcom,msm-id = <145 1 0x20000>, + <158 1 0x20000>, + <159 1 0x20000>, + <198 1 0x20000>, + <205 1 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-mtp.dts new file mode 100644 index 000000000..f15dd4cb9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v2.dtsi" +/include/ "msm8226-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8226v2 MTP"; + compatible = "qcom,msm8226-mtp", "qcom,msm8226", "qcom,mtp"; + qcom,msm-id = <145 8 0x20000>, + <158 8 0x20000>, + <159 8 0x20000>, + <198 8 0x20000>, + <205 8 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-qrd.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-qrd.dts new file mode 100644 index 000000000..1a89d7894 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2-qrd.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v2.dtsi" +/include/ "msm8226-qrd.dtsi" + +/ { + model = "Qualcomm MSM 8226v2 QRD"; + compatible = "qcom,msm8226-qrd", "qcom,msm8226", "qcom,qrd"; + qcom,msm-id = <145 11 0x20000>, + <158 11 0x20000>, + <159 11 0x20000>, + <198 11 0x20000>, + <205 11 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2.dtsi new file mode 100644 index 000000000..d471bece9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226-v2.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8226.dtsi file. + */ + +/include/ "msm8226.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226.dtsi new file mode 100644 index 000000000..7c981043c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8226.dtsi @@ -0,0 +1,1248 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM 8226"; + compatible = "qcom,msm8226"; + interrupt-parent = <&intc>; + + aliases { + spi0 = &spi_0; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + memory { + secure_mem: secure_region { + linux,contiguous-region; + reg = <0 0x6D00000>; + label = "secure_mem"; + }; + + qsecom_mem: qsecom_region { + linux,contiguous-region; + reg = <0 0x780000>; + label = "qsecom_mem"; + }; + }; + + soc: soc { }; +}; + +/include/ "msm8226-ion.dtsi" +/include/ "msm8226-camera.dtsi" +/include/ "msm-gdsc.dtsi" +/include/ "msm8226-iommu.dtsi" +/include/ "msm8226-pm.dtsi" +/include/ "msm8226-smp2p.dtsi" +/include/ "msm8226-gpu.dtsi" +/include/ "msm8226-bus.dtsi" +/include/ "msm8226-mdss.dtsi" +/include/ "msm8226-coresight.dtsi" +/include/ "msm8226-iommu-domains.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <117>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + qcom,mpm2-sleep-counter@fc4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xfc4a3000 0x1000>; + clock-frequency = <32768>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + qcom,vidc@fdc00000 { + compatible = "qcom,msm-vidc"; + reg = <0xfdc00000 0xff000>; + interrupts = <0 44 0>; + qcom,load-freq-tbl = <352800 160000000>, + <244800 133330000>, + <108000 66700000>; + qcom,hfi = "venus"; + qcom,bus-ports = <1>; + qcom,reg-presets = <0xE0024 0x0>, + <0x80124 0x3>, + <0xE0020 0x5555556>, + <0x800B0 0x10101001>, + <0x800B4 0x00101010>, + <0x800C0 0x1010100f>, + <0x800C4 0x00101010>, + <0x800D0 0x00000010>, + <0x800D4 0x00000010>, + <0x800D8 0x00000707>; + qcom,enc-ddr-ab-ib = <0 0>, + <129000 142000>, + <384000 422000>, + <866000 953000>; + qcom,dec-ddr-ab-ib = <0 0>, + <103000 134000>, + <268000 348000>, + <505000 657000>; + qcom,iommu-groups = <&venus_domain_ns &venus_domain_cp>; + qcom,iommu-group-buffer-types = <0xfff 0x1ff>; + qcom,buffer-type-tz-usage-table = <0x1 0x1>, + <0x1fe 0x2>; + qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */ + }; + + qcom,wfd { + compatible = "qcom,msm-wfd"; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + serial@f995e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf995e000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + qcom,sps@f9984000 { + compatible = "qcom,msm_sps"; + reg = <0xf9984000 0x15000>, + <0xf9999000 0xb000>; + interrupts = <0 94 0>; + }; + + qcom,usbbam@f9a44000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xf9a44000 0x11000>; + reg-names = "hsusb"; + interrupts = <0 135 0>; + interrupt-names = "hsusb"; + qcom,usb-bam-num-pipes = <16>; + qcom,usb-bam-fifo-baseaddr = <0xfe803000>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + + qcom,pipe0 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <3>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37c000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x600>; + qcom,descriptor-fifo-offset = <0x600>; + qcom,descriptor-fifo-size = <0x200>; + }; + }; + + usb_otg: usb@f9a55000 { + compatible = "qcom,hsusb-otg"; + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0>, <0 140 0>; + interrupt-names = "core_irq", "async_irq"; + hsusb_vdd_dig-supply = <&pm8226_s1_corner>; + HSUSB_1p8-supply = <&pm8226_l10>; + HSUSB_3p3-supply = <&pm8226_l20>; + qcom,vdd-voltage-level = <1 5 7>; + + qcom,hsusb-otg-phy-init-seq = + <0x44 0x80 0x68 0x81 0x24 0x82 0x13 0x83 0xffffffff>; + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <2>; + qcom,hsusb-otg-disable-reset; + qcom,dp-manual-pullup; + + qcom,msm-bus,name = "usb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 60000 960000>; + }; + + android_usb@fe8050c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8050c8 0xc8>; + qcom,android-usb-cdrom; + qcom,android-usb-swfi-latency = <1>; + }; + + wcd9xxx_intc: wcd9xxx-irq { + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&msmgpio>; + interrupts = <68 0>; + interrupt-names = "cdc-int"; + }; + + slim_msm: slim@fe12f000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xfe12f000 0x35000>, + <0xfe104000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + + tapan_codec { + compatible = "qcom,tapan-slim-pgd"; + elemental-addr = [00 01 E0 00 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28>; + qcom,cdc-reset-gpio = <&msmgpio 72 0>; + + cdc-vdd-buck-supply = <&pm8226_s4>; + qcom,cdc-vdd-buck-voltage = <2100000 2100000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-vdd-h-supply = <&pm8226_l6>; + qcom,cdc-vdd-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-h-current = <25000>; + + cdc-vdd-px-supply = <&pm8226_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <25000>; + + cdc-vdd-a-1p2v-supply = <&pm8226_l4>; + qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-a-1p2v-current = <10000>; + + cdc-vdd-cx-supply = <&pm8226_l4>; + qcom,cdc-vdd-cx-voltage = <1200000 1200000>; + qcom,cdc-vdd-cx-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-vdd-h", + "cdc-vdd-px", + "cdc-vdd-a-1p2v", + "cdc-vdd-cx"; + + qcom,cdc-micbias-ldoh-v = <0x3>; + qcom,cdc-micbias-cfilt1-mv = <1800>; + qcom,cdc-micbias-cfilt2-mv = <2700>; + qcom,cdc-micbias-cfilt3-mv = <1800>; + + qcom,cdc-micbias1-cfilt-sel = <0x0>; + qcom,cdc-micbias2-cfilt-sel = <0x1>; + qcom,cdc-micbias3-cfilt-sel = <0x2>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tapan-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 E0 00 17 02]; + }; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + sound { + compatible = "qcom,msm8226-audio-tapan"; + qcom,model = "msm8226-tapan-snd-card"; + qcom,tapan-mclk-clk-freq = <9600000>; + qcom,prim-auxpcm-gpio-clk = <&msmgpio 63 0>; + qcom,prim-auxpcm-gpio-sync = <&msmgpio 64 0>; + qcom,prim-auxpcm-gpio-din = <&msmgpio 65 0>; + qcom,prim-auxpcm-gpio-dout = <&msmgpio 66 0>; + qcom,prim-auxpcm-gpio-set = "prim-gpio-prim"; + }; + + qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + }; + + qcom,msm-pcm-lpa { + compatible = "qcom,msm-pcm-lpa"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + }; + + qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + qcom,msm-dai-q6-hdmi { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <8>; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + qcom,msm-dai-q6-sb-0-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16384>; + }; + + qcom,msm-dai-q6-sb-0-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16385>; + }; + + qcom,msm-dai-q6-sb-1-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16386>; + }; + + qcom,msm-dai-q6-sb-1-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16387>; + }; + + qcom,msm-dai-q6-sb-3-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16390>; + }; + + qcom,msm-dai-q6-sb-3-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16391>; + }; + + qcom,msm-dai-q6-sb-4-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16392>; + }; + + qcom,msm-dai-q6-sb-4-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16393>; + }; + + qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + qcom,msm-auxpcm { + compatible = "qcom,msm-auxpcm-resource"; + qcom,msm-cpudai-auxpcm-clk = "pcm_clk"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-slot = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + + qcom,msm-prim-auxpcm-rx { + qcom,msm-auxpcm-dev-id = <4106>; + compatible = "qcom,msm-auxpcm-dev"; + }; + + qcom,msm-prim-auxpcm-tx { + qcom,msm-auxpcm-dev-id = <4107>; + compatible = "qcom,msm-auxpcm-dev"; + }; + }; + + qcom,wcnss-wlan@fb000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xfb000000 0x280000>, + <0xf9011008 0x04>; + reg-names = "wcnss_mmio", "wcnss_fiq"; + interrupts = <0 145 0 0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8226_l3>; + qcom,pronto-vddcx-supply = <&pm8226_s1>; + qcom,pronto-vddpx-supply = <&pm8226_l6>; + qcom,iris-vddxo-supply = <&pm8226_l10>; + qcom,iris-vddrfa-supply = <&pm8226_l24>; + qcom,iris-vddpa-supply = <&pm8226_l16>; + qcom,iris-vdddig-supply = <&pm8226_l24>; + + gpios = <&msmgpio 40 0>, <&msmgpio 41 0>, <&msmgpio 42 0>, <&msmgpio 43 0>, <&msmgpio 44 0>; + qcom,has-pronto-hw; + qcom,has-autodetect-xo; + }; + + qcom,msm-adsp-sensors { + compatible = "qcom,msm-adsp-sensors"; + qcom,src-id = <11>; + qcom,dst-id = <604>; + qcom,ab = <32505856>; + qcom,ib = <32505856>; + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + }; + + qcom,smem@fa00000 { + compatible = "qcom,smem"; + reg = <0xfa00000 0x100000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1000>; + qcom,pil-string = "modem"; + interrupts = <0 25 1>; + }; + + qcom,smsm-modem { + compatible = "qcom,smsm"; + qcom,smsm-edge = <0>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x2000>; + interrupts = <0 26 1>; + }; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-wcnss { + compatible = "qcom,smd"; + qcom,smd-edge = <6>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x20000>; + qcom,pil-string = "wcnss"; + interrupts = <0 142 1>; + }; + + qcom,smsm-wcnss { + compatible = "qcom,smsm"; + qcom,smsm-edge = <6>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x80000>; + interrupts = <0 144 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,bcl { + compatible = "qcom,bcl"; + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + + reg = <0xf9824000 0x800>, + <0xf9824800 0x100>, + <0xf9804000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 123 0>, <0 137 0>; + interrupt-names = "core_irq", "bam_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdhc_1: sdhci@f9824900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + + reg = <0xf98a4000 0x800>, + <0xf98a4800 0x100>, + <0xf9884000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 125 0>, <0 220 0>; + interrupt-names = "core_irq", "bam_irq"; + + qcom,bus-width = <4>; + status = "disabled"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + status = "disabled"; + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0>, <0 187 0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + i2c@f9926000 { /* BLSP-1 QUP-4 */ + cell-index = <0>; + compatible = "qcom,i2c-qup"; + reg = <0xf9926000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 98 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + }; + + i2c@f9927000 { /* BLSP1 QUP5 */ + cell-index = <5>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9927000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 99 0>; + qcom,i2c-bus-freq = <384000>; + qcom,i2c-src-freq = <19200000>; + }; + + qcom,acpuclk@f9011050 { + compatible = "qcom,acpuclk-a7"; + reg = <0xf9011050 0x8>; + reg-names = "rcg_base"; + a7_cpu-supply = <&apc_vreg_corner>; + }; + + qcom,ocmem@fdd00000 { + compatible = "qcom,msm-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfdd02000 0x2000>, + <0xfe039000 0x400>, + <0xfec00000 0x20000>; + reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical"; + interrupts = <0 76 0 0 77 0>; + interrupt-names = "ocmem_irq", "dm_irq"; + qcom,ocmem-num-regions = <0x1>; + qcom,ocmem-num-macros = <0x2>; + qcom,resource-type = <0x706d636f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfec00000 0x20000>; + + partition@0 { + reg = <0x0 0x20000>; + qcom,ocmem-part-name = "graphics"; + qcom,ocmem-part-min = <0x20000>; + }; + }; + + qcom,venus@fdce0000 { + compatible = "qcom,pil-venus"; + reg = <0xfdce0000 0x4000>, + <0xfdc80000 0x400>; + reg-names = "wrapper_base", "vbif_base"; + vdd-supply = <&gdsc_venus>; + + qcom,firmware-name = "venus"; + }; + + qcom,pronto@fb21b000 { + compatible = "qcom,pil-pronto"; + reg = <0xfb21b000 0x3000>, + <0xfc401700 0x4>, + <0xfd485300 0xc>; + reg-names = "pmu_base", "clk_base", "halt_base"; + interrupts = <0 149 1>; + vdd_pronto_pll-supply = <&pm8226_l8>; + + qcom,firmware-name = "wcnss"; + + /* GPIO inputs from wcnss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>; + + /* GPIO output to wcnss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>; + }; + + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + + qcom,lpass@fe200000 { + compatible = "qcom,pil-q6v5-lpass"; + reg = <0xfe200000 0x00100>, + <0xfd485100 0x00010>, + <0xfc4016c0 0x00004>; + reg-names = "qdsp6_base", "halt_base", "restart_reg"; + vdd_cx-supply = <&pm8226_s1_corner>; + interrupts = <0 162 1>; + + qcom,firmware-name = "adsp"; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + qcom,mss@fc880000 { + compatible = "qcom,pil-q6v5-mss"; + reg = <0xfc880000 0x100>, + <0xfd485000 0x400>, + <0xfc820000 0x020>, + <0xfc401680 0x004>, + <0xfd485194 0x4>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg", "cxrail_bhs_reg"; + + interrupts = <0 24 1>; + vdd_cx-supply = <&pm8226_s1_corner>; + vdd_mx-supply = <&pm8226_l3>; + vdd_pll-supply = <&pm8226_l8>; + qcom,vdd_pll = <1800000>; + + qcom,is-loadable; + qcom,firmware-name = "mba"; + qcom,pil-self-auth; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x6400000 0x9b00000>; /* Address and Size of Hole */ + }; + + tsens: tsens@fc4a8000 { + compatible = "qcom,msm-tsens"; + reg = <0xfc4a8000 0x2000>, + <0xfc4b8000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + qcom,sensors = <4>; + qcom,slope = <2901 2846 3038 2955>; + qcom,calib-mode = "fuse_map2"; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <0>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-control-mask = <0xf>; + }; + + spi_0: spi@f9923000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xf9923000 0x1000>, + <0xf9904000 0xF000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 0>, <0 238 0>; + spi-max-frequency = <19200000>; + + gpios = <&msmgpio 3 0>, /* CLK */ + <&msmgpio 1 0>, /* MISO */ + <&msmgpio 0 0>; /* MOSI */ + cs-gpios = <&msmgpio 22 0>; + + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + }; + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + qcom,msm-rng@f9bff000 { + compatible = "qcom,msm-rng"; + reg = <0xf9bff000 0x200>; + qcom,msm-rng-iface-clk; + }; + + qcom,tz-log@fe805720 { + compatible = "qcom,tz-log"; + reg = <0x0fe805720 0x1000>; + }; + + jtag_mm0: jtagmm@fc33c000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc33c000 0x1000>, + <0xfc330000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm1: jtagmm@fc33d000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc33d000 0x1000>, + <0xfc332000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm2: jtagmm@fc33e000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc33e000 0x1000>, + <0xfc334000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm3: jtagmm@fc33f000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc33f000 0x1000>, + <0xfc336000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + qcom,qseecom@d980000 { + compatible = "qcom,qseecom"; + reg = <0xd980000 0x256000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; + + qcom,qcrypto@fd404000 { + compatible = "qcom,qcrypto"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + }; + + qcom,qcedev@fd400000 { + compatible = "qcom,qcedev"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + }; + + cpu-pmu { + compatible = "arm,cortex-a7-pmu"; + qcom,irq-is-percpu; + interrupts = <1 7 0xf00>; + }; +}; + +&gdsc_venus { + qcom,clock-names = "core_clk"; + status = "ok"; +}; + +&gdsc_mdss { + qcom,clock-names = "core_clk", "lut_clk"; + status = "ok"; +}; + +&gdsc_jpeg { + qcom,clock-names = "core_clk"; + status = "ok"; +}; + +&gdsc_vfe { + qcom,clock-names = "core_clk", "csi_clk", "cpp_clk"; + status = "ok"; +}; + +&gdsc_oxili_cx { + qcom,clock-names = "core_clk"; + status = "ok"; +}; + +&gdsc_usb_hsic { + status = "ok"; +}; + +/include/ "msm-pm8226-rpm-regulator.dtsi" +/include/ "msm-pm8226.dtsi" +/include/ "msm8226-regulator.dtsi" + +&pm8226_vadc { + chan@0 { + label = "usb_in"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@2 { + label = "vchg_sns"; + reg = <2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <3>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@31 { + label = "batt_id"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b2 { + label = "xo_therm_pu2"; + reg = <0xb2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@39 { + label = "usb_id_nopull"; + reg = <0x39>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8226_adc_tm { + /* Channel Node */ + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x48>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x68>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x70>; + }; + + chan@14 { + label = "pa_therm0"; + reg = <0x14>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; + + chan@17 { + label = "pa_therm1"; + reg = <0x17>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x80>; + qcom,thermal-node; + }; +}; + +&pm8226_chg { + status = "ok"; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-bus.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-bus.dtsi new file mode 100644 index 000000000..d9bb6ab20 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-bus.dtsi @@ -0,0 +1,1014 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm-mmss-noc@fc478000 { + compatible = "msm-bus-fabric"; + reg = <0xfc478000 0x00004000>; + cell-id = <2048>; + label = "msm_mmss_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <52>; + coresight-name = "coresight-mnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <5>; + + mas-mdp-port0 { + cell-id = <22>; + label = "mas-mdp-port0"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <8>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + mas-vfe { + cell-id = <29>; + label = "mas-vfe"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <2>; + qcom,mas-hw-id = <11>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + mas-mdpe { + cell-id = <92>; + label = "mas-mdpe"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,ws = <10000>; + qcom,qport = <7>; + qcom,mas-hw-id = <11>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + fab-bimc { + cell-id = <0>; + label = "fab-bimc"; + qcom,gateway; + qcom,slavep = <16>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <16>; + }; + + slv-camera-cfg { + cell-id = <589>; + label = "slv-camera-cfg"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <3>; + }; + + slv-display-cfg { + cell-id = <590>; + label = "slv-display-cfg"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <4>; + }; + + slv-cpr-cfg { + cell-id = <592>; + label = "slv-cpr-cfg"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <6>; + }; + + slv-cpr-xpu-cfg { + cell-id = <593>; + label = "slv-cpr-xpu-cfg"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <7>; + }; + + slv-misc-cfg { + cell-id = <594>; + label = "slv-misc-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <8>; + }; + + slv-misc-xpu-cfg { + cell-id = <595>; + label = "slv-misc-xpu-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <9>; + }; + + slv-gfx3d-cfg { + cell-id = <598>; + label = "slv-gfx3d-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <11>; + }; + + slv-mmss-clk-cfg { + cell-id = <599>; + label = "slv-mmss-clk-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <12>; + }; + + slv-mmss-clk-xpu-cfg { + cell-id = <600>; + label = "slv-mmss-clk-xpu-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <13>; + }; + + slv-mnoc-mpu-cfg { + cell-id = <601>; + label = "slv-mnoc-mpu-cfg"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <14>; + }; + + slv-onoc-mpu-cfg { + cell-id = <602>; + label = "slv-onoc-mpu-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <15>; + }; + + slv-service-mnoc { + cell-id = <603>; + label = "slv-service-mnoc"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <17>; + }; + + slv-dsi-cfg { + cell-id = <649>; + label = "slv-dsi-cfg"; + qcom,slavep = <19>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <19>; + }; + }; + + msm-sys-noc@fc460000 { + compatible = "msm-bus-fabric"; + reg = <0xfc460000 0x00004000>; + cell-id = <1024>; + label = "msm_sys_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <50>; + coresight-name = "coresight-snoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <3>; + + mas-lpass-ahb { + cell-id = <52>; + label = "mas-lpass-ahb"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,mas-hw-id = <18>; + }; + + mas-qdss-bam { + cell-id = <53>; + label = "mas-qdss-bam"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,mas-hw-id = <19>; + }; + + mas-snoc-cfg { + cell-id = <54>; + label = "mas-snoc-cfg"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,mas-hw-id = <20>; + }; + + fab-bimc { + cell-id = <0>; + label= "fab-bimc"; + qcom,gateway; + qcom,slavep = <7>; + qcom,masterp = <3>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <21>; + qcom,slv-hw-id = <24>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,slavep = <8>; + qcom,masterp = <4>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <22>; + qcom,slv-hw-id = <25>; + }; + + fab-pnoc { + cell-id = <4096>; + label = "fab-pnoc"; + qcom,gateway; + qcom,slavep = <10>; + qcom,masterp = <10>; + qcom,buswidth = <8>; + qcom,qport = <8>; + qcom,mas-hw-id = <29>; + qcom,slv-hw-id = <28>; + qcom,mode = "Fixed"; + qcom,prio0 = <2>; + qcom,prio1 = <2>; + }; + + fab-ovnoc { + cell-id = <6144>; + label = "fab-ovnoc"; + qcom,gateway; + qcom,buswidth = <8>; + qcom,mas-hw-id = <53>; + qcom,slv-hw-id = <77>; + }; + + mas-crypto-core0 { + cell-id = <55>; + label = "mas-crypto-core0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,mas-hw-id = <23>; + qcom,hw-sel = "NoC"; + qcom,prio0 = <1>; + qcom,prio1 = <1>; + }; + + mas-mss { + cell-id = <38>; + label = "mas-mss"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,mas-hw-id = <26>; + }; + + mas-mss-nav { + cell-id = <57>; + label = "mas-mss-nav"; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,mas-hw-id = <27>; + }; + + mas-ocmem-dma { + cell-id = <58>; + label = "mas-ocmem-dma"; + qcom,masterp = <9>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <7>; + qcom,mas-hw-id = <28>; + }; + + mas-wcss { + cell-id = <59>; + label = "mas-wcss"; + qcom,masterp = <11>; + qcom,tier = <2>; + qcom,mas-hw-id = <30>; + }; + + mas-qdss-etr { + cell-id = <60>; + label = "mas-qdss-etr"; + qcom,masterp = <12>; + qcom,tier = <2>; + qcom,qport = <10>; + qcom,mode = "Fixed"; + qcom,mas-hw-id = <31>; + }; + + slv-ocmem { + cell-id = <604>; + label = "slv-gmem"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <18>; + }; + + slv-ampss { + cell-id = <520>; + label = "slv-ampss"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <20>; + }; + + slv-lpass { + cell-id = <522>; + label = "slv-lpass"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <21>; + }; + + slv-wcss { + cell-id = <584>; + label = "slv-wcss"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <23>; + }; + + slv-ocimem { + cell-id = <585>; + label = "slv-ocimem"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <26>; + }; + + slv-service-snoc { + cell-id = <587>; + label = "slv-service-snoc"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <29>; + }; + + slv-qdss-stm { + cell-id = <588>; + label = "slv-qdss-stm"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <30>; + }; + + }; + + msm-periph-noc@fc468000 { + compatible = "msm-bus-fabric"; + reg = <0xfc468000 0x00004000>; + cell-id = <4096>; + label = "msm_periph_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <54>; + coresight-name = "coresight-pnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <6>; + + mas-pnoc-cfg { + cell-id = <88>; + label = "mas-pnoc-cfg"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <43>; + }; + + mas-sdcc-1 { + cell-id = <78>; + label = "mas-sdcc-1"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <33>; + }; + + mas-sdcc-2 { + cell-id = <81>; + label = "mas-sdcc-2"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <35>; + }; + + mas-blsp-1 { + cell-id = <86>; + label = "mas-blsp-1"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <41>; + }; + + mas-usb-hs { + cell-id = <87>; + label = "mas-usb-hs"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <42>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <12>; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <45>; + qcom,mas-hw-id = <44>; + }; + + slv-sdcc-1 { + cell-id = <606>; + label = "slv-sdcc-1"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <31>; + }; + + slv-sdcc-2 { + cell-id = <608>; + label = "slv-sdcc-2"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <33>; + }; + + slv-blsp-1 { + cell-id = <613>; + label = "slv-blsp-1"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <39>; + }; + + slv-usb-hs { + cell-id = <614>; + label = "slv-usb-hs"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <40>; + }; + + slv-pdm { + cell-id = <615>; + label = "slv-pdm"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <41>; + }; + + slv-periph-apu-cfg { + cell-id = <616>; + label = "slv-periph-apu-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <42>; + }; + + slv-pnoc-mpu-cfg { + cell-id = <617>; + label = "slv-pnoc-mpu-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <43>; + }; + + slv-prng { + cell-id = <618>; + label = "slv-prng"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <44>; + }; + + slv-service-pnoc { + cell-id = <619>; + label = "slv-service-pnoc"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <46>; + }; + + }; + + msm-config-noc@fc480000 { + compatible = "msm-bus-fabric"; + reg = <0xfc480000 0x00004000>; + cell-id = <5120>; + label = "msm_config_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-rpm-inst { + cell-id = <72>; + label = "mas-rpm-inst"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <45>; + }; + + mas-rpm-data { + cell-id = <73>; + label = "mas-rpm-data"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <46>; + }; + + mas-rpm-sys { + cell-id = <74>; + label = "mas-rpm-sys"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <47>; + }; + + mas-dehr { + cell-id = <75>; + label = "mas-dehr"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <48>; + }; + + mas-qdss-dsp { + cell-id = <76>; + label = "mas-qdss-dap"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <49>; + }; + + mas-spdm { + cell-id = <36>; + label = "mas-spdm"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <50>; + }; + + mas-tic { + cell-id = <77>; + label = "mas-tic"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <51>; + }; + + slv-clk-ctl { + cell-id = <620>; + label = "slv-clk-ctl"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <47>; + }; + + slv-cnoc-mss { + cell-id = <621>; + label = "slv-cnoc-mss"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <48>; + }; + + slv-security { + cell-id = <622>; + label = "slv-security"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <49>; + }; + + slv-tcsr { + cell-id = <623>; + label = "slv-tcsr"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <50>; + }; + + slv-tlmm { + cell-id = <624>; + label = "slv-tlmm"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <51>; + }; + + slv-crypto-0-cfg { + cell-id = <625>; + label = "slv-crypto-0-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <52>; + }; + + slv-imem-cfg { + cell-id = <627>; + label = "slv-imem-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <54>; + }; + + slv-message-ram { + cell-id = <628>; + label = "slv-message-ram"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <55>; + }; + + slv-bimc-cfg { + cell-id = <629>; + label = "slv-bimc-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <56>; + }; + + slv-boot-rom { + cell-id = <630>; + label = "slv-boot-rom"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <57>; + }; + + slv-pmic-arb { + cell-id = <632>; + label = "slv-pmic-arb"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <59>; + }; + + slv-spdm-wrapper { + cell-id = <633>; + label = "slv-spdm-wrapper"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <60>; + }; + + slv-dehr-cfg { + cell-id = <634>; + label = "slv-dehr-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <61>; + }; + + slv-mpm { + cell-id = <536>; + label = "slv-mpm"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <62>; + }; + + slv-qdss-cfg { + cell-id = <635>; + label = "slv-qdss-cfg"; + qcom,slavep = <16>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <63>; + }; + + slv-rbcpr-cfg { + cell-id = <636>; + label = "slv-rbcpr-cfg"; + qcom,slavep = <17>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <64>; + }; + + slv-rbcpr-qdss-apu-cfg { + cell-id = <637>; + label = "slv-rbcpr-qdss-apu-cfg"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <65>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <26>; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <52>; + qcom,slv-hw-id = <75>; + }; + + slv-cnoc-mnoc-mmss-cfg { + cell-id = <631>; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <58>; + }; + + slv-cnoc-mnoc-cfg { + cell-id = <640>; + label = "slv-cnoc-mnoc-cfg"; + qcom,slavep = <19>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <66>; + }; + + slv-pnoc-cfg { + cell-id = <641>; + label = "slv-pnoc-cfg"; + qcom,slavep = <21>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <69>; + }; + + slv-snoc-mpu-cfg { + cell-id = <638>; + label = "slv-snoc-mpu-cfg"; + qcom,slavep = <20>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <67>; + }; + + slv-snoc-cfg { + cell-id = <642>; + label = "slv-snoc-cfg"; + qcom,slavep = <22>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <70>; + }; + + slv-phy-apu-cfg { + cell-id = <644>; + label = "slv-phy-apu-cfg"; + qcom,slavep = <23>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <72>; + }; + + slv-ebi1-phy-cfg { + cell-id = <645>; + label = "slv-ebi1-phy-cfg"; + qcom,slavep = <24>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <73>; + }; + + slv-rpm { + cell-id = <534>; + label = "slv-rpm"; + qcom,slavep = <25>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <74>; + }; + + slv-service-cnoc { + cell-id = <646>; + label = "slv-service-cnoc"; + qcom,slavep = <27>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <76>; + }; + + }; + + msm-bimc@0xfc380000 { + compatible = "msm-bus-fabric"; + reg = <0xfc380000 0x0006A000>; + cell-id = <0>; + label = "msm_bimc"; + qcom,fabclk-dual = "mem_clk"; + qcom,fabclk-active = "mem_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "BIMC"; + qcom,rpm-en; + + coresight-id = <55>; + coresight-name = "coresight-bimc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <3>; + + mas-ampss-m0 { + cell-id = <1>; + label = "mas-ampss-m0"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Fixed"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <0>; + qcom,prio-rd = <1>; + qcom,prio-wr = <1>; + qcom,prio-lvl = <1>; + }; + + mas-mss-proc { + cell-id = <65>; + label = "mas-mss-proc"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <1>; + }; + + fab-mmss-noc { + cell-id = <2048>; + label = "fab_mmss_noc"; + qcom,masterp = <1>; + qcom,qport = <1>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Bypass"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <2>; + qcom,masterp = <2>; + qcom,qport = <2>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <3>; + qcom,slv-hw-id = <2>; + }; + + mas-lpass-proc { + cell-id = <11>; + label = "mas-lpass-proc"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,qport = <4>; + qcom,mas-hw-id = <25>; + qcom,mode = "Fixed"; + qcom,prio0 = <1>; + qcom,prio1 = <1>; + }; + + mas-gfx3d { + cell-id = <26>; + label = "mas-gfx3d"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,ws = <10000>; + qcom,qport = <5>; + qcom,mas-hw-id = <6>; + }; + + + slv-ebi-ch0 { + cell-id = <512>; + label = "slv-ebi-ch0"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <0>; + }; + }; + +}; + + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-camera-sensor-cdp-mtp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-camera-sensor-cdp-mtp.dtsi new file mode 100644 index 000000000..d05726006 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-camera-sensor-cdp-mtp.dtsi @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&i2c { + + led_flash0: qcom,led-flash@60 { + cell-index = <0>; + reg = <0x60>; + qcom,slave-id = <0x60 0x00 0x0011>; + compatible = "qcom,led-flash"; + qcom,flash-name = "adp1600"; + qcom,flash-type = <1>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 18 0>, + <&msmgpio 19 0>; + qcom,gpio-flash-en = <0>; + qcom,gpio-flash-now = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <0 0>; + qcom,gpio-req-tbl-label = "FLASH_EN", + "FLASH_NOW"; + }; + + actuator0: qcom,actuator@6e { + cell-index = <3>; + reg = <0x6c>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6f { + compatible = "qcom,ov8825"; + reg = <0x6f>; + qcom,slave-id = <0x6c 0x300a 0x8825>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov8825"; + cam_vdig-supply = <&pm8110_l2>; + cam_vana-supply = <&pm8110_l19>; + cam_vio-supply = <&pm8110_l14>; + cam_vaf-supply = <&pm8110_l16>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 0 0 0>; + qcom,cam-vreg-min-voltage = <1200000 1800000 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1200000 1800000 2850000 3000000>; + qcom,cam-vreg-op-mode = <200000 8000 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 13 0>, + <&msmgpio 21 0>, + <&msmgpio 20 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,csi-lane-assign = <0xe4>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; + + qcom,camera@6d { + compatible = "qcom,ov9724"; + reg = <0x6d>; + qcom,slave-id = <0x20 0x0 0x9724>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov9724"; + cam_vdig-supply = <&pm8110_l4>; + cam_vana-supply = <&pm8110_l19>; + cam_vio-supply = <&pm8110_l14>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-type = <0 1 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 14 0>, + <&msmgpio 15 0>, + <&msmgpio 8 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0xe4>; + qcom,csi-lane-mask = <0x1>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-camera.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-camera.dtsi new file mode 100644 index 000000000..b1c94dd24 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-camera.dtsi @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc{ + qcom,msm-cam@fd8c0000 { + compatible = "qcom,msm-cam"; + reg = <0xfd8C0000 0x10000>; + reg-names = "msm-cam"; + }; + + qcom,csiphy@fda00c00 { + cell-index = <0>; + compatible = "qcom,csiphy"; + reg = <0xfda00c00 0x1f4>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + }; + + qcom,csiphy@fda01000 { + cell-index = <1>; + compatible = "qcom,csiphy"; + reg = <0xfda01000 0x1f4>; + reg-names = "csiphy"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + }; + + qcom,csid@fda00000 { + cell-index = <0>; + compatible = "qcom,csid"; + reg = <0xfda00000 0x100>; + reg-names = "csid"; + interrupts = <0 50 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8110_l4>; + }; + + qcom,csid@fda00400 { + cell-index = <1>; + compatible = "qcom,csid"; + reg = <0xfda00400 0x100>; + reg-names = "csid"; + interrupts = <0 51 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8110_l4>; + }; + + qcom,ispif@fda00800 { + cell-index = <0>; + compatible = "qcom,ispif"; + reg = <0xfda00800 0x200>; + reg-names = "ispif"; + interrupts = <0 52 0>; + interrupt-names = "ispif"; + }; + + qcom,vfe@fde00000 { + cell-index = <0>; + compatible = "qcom,vfe32"; + reg = <0xfde00000 0x800>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 49 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + }; + +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-cdp.dts new file mode 100644 index 000000000..bbdc2b8df --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-cdp.dts @@ -0,0 +1,396 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" +/include/ "dsi-v2-panel-truly-wvga-video.dtsi" +/include/ "msm8610-camera-sensor-cdp-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8610 CDP"; + compatible = "qcom,msm8610-cdp", "qcom,msm8610", "qcom,cdp"; + qcom,msm-id = <147 1 0>, <165 1 0>, <161 1 0>, <162 1 0>, + <163 1 0>, <164 1 0>, <166 1 0>; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; + + i2c@f9923000{ + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <1 0x2>; + vdd_ana-supply = <&pm8110_l19>; + vcc_i2c-supply = <&pm8110_l14>; + atmel,reset-gpio = <&msmgpio 0 0x00>; + atmel,irq-gpio = <&msmgpio 1 0x00>; + atmel,panel-coords = <0 0 508 880>; + atmel,display-coords = <0 0 480 800>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x81>; + atmel,variant-id = <0x15>; + atmel,version = <0x11>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 1D 01 00 0C 04 0D 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 + /* Object 8, Instance = 0 */ + 19 00 14 14 FF 00 FF 00 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 13 0B 00 20 32 01 03 + 00 32 05 30 0A 05 0A 00 70 03 + FC 01 00 36 2F 2C 00 00 40 00 + 00 0A 00 00 02 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 03 00 18 79 A8 61 + /* Object 58, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 42, Instance = 0 */ + 00 00 00 00 00 00 00 00 + /* Object 46, Instance = 0 */ + 04 03 08 10 00 00 00 00 00 + /* Object 47, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + /* Object 48, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <480>; + qcom,disp-maxy = <800>; + qcom,panel-maxx = <508>; + qcom,panel-maxy = <880>; + qcom,key-codes = <158 102 139>; + qcom,y-offset = <35>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 73 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 74 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 72 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "INT_LDO_H", "MCLK", + "MIC BIAS External", "Handset Mic", + "MIC BIAS Internal2", "Headset Mic", + "AMIC1", "MIC BIAS External", + "AMIC2", "MIC BIAS Internal2"; + }; +}; + +&i2c_cdc { + msm8x10_wcd_codec@0d{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x0d>; + cdc-vdda-cp-supply = <&pm8110_s4>; + qcom,cdc-vdda-cp-voltage = <2150000 2150000>; + qcom,cdc-vdda-cp-current = <650000>; + + cdc-vdda-h-supply = <&pm8110_l6>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <250000>; + + cdc-vdd-px-supply = <&pm8110_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-1p2v-supply = <&pm8110_l4>; + qcom,cdc-vdd-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-1p2v-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8110_l20>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias-cfilt-sel = <0x0>; + qcom,cdc-micbias-cfilt-mv = <1800000>; + qcom,cdc-mclk-clk-rate = <12288000>; + }; + + msm8x10_wcd_codec@77{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x77>; + }; + + msm8x10_wcd_codec@66{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x66>; + }; + + msm8x10_wcd_codec@55{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x55>; + }; +}; + +&spmi_bus { + qcom,pm8110@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux-default-trigger = "hr-trigger"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + qcom,mode = "manual"; + }; + }; + + qcom,leds@a200 { + status = "okay"; + qcom,led_mpp_3 { + label = "mpp"; + linux,name = "wled-backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,default-state = "on"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x10>; + qcom,mode = "manual"; + }; + }; + }; +}; + +&spmi_bus { + qcom,pm8110@1 { + qcom,vibrator@c000 { + status = "okay"; + qcom,vib-timeout-ms = <15000>; + qcom,vib-vtg-level-mV = <3100>; + }; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm8110_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 400000>; + + vdd-io-supply = <&pm8110_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 60000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8110_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 400000>; + + vdd-io-supply = <&pm8110_l21>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 50000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 42 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 42 0x1>; + + status = "ok"; +}; + +&pm8110_chg { + status = "ok"; + qcom,charging-disabled; + qcom,use-default-batt-values; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8110_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; +}; + +&pm8110_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + status = "disabled"; + }; + + mpp@a200 { /* MPP 3 */ + status = "disabled"; + }; + + mpp@a300 { /* MPP 4 */ + /* PA_THERM config */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; +}; + +/* CoreSight */ +&tpiu { + qcom,seta-gpios = <&msmgpio 4 0>, + <&msmgpio 5 0>, + <&msmgpio 6 0>, + <&msmgpio 7 0>, + <&msmgpio 22 0>, + <&msmgpio 23 0>, + <&msmgpio 24 0>, + <&msmgpio 25 0>, + <&msmgpio 26 0>, + <&msmgpio 27 0>, + <&msmgpio 28 0>, + <&msmgpio 29 0>, + <&msmgpio 30 0>, + <&msmgpio 31 0>, + <&msmgpio 94 0>, + <&msmgpio 95 0>, + <&msmgpio 96 0>, + <&msmgpio 97 0>; + qcom,seta-gpios-func = <9 9 8 11 2 2 2 2 2 2 3 2 3 3 4 4 4 4>; + qcom,seta-gpios-drv = <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>; + qcom,seta-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + qcom,seta-gpios-dir = <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>; + + qcom,setb-gpios = <&msmgpio 8 0>, + <&msmgpio 10 0>, + <&msmgpio 11 0>, + <&msmgpio 13 0>, + <&msmgpio 14 0>, + <&msmgpio 15 0>, + <&msmgpio 16 0>, + <&msmgpio 17 0>, + <&msmgpio 18 0>, + <&msmgpio 19 0>, + <&msmgpio 20 0>, + <&msmgpio 21 0>, + <&msmgpio 42 0>, + <&msmgpio 80 0>, + <&msmgpio 81 0>, + <&msmgpio 82 0>, + <&msmgpio 83 0>, + <&msmgpio 84 0>; + qcom,setb-gpios-func = <10 8 8 6 9 9 9 9 9 9 9 9 5 7 7 8 8 8>; + qcom,setb-gpios-drv = <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>; + qcom,setb-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + qcom,setb-gpios-dir = <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-coresight.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-coresight.dtsi new file mode 100644 index 000000000..516522eb0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-coresight.dtsi @@ -0,0 +1,357 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@fc326000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc326000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + }; + + tpiu: tpiu@fc320000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc320000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + vdd-supply = <&pm8110_l18>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 400000>; + }; + + replicator: replicator@fc324000 { + compatible = "qcom,coresight-replicator"; + reg = <0xfc324000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + }; + + tmc_etf: tmc@fc325000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc325000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + }; + + funnel_merg: funnel@fc323000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc323000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc321000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc321000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + funnel_in1: funnel@fc322000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc322000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <6>; + coresight-name = "coresight-funnel-in1"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <1>; + }; + + funnel_a7ss: funnel@fc355000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc355000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <7>; + coresight-name = "coresight-funnel-a7ss"; + coresight-nr-inports = <4>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <6>; + }; + + stm: stm@fc302000 { + compatible = "arm,coresight-stm"; + reg = <0xfc302000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <8>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc34c000 { + compatible = "arm,coresight-etm"; + reg = <0xfc34c000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <9>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <0>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm1: etm@fc34d000 { + compatible = "arm,coresight-etm"; + reg = <0xfc34d000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <10>; + coresight-name = "coresight-etm1"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <1>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm2: etm@fc34e000 { + compatible = "arm,coresight-etm"; + reg = <0xfc34e000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <11>; + coresight-name = "coresight-etm2"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <2>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm3: etm@fc34f000 { + compatible = "arm,coresight-etm"; + reg = <0xfc34f000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <12>; + coresight-name = "coresight-etm3"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <3>; + + qcom,pc-save; + qcom,round-robin; + }; + + csr: csr@fc301000 { + compatible = "qcom,coresight-csr"; + reg = <0xfc301000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <13>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <1>; + }; + + cti0: cti@fc310000 { + compatible = "arm,coresight-cti"; + reg = <0xfc310000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <14>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + }; + + cti1: cti@fc311000 { + compatible = "arm,coresight-cti"; + reg = <0xfc311000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + cti2: cti@fc312000 { + compatible = "arm,coresight-cti"; + reg = <0xfc312000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + }; + + cti3: cti@fc313000 { + compatible = "arm,coresight-cti"; + reg = <0xfc313000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + }; + + cti4: cti@fc314000 { + compatible = "arm,coresight-cti"; + reg = <0xfc314000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <18>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + }; + + cti5: cti@fc315000 { + compatible = "arm,coresight-cti"; + reg = <0xfc315000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <19>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + }; + + cti6: cti@fc316000 { + compatible = "arm,coresight-cti"; + reg = <0xfc316000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <20>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + }; + + cti7: cti@fc317000 { + compatible = "arm,coresight-cti"; + reg = <0xfc317000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <21>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + }; + + cti8: cti@fc318000 { + compatible = "arm,coresight-cti"; + reg = <0xfc318000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <22>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + }; + + cti_cpu0: cti@fc351000 { + compatible = "arm,coresight-cti"; + reg = <0xfc351000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <23>; + coresight-name = "coresight-cti-cpu0"; + coresight-nr-inports = <0>; + }; + + cti_cpu1: cti@fc352000 { + compatible = "arm,coresight-cti"; + reg = <0xfc352000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <24>; + coresight-name = "coresight-cti-cpu1"; + coresight-nr-inports = <0>; + }; + + cti_cpu2: cti@fc353000 { + compatible = "arm,coresight-cti"; + reg = <0xfc353000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <25>; + coresight-name = "coresight-cti-cpu2"; + coresight-nr-inports = <0>; + }; + + cti_cpu3: cti@fc354000 { + compatible = "arm,coresight-cti"; + reg = <0xfc354000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <26>; + coresight-name = "coresight-cti-cpu3"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@fd820018 { + compatible = "qcom,coresight-hwevent"; + reg = <0xfd820018 0x80>, + <0xf9011080 0x80>, + <0xfd4ab160 0x80>; + reg-names = "mmss-mux", "apcs-mux", "ppss-mux"; + + coresight-id = <27>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + + qcom,hwevent-clks = "core_mmss_clk"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-gpu.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-gpu.dtsi new file mode 100644 index 000000000..7e3ee0dcb --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-gpu.dtsi @@ -0,0 +1,167 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + msm_gpu: qcom,kgsl-3d0@fdc00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0xfdc00000 0x10000 + 0xfdc10000 0x10000>; + reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_shader_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03000520>; + + qcom,initial-pwrlevel = <1>; + + qcom,idle-timeout = <8>; /* */ + qcom,strtstp-sleepwake; + qcom,clk-map = <0x000005E>; /* KGSL_CLK_CORE | + KGSL_CLK_IFACE | KGSL_CLK_MEM | KGSL_CLK_MEM_IFACE | + KGSL_CLK_ALT_MEM_IFACE */ + + /* Bus Scale Settings */ + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 800000>, + <26 512 0 1600000>, + <26 512 0 2128000>; + + /* GDSC oxili regulators */ + vdd-supply = <&gdsc_oxili_cx>; + + /* IOMMU Data */ + iommu = <&gfx_iommu>; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <3>; + qcom,io-fraction = <0>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <300000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <150000000>; + qcom,bus-freq = <1>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,io-fraction = <0>; + }; + }; + + /* DVCS Info */ + qcom,dcvs-core-info { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,dcvs-core-info"; + + qcom,num-cores = <1>; + qcom,sensors = <0>; + + qcom,core-core-type = <1>; + + qcom,algo-disable-pc-threshold = <0>; + qcom,algo-em-win-size-min-us = <100000>; + qcom,algo-em-win-size-max-us = <300000>; + qcom,algo-em-max-util-pct = <97>; + qcom,algo-group-id = <95>; + qcom,algo-max-freq-chg-time-us = <100000>; + qcom,algo-slack-mode-dynamic = <100000>; + qcom,algo-slack-weight-thresh-pct = <0>; + qcom,algo-slack-time-min-us = <39000>; + qcom,algo-slack-time-max-us = <39000>; + qcom,algo-ss-win-size-min-us = <1000000>; + qcom,algo-ss-win-size-max-us = <1000000>; + qcom,algo-ss-util-pct = <95>; + qcom,algo-ss-no-corr-below-freq = <0>; + + qcom,energy-active-coeff-a = <2492>; + qcom,energy-active-coeff-b = <0>; + qcom,energy-active-coeff-c = <0>; + qcom,energy-leakage-coeff-a = <11>; + qcom,energy-leakage-coeff-b = <157150>; + qcom,energy-leakage-coeff-c = <0>; + qcom,energy-leakage-coeff-d = <0>; + + qcom,power-current-temp = <25>; + qcom,power-num-freq = <4>; + + qcom,dcvs-freq@0 { + reg = <0>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@1 { + reg = <1>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@2 { + reg = <2>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@3 { + reg = <3>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <844545>; + qcom,leakage-energy-offset = <0>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-iommu-domains.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-iommu-domains.dtsi new file mode 100644 index 000000000..6f438972d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-iommu-domains.dtsi @@ -0,0 +1,36 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,iommu-domains { + compatible = "qcom,iommu-domains"; + + qcom,iommu-domain1 { + label = "lpass_secure"; + qcom,iommu-contexts = <&lpass_q6_fw>; + qcom,virtual-addr-pool = <0x00000000 0x0FFFFFFF + 0xF0000000 0x0FFFFFFF>; + }; + + qcom,iommu-domain2 { + label = "lpass_audio"; + qcom,iommu-contexts = <&lpass_audio_shared>; + qcom,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; + }; + + q6_domain_ns:qcom,iommu-domain3 { + label = "lpass_video"; + qcom,iommu-contexts = <&lpass_video_shared>; + qcom,virtual-addr-pool = <0x20000000 0x0FFFFFFF>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-ion.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-ion.dtsi new file mode 100644 index 000000000..456b60ced --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-ion.dtsi @@ -0,0 +1,38 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + qcom,ion-heap@27 { /* QSECOM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <27>; + linux,contiguous-region = <&qsecom_mem>; + }; + }; +}; + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-mdss.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-mdss.dtsi new file mode 100644 index 000000000..af0e3e4e3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-mdss.dtsi @@ -0,0 +1,37 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_mdp@fd900000 { + compatible = "qcom,mdss_mdp3"; + reg = <0xfd900000 0x100000>; + reg-names = "mdp_phys"; + interrupts = <0 72 0>; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x300000>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi@fdd00000 { + compatible = "qcom,msm-dsi-v2"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0xfdd00000 0x100000>; + interrupts = <0 30 0>; + vdda-supply = <&pm8110_l4>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-mtp.dts new file mode 100644 index 000000000..9406a0911 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-mtp.dts @@ -0,0 +1,354 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" +/include/ "dsi-v2-panel-truly-wvga-video.dtsi" +/include/ "msm8610-camera-sensor-cdp-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8610 MTP"; + compatible = "qcom,msm8610-mtp", "qcom,msm8610", "qcom,mtp"; + qcom,msm-id = <147 8 0>, <165 8 0>, <161 8 0>, <162 8 0>, + <163 8 0>, <164 8 0>, <166 8 0>; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; + + i2c@f9923000{ + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <1 0x2>; + vdd_ana-supply = <&pm8110_l19>; + vcc_i2c-supply = <&pm8110_l14>; + atmel,reset-gpio = <&msmgpio 0 0x00>; + atmel,irq-gpio = <&msmgpio 1 0x00>; + atmel,panel-coords = <0 0 508 880>; + atmel,display-coords = <0 0 480 800>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x81>; + atmel,variant-id = <0x15>; + atmel,version = <0x11>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 1D 01 00 0C 04 0D 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 + /* Object 8, Instance = 0 */ + 19 00 14 14 FF 00 FF 00 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 13 0B 00 20 32 01 03 + 00 32 05 30 0A 05 0A 00 70 03 + FC 01 00 36 2F 2C 00 00 40 00 + 00 0A 00 00 02 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 03 00 18 79 A8 61 + /* Object 58, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 42, Instance = 0 */ + 00 00 00 00 00 00 00 00 + /* Object 46, Instance = 0 */ + 04 03 08 10 00 00 00 00 00 + /* Object 47, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + /* Object 48, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <480>; + qcom,disp-maxy = <800>; + qcom,panel-maxx = <508>; + qcom,panel-maxy = <880>; + qcom,key-codes = <158 102 139>; + qcom,y-offset = <35>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 73 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 74 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 72 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "INT_LDO_H", "MCLK", + "MIC BIAS External", "Handset Mic", + "MIC BIAS Internal2", "Headset Mic", + "AMIC1", "MIC BIAS External", + "AMIC2", "MIC BIAS Internal2"; + }; +}; + +&i2c_cdc { + msm8x10_wcd_codec@0d{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x0d>; + cdc-vdda-cp-supply = <&pm8110_s4>; + qcom,cdc-vdda-cp-voltage = <2150000 2150000>; + qcom,cdc-vdda-cp-current = <650000>; + + cdc-vdda-h-supply = <&pm8110_l6>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <250000>; + + cdc-vdd-px-supply = <&pm8110_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-1p2v-supply = <&pm8110_l4>; + qcom,cdc-vdd-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-1p2v-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8110_l20>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias-cfilt-sel = <0x0>; + qcom,cdc-micbias-cfilt-mv = <1800000>; + qcom,cdc-mclk-clk-rate = <12288000>; + }; + + msm8x10_wcd_codec@77{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x77>; + }; + + msm8x10_wcd_codec@66{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x66>; + }; + + msm8x10_wcd_codec@55{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x55>; + }; +}; + +&spmi_bus { + qcom,pm8110@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux-default-trigger = "hr-trigger"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + qcom,mode = "manual"; + }; + }; + + qcom,leds@a200 { + status = "okay"; + qcom,led_mpp_3 { + label = "mpp"; + linux,name = "wled-backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,default-state = "on"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x10>; + qcom,mode = "manual"; + }; + }; + }; +}; + +&spmi_bus { + qcom,pm8110@1 { + qcom,vibrator@c000 { + status = "okay"; + qcom,vib-timeout-ms = <15000>; + qcom,vib-vtg-level-mV = <3100>; + }; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm8110_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 400000>; + + vdd-io-supply = <&pm8110_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 60000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8110_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 400000>; + + vdd-io-supply = <&pm8110_l21>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 50000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 42 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 42 0x1>; + + status = "ok"; +}; + +&pm8110_chg { + status = "ok"; + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8110_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; +}; + +&pm8110_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + status = "disabled"; + }; + + mpp@a200 { /* MPP 3 */ + status = "disabled"; + }; + + mpp@a300 { /* MPP 4 */ + /* PA_THERM config */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; +}; + +&pm8110_bms { + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-pm.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-pm.dtsi new file mode 100644 index 000000000..938b2aa2a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-pm.dtsi @@ -0,0 +1,391 @@ +/* Copyright (c) 2013 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f9099000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,core-id = <1>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f90a9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,core-id = <2>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f90b9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,core-id = <3>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f9012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9012000 0x1000>; + qcom,core-id = <0xffff>; /* L2/APCS SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-pmic-data0 = <0x02030080>; + qcom,saw2-pmic-data1 = <0x00030000>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + qcom,saw2-spm-cmd-ret = [00 03 00 7b 0f]; + qcom,saw2-spm-cmd-pc = [00 32 b0 10 e0 d0 6b c0 42 f0 + 11 07 01 b0 4e c0 d0 12 e0 6b 50 02 32 + 50 f0 7b 0f]; /*APCS_PMIC_OFF_L2RAM_OFF*/ + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x61706d73>; /* "smpa" */ + qcom,id = <0x01>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <3>; /* SVS SOC */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x616F646C>; /* "ldoa" */ + qcom,id = <0x03>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <3>; /* SVS SOC */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + + qcom,lpm-resources@3 { + reg = <0x3>; + qcom,name = "l2"; + qcom,local-resource-type; + qcom,init-value = "l2_cache_retention"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <1>; + qcom,ss-power = <784>; + qcom,energy-overhead = <190000>; + qcom,time-overhead = <100>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3000>; + qcom,ss-power = <725>; + qcom,energy-overhead = <99500>; + qcom,time-overhead = <3130>; + }; + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_retention"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <8000>; + qcom,ss-power = <138>; + qcom,energy-overhead = <1208400>; + qcom,time-overhead = <9200>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <4>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <9000>; + qcom,ss-power = <110>; + qcom,energy-overhead = <1250300>; + qcom,time-overhead = <9500>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <16300>; + qcom,ss-power = <63>; + qcom,energy-overhead = <2128000>; + qcom,time-overhead = <24200>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <4>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,latency-us = <24000>; + qcom,ss-power = <10>; + qcom,energy-overhead = <3202600>; + qcom,time-overhead = <33000>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <1>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <26000>; + qcom,ss-power = <2>; + qcom,energy-overhead = <4252000>; + qcom,time-overhead = <38000>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <47 172>, /* usb2_hsic_async_wakeup_irq */ + <53 104>, /* mdss_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <2 216>, /* tsens_upper_lower_int */ + <0xff 56>, /* q6_wdog_expired_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 61>, /* mss_a2_bam_irq */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_low */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr + <0xff 181>, /* o_wcss_apss_wdog_bite_and_reset_rdy */ + <0xff 161>, /* lpass_irq_out_spare[4] / + <0xff 162>, /* lpass_irq_out_spare[5]*/ + <0xff 234>, /* lpass_irq_out_spare[6]*/ + <0xff 235>, /* lpass_irq_out_spare[7]*/ + <0xff 188>, /* lpass_irq_out_apcs(0) */ + <0xff 189>, /* lpass_irq_out_apcs(1) */ + <0xff 190>, /* lpass_irq_out_apcs(2) */ + <0xff 191>, /* lpass_irq_out_apcs(3) */ + <0xff 192>, /* lpass_irq_out_apcs(4) */ + <0xff 194>, /* lpass_irq_out_apcs(6) */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 258>, /* rpm_ipc(28) */ + <0xff 259>, /* rpm_ipc(29) */ + <0xff 275>, /* rpm_ipc(30) */ + <0xff 276>, /* rpm_ipc(31) */ + <0xff 269>, /* rpm_wdog_expired_irq */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <3 1>, + <4 4 >, + <5 5 >, + <6 9 >, + <7 13>, + <8 17>, + <9 21>, + <10 27>, + <11 29>, + <12 31>, + <13 33>, + <14 35>, + <15 37>, + <16 38>, + <17 39>, + <18 41>, + <19 46>, + <20 48>, + <21 49>, + <22 50>, + <23 51>, + <24 52>, + <25 54>, + <26 62>, + <27 63>, + <28 64>, + <29 65>, + <30 66>, + <31 67>, + <32 68>, + <33 69>, + <34 71>, + <35 72>, + <36 106>, + <37 107>, + <38 108>, + <39 109>, + <40 110>, + <54 111>, + <55 113>; + }; + + qcom,pm-8x60@fe805664 { + compatible = "qcom,pm-8x60"; + reg = <0xfe805664 0x40>; + qcom,pc-mode = "tz_l2_int"; + qcom,use-sync-timer; + qcom,pc-resets-timer; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-qrd.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-qrd.dts new file mode 100644 index 000000000..5f9365a2a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-qrd.dts @@ -0,0 +1,267 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" +/include/ "dsi-v2-panel-hx8379a-wvga-video.dtsi" + +/ { + model = "Qualcomm MSM 8610 QRD"; + compatible = "qcom,msm8610-qrd", "qcom,msm8610", "qcom,qrd"; + qcom,msm-id = <147 11 0>, <165 11 0>, <161 11 0>, <162 11 0>, + <163 11 0>, <164 11 0>, <166 11 0>; +}; + +&soc { + i2c@f9923000{ + focaltech@38{ + compatible = "focaltech,5x06"; + reg = <0x38>; + interrupt-parent = <&msmgpio>; + interrupts = <1 0x2>; + vdd-supply = <&pm8110_l19>; + vcc_i2c-supply = <&pm8110_l14>; + focaltech,family-id = <0x06>; + focaltech,reset-gpio = <&msmgpio 0 0x00>; + focaltech,irq-gpio = <&msmgpio 1 0x00>; + focaltech,display-coords = <0 0 480 800>; + focaltech,panel-coords = <0 0 480 800>; + focaltech,button-map= <139 102 158>; + focaltech,no-force-update; + focaltech,i2c-pull-up; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "ft5x06_ts"; + qcom,disp-maxx = <480>; + qcom,disp-maxy = <800>; + qcom,panel-maxx = <481>; + qcom,panel-maxy = <940>; + qcom,key-codes = <139 0 102 158 0 0 0>; + qcom,y-offset = <0>; + }; + serial@f991e000 { + status = "ok"; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 73 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 74 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 72 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + i2c@f9927000 { + msm8x10_wcd_codec@0d{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x0d>; + cdc-vdda-cp-supply = <&pm8110_s4>; + qcom,cdc-vdda-cp-voltage = <2150000 2150000>; + qcom,cdc-vdda-cp-current = <650000>; + + cdc-vdda-h-supply = <&pm8110_l6>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <250000>; + + cdc-vdd-px-supply = <&pm8110_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-1p2v-supply = <&pm8110_l4>; + qcom,cdc-vdd-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-1p2v-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8110_l20>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias-cfilt-sel = <0x0>; + qcom,cdc-micbias-cfilt-mv = <1800000>; + qcom,cdc-mclk-clk-rate = <12288000>; + }; + + msm8x10_wcd_codec@77{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x77>; + }; + + msm8x10_wcd_codec@66{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x66>; + }; + + msm8x10_wcd_codec@55{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x55>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "INT_LDO_H", "MCLK", + "MIC BIAS Internal1", "Handset Mic", + "MIC BIAS Internal2", "Headset Mic", + "AMIC1", "MIC BIAS Internal1", + "AMIC2", "MIC BIAS Internal2"; + }; +}; + +&spmi_bus { + qcom,pm8110@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "wled-homerow"; + linux-default-trigger = "hr-trigger"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x61>; + }; + }; + + qcom,leds@a200 { + status = "okay"; + qcom,led_mpp_3 { + label = "mpp"; + linux,name = "wled-backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,default-state = "on"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x10>; + }; + }; + }; +}; + +&spmi_bus { + qcom,pm8110@1 { + qcom,vibrator@c000 { + status = "okay"; + qcom,vib-timeout-ms = <15000>; + qcom,vib-vtg-level-mV = <3100>; + }; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm8110_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 400000>; + + vdd-io-supply = <&pm8110_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 60000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8110_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 400000>; + + vdd-io-supply = <&pm8110_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 50000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 42 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 42 0x1>; + + status = "ok"; +}; + +&pm8110_chg { + status = "ok"; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-regulator.dtsi new file mode 100644 index 000000000..09520c537 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-regulator.dtsi @@ -0,0 +1,358 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SPM controlled regulators */ + +&spmi_bus { + qcom,pm8110@1 { + pm8110_s2: spm-regulator@1700 { + compatible = "qcom,spm-regulator"; + regulator-name = "8110_s2"; + reg = <0x1700 0x100>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + }; + }; +}; + +/* CPR controlled regulator */ + +&soc { + apc_vreg_corner: regulator@f9018000 { + status = "okay"; + compatible = "qcom,cpr-regulator"; + reg = <0xf9018000 0x1000>, <0xf9011064 4>, <0xfc4b80b0 8>, + <0xfc4bc450 16>; + reg-names = "rbcpr", "rbcpr_clk", "pvs_efuse", "cpr_efuse"; + interrupts = <0 15 0>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + qcom,num-efuse-bits = <5>; + qcom,pvs-bin-process = <0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 2 + 2 2 2 2 3 3 3 3 3 3 3 3 0 0 0 0>; + qcom,pvs-corner-ceiling-slow = <1150000 1150000 1275000>; + qcom,pvs-corner-ceiling-nom = <975000 1075000 1200000>; + qcom,pvs-corner-ceiling-fast = <900000 1000000 1140000>; + vdd-apc-supply = <&pm8110_s2>; + + vdd-mx-supply = <&pm8110_l3_ao>; + qcom,vdd-mx-vmax = <1350000>; + qcom,vdd-mx-vmin-method = <1>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <1>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <15>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <5>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <5000>; + }; +}; + +/* RPM controlled regulators: */ + +&rpm_bus { + + rpm-regulator-smpa1 { + status = "okay"; + pm8110_s1: regulator-s1 { + status = "okay"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1275000>; + }; + + pm8110_s1_corner: regulator-s1-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s1_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + qcom,consumer-supplies = "vdd_dig", ""; + }; + + pm8110_s1_corner_ao: regulator-s1-corner-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s1_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + qcom,consumer-supplies = "vdd_sr2_dig", ""; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8110_s3: regulator-s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8110_s4: regulator-s4 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + qcom,init-voltage = <2150000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8110_l1: regulator-l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8110_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8110_l3: regulator-l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + + pm8110_l3_ao: regulator-l3-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l3_ao"; + qcom,set = <1>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + + pm8110_l3_so: regulator-l3-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l3_so"; + qcom,set = <2>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + qcom,init-voltage = <750000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8110_l4: regulator-l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8110_l5: regulator-l5 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8110_l6: regulator-l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8110_l7: regulator-l7 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8110_l8: regulator-l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8110_l9: regulator-l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8110_l10: regulator-l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8110_l10_ao: regulator-l10-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l10_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,consumer-supplies = "vdd_sr2_pll", ""; + }; + + pm8110_l10_so: regulator-l10-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l10_so"; + qcom,set = <2>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-enable = <0>; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8110_l12: regulator-l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8110_l14: regulator-l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8110_l15: regulator-l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8110_l16: regulator-l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8110_l17: regulator-l17 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8110_l18: regulator-l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8110_l19: regulator-l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + pm8110_l20: regulator-l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + pm8110_l21: regulator-l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8110_l22: regulator-l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + status = "okay"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-rumi.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-rumi.dts new file mode 100644 index 000000000..7f0648541 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-rumi.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" + +/ { + model = "Qualcomm MSM 8610 Rumi"; + compatible = "qcom,msm8610-rumi", "qcom,msm8610", "qcom,rumi"; + qcom,msm-id = <147 15 0>; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; +}; + +&gfx_iommu { + status = "disabled"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-sim.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-sim.dts new file mode 100644 index 000000000..7c57fe667 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-sim.dts @@ -0,0 +1,72 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" + +/ { + model = "Qualcomm MSM 8610 Simulator"; + compatible = "qcom,msm8610-sim", "qcom,msm8610", "qcom,sim"; + qcom,msm-id = <147 16 0>; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; +}; + +&i2c_cdc { + msm8x10_wcd_codec@0d{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x0d>; + cdc-vdda-cp-supply = <&pm8110_s4>; + qcom,cdc-vdda-cp-voltage = <2150000 2150000>; + qcom,cdc-vdda-cp-current = <650000>; + + cdc-vdda-h-supply = <&pm8110_l6>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <250000>; + + cdc-vdd-px-supply = <&pm8110_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-1p2v-supply = <&pm8110_l4>; + qcom,cdc-vdd-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-1p2v-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8110_l20>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias-cfilt-sel = <0x0>; + qcom,cdc-micbias-cfilt-mv = <1800000>; + qcom,cdc-mclk-clk-rate = <12288000>; + }; + + msm8x10_wcd_codec@77{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x77>; + }; + + msm8x10_wcd_codec@66{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x66>; + }; + + msm8x10_wcd_codec@55{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x55>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-smp2p.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-smp2p.dtsi new file mode 100644 index 000000000..3921a686a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610-smp2p.dtsi @@ -0,0 +1,225 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-wcnss { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <4>; + qcom,irq-bitmask = <0x40000>; + interrupts = <0 143 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + /* SMP2P SSR Driver for inbound entry from lpass. */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* SMP2P SSR Driver for outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_4_in: qcom,smp2pgpio-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_in { + compatible = "qcom,smp2pgpio_test_smp2p_4_in"; + gpios = <&smp2pgpio_smp2p_4_in 0 0>; + }; + + smp2pgpio_smp2p_4_out: qcom,smp2pgpio-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_in: qcom,smp2pgpio-ssr-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_out: qcom,smp2pgpio-ssr-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_out { + compatible = "qcom,smp2pgpio_test_smp2p_4_out"; + gpios = <&smp2pgpio_smp2p_4_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610.dtsi new file mode 100644 index 000000000..a62df58d9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8610.dtsi @@ -0,0 +1,1075 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM 8610"; + compatible = "qcom,msm8610"; + interrupt-parent = <&intc>; + + memory { + qsecom_mem: qsecom_region { + linux,contiguous-region; + reg = <0 0x100000>; + label = "qsecom_mem"; + }; + }; + + aliases { + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + spi4 = &spi_4; + }; + + soc: soc { }; +}; + +/include/ "msm8610-camera.dtsi" +/include/ "msm-iommu-v0.dtsi" +/include/ "msm8610-ion.dtsi" +/include/ "msm8610-gpu.dtsi" +/include/ "msm-gdsc.dtsi" +/include/ "msm8610-coresight.dtsi" +/include/ "msm8610-pm.dtsi" +/include/ "msm8610-smp2p.dtsi" +/include/ "msm8610-bus.dtsi" +/include/ "msm8610-mdss.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <102>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + qcom,mpm2-sleep-counter@fc4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xfc4a3000 0x1000>; + clock-frequency = <32768>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,smmu-enabled; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + serial@f991e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991e000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + }; + + qcom,vidc@fdc00000 { + compatible = "qcom,msm-vidc"; + qcom,vidc-ns-map = <0x40000000 0x40000000>; + qcom,iommu-groups = <&q6_domain_ns>; + qcom,iommu-group-buffer-types = <0xfff>; + qcom,buffer-type-tz-usage-map = <0x1 0x1>, + <0x1fe 0x2>; + qcom,hfi = "q6"; + qcom,max-hw-load = <108000>; /* 720p @ 30 * 1 */ + }; + + qcom,usbbam@f9a44000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xf9a44000 0x11000>; + reg-names = "hsusb"; + interrupts = <0 135 0>; + interrupt-names = "hsusb"; + qcom,usb-bam-num-pipes = <16>; + qcom,usb-bam-fifo-baseaddr = <0xfe803000>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + + qcom,pipe0 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <3>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37c000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x600>; + qcom,descriptor-fifo-offset = <0x600>; + qcom,descriptor-fifo-size = <0x200>; + }; + }; + + usb@f9a55000 { + compatible = "qcom,hsusb-otg"; + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0>, <0 140 0>; + interrupt-names = "core_irq", "async_irq"; + HSUSB_VDDCX-supply = <&pm8110_s1>; + HSUSB_1p8-supply = <&pm8110_l10>; + HSUSB_3p3-supply = <&pm8110_l20>; + + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <2>; + qcom,hsusb-otg-disable-reset; + qcom,dp-manual-pullup; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 60000 960000>; + }; + + android_usb@fe8050c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8050c8 0xc8>; + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>, + <0xf9824800 0x100>, + <0xf9804000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 123 0>, <0 137 0>; + interrupt-names = "core_irq", "bam_irq"; + + vdd-supply = <&pm8110_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <9000 400000>; + + vdd-io-supply = <&pm8110_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <9000 60000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2900 2900>; + qcom,bus-width = <8>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + status = "disabled"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>, + <0xf98a4800 0x100>, + <0xf9884000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 125 0>, <0 220 0>; + interrupt-names = "core_irq", "bam_irq"; + + vdd-supply = <&pm8110_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 400000>; + + vdd-io-supply = <&pm8110_l21>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <9000 50000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <4>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + status = "disabled"; + }; + + sdhc_1: sdhci@f9824900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + status = "disabled"; + }; + + qcom,sps { + compatible = "qcom,msm_sps"; + qcom,device-type = <3>; + }; + + qcom,smem@d900000 { + compatible = "qcom,smem"; + reg = <0xd900000 0x100000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1000>; + qcom,pil-string = "modem"; + interrupts = <0 25 1>; + }; + + qcom,smsm-modem { + compatible = "qcom,smsm"; + qcom,smsm-edge = <0>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x2000>; + interrupts = <0 26 1>; + }; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-wcnss { + compatible = "qcom,smd"; + qcom,smd-edge = <6>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x20000>; + qcom,pil-string = "wcnss"; + interrupts = <0 142 1>; + }; + + qcom,smsm-wcnss { + compatible = "qcom,smsm"; + qcom,smsm-edge = <6>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x80000>; + interrupts = <0 144 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + rpm-standalone; + }; + + qcom,bcl { + compatible = "qcom,bcl"; + }; + + qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x07B00000 0x6400000>; /* Address and Size of Hole */ + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + }; + + qcom,acpuclk@f9011050 { + compatible = "qcom,acpuclk-a7"; + reg = <0xf9011050 0x8>; + reg-names = "rcg_base"; + a7_cpu-supply = <&apc_vreg_corner>; + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0>, <0 187 0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + i2c@f9923000 { /* BLSP-1 QUP-1 */ + cell-index = <1>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9923000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 95 0>; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + qcom,sda-gpio = <&msmgpio 2 0>; + qcom,scl-gpio = <&msmgpio 3 0>; + }; + + i2c_cdc: i2c@f9927000 { /* BLSP1 QUP5 */ + cell-index = <5>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9927000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 99 0>; + qcom,i2c-bus-freq = <100000>; + }; + + i2c: i2c@f9928000 { /* BLSP1 QUP6 */ + cell-index = <6>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9928000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 100 0>; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + qcom,sda-gpio = <&msmgpio 16 0>; + qcom,scl-gpio = <&msmgpio 17 0>; + }; + + i2c@f9925000 { /* BLSP-1 QUP-3 */ + cell-index = <0>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9925000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 97 0>; + qcom,i2c-bus-freq = <100000>; + }; + + spi_4: spi@f9926000 { /* BLSP1 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xf9926000 0x1000>, + <0xf9904000 0x15000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 0>, <0 238 0>; + spi-max-frequency = <50000000>; + + gpios = <&msmgpio 89 0>, /* CLK */ + <&msmgpio 87 0>, /* MISO */ + <&msmgpio 86 0>; /* MOSI */ + cs-gpios = <&msmgpio 88 0>; + + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <18>; + qcom,bam-producer-pipe-index = <19>; + }; + + qcom,pronto@fb21b000 { + compatible = "qcom,pil-pronto"; + reg = <0xfb21b000 0x3000>, + <0xfc401700 0x4>, + <0xfd485300 0xc>; + reg-names = "pmu_base", "clk_base", "halt_base"; + interrupts = <0 149 1>; + vdd_pronto_pll-supply = <&pm8110_l10>; + + qcom,firmware-name = "wcnss"; + + /* GPIO inputs from wcnss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>; + + /* GPIO output to wcnss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>; + }; + + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + + sound { + compatible = "qcom,msm8x10-audio-codec"; + qcom,model = "msm8x10-snd-card"; + }; + + qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + }; + + qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + qcom,msm-pcm-lpa { + compatible = "qcom,msm-pcm-lpa"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + }; + + qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <3>; + }; + + qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <3>; + qcom,msm-mi2s-tx-lines = <0>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + qcom,wcnss-wlan@fb000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xfb000000 0x280000>, + <0xf9011008 0x04>; + reg-names = "wcnss_mmio", "wcnss_fiq"; + interrupts = <0 145 0>, <0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8110_l3>; + qcom,pronto-vddcx-supply = <&pm8110_s1>; + qcom,pronto-vddpx-supply = <&pm8110_l6>; + qcom,iris-vddxo-supply = <&pm8110_l10>; + qcom,iris-vddrfa-supply = <&pm8110_l5>; + qcom,iris-vddpa-supply = <&pm8110_l16>; + qcom,iris-vdddig-supply = <&pm8110_l5>; + + gpios = <&msmgpio 23 0>, <&msmgpio 24 0>, <&msmgpio 25 0>, <&msmgpio 26 0>, <&msmgpio 27 0>; + qcom,has-pronto-hw; + qcom,wlan-rx-buff-count = <256>; + }; + + qcom,mss@fc880000 { + compatible = "qcom,pil-q6v5-mss"; + reg = <0xfc880000 0x100>, + <0xfd485000 0x400>, + <0xfc820000 0x020>, + <0xfc401680 0x004>, + <0xfd485194 0x4>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg", "cxrail_bhs_reg"; + + interrupts = <0 24 1>; + vdd_cx-supply = <&pm8110_s1_corner>; + vdd_mx-supply = <&pm8110_l3>; + vdd_pll-supply = <&pm8110_l10>; + qcom,vdd_pll = <1800000>; + qcom,is-loadable; + qcom,firmware-name = "mba"; + qcom,pil-self-auth; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + qcom,lpass@fe200000 { + compatible = "qcom,pil-q6v5-lpass"; + reg = <0xfe200000 0x00100>, + <0xfd485100 0x00010>, + <0xfc4016c0 0x00004>; + reg-names = "qdsp6_base", "halt_base", "restart_reg"; + interrupts = <0 162 1>; + vdd_cx-supply = <&pm8110_s1_corner>; + qcom,firmware-name = "adsp"; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + tsens: tsens@fc4a8000 { + compatible = "qcom,msm-tsens"; + reg = <0xfc4a8000 0x2000>, + <0xfc4b8000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + qcom,sensors = <2>; + qcom,slope = <2901 2846>; + qcom,calib-mode = "fuse_map3"; + qcom,sensor-id = <0 5>; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <5>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-control-mask = <0xf>; + }; + + qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + }; + + qcom,qseecom@7B00000 { + compatible = "qcom,qseecom"; + reg = <0x7B00000 0x500000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; + + qcom,msm-rng@f9bff000 { + compatible = "qcom,msm-rng"; + reg = <0xf9bff000 0x200>; + qcom,msm-rng-iface-clk; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + jtag_mm0: jtagmm@fc34c000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc34c000 0x1000>, + <0xfc340000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm1: jtagmm@fc34d000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc34d000 0x1000>, + <0xfc342000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm2: jtagmm@fc34e000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc34e000 0x1000>, + <0xfc344000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm3: jtagmm@fc34f000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc34f000 0x1000>, + <0xfc346000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + qcom,tz-log@fe805720 { + compatible = "qcom,tz-log"; + reg = <0x0fe805720 0x1000>; + }; + + qcom,qcrypto@fd404000 { + compatible = "qcom,qcrypto"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <1>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 3936000>; + }; + + qcom,qcedev@fd400000 { + compatible = "qcom,qcedev"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <1>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 3936000>; + }; + +}; + +&gdsc_vfe { + status = "ok"; +}; + +&gdsc_oxili_cx { + status = "ok"; +}; + +&lpass_iommu { + status = "ok"; +}; + +&copss_iommu { + status = "ok"; +}; + +&mdpe_iommu { + status = "ok"; +}; + +&mdps_iommu { + status = "ok"; +}; + +&gfx_iommu { + status = "ok"; +}; + +&vfe_iommu { + status = "ok"; +}; + +/include/ "msm8610-iommu-domains.dtsi" + +/include/ "msm-pm8110-rpm-regulator.dtsi" +/include/ "msm-pm8110.dtsi" +/include/ "msm8610-regulator.dtsi" + +&pm8110_vadc { + chan@0 { + label = "usb_in"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@2 { + label = "vchg_sns"; + reg = <2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <2>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@31 { + label = "batt_id"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b2 { + label = "xo_therm_pu2"; + reg = <0xb2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@13 { + label = "pa_therm0"; + reg = <0x13>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8110_adc_tm { + /* Channel Node */ + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x48>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x68>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x70>; + }; + + chan@13 { + label = "pa_therm0"; + reg = <0x13>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8660-surf.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8660-surf.dts new file mode 100644 index 000000000..4518fc4a3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8660-surf.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM8660 SURF"; + compatible = "qcom,msm8660-surf", "qcom,msm8660", "qcom,surf"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@02080000 { + compatible = "qcom,msm-8660-qgic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02080000 0x1000 >, + < 0x02081000 0x1000 >; + }; + + serial@19c400000 { + compatible = "qcom,msm-hsuart", "qcom,msm-uart"; + reg = <0x19c40000 0x1000>, + <0x19c00000 0x1000>; + interrupts = <0 195 0x0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-cdp.dts new file mode 100644 index 000000000..7a91d40ee --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-cdp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/include/ "msm8926.dtsi" +/include/ "msm8226-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8926 CDP"; + compatible = "qcom,msm8926-cdp", "qcom,msm8926", "qcom,cdp"; + qcom,msm-id = <200 1 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-mtp.dts new file mode 100644 index 000000000..fea925d62 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/include/ "msm8926.dtsi" +/include/ "msm8226-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8926 MTP"; + compatible = "qcom,msm8926-mtp", "qcom,msm8926", "qcom,mtp"; + qcom,msm-id = <200 8 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-qrd.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-qrd.dts new file mode 100644 index 000000000..e056b7e87 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926-qrd.dts @@ -0,0 +1,21 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8926.dtsi" +/include/ "msm8226-qrd.dtsi" + +/ { + model = "Qualcomm MSM 8926 QRD"; + compatible = "qcom,msm8926-qrd", "qcom,msm8926", "qcom,qrd"; + qcom,msm-id = <200 11 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926.dtsi new file mode 100644 index 000000000..6f3f59251 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8926.dtsi @@ -0,0 +1,30 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Only 8926-specific property overrides should be placed inside this + * file. Device definitions should be placed inside the msm8226.dtsi + * file. + */ + +/include/ "msm8226.dtsi" + +/ { + model = "Qualcomm MSM 8926"; + compatible = "qcom,msm8926"; +}; + +&soc { + qcom,mss@fc880000 { + vdd_mss-supply = <&pm8226_s5>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-bus.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-bus.dtsi new file mode 100644 index 000000000..609a1b302 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-bus.dtsi @@ -0,0 +1,1411 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm-mmss-noc@fc478000 { + compatible = "msm-bus-fabric"; + reg = <0xfc478000 0x00004000>; + cell-id = <2048>; + label = "msm_mmss_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <52>; + coresight-name = "coresight-mnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <5>; + + mas-gfx3d { + cell-id = <26>; + label = "mas-gfx3d"; + qcom,masterp = <2 3>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <2 3>; + qcom,mas-hw-id = <6>; + }; + + mas-jpeg { + cell-id = <62>; + label = "mas-jpeg"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <7>; + }; + + mas-mdp-port0 { + cell-id = <22>; + label = "mas-mdp-port0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,qport = <1>; + qcom,ws = <10000>; + qcom,mas-hw-id = <8>; + }; + + mas-video-p0 { + cell-id = <63>; + label = "mas-video-p0"; + qcom,masterp = <6 7>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <4 5>; + qcom,mas-hw-id = <9>; + }; + + mas-vfe { + cell-id = <29>; + label = "mas-vfe"; + qcom,masterp = <16>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <6>; + qcom,mas-hw-id = <11>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,masterp = <0 1>; + qcom,buswidth = <16>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <4>; + }; + + fab-bimc { + cell-id = <0>; + label = "fab-bimc"; + qcom,gateway; + qcom,slavep = <16 17>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <16>; + }; + + slv-camera-cfg { + cell-id = <589>; + label = "slv-camera-cfg"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <3>; + }; + + slv-display-cfg { + cell-id = <590>; + label = "slv-display-cfg"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <4>; + }; + + slv-ocmem-cfg { + cell-id = <591>; + label = "slv-ocmem-cfg"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <5>; + }; + + slv-cpr-cfg { + cell-id = <592>; + label = "slv-cpr-cfg"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <6>; + }; + + slv-cpr-xpu-cfg { + cell-id = <593>; + label = "slv-cpr-xpu-cfg"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <7>; + }; + + slv-misc-cfg { + cell-id = <594>; + label = "slv-misc-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <8>; + }; + + slv-misc-xpu-cfg { + cell-id = <595>; + label = "slv-misc-xpu-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <9>; + }; + + slv-venus-cfg { + cell-id = <596>; + label = "slv-venus-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <10>; + }; + + slv-gfx3d-cfg { + cell-id = <598>; + label = "slv-gfx3d-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <11>; + }; + + slv-mmss-clk-cfg { + cell-id = <599>; + label = "slv-mmss-clk-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <12>; + }; + + slv-mmss-clk-xpu-cfg { + cell-id = <600>; + label = "slv-mmss-clk-xpu-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <13>; + }; + + slv-mnoc-mpu-cfg { + cell-id = <601>; + label = "slv-mnoc-mpu-cfg"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <14>; + }; + + slv-onoc-mpu-cfg { + cell-id = <602>; + label = "slv-onoc-mpu-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <15>; + }; + + slv-service-mnoc { + cell-id = <603>; + label = "slv-service-mnoc"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <17>; + }; + + }; + + msm-sys-noc@fc460000 { + compatible = "msm-bus-fabric"; + reg = <0xfc460000 0x00004000>; + cell-id = <1024>; + label = "msm_sys_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <50>; + coresight-name = "coresight-snoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <3>; + + msm-lpass-ahb { + cell-id = <52>; + label = "mas-lpass-ahb"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,qport = <0>; + qcom,mas-hw-id = <18>; + qcom,mode = "Fixed"; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + mas-qdss-bam { + cell-id = <53>; + label = "mas-qdss-bam"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <1>; + qcom,mas-hw-id = <19>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,hw-sel = "NoC"; + }; + + mas-snoc-cfg { + cell-id = <54>; + label = "mas-snoc-cfg"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,mas-hw-id = <20>; + }; + + fab-bimc { + cell-id = <0>; + label= "fab-bimc"; + qcom,gateway; + qcom,slavep = <7 8>; + qcom,masterp = <3>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <21>; + qcom,slv-hw-id = <24>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,slavep = <9>; + qcom,masterp = <4>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <22>; + qcom,slv-hw-id = <25>; + }; + + fab-pnoc { + cell-id = <4096>; + label = "fab-pnoc"; + qcom,gateway; + qcom,slavep = <12>; + qcom,masterp = <11>; + qcom,buswidth = <8>; + qcom,qport = <8>; + qcom,mas-hw-id = <29>; + qcom,slv-hw-id = <28>; + qcom,mode = "Fixed"; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + fab-ovnoc { + cell-id = <6144>; + label = "fab-ovnoc"; + qcom,gateway; + qcom,buswidth = <8>; + qcom,mas-hw-id = <53>; + qcom,slv-hw-id = <77>; + }; + + mas-crypto-core0 { + cell-id = <55>; + label = "mas-crypto-core0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <2>; + qcom,mas-hw-id = <23>; + qcom,hw-sel = "NoC"; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + }; + + mas-crypto-core1 { + cell-id = <56>; + label = "mas-crypto-core1"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <3>; + qcom,mas-hw-id = <24>; + qcom,hw-sel = "NoC"; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + }; + + mas-lpass-proc { + cell-id = <11>; + label = "mas-lpass-proc"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,qport = <4>; + qcom,mas-hw-id = <25>; + qcom,mode = "Fixed"; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + mas-mss { + cell-id = <38>; + label = "mas-mss"; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,mas-hw-id = <26>; + }; + + mas-mss-nav { + cell-id = <57>; + label = "mas-mss-nav"; + qcom,masterp = <9>; + qcom,tier = <2>; + qcom,mas-hw-id = <27>; + }; + + mas-ocmem-dma { + cell-id = <58>; + label = "mas-ocmem-dma"; + qcom,masterp = <10>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <7>; + qcom,mas-hw-id = <28>; + }; + + mas-wcss { + cell-id = <59>; + label = "mas-wcss"; + qcom,masterp = <12>; + qcom,tier = <2>; + qcom,mas-hw-id = <30>; + }; + + mas-qdss-etr { + cell-id = <60>; + label = "mas-qdss-etr"; + qcom,masterp = <13>; + qcom,tier = <2>; + qcom,qport = <10>; + qcom,mode = "Fixed"; + qcom,mas-hw-id = <31>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,hw-sel = "NoC"; + }; + + mas-usb3 { + cell-id = <61>; + label = "mas-usb3"; + qcom,masterp = <14>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <11>; + qcom,mas-hw-id = <32>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,hw-sel = "NoC"; + qcom,iface-clk-node = "msm_usb3"; + }; + + slv-ampss { + cell-id = <520>; + label = "slv-ampss"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <20>; + }; + + slv-lpass { + cell-id = <522>; + label = "slv-lpass"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <21>; + }; + + slv-usb3 { + cell-id = <583>; + label = "slv-usb3"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <22>; + }; + + slv-wcss { + cell-id = <584>; + label = "slv-wcss"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <23>; + }; + + slv-ocimem { + cell-id = <585>; + label = "slv-ocimem"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <26>; + }; + + slv-snoc-ocmem { + cell-id = <586>; + label = "slv-snoc-ocmem"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <27>; + }; + + slv-service-snoc { + cell-id = <587>; + label = "slv-service-snoc"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <29>; + }; + + slv-qdss-stm { + cell-id = <588>; + label = "slv-qdss-stm"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <30>; + }; + + }; + + msm-periph-noc@fc468000 { + compatible = "msm-bus-fabric"; + reg = <0xfc468000 0x00004000>; + cell-id = <4096>; + label = "msm_periph_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <54>; + coresight-name = "coresight-pnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <6>; + + mas-pnoc-cfg { + cell-id = <88>; + label = "mas-pnoc-cfg"; + qcom,masterp = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <43>; + }; + + mas-sdcc-1 { + cell-id = <78>; + label = "mas-sdcc-1"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <33>; + }; + + mas-sdcc-3 { + cell-id = <79>; + label = "mas-sdcc-3"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <34>; + }; + + mas-sdcc-4 { + cell-id = <80>; + label = "mas-sdcc-4"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <36>; + }; + + mas-sdcc-2 { + cell-id = <81>; + label = "mas-sdcc-2"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <35>; + }; + + mas-tsif { + cell-id = <82>; + label = "mas-tsif"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <37>; + }; + + mas-bam-dma { + cell-id = <83>; + label = "mas-bam-dma"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <38>; + }; + + mas-blsp-2 { + cell-id = <84>; + label = "mas-blsp-2"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <39>; + }; + + mas-usb-hsic { + cell-id = <85>; + label = "mas-usb-hsic"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <40>; + }; + + mas-blsp-1 { + cell-id = <86>; + label = "mas-blsp-1"; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <41>; + }; + + mas-usb-hs { + cell-id = <87>; + label = "mas-usb-hs"; + qcom,masterp = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <42>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <14>; + qcom,masterp = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <45>; + qcom,mas-hw-id = <44>; + }; + + slv-sdcc-1 { + cell-id = <606>; + label = "slv-sdcc-1"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <31>; + }; + + slv-sdcc-3 { + cell-id = <607>; + label = "slv-sdcc-3"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <32>; + }; + + slv-sdcc-2 { + cell-id = <608>; + label = "slv-sdcc-2"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <33>; + }; + + slv-sdcc-4 { + cell-id = <609>; + label = "slv-sdcc-4"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <34>; + }; + + slv-tsif { + cell-id = <575>; + label = "slv-tsif"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <35>; + }; + + slv-bam-dma { + cell-id = <610>; + label = "slv-bam-dma"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <36>; + }; + + slv-blsp-2 { + cell-id = <611>; + label = "slv-blsp-2"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <37>; + }; + + slv-usb-hsic { + cell-id = <612>; + label = "slv-usb-hsic"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <38>; + }; + + slv-blsp-1 { + cell-id = <613>; + label = "slv-blsp-1"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <39>; + }; + + slv-usb-hs { + cell-id = <614>; + label = "slv-usb-hs"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <40>; + }; + + slv-pdm { + cell-id = <615>; + label = "slv-pdm"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <41>; + }; + + slv-periph-apu-cfg { + cell-id = <616>; + label = "slv-periph-apu-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <42>; + }; + + slv-pnoc-mpu-cfg { + cell-id = <617>; + label = "slv-pnoc-mpu-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <43>; + }; + + slv-prng { + cell-id = <618>; + label = "slv-prng"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <44>; + }; + + slv-service-pnoc { + cell-id = <619>; + label = "slv-service-pnoc"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <46>; + }; + + }; + + msm-config-noc@fc480000 { + compatible = "msm-bus-fabric"; + reg = <0xfc480000 0x00004000>; + cell-id = <5120>; + label = "msm_config_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-rpm-inst { + cell-id = <72>; + label = "mas-rpm-inst"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <45>; + }; + + mas-rpm-data { + cell-id = <73>; + label = "mas-rpm-data"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <46>; + }; + + mas-rpm-sys { + cell-id = <74>; + label = "mas-rpm-sys"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <47>; + }; + + mas-dehr { + cell-id = <75>; + label = "mas-dehr"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <48>; + }; + + mas-qdss-dsp { + cell-id = <76>; + label = "mas-qdss-dap"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <49>; + }; + + mas-spdm { + cell-id = <36>; + label = "mas-spdm"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <50>; + }; + + mas-tic { + cell-id = <77>; + label = "mas-tic"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <51>; + }; + + slv-clk-ctl { + cell-id = <620>; + label = "slv-clk-ctl"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <47>; + }; + + slv-cnoc-mss { + cell-id = <621>; + label = "slv-cnoc-mss"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <48>; + }; + + slv-security { + cell-id = <622>; + label = "slv-security"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <49>; + }; + + slv-tcsr { + cell-id = <623>; + label = "slv-tcsr"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <50>; + }; + + slv-tlmm { + cell-id = <624>; + label = "slv-tlmm"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <51>; + }; + + slv-crypto-0-cfg { + cell-id = <625>; + label = "slv-crypto-0-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <52>; + }; + + slv-crypto-1-cfg { + cell-id = <626>; + label = "slv-crypto-1-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <53>; + }; + + slv-imem-cfg { + cell-id = <627>; + label = "slv-imem-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <54>; + }; + + slv-message-ram { + cell-id = <628>; + label = "slv-message-ram"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <55>; + }; + + slv-bimc-cfg { + cell-id = <629>; + label = "slv-bimc-cfg"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <56>; + }; + + slv-boot-rom { + cell-id = <630>; + label = "slv-boot-rom"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <57>; + }; + + slv-pmic-arb { + cell-id = <632>; + label = "slv-pmic-arb"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <59>; + }; + + slv-spdm-wrapper { + cell-id = <633>; + label = "slv-spdm-wrapper"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <60>; + }; + + slv-dehr-cfg { + cell-id = <634>; + label = "slv-dehr-cfg"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <61>; + }; + + slv-mpm { + cell-id = <536>; + label = "slv-mpm"; + qcom,slavep = <16>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <62>; + }; + + slv-qdss-cfg { + cell-id = <635>; + label = "slv-qdss-cfg"; + qcom,slavep = <17>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <63>; + }; + + slv-rbcpr-cfg { + cell-id = <636>; + label = "slv-rbcpr-cfg"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <64>; + }; + + slv-rbcpr-qdss-apu-cfg { + cell-id = <637>; + label = "slv-rbcpr-qdss-apu-cfg"; + qcom,slavep = <19>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <65>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <29>; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <52>; + qcom,slv-hw-id = <75>; + }; + + slv-cnoc-onoc-cfg { + cell-id = <639>; + label = "slv-cnoc-onoc-cfg"; + qcom,slavep = <22>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <68>; + }; + + slv-cnoc-mnoc-mmss-cfg { + cell-id = <631>; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <58>; + }; + + slv-cnoc-mnoc-cfg { + cell-id = <640>; + label = "slv-cnoc-mnoc-cfg"; + qcom,slavep = <20>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <66>; + }; + + slv-pnoc-cfg { + cell-id = <641>; + label = "slv-pnoc-cfg"; + qcom,slavep = <23>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <69>; + }; + + slv-snoc-mpu-cfg { + cell-id = <638>; + label = "slv-snoc-mpu-cfg"; + qcom,slavep = <21>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <67>; + }; + + slv-snoc-cfg { + cell-id = <642>; + label = "slv-snoc-cfg"; + qcom,slavep = <24>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <70>; + }; + + slv-ebi1-dll-cfg { + cell-id = <643>; + label = "slv-ebi1-dll-cfg"; + qcom,slavep = <25>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <71>; + }; + + slv-phy-apu-cfg { + cell-id = <644>; + label = "slv-phy-apu-cfg"; + qcom,slavep = <26>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <72>; + }; + + slv-ebi1-phy-cfg { + cell-id = <645>; + label = "slv-ebi1-phy-cfg"; + qcom,slavep = <27>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <73>; + }; + + slv-rpm { + cell-id = <534>; + label = "slv-rpm"; + qcom,slavep = <28>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <74>; + }; + + slv-service-cnoc { + cell-id = <646>; + label = "slv-service-cnoc"; + qcom,slavep = <30>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <76>; + }; + + }; + + msm-bimc@0xfc380000 { + compatible = "msm-bus-fabric"; + reg = <0xfc380000 0x0006A000>; + cell-id = <0>; + label = "msm_bimc"; + qcom,fabclk-dual = "mem_clk"; + qcom,fabclk-active = "mem_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <19200>; + qcom,hw-sel = "BIMC"; + qcom,rpm-en; + + coresight-id = <55>; + coresight-name = "coresight-bimc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <3>; + + mas-ampss-m0 { + cell-id = <1>; + label = "mas-ampss-m0"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Limiter"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,mode-thresh = "Fixed"; + qcom,thresh = <2000000>; + qcom,dual-conf; + qcom,bimc,bw = <300000>; + qcom,bimc,gp = <5>; + qcom,bimc,thmp = <50>; + }; + + mas-ampss-m1 { + cell-id = <2>; + label = "mas-ampss-m1"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Limiter"; + qcom,qport = <1>; + qcom,ws = <10000>; + qcom,mas-hw-id = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,mode-thresh = "Fixed"; + qcom,thresh = <2000000>; + qcom,dual-conf; + qcom,bimc,bw = <300000>; + qcom,bimc,gp = <5>; + qcom,bimc,thmp = <50>; + }; + + mas-mss-proc { + cell-id = <65>; + label = "mas-mss-proc"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <1>; + }; + + fab-mmss-noc { + cell-id = <2048>; + label = "fab_mmss_noc"; + qcom,gateway; + qcom,masterp = <3 4>; + qcom,qport = <3 4>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Bypass"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <3>; + qcom,masterp = <5 6>; + qcom,qport = <5 6>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <3>; + qcom,slv-hw-id = <2>; + qcom,mode = "Bypass"; + qcom,hw-sel = "RPM"; + }; + + slv-ebi-ch0 { + cell-id = <512>; + label = "slv-ebi-ch0"; + qcom,slavep = <0 1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <0>; + qcom,mode = "Bypass"; + }; + + slv-ampss-l2 { + cell-id = <514>; + label = "slv-ampss-l2"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <1>; + }; + }; + + msm-ocmem-vnoc@6144 { + compatible = "msm-bus-fabric"; + reg = <0x6144 0x2>; + cell-id = <6144>; + label = "msm-ocmem-vnoc"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + qcom,virt; + + mas-v-ocmem-gfx3d { + cell-id = <89>; + label = "mas-v-ocmem-gfx3d"; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <55>; + }; + + slv-ocmem { + cell-id = <604>; + label = "slv-ocmem"; + qcom,slavep = <0 1>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,slv-hw-id = <18>; + qcom,slaveclk-dual = "ocmem_clk"; + qcom,slaveclk-active = "ocmem_a_clk"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <57>; + qcom,slv-hw-id = <80>; + }; + + fab-onoc { + cell-id = <3072>; + label = "fab-onoc"; + qcom,gateway; + qcom,buswidth = <16>; + qcom,ws = <10000>; + qcom,mas-hw-id = <56>; + qcom,slv-hw-id = <79>; + }; + + }; + + msm-ocmem-noc@fc470000 { + compatible = "msm-bus-fabric"; + reg = <0xfc470000 0x00004000>; + cell-id = <3072>; + label = "msm_ocmem_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <51>; + coresight-name = "coresight-onoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <4>; + + fab-ocmem-vnoc { + cell-id = <6144>; + label = "fab-ocmem-vnoc"; + qcom,gateway; + qcom,buswidth = <16>; + qcom,mas-hw-id = <54>; + qcom,slv-hw-id = <78>; + }; + + mas-jpeg-ocmem { + cell-id = <66>; + label = "mas-jpeg-ocmem"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,qport = <0>; + qcom,mas-hw-id = <13>; + qcom,hw-sel = "NoC"; + }; + + mas-mdp-ocmem { + cell-id = <67>; + label = "mas-mdp-ocmem"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,mas-hw-id = <14>; + qcom,hw-sel = "NoC"; + }; + + mas-video-ocmem { + cell-id = <68>; + label = "mas-video-ocmem"; + qcom,masterp = <3 4>; + qcom,tier = <2>; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,qport = <2 3>; + qcom,mas-hw-id = <15>; + qcom,hw-sel = "NoC"; + }; + + mas-vfe-ocmem { + cell-id = <70>; + label = "mas-vfe-ocmem"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,qport = <4>; + qcom,mas-hw-id = <17>; + qcom,hw-sel = "NoC"; + qcom,prio-rd = <1>; + qcom,prio-wr = <1>; + }; + + mas-cnoc-onoc-cfg { + cell-id = <71>; + label = "mas-cnoc-onoc-cfg"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,mas-hw-id = <12>; + qcom,hw-sel = "NoC"; + }; + + slv-service-onoc { + cell-id = <605>; + label = "slv-service-onoc"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,slv-hw-id = <19>; + }; + }; +}; + + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-cdp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-cdp.dtsi new file mode 100644 index 000000000..4a9820dab --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-cdp.dtsi @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18 0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e 0x0>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "s5k3l1yx"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "imx135"; + qcom,actuator-src = <&actuator1>; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,sensor-type = <0>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c 0x0>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov2720"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90 0x0>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "mt9m114"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 92 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-dragonboard.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-dragonboard.dtsi new file mode 100644 index 000000000..e84a47d62 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-dragonboard.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18 0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e 0x0>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,actuator-src = <&actuator0>; + qcom,sensor-name = "s5k3l1yx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "imx135"; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c 0x0>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <180>; + qcom,sensor-name = "ov2720"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90 0x0>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "mt9m114"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 94 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-fluid.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-fluid.dtsi new file mode 100644 index 000000000..f61b83a45 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-fluid.dtsi @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <270>; + qcom,sensor-name = "s5k3l1yx"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,sensor-name = "imx135"; + qcom,actuator-src = <&actuator1>; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,sensor-type = <0>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov2720"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <1>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "mt9m114"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 92 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-liquid.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-liquid.dtsi new file mode 100644 index 000000000..cf968d208 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-liquid.dtsi @@ -0,0 +1,190 @@ + +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,actuator-src = <&actuator0>; + qcom,sensor-name = "s5k3l1yx"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs2>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "imx135"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs2>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,sensor-type = <0>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <180>; + qcom,sensor-name = "ov2720"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs2>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + qcom,sensor-name = "mt9m114"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs2>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 92 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-mtp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-mtp.dtsi new file mode 100644 index 000000000..6ad62137c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera-sensor-mtp.dtsi @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "s5k3l1yx"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "imx135"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,sensor-type = <0>; + qcom,cci-master = <0>; + status = "ok"; + }; + + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov2720"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <1>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "mt9m114"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 92 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera.dtsi new file mode 100644 index 000000000..786e9e381 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-camera.dtsi @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,msm-cam@fd8C0000 { + compatible = "qcom,msm-cam"; + reg = <0xfd8C0000 0x10000>; + reg-names = "msm-cam"; + }; + + qcom,csiphy@fda0ac00 { + cell-index = <0>; + compatible = "qcom,csiphy"; + reg = <0xfda0ac00 0x200>, + <0xfda00030 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + }; + + qcom,csiphy@fda0b000 { + cell-index = <1>; + compatible = "qcom,csiphy"; + reg = <0xfda0b000 0x200>, + <0xfda00038 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + }; + + qcom,csiphy@fda0b400 { + cell-index = <2>; + compatible = "qcom,csiphy"; + reg = <0xfda0b400 0x200>, + <0xfda00040 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 80 0>; + interrupt-names = "csiphy"; + }; + + qcom,csid@fda08000 { + cell-index = <0>; + compatible = "qcom,csid"; + reg = <0xfda08000 0x100>; + reg-names = "csid"; + interrupts = <0 51 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + }; + + qcom,csid@fda08400 { + cell-index = <1>; + compatible = "qcom,csid"; + reg = <0xfda08400 0x100>; + reg-names = "csid"; + interrupts = <0 52 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + }; + + qcom,csid@fda08800 { + cell-index = <2>; + compatible = "qcom,csid"; + reg = <0xfda08800 0x100>; + reg-names = "csid"; + interrupts = <0 53 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + }; + + qcom,csid@fda08C00 { + cell-index = <3>; + compatible = "qcom,csid"; + reg = <0xfda08C00 0x100>; + reg-names = "csid"; + interrupts = <0 54 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + }; + + qcom,ispif@fda0A000 { + cell-index = <0>; + compatible = "qcom,ispif"; + reg = <0xfda0A000 0x500>, + <0xfda00020 0x10>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 55 0>; + interrupt-names = "ispif"; + }; + + qcom,vfe@fda10000 { + cell-index = <0>; + compatible = "qcom,vfe40"; + reg = <0xfda10000 0x1000>, + <0xfda40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 57 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + }; + + qcom,vfe@fda14000 { + cell-index = <1>; + compatible = "qcom,vfe40"; + reg = <0xfda14000 0x1000>, + <0xfda40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 58 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + }; + + qcom,jpeg@fda1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0xfda1c000 0x400>; + reg-names = "jpeg"; + interrupts = <0 59 0>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + }; + + qcom,jpeg@fda20000 { + cell-index = <1>; + compatible = "qcom,jpeg"; + reg = <0xfda20000 0x400>; + reg-names = "jpeg"; + interrupts = <0 60 0>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + }; + + qcom,jpeg@fda24000 { + cell-index = <2>; + compatible = "qcom,jpeg"; + reg = <0xfda24000 0x400>; + reg-names = "jpeg"; + interrupts = <0 61 0>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + }; + + qcom,irqrouter@fda00000 { + cell-index = <0>; + compatible = "qcom,irqrouter"; + reg = <0xfda00000 0x100>; + reg-names = "irqrouter"; + }; + + qcom,cpp@fda04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xfda04000 0x100>, + <0xfda40000 0x200>, + <0xfda18000 0x008>; + reg-names = "cpp", "cpp_vbif", "cpp_hw"; + interrupts = <0 49 0>; + interrupt-names = "cpp"; + vdd-supply = <&gdsc_vfe>; + }; + + led_flash0: qcom,camera-led-flash { + cell-index = <0>; + compatible = "qcom,camera-led-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pm8941_flash0 &pm8941_flash1>; + }; + + cci: qcom,cci@fda0C000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xfda0C000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 50 0>; + interrupt-names = "cci"; + gpios = <&msmgpio 19 0>, + <&msmgpio 20 0>, + <&msmgpio 21 0>, + <&msmgpio 22 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + qcom,hw-thigh = <78>; + qcom,hw-tlow = <114>; + qcom,hw-tsu-sto = <28>; + qcom,hw-tsu-sta = <28>; + qcom,hw-thd-dat = <10>; + qcom,hw-thd-sta = <77>; + qcom,hw-tbuf = <118>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-cdp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-cdp.dtsi new file mode 100644 index 000000000..2a60df4f4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-cdp.dtsi @@ -0,0 +1,729 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-toshiba-720p-video.dtsi" +/include/ "dsi-panel-orise-720p-video.dtsi" +/include/ "msm8974-leds.dtsi" +/include/ "msm8974-camera-sensor-cdp.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_dsi_toshiba_720p_video { + status = "ok"; + qcom,cont-splash-enabled; + }; + + qcom,mdss_dsi_orise_720p_video { + status = "disable"; + }; + + qcom,hdmi_tx@fd922100 { + status = "ok"; + }; + + i2c@f9924000 { + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l18>; + vcc_i2c-supply = <&pm8941_lvs1>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 760 1424>; + atmel,display-coords = <0 0 720 1280>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x82>; + atmel,variant-id = <0x19>; + atmel,version = <0x10>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 15 01 00 03 0A 0C 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 03 + /* Object 8, Instance = 0 */ + 0F 00 0A 0A 00 00 0A 0A 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 18 0E 00 70 46 02 01 + 00 0A 03 31 04 05 0A 0A 90 05 + F8 02 05 F1 F1 0F 00 00 08 2D + 12 06 00 00 00 01 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 23, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 00 00 00 00 + /* Object 42, Instance = 0 */ + 33 1E 19 10 80 00 00 00 FF 00 + /* Object 46, Instance = 0 */ + 00 00 10 10 00 00 03 00 00 01 + /* Object 47, Instance = 0 */ + 08 0A 28 0A 02 0A 00 8C 00 20 + 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 00 00 00 18 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 01 2A 00 16 00 00 00 00 0B 01 + 02 03 04 08 00 00 08 10 18 05 + 00 0A 05 05 50 14 19 34 1A 7F + 00 00 00 00 00 00 00 00 00 30 + 05 02 00 01 00 05 00 00 00 00 + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <720>; + qcom,disp-maxy = <1280>; + qcom,panel-maxx = <760>; + qcom,panel-maxy = <1424>; + qcom,key-codes = <158 139 102 217>; + }; + + i2c@f9967000 { + isa1200@48 { + status = "okay"; + reg = <0x48>; + vcc_i2c-supply = <&pm8941_s3>; + compatible = "imagis,isa1200"; + label = "vibrator"; + imagis,chip-en; + imagis,smart-en; + imagis,need-pwm-clk; + imagis,ext-clk-en; + imagis,hap-en-gpio = <&msmgpio 86 0x00>; + imagis,max-timeout = <15000>; + imagis,pwm-div = <256>; + imagis,mode-ctrl = <2>; + imagis,regulator { + regulator-name = "vcc_i2c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-max-microamp = <9360>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@2 { + compatible = "micrel,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <94 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&pm8941_mpps 6 0>; + vdd-io-supply = <&spi_eth_vreg>; + vdd-phy-supply = <&spi_eth_vreg>; + }; + }; + + sound { + qcom,model = "msm8974-taiko-cdp-snd-card"; + qcom,hdmi-audio-rx; + qcom,us-euro-gpios = <&pm8941_gpios 20 0>; + qcom,cdc-micbias2-headset-only; + }; + + usb2_otg_sw: regulator-tpd4s214 { + compatible = "regulator-fixed"; + regulator-name = "usb2_otg_sw"; + gpio = <&pm8941_gpios 18 0>; + parent-supply = <&pm8941_boost>; + startup-delay-us = <17000>; + enable-active-high; + }; + + hsic_host: hsic@f9a00000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a00000 0x400>; + #address-cells = <0>; + interrupt-parent = <&hsic_host>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 136 0 + 1 &intc 0 148 0 + 2 &msmgpio 144 0x8>; + interrupt-names = "core_irq", "async_irq", "wakeup"; + HSIC_VDDCX-supply = <&pm8841_s2>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + hsic,strobe-gpio = <&msmgpio 144 0x00>; + hsic,data-gpio = <&msmgpio 145 0x00>; + hsic,resume-gpio = <&msmgpio 80 0x00>; + hsic,ignore-cal-pad-config; + hsic,strobe-pad-offset = <0x2050>; + hsic,data-pad-offset = <0x2054>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>; + }; + + wlan0: qca,wlan { + compatible = "qca,ar6004-hsic"; + qcom,msm-bus,name = "wlan"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>, + <85 512 40000 320000>, + <85 512 40000 480000>, + <85 512 40000 800000>; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <25>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <2>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + + qcom,leds@d900 { + status = "disabled"; + }; + + qcom,leds@da00 { + status = "disabled"; + }; + + qcom,leds@db00 { + status = "disabled"; + }; + + qcom,leds@dc00 { + status = "disabled"; + }; + + qcom,leds@dd00 { + status = "disabled"; + }; + + qcom,leds@de00 { + status = "disabled"; + }; + + qcom,leds@df00 { + status = "disabled"; + }; + + qcom,leds@e000 { + status = "disabled"; + }; + + qcom,leds@e100 { + status = "disabled"; + }; + }; +}; + +&sdcc1 { + status = "disabled"; +}; + +&sdcc2 { + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + wp-gpios = <&pm8941_gpios 29 0x1>; + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; + +/* Drive strength recommendations for clock line from hardware team is 10 mA. + * But since the driver has been been using the below values from the start + * without any problems, continue to use those. + */ +&sdcc1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdcc2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&uart7 { + status = "ok"; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; +}; + +&usb3 { + qcom,otg-capability; +}; + +&pm8941_chg { + status = "ok"; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c300 { /* GPIO 4 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <1>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <2>; + qcom,vin-sel = <2>; + qcom,out-strength = <2>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + /* usb2_otg_sw regulator enable */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS logic */ + qcom,invert = <0>; /* Output low initially */ + qcom,vin-sel = <2>; /* PM8941 S3 = 1.8 V */ + qcom,src-sel = <0>; /* Constant */ + qcom,out-strength = <2>; /* Medium drive strength */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,invert = <0>; /* Output low initially */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; + + gpio@d600 { /* GPIO 23 */ + }; + + gpio@d700 { /* GPIO 24 */ + }; + + gpio@d800 { /* GPIO 25 */ + }; + + gpio@d900 { /* GPIO 26 */ + }; + + gpio@da00 { /* GPIO 27 */ + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,pull = <0>; /* set to default pull */ + qcom,master-en = <1>; + qcom,vin-sel = <2>; /* select 1.8 V source */ + }; + + gpio@dd00 { /* GPIO 30 */ + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + }; + + gpio@e000 { /* GPIO 33 */ + }; + + gpio@e100 { /* GPIO 34 */ + }; + + gpio@e200 { /* GPIO 35 */ + }; + + gpio@e300 { /* GPIO 36 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <3>; /* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */ + qcom,master-en = <1>; + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + status = "disabled"; + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + /* SPI_ETH config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a500 { /* MPP 6 */ + /* SPI_ETH_RST config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; +}; + +/* CoreSight */ +&tpiu { + qcom,seta-gpios = <&msmgpio 31 0>, + <&msmgpio 32 0>, + <&msmgpio 33 0>, + <&msmgpio 34 0>, + <&msmgpio 35 0>, + <&msmgpio 36 0>, + <&msmgpio 37 0>, + <&msmgpio 38 0>, + <&msmgpio 39 0>, + <&msmgpio 40 0>, + <&msmgpio 41 0>, + <&msmgpio 42 0>, + <&msmgpio 43 0>, + <&msmgpio 44 0>, + <&msmgpio 45 0>, + <&msmgpio 46 0>, + <&msmgpio 47 0>, + <&msmgpio 48 0>; + qcom,seta-gpios-func = <4 4 4 3 4 4 4 3 4 3 5 5 5 5 4 4 5 5>; + qcom,seta-gpios-drv = <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>; + qcom,seta-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + qcom,seta-gpios-dir = <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>; + + qcom,setb-gpios = <&msmgpio 15 0>, + <&msmgpio 16 0>, + <&msmgpio 17 0>, + <&msmgpio 18 0>, + <&msmgpio 19 0>, + <&msmgpio 20 0>, + <&msmgpio 21 0>, + <&msmgpio 22 0>, + <&msmgpio 23 0>, + <&msmgpio 24 0>, + <&msmgpio 25 0>, + <&msmgpio 26 0>, + <&msmgpio 27 0>, + <&msmgpio 28 0>, + <&msmgpio 89 0>, + <&msmgpio 90 0>, + <&msmgpio 91 0>, + <&msmgpio 92 0>; + qcom,setb-gpios-func = <2 2 2 2 5 5 5 5 6 6 6 7 7 5 2 3 3 3>; + qcom,setb-gpios-drv = <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>; + qcom,setb-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + qcom,setb-gpios-dir = <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias1-ext-cap; + qcom,cdc-micbias3-ext-cap; + qcom,cdc-micbias4-ext-cap; + + /* If boot isn't available, vph_pwr_vreg can be used instead */ + cdc-vdd-spkdrv-supply = <&pm8941_boost>; + qcom,cdc-vdd-spkdrv-voltage = <5000000 5000000>; + qcom,cdc-vdd-spkdrv-current = <1250000>; + + qcom,cdc-on-demand-supplies = "cdc-vdd-spkdrv"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-clock.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-clock.dtsi new file mode 100644 index 000000000..bed5d70be --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-clock.dtsi @@ -0,0 +1,27 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + + qcom,pm8941@0 { + + pm8941_clkdiv1: clkdiv@5b00 { + qcom,cxo-div = <2>; + }; + + pm8941_clkdiv2: clkdiv@5c00 { + }; + + pm8941_clkdiv3: clkdiv@5d00 { + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-coresight.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-coresight.dtsi new file mode 100644 index 000000000..1610f1f43 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-coresight.dtsi @@ -0,0 +1,381 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@fc322000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc322000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + }; + + tpiu: tpiu@fc318000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc318000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + vdd-supply = <&pm8941_l21>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + }; + + replicator: replicator@fc31c000 { + compatible = "qcom,coresight-replicator"; + reg = <0xfc31c000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + }; + + tmc_etf: tmc@fc307000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc307000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + }; + + funnel_merg: funnel@fc31b000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31b000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc319000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc319000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + funnel_in1: funnel@fc31a000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31a000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <6>; + coresight-name = "coresight-funnel-in1"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <1>; + }; + + funnel_kpss: funnel@fc345000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc345000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <7>; + coresight-name = "coresight-funnel-kpss"; + coresight-nr-inports = <4>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <5>; + }; + + funnel_mmss: funnel@fc364000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc364000 0x1000>; + reg-names = "funnel-base"; + + + coresight-id = <8>; + coresight-name = "coresight-funnel-mmss"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <1>; + }; + + stm: stm@fc321000 { + compatible = "arm,coresight-stm"; + reg = <0xfc321000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <9>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc33c000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33c000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <10>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <0>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm1: etm@fc33d000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33d000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <11>; + coresight-name = "coresight-etm1"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <1>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm2: etm@fc33e000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33e000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <12>; + coresight-name = "coresight-etm2"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <2>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm3: etm@fc33f000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33f000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <13>; + coresight-name = "coresight-etm3"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <3>; + + qcom,pc-save; + qcom,round-robin; + }; + + csr: csr@fc302000 { + compatible = "qcom,coresight-csr"; + reg = <0xfc302000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <14>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <3>; + }; + + cti0: cti@fc308000 { + compatible = "arm,coresight-cti"; + reg = <0xfc308000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + }; + + cti1: cti@fc309000 { + compatible = "arm,coresight-cti"; + reg = <0xfc309000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + cti2: cti@fc30a000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30a000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + }; + + cti3: cti@fc30b000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30b000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <18>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + }; + + cti4: cti@fc30c000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30c000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <19>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + }; + + cti5: cti@fc30d000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30d000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <20>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + }; + + cti6: cti@fc30e000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30e000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <21>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + }; + + cti7: cti@fc30f000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30f000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <22>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + }; + + cti8: cti@fc310000 { + compatible = "arm,coresight-cti"; + reg = <0xfc310000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <23>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + }; + + cti_l2: cti@fc340000 { + compatible = "arm,coresight-cti"; + reg = <0xfc340000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <24>; + coresight-name = "coresight-cti-l2"; + coresight-nr-inports = <0>; + }; + + cti_cpu0: cti@fc341000 { + compatible = "arm,coresight-cti"; + reg = <0xfc341000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <25>; + coresight-name = "coresight-cti-cpu0"; + coresight-nr-inports = <0>; + }; + + cti_cpu1: cti@fc342000 { + compatible = "arm,coresight-cti"; + reg = <0xfc342000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <26>; + coresight-name = "coresight-cti-cpu1"; + coresight-nr-inports = <0>; + }; + + cti_cpu2: cti@fc343000 { + compatible = "arm,coresight-cti"; + reg = <0xfc343000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <27>; + coresight-name = "coresight-cti-cpu2"; + coresight-nr-inports = <0>; + }; + + cti_cpu3: cti@fc344000 { + compatible = "arm,coresight-cti"; + reg = <0xfc344000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <28>; + coresight-name = "coresight-cti-cpu3"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@fdf30018 { + compatible = "qcom,coresight-hwevent"; + reg = <0xfdf30018 0x80>, + <0xf9011080 0x80>, + <0xfd4ab160 0x80>; + reg-names = "mmss-mux", "apcs-mux", "ppss-mux"; + + coresight-id = <29>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + + qcom,hwevent-clks = "core_mmss_clk"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-fluid.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-fluid.dtsi new file mode 100644 index 000000000..a822af5fa --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-fluid.dtsi @@ -0,0 +1,667 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-toshiba-720p-video.dtsi" +/include/ "msm8974-camera-sensor-fluid.dtsi" +/include/ "msm8974-leds.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_dsi_toshiba_720p_video { + status = "ok"; + qcom,cont-splash-enabled; + }; + + qcom,hdmi_tx@fd922100 { + status = "ok"; + }; + + i2c@f9924000 { + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l18>; + vcc_i2c-supply = <&pm8941_lvs1>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 760 1424>; + atmel,display-coords = <0 0 720 1280>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x82>; + atmel,variant-id = <0x19>; + atmel,version = <0x10>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 15 01 00 03 0A 0C 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 03 + /* Object 8, Instance = 0 */ + 0F 00 0A 0A 00 00 0A 0A 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 18 0E 00 70 46 02 01 + 00 0A 03 31 04 05 0A 0A 90 05 + F8 02 05 F1 F1 0F 00 00 08 2D + 12 06 00 00 00 01 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 23, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 00 00 00 00 + /* Object 42, Instance = 0 */ + 33 1E 19 10 80 00 00 00 FF 00 + /* Object 46, Instance = 0 */ + 00 00 10 10 00 00 03 00 00 01 + /* Object 47, Instance = 0 */ + 08 0A 28 0A 02 0A 00 8C 00 20 + 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 00 00 00 18 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 01 2A 00 16 00 00 00 00 0B 01 + 02 03 04 08 00 00 08 10 18 05 + 00 0A 05 05 50 14 19 34 1A 7F + 00 00 00 00 00 00 00 00 00 30 + 05 02 00 01 00 05 00 00 00 00 + 00 00 00 00 + ]; + }; + }; + }; + + i2c@f9967000 { + sii8334@72 { + compatible = "qcom,mhl-sii8334"; + reg = <0x72>; + interrupt-parent = <&msmgpio>; + interrupts = <82 0x8>; + mhl-intr-gpio = <&msmgpio 82 0>; + mhl-pwr-gpio = <&msmgpio 12 0>; + mhl-rst-gpio = <&pm8941_mpps 8 0>; + avcc_18-supply = <&pm8941_l24>; + avcc_12-supply = <&pm8941_l2>; + smps3a-supply = <&pm8941_s3>; + vdda-supply = <&pm8941_l12>; + qcom,hdmi-tx-map = <&mdss_hdmi_tx>; + }; + + isa1200@48 { + status = "okay"; + reg = <0x48>; + vcc_i2c-supply = <&pm8941_s3>; + compatible = "imagis,isa1200"; + label = "vibrator"; + imagis,chip-en; + imagis,need-pwm-clk; + imagis,ext-clk-en; + imagis,hap-en-gpio = <&msmgpio 86 0x00>; + imagis,max-timeout = <15000>; + imagis,pwm-div = <256>; + imagis,mode-ctrl = <2>; + imagis,regulator { + regulator-name = "vcc_i2c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-max-microamp = <9360>; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <720>; + qcom,disp-maxy = <1280>; + qcom,panel-maxx = <760>; + qcom,panel-maxy = <1424>; + qcom,key-codes = <158 139 102 217>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@2 { + compatible = "micrel,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <94 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&pm8941_mpps 6 0>; + vdd-io-supply = <&spi_eth_vreg>; + vdd-phy-supply = <&spi_eth_vreg>; + }; + }; + + sound { + qcom,model = "msm8974-taiko-fluid-snd-card"; + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "AMIC1", "MIC BIAS1 Internal1", + "MIC BIAS1 Internal1", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC2", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic2", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4", + "DMIC5", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic5", + "DMIC6", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic6", + "Lineout_1 amp", "LINEOUT1", + "Lineout_3 amp", "LINEOUT3"; + + qcom,hdmi-audio-rx; + qcom,ext-ult-lo-amp-gpio = <&pm8941_gpios 6 0>; + qcom,cdc-micbias2-headset-only; + }; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias1-ext-cap; + qcom,cdc-micbias2-ext-cap; + qcom,cdc-micbias3-ext-cap; + qcom,cdc-micbias4-ext-cap; + + /* If boot isn't available, vph_pwr_vreg can be used instead */ + cdc-vdd-spkdrv-supply = <&pm8941_boost>; + qcom,cdc-vdd-spkdrv-voltage = <5000000 5000000>; + qcom,cdc-vdd-spkdrv-current = <1250000>; + + qcom,cdc-on-demand-supplies = "cdc-vdd-spkdrv"; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <25>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <2>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + + qcom,leds@d900 { + status = "disabled"; + }; + + qcom,leds@da00 { + status = "disabled"; + }; + + qcom,leds@db00 { + status = "disabled"; + }; + + qcom,leds@dc00 { + status = "disabled"; + }; + + qcom,leds@dd00 { + status = "disabled"; + }; + + qcom,leds@de00 { + status = "disabled"; + }; + + qcom,leds@df00 { + status = "disabled"; + }; + + qcom,leds@e000 { + status = "disabled"; + }; + + qcom,leds@e100 { + status = "disabled"; + }; + }; +}; + +&sdcc1 { + status = "disabled"; +}; + +&sdcc2 { + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; + +/* Drive strength recommendations for clock line from hardware team is 10 mA. + * But since the driver has been been using the below values from the start + * without any problems, continue to use those. + */ +&sdcc1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdcc2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&usb3 { + qcom,otg-capability; +}; + +&pm8941_bms { + status = "ok"; +}; + +&pm8941_chg { + status = "ok"; + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c300 { /* GPIO 4 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <1>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; + + gpio@d600 { /* GPIO 23 */ + }; + + gpio@d700 { /* GPIO 24 */ + }; + + gpio@d800 { /* GPIO 25 */ + }; + + gpio@d900 { /* GPIO 26 */ + }; + + gpio@da00 { /* GPIO 27 */ + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,pull = <0>; /* set to default pull */ + qcom,master-en = <1>; + qcom,vin-sel = <2>; /* select 1.8 V source */ + }; + + gpio@dd00 { /* GPIO 30 */ + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + }; + + gpio@e000 { /* GPIO 33 */ + }; + + gpio@e100 { /* GPIO 34 */ + }; + + gpio@e200 { /* GPIO 35 */ + }; + + gpio@e300 { /* GPIO 36 */ + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + status = "disabled"; + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + /* SPI_ETH_RST config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,pull = <0>; + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; +}; + +&spi_epm { + epm-adc@0 { + compatible = "cy,epm-adc-cy8c5568lti-114"; + reg = <0>; + interrupt-parent = <&msmgpio>; + spi-max-frequency = <960000>; + qcom,channels = <31>; + qcom,gain = <100 100 100 50 100 100 1 100 1 50 + 1 100 1 100 50 50 50 50 50 50 + 100 50 100 50 50 50 50 50 50 50 + 50>; + qcom,rsense = <2 2 2 200 20 2 1 2 1 30 + 1 10 1 30 50 30 500 30 100 30 + 100 500 20 200 1000 20 1000 1000 70 200 + 50>; + qcom,channel-type = <0x1540>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-gpu.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-gpu.dtsi new file mode 100644 index 000000000..06b9c187b --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-gpu.dtsi @@ -0,0 +1,185 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + msm_gpu: qcom,kgsl-3d0@fdb00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0xfdb00000 0x10000 + 0xfdb20000 0x10000>; + reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03030000>; + + qcom,initial-pwrlevel = <2>; + qcom,step-pwrlevel = <2>; + + qcom,idle-timeout = <8>; // + qcom,strtstp-sleepwake; + qcom,clk-map = <0x0000006>; //KGSL_CLK_CORE | KGSL_CLK_IFACE + + /* Bus Scale Settings */ + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, <89 604 0 0>, + <26 512 0 2200000>, <89 604 0 3000000>, + <26 512 0 4000000>, <89 604 0 3000000>, + <26 512 0 4000000>, <89 604 0 4500000>, + <26 512 0 6400000>, <89 604 0 4500000>, + <26 512 0 6400000>, <89 604 0 7600000>; + + /* GDSC oxili regulators */ + vddcx-supply = <&gdsc_oxili_cx>; + vdd-supply = <&gdsc_oxili_gx>; + + /* Power levels */ + + /* IOMMU Data */ + iommu = <&kgsl_iommu>; + + /* Trace bus */ + coresight-id = <67>; + coresight-name = "coresight-gfx"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_mmss>; + coresight-child-ports = <7>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <450000000>; + qcom,bus-freq = <5>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,io-fraction = <66>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <3>; + qcom,io-fraction = <66>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <1>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,io-fraction = <0>; + }; + }; + + qcom,dcvs-core-info { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,dcvs-core-info"; + + qcom,num-cores = <1>; + qcom,sensors = <0>; + + qcom,core-core-type = <1>; + + qcom,algo-disable-pc-threshold = <0>; + qcom,algo-em-win-size-min-us = <100000>; + qcom,algo-em-win-size-max-us = <300000>; + qcom,algo-em-max-util-pct = <97>; + qcom,algo-group-id = <95>; + qcom,algo-max-freq-chg-time-us = <100000>; + qcom,algo-slack-mode-dynamic = <100000>; + qcom,algo-slack-weight-thresh-pct = <0>; + qcom,algo-slack-time-min-us = <39000>; + qcom,algo-slack-time-max-us = <39000>; + qcom,algo-ss-win-size-min-us = <1000000>; + qcom,algo-ss-win-size-max-us = <1000000>; + qcom,algo-ss-util-pct = <95>; + qcom,algo-ss-no-corr-below-freq = <0>; + + qcom,energy-active-coeff-a = <2492>; + qcom,energy-active-coeff-b = <0>; + qcom,energy-active-coeff-c = <0>; + qcom,energy-leakage-coeff-a = <11>; + qcom,energy-leakage-coeff-b = <157150>; + qcom,energy-leakage-coeff-c = <0>; + qcom,energy-leakage-coeff-d = <0>; + + qcom,power-current-temp = <25>; + qcom,power-num-freq = <4>; + + qcom,dcvs-freq@0 { + reg = <0>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@1 { + reg = <1>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@2 { + reg = <2>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@3 { + reg = <3>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <844545>; + qcom,leakage-energy-offset = <0>; + }; + }; + + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-ion.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-ion.dtsi new file mode 100644 index 000000000..63f6d59c2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-ion.dtsi @@ -0,0 +1,59 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@8 { /* CP_MM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <8>; + qcom,heap-align = <0x1000>; + linux,contiguous-region = <&secure_mem>; + }; + + qcom,ion-heap@22 { /* adsp heap */ + compatible = "qcom,msm-ion-reserve"; + reg = <22>; + qcom,heap-align = <0x1000>; + linux,contiguous-region = <&adsp_mem>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + qcom,ion-heap@27 { /* QSECOM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <27>; + linux,contiguous-region = <&qsecom_mem>; + }; + + qcom,ion-heap@28 { /* AUDIO HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <28>; + qcom,heap-align = <0x1000>; + qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */ + qcom,memory-reservation-size = <0x614000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-leds.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-leds.dtsi new file mode 100644 index 000000000..5e91f4597 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-leds.dtsi @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d000 { + status = "okay"; + qcom,rgb_0 { + label = "rgb"; + linux,name = "led:rgb_red"; + qcom,mode = "pwm"; + qcom,pwm-channel = <6>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + qcom,id = <3>; + linux,default-trigger = + "battery-charging"; + }; + + qcom,rgb_1 { + label = "rgb"; + linux,name = "led:rgb_green"; + qcom,mode = "pwm"; + qcom,pwm-channel = <5>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + qcom,id = <4>; + linux,default-trigger = "battery-full"; + }; + + qcom,rgb_2 { + label = "rgb"; + linux,name = "led:rgb_blue"; + qcom,mode = "pwm"; + qcom,pwm-channel = <4>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,id = <5>; + status = "disabled"; + }; + }; + + qcom,leds@d100 { + status = "disabled"; + }; + + qcom,leds@d200 { + status = "disabled"; + }; + + qcom,leds@d300 { + status = "okay"; + pm8941_flash0: qcom,flash_0 { + qcom,max-current = <1000>; + qcom,default-state = "off"; + qcom,headroom = <3>; + qcom,duration = <1280>; + qcom,clamp-curr = <200>; + qcom,startup-dly = <3>; + qcom,safety-timer; + label = "flash"; + linux,default-trigger = + "flash0_trigger"; + qcom,id = <1>; + linux,name = "led:flash_0"; + qcom,current = <625>; + }; + + pm8941_flash1: qcom,flash_1 { + qcom,max-current = <1000>; + qcom,default-state = "off"; + qcom,headroom = <3>; + qcom,duration = <1280>; + qcom,clamp-curr = <200>; + qcom,startup-dly = <3>; + qcom,safety-timer; + linux,default-trigger = + "flash1_trigger"; + label = "flash"; + qcom,id = <2>; + linux,name = "led:flash_1"; + qcom,current = <625>; + }; + + pm8941_torch: qcom,flash_torch { + qcom,max-current = <200>; + qcom,default-state = "off"; + qcom,headroom = <0>; + qcom,startup-dly = <1>; + linux,default-trigger = + "torch_trigger"; + label = "flash"; + qcom,id = <2>; + linux,name = "led:flash_torch"; + qcom,current = <200>; + qcom,torch-enable; + }; + }; + + qcom,leds@d400 { + status = "disabled"; + }; + + qcom,leds@d500 { + status = "disabled"; + }; + + qcom,leds@d600 { + status = "disabled"; + }; + + qcom,leds@d700 { + status = "disabled"; + }; + }; +}; + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-liquid.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-liquid.dtsi new file mode 100644 index 000000000..2dc52b6be --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-liquid.dtsi @@ -0,0 +1,893 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm8974-leds.dtsi" +/include/ "msm8974-camera-sensor-liquid.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_edp@fd923400 { + status = "ok"; + }; + + i2c@f9967000 { + battery@b { + compatible = "ti,bq28400-battery"; + reg = <0xb>; + ti,temp-cold = <2>; /* degree celsius */ + ti,temp-hot = <43>; /* degree celsius */ + }; + + charger@2b { + compatible = "summit,smb350-charger"; + reg = <0x2b>; /* 0x56/0x57 */ + summit,stat-gpio = <&pm8941_gpios 30 0x00>; + summit,chg-en-n-gpio = <&pm8941_gpios 10 0x00>; + summit,chg-susp-n-gpio = <&pm8941_gpios 13 0x00>; + summit,chg-current-ma = <1600>; + summit,term-current-ma = <300>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + home { + label = "home"; + gpios = <&pm8941_gpios 1 0x1>; + linux,input-type = <1>; + linux,code = <102>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 0x1>; + linux,input-type = <1>; + linux,code = <114>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + qcom,hdmi_tx@fd922100 { + status = "ok"; + + qcom,hdmi-tx-mux-sel = <&pm8841_mpps 3 0>; + qcom,hdmi-tx-mux-en = <&pm8841_mpps 4 0>; + }; + + drv2667_vreg: drv2667_vdd_vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_drv2667"; + }; + + i2c@f9967000 { + ti-drv2667@59 { + compatible = "ti,drv2667"; + reg = <0x59>; + vdd-supply = <&drv2667_vreg>; + vdd-i2c-supply = <&pm8941_s3>; + ti,label = "vibrator"; + ti,gain = <2>; + ti,idle-timeout-ms = <20>; + ti,max-runtime-ms = <15000>; + ti,mode = <2>; + ti,wav-seq = [ + /* wave form id */ + 01 + /* header size, start and stop bytes */ + 05 80 06 00 09 + /* repeat, amp, freq, duration, envelope */ + 01 ff 19 02 00]; + }; + }; + + i2c@f9924000 { + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l22>; + vcc_i2c-supply = <&pm8941_s3>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 1080 1920>; + atmel,display-coords = <0 0 1080 1920>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0xa2>; + atmel,variant-id = <0x00>; + atmel,version = <0x11>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 16 00 00 14 09 0C 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 7, Instance = 0 */ + FF FF 0A 03 + /* Object 8, Instance = 0 */ + 5F 00 14 14 00 00 00 01 00 00 + /* Object 9, Instance = 0 */ + 8F 00 00 20 34 00 87 3C 08 03 + 00 05 03 80 0A 14 14 0A 80 07 + 38 04 00 00 00 00 00 00 00 00 + 0F 0F 2E 33 02 00 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 04 00 + /* Object 24, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 54 6F F0 55 00 00 00 00 + 00 00 00 00 00 + /* Object 27, Instance = 0 */ + 00 00 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 14 14 14 14 + /* Object 42, Instance = 0 */ + 20 14 00 00 00 14 11 00 03 00 + /* Object 43, Instance = 0 */ + 09 00 01 01 91 00 80 00 00 00 + 00 00 + /* Object 46, Instance = 0 */ + 00 00 10 10 00 00 01 00 00 0F + 0A + /* Object 47, Instance = 0 */ + 00 14 23 02 05 1E 01 78 03 10 + 00 00 0C 00 00 00 00 00 00 00 + 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 02 00 01 30 13 14 14 14 15 15 + 15 15 15 15 15 16 16 16 16 16 + 16 16 16 16 16 15 14 14 14 14 + 15 14 14 14 14 13 00 00 01 02 + 05 05 00 00 00 00 00 00 00 00 + 00 + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 00 01 03 01 00 00 00 00 00 0A + 0F 14 19 23 05 00 0A 05 05 69 + 23 23 34 11 64 06 06 04 40 00 + 00 00 00 00 69 4B 02 00 00 80 + 0A 14 14 18 18 10 10 80 00 80 + 00 00 0F 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 63, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 + ]; + }; + atmel,cfg_2 { + atmel,family-id = <0xa2>; + atmel,variant-id = <0x00>; + atmel,version = <0x11>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 19 03 00 1E 05 0D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 C3 + /* Object 8, Instance = 0 */ + 41 00 14 14 00 00 00 01 00 00 + /* Object 9, Instance = 0 */ + 8F 00 00 20 34 00 87 4B 02 03 + 00 05 03 41 0A 14 14 0A 80 07 + 38 04 00 00 03 03 08 28 02 3C + 0F 0F 2E 33 01 00 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 04 00 + /* Object 24, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 54 6F F0 55 00 00 00 00 + 00 00 00 00 00 + /* Object 27, Instance = 0 */ + 00 00 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 14 14 14 14 + /* Object 42, Instance = 0 */ + 23 32 14 14 80 00 0A 00 05 05 + /* Object 43, Instance = 0 */ + 08 00 01 01 91 00 80 00 00 00 + 00 00 + /* Object 46, Instance = 0 */ + 00 00 18 18 00 00 01 00 00 0F + 0A + /* Object 47, Instance = 0 */ + 00 14 28 02 05 28 01 78 03 10 + 00 00 0C 00 00 00 00 00 00 00 + 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 01 00 00 30 13 14 14 14 15 15 + 15 15 15 15 15 16 16 16 16 16 + 16 16 16 16 16 15 14 14 14 14 + 15 14 14 14 14 13 03 20 03 01 + 0A 04 00 00 00 00 00 00 00 00 + 1A + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 00 03 00 07 02 00 00 00 00 00 + 0F 17 23 2D 05 00 05 03 03 69 + 14 14 34 11 64 06 06 04 40 00 + 00 00 00 00 69 3C 02 04 01 00 + 0A 14 14 03 03 03 03 00 00 00 + 00 64 1E 01 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 63, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 + /* Object 65, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 + /* Object 66, Instance = 0 */ + 00 00 00 00 00 + ]; + }; + }; + }; + + ext_5v: regulator-smb210 { + compatible = "regulator-fixed"; + regulator-name = "ext_5v"; + gpio = <&pm8941_mpps 2 0>; + startup-delay-us = <12000>; + enable-active-high; + }; + + ath_chip_pwd_l: ath_chip_reset { + compatible = "regulator-fixed"; + regulator-name = "ath_chip_pwd_l"; + gpio = <&pm8941_gpios 33 0>; + enable-active-high; + }; + + bt_ar3002 { + compatible = "qca,ar3002"; + qca,bt-reset-gpio = <&pm8941_gpios 34 0>; + qca,bt-chip-pwd-supply = <&ath_chip_pwd_l>; + qca,bt-vdd-io-supply = <&pm8941_s3>; + qca,bt-vdd-pa-supply = <&pm8941_l19>; + }; + + bt_ar3002_sleep { + compatible = "qca,ar3002_bluesleep"; + host-wake-gpio = <&msmgpio 79 0>; + ext-wake-gpio = <&msmgpio 51 0>; + interrupt-parent = <&msmgpio>; + interrupts = <79 2>; + interrupt-names = "host_wake"; + }; + + sound { + qcom,model = "msm8974-taiko-liquid-snd-card"; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "Lineout_1 amp", "LINEOUT1", + "Lineout_3 amp", "LINEOUT3", + "Lineout_2 amp", "LINEOUT2", + "Lineout_4 amp", "LINEOUT4", + "SPK_ultrasound amp", "SPK_OUT", + "AMIC1", "MIC BIAS4 External", + "MIC BIAS4 External", "Analog Mic4", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic6", + "AMIC6", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic7", + "DMIC1", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic1", + "DMIC2", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic2", + "DMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4", + "DMIC5", "MIC BIAS2 External", + "MIC BIAS2 External", "Digital Mic5", + "DMIC6", "MIC BIAS2 External", + "MIC BIAS2 External", "Digital Mic6"; + + qcom,ext-spk-amp-supply = <&ext_5v>; + qcom,ext-spk-amp-gpio = <&pm8841_mpps 1 0>; + qcom,dock-plug-det-irq = <&pm8841_mpps 2 0>; + qcom,ext-ult-spk-amp-gpio = <&pm8941_gpios 6 0>; + qcom,hdmi-audio-rx; + + qcom,prim-auxpcm-gpio-clk = <&msmgpio 74 0>; + qcom,prim-auxpcm-gpio-sync = <&msmgpio 75 0>; + qcom,prim-auxpcm-gpio-din = <&msmgpio 76 0>; + qcom,prim-auxpcm-gpio-dout = <&msmgpio 77 0>; + qcom,prim-auxpcm-gpio-set = "prim-gpio-tert"; + }; + + hsic_hub { + compatible = "qcom,hsic-smsc-hub"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + smsc,reset-gpio = <&pm8941_gpios 8 0x00>; + smsc,refclk-gpio = <&pm8941_gpios 16 0x00>; + smsc,int-gpio = <&msmgpio 50 0x00>; + hub_int-supply = <&pm8941_l10>; + hub_vbus-supply = <&ext_5v>; + + hsic_host: hsic@f9a00000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a00000 0x400>; + #address-cells = <0>; + interrupt-parent = <&hsic_host>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 136 0 + 1 &intc 0 148 0 + 2 &msmgpio 144 0x8>; + interrupt-names = "core_irq", "async_irq", "wakeup"; + HSIC_VDDCX-supply = <&pm8841_s2>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + hsic,strobe-gpio = <&msmgpio 144 0x00>; + hsic,data-gpio = <&msmgpio 145 0x00>; + hsic,ignore-cal-pad-config; + hsic,strobe-pad-offset = <0x2050>; + hsic,data-pad-offset = <0x2054>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>; + }; + }; + + wlan0: qca,wlan { + compatible = "qca,ar6004-hsic"; + qcom,msm-bus,name = "wlan"; + qca,wifi-chip-pwd-supply = <&ath_chip_pwd_l>; + qca,wifi-vddpa-supply = <&pm8941_l19>; + qca,wifi-vddio-supply = <&pm8941_l10>; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>, + <85 512 40000 320000>, + <85 512 40000 480000>, + <85 512 40000 800000>; + }; + + wlan_sdio:qca,wlan_sdio { + compatible = "qca,ar6004-sdio"; + qcom,msm-bus,name = "wlan_sdio"; + qca,wifi-chip-pwd-supply = <&ath_chip_pwd_l>; + }; +}; + +&mdss_fb0 { + qcom,memory-reservation-size = <0x1000000>; /* size 16MB */ +}; + +&uart7 { + status = "ok"; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; +}; + +&usb3 { + qcom,otg-capability; +}; + +&pm8941_mvs2 { + parent-supply = <&ext_5v>; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c500 { /* GPIO 6 */ + /* ULTRASOUND_EN_1 PA AB enable */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,pull = <4>; /* PULL_DOWN */ + qcom,vin-sel = <0>; /* VPH */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + /* HSIC_HUB-RESET */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,pull = <5>; /* PULL_NO */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,master-en = <1>; + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + /* SMB350-CHG-EN-N */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,pull = <5>; /* PULL_NO */ + qcom,vin-sel = <0>; /* VPH */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + /* SMB350-CHG-SUSP-N */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,pull = <5>; /* PULL_NO */ + qcom,vin-sel = <0>; /* VPH */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <1>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + /* HSIC_HUB-INT_N */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; + + gpio@d600 { /* GPIO 23 */ + }; + + gpio@d700 { /* GPIO 24 */ + }; + + gpio@d800 { /* GPIO 25 */ + }; + + gpio@d900 { /* GPIO 26 */ + }; + + gpio@da00 { /* GPIO 27 */ + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,pull = <0>; /* set to default pull */ + qcom,master-en = <1>; + qcom,vin-sel = <2>; /* select 1.8 V source */ + }; + + gpio@dd00 { /* GPIO 30 */ + /* SMB350-STAT */ + qcom,mode = <0>; /* DIG_IN */ + qcom,pull = <5>; /* PULL_NO */ + qcom,vin-sel = <2>; /* S3 1.8V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + }; + + gpio@e000 { /* GPIO 33 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; + qcom,master-en = <1>; + }; + + gpio@e100 { /* GPIO 34 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <0>; + qcom,master-en = <1>; + }; + + gpio@e200 { /* GPIO 35 */ + }; + + gpio@e300 { /* GPIO 36 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <3>; /* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */ + qcom,master-en = <1>; + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + status = "disabled"; + }; + + mpp@a100 { /* MPP 2 */ + /* ext_5v regulator enable */ + qcom,mode = <1>; /* Digital output */ + qcom,invert = <0>; /* Output low initially */ + qcom,vin-sel = <2>; /* PM8941 S3 = 1.8 V */ + qcom,src-sel = <0>; /* Constant */ + qcom,master-en = <1>; /* Enable MPP */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + /* SPI_ETH config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a500 { /* MPP 6 */ + /* SPI_ETH_RST config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + /* CLASS_D_EN speakers PA */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* PNP_PIN_OUT_BUF_CMOS */ + qcom,vin-sel = <2>; /* S3A 1.8v */ + qcom,src-select = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a100 { /* MPP 2 */ + /* DOCK_PLUG_DET speakers+docking detect irq*/ + qcom,mode = <0>; /* DIG_IN */ + qcom,vin-sel = <2>; /* S3A 1.8v */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a200 { /* HDMI_MUX_SEL MPP 3*/ + status = "ok"; + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8841_S3A 1.8V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a300 { /* HDMI_MUX_EN MPP 4*/ + status = "ok"; + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <0>; /* PM8841_VPH 3.4V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; +}; + +&vph_pwr_vreg { + status = "ok"; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias1-ext-cap; + qcom,cdc-micbias2-ext-cap; + qcom,cdc-micbias3-ext-cap; + qcom,cdc-micbias4-ext-cap; + + /* + * Liquid has external spkrdrv supply. Give a dummy supply to + * make codec driver's happy. + */ + cdc-vdd-spkdrv-supply = <&vph_pwr_vreg>; + qcom,cdc-vdd-spkdrv-voltage = <0 0>; + qcom,cdc-vdd-spkdrv-current = <0>; + + qcom,cdc-on-demand-supplies = "cdc-vdd-spkdrv"; + }; +}; + +&spi_epm { + epm-adc@0 { + compatible = "cy,epm-adc-cy8c5568lti-114"; + reg = <0>; + interrupt-parent = <&msmgpio>; + spi-max-frequency = <960000>; + qcom,channels = <31>; + qcom,gain = <50 50 50 50 50 100 50 50 50 50 + 50 50 50 50 100 50 50 50 50 100 + 50 50 50 100 50 50 50 1 1 1 + 1>; + qcom,rsense = <40 10 10 25 10 1000 75 25 10 25 + 33 500 200 10 500 100 33 200 25 100 + 75 500 50 200 5 5 3 1 1 1 + 1>; + qcom,channel-type = <0xf0000000>; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d000 { + qcom,rgb_2 { + status = "ok"; + qcom,default-state = "on"; + qcom,turn-off-delay-ms = <1000>; + }; + }; + }; +}; + +&pm8941_chg { + status = "ok"; + otg-parent-supply = <&ext_5v>; + + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&sdcc1 { + status = "disabled"; +}; + +&sdcc2 { + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; + +/* Drive strength recommendations for clock line from hardware team is 10 mA. + * But since the driver has been been using the below values from the start + * without any problems, continue to use those. + */ +&sdcc1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdcc2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-mdss.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-mdss.dtsi new file mode 100644 index 000000000..6b8d600ed --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-mdss.dtsi @@ -0,0 +1,148 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_mdp: qcom,mdss_mdp@fd900000 { + compatible = "qcom,mdss_mdp"; + reg = <0xfd900000 0x22100>, + <0xfd924000 0x1000>; + reg-names = "mdp_phys", "vbif_phys"; + interrupts = <0 72 0>; + vdd-supply = <&gdsc_mdss>; + + qcom,max-clk-rate = <320000000>; + qcom,mdss-pipe-vig-off = <0x00001200 0x00001600 + 0x00001A00>; + qcom,mdss-pipe-rgb-off = <0x00001E00 0x00002200 + 0x00002600>; + qcom,mdss-pipe-dma-off = <0x00002A00 0x00002E00>; + qcom,mdss-pipe-vig-fetch-id = <1 4 7>; + qcom,mdss-pipe-rgb-fetch-id = <16 17 18>; + qcom,mdss-pipe-dma-fetch-id = <10 13>; + qcom,mdss-smp-data = <22 4096>; + + qcom,mdss-ctl-off = <0x00000600 0x00000700 0x00000800 + 0x00000900 0x0000A00>; + qcom,mdss-mixer-intf-off = <0x00003200 0x00003600 + 0x00003A00>; + qcom,mdss-mixer-wb-off = <0x00003E00 0x00004200>; + qcom,mdss-dspp-off = <0x00004600 0x00004A00 0x00004E00>; + qcom,mdss-wb-off = <0x00011100 0x00013100 0x00015100 + 0x00017100 0x00019100>; + qcom,mdss-intf-off = <0x00021100 0x00021300 + 0x00021500 0x00021700>; + + qcom,vbif-settings = <0x0004 0x00000001>, + <0x00D8 0x00000707>, + <0x00F0 0x00000030>, + <0x0124 0x00000001>, + <0x0178 0x00000FFF>, + <0x017C 0x0FFF0FFF>, + <0x0160 0x22222222>, + <0x0164 0x00002222>; + qcom,mdp-settings = <0x02E0 0x000000E9>, + <0x02E4 0x00000055>, + <0x03AC 0xC0000CCC>, + <0x03B4 0xC0000CCC>, + <0x03BC 0x00CCCCCC>, + <0x04A8 0x0CCCC0C0>, + <0x04B0 0xCCCCC0C0>, + <0x04B8 0xCCCCC000>; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x800000>; + }; + + mdss_fb1: qcom,mdss_fb_external { + cell-index = <1>; + compatible = "qcom,mdss-fb"; + }; + + mdss_fb2: qcom,mdss_fb_wfd { + cell-index = <2>; + compatible = "qcom,mdss-fb"; + }; + }; + + mdss_dsi0: qcom,mdss_dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0xfd922800 0x600>; + vdd-supply = <&pm8941_l22>; + vddio-supply = <&pm8941_l12>; + vdda-supply = <&pm8941_l2>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; + + mdss_dsi1: qcom,mdss_dsi@fd922e00 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->1"; + cell-index = <1>; + reg = <0xfd922e00 0x600>; + vdd-supply = <&pm8941_l22>; + vddio-supply = <&pm8941_l12>; + vdda-supply = <&pm8941_l2>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; + + mdss_hdmi_tx: qcom,hdmi_tx@fd922100 { + cell-index = <0>; + compatible = "qcom,hdmi-tx"; + reg = <0xfd922100 0x35C>, + <0xfd922500 0x7C>, + <0xfc4b8000 0x60F0>; + reg-names = "core_physical", "phy_physical", "qfprom_physical"; + + hpd-gdsc-supply = <&gdsc_mdss>; + hpd-5v-supply = <&pm8941_mvs2>; + core-vdda-supply = <&pm8941_l12>; + core-vcc-supply = <&pm8941_s3>; + qcom,hdmi-tx-supply-names = "hpd-gdsc", "hpd-5v", "core-vdda", "core-vcc"; + qcom,hdmi-tx-min-voltage-level = <0 0 1800000 1800000>; + qcom,hdmi-tx-max-voltage-level = <0 0 1800000 1800000>; + qcom,hdmi-tx-peak-current = <0 0 1800000 0>; + + qcom,hdmi-tx-cec = <&msmgpio 31 0>; + qcom,hdmi-tx-ddc-clk = <&msmgpio 32 0>; + qcom,hdmi-tx-ddc-data = <&msmgpio 33 0>; + qcom,hdmi-tx-hpd = <&msmgpio 34 0>; + qcom,mdss-fb-map = <&mdss_fb1>; + qcom,msm-hdmi-audio-rx { + compatible = "qcom,msm-hdmi-audio-codec-rx"; + }; + }; + + qcom,mdss_wb_panel { + compatible = "qcom,mdss_wb"; + qcom,mdss_pan_res = <1920 1080>; + qcom,mdss_pan_bpp = <24>; + qcom,mdss-fb-map = <&mdss_fb2>; + }; + + mdss_edp: qcom,mdss_edp@fd923400 { + compatible = "qcom,mdss-edp"; + reg = <0xfd923400 0x700>, + <0xfd8c2000 0x1000>; + reg-names = "edp_base", "mmss_cc_base"; + vdda-supply = <&pm8941_l12>; + gpio-panel-en = <&msmgpio 58 0>; + gpio-panel-pwm = <&pm8941_gpios 36 0>; + qcom,panel-lpg-channel = <7>; /* LPG Channel 8 */ + qcom,panel-pwm-period = <53>; + status = "disable"; + qcom,mdss-fb-map = <&mdss_fb0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-mtp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-mtp.dtsi new file mode 100644 index 000000000..e798fc0f9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-mtp.dtsi @@ -0,0 +1,705 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-toshiba-720p-video.dtsi" +/include/ "msm8974-camera-sensor-mtp.dtsi" +/include/ "msm8974-leds.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_dsi_toshiba_720p_video { + status = "ok"; + qcom,cont-splash-enabled; + }; + + qcom,hdmi_tx@fd922100 { + status = "disabled"; + }; + + i2c@f9924000 { + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l18>; + vcc_i2c-supply = <&pm8941_lvs1>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 760 1424>; + atmel,display-coords = <0 0 720 1280>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x82>; + atmel,variant-id = <0x19>; + atmel,version = <0x10>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 15 01 00 03 0A 0C 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 03 + /* Object 8, Instance = 0 */ + 0F 00 0A 0A 00 00 0A 0A 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 18 0E 00 70 46 02 01 + 00 0A 03 31 04 05 0A 0A 90 05 + F8 02 05 F1 F1 0F 00 00 08 2D + 12 06 00 00 00 01 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 23, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 00 00 00 00 + /* Object 42, Instance = 0 */ + 33 1E 19 10 80 00 00 00 FF 00 + /* Object 46, Instance = 0 */ + 00 00 10 10 00 00 03 00 00 01 + /* Object 47, Instance = 0 */ + 08 0A 28 0A 02 0A 00 8C 00 20 + 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 00 00 00 18 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 01 2A 00 16 00 00 00 00 0B 01 + 02 03 04 08 00 00 08 10 18 05 + 00 0A 05 05 50 14 19 34 1A 7F + 00 00 00 00 00 00 00 00 00 30 + 05 02 00 01 00 05 00 00 00 00 + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <720>; + qcom,disp-maxy = <1280>; + qcom,panel-maxx = <760>; + qcom,panel-maxy = <1424>; + qcom,key-codes = <158 139 102 217>; + }; + + i2c@f9967000 { + isa1200@48 { + status = "okay"; + reg = <0x48>; + vcc_i2c-supply = <&pm8941_s3>; + compatible = "imagis,isa1200"; + label = "vibrator"; + imagis,chip-en; + imagis,need-pwm-clk; + imagis,ext-clk-en; + imagis,hap-en-gpio = <&msmgpio 86 0x00>; + imagis,max-timeout = <15000>; + imagis,pwm-div = <256>; + imagis,mode-ctrl = <2>; + imagis,regulator { + regulator-name = "vcc_i2c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-max-microamp = <9360>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@2 { + compatible = "micrel,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <94 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&pm8941_mpps 6 0>; + vdd-io-supply = <&spi_eth_vreg>; + vdd-phy-supply = <&spi_eth_vreg>; + }; + }; + + sound { + qcom,model = "msm8974-taiko-mtp-snd-card"; + qcom,cdc-micbias2-headset-only; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <25>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <2>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + + qcom,leds@d900 { + status = "disabled"; + }; + + qcom,leds@da00 { + status = "disabled"; + }; + + qcom,leds@db00 { + status = "disabled"; + }; + + qcom,leds@dc00 { + status = "disabled"; + }; + + qcom,leds@dd00 { + status = "disabled"; + }; + + qcom,leds@de00 { + status = "disabled"; + }; + + qcom,leds@df00 { + status = "disabled"; + }; + + qcom,leds@e000 { + status = "disabled"; + }; + + qcom,leds@e100 { + status = "disabled"; + }; + }; +}; + +&sdcc1 { + status = "disabled"; +}; + +&sdcc2 { + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; + +/* Drive strength recommendations for clock line from hardware team is 10 mA. + * But since the driver has been been using the below values from the start + * without any problems, continue to use those. + */ +&sdcc1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdcc2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&usb_otg { + qcom,hsusb-otg-otg-control = <2>; +}; + +&uart7 { + status = "ok"; +}; + +&usb3 { + qcom,otg-capability; +}; + +&pm8941_bms { + status = "ok"; +}; + +&pm8941_chg { + status = "ok"; + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c200 { /* GPIO 3 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,vin-sel = <2>; + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@c300 { /* GPIO 4 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@c500 { /* GPIO 6 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c600 { /* GPIO 7 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c700 { /* GPIO 8 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c800 { /* GPIO 9 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@c900 { /* GPIO 10 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@ca00 { /* GPIO 11 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@cb00 { /* GPIO 12 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@cd00 { /* GPIO 14 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <1>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <3>; + qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */ + qcom,master-en = <1>; + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@d600 { /* GPIO 23 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@d700 { /* GPIO 24 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@d800 { /* GPIO 25 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@d900 { /* GPIO 26 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@da00 { /* GPIO 27 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@dd00 { /* GPIO 30 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@e000 { /* GPIO 33 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@e100 { /* GPIO 34 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@e200 { /* GPIO 35 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@e300 { /* GPIO 36 */ + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + status = "disabled"; + }; + + mpp@a100 { /* MPP 2 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,master-en = <1>; + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + /* SPI_ETH_RST config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a600 { /* MPP 7 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,master-en = <1>; + }; + + mpp@a700 { /* MPP 8 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,master-en = <1>; + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias1-ext-cap; + qcom,cdc-micbias2-ext-cap; + qcom,cdc-micbias4-ext-cap; + }; +}; + +&spi_epm { + epm-adc@0 { + compatible = "cy,epm-adc-cy8c5568lti-114"; + reg = <0>; + interrupt-parent = <&msmgpio>; + spi-max-frequency = <960000>; + qcom,channels = <31>; + qcom,gain = <100 100 100 50 100 100 1 100 1 50 + 1 100 1 100 50 50 50 50 50 50 + 100 50 100 50 50 50 50 50 50 50 + 50>; + qcom,rsense = <2 2 2 200 20 2 1 2 1 30 + 1 10 1 30 50 30 500 30 100 30 + 100 500 20 200 1000 20 1000 1000 70 200 + 50>; + qcom,channel-type = <0x1540>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-regulator.dtsi new file mode 100644 index 000000000..2114686eb --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-regulator.dtsi @@ -0,0 +1,568 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* QPNP controlled regulators: */ + +&spmi_bus { + + qcom,pm8941@1 { + + pm8941_boost: regulator@a000 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + qcom,enable-time = <500>; + status = "okay"; + }; + + pm8941_mvs1: regulator@8300 { + parent-supply = <&pm8941_chg_otg>; + qcom,enable-time = <1000>; + qcom,pull-down-enable = <1>; + interrupts = <0x1 0x83 0x2>; + interrupt-names = "ocp"; + qcom,ocp-enable = <1>; + qcom,ocp-max-retries = <10>; + qcom,ocp-retry-delay = <30>; + qcom,soft-start-enable = <1>; + qcom,vs-soft-start-strength = <0>; + qcom,hpm-enable = <1>; + qcom,auto-mode-enable = <0>; + status = "okay"; + }; + + pm8941_mvs2: regulator@8400 { + parent-supply = <&pm8941_boost>; + qcom,enable-time = <1000>; + qcom,pull-down-enable = <1>; + interrupts = <0x1 0x84 0x2>; + interrupt-names = "ocp"; + qcom,ocp-enable = <1>; + qcom,ocp-max-retries = <10>; + qcom,ocp-retry-delay = <30>; + qcom,soft-start-enable = <1>; + qcom,vs-soft-start-strength = <0>; + qcom,hpm-enable = <1>; + qcom,auto-mode-enable = <0>; + status = "okay"; + }; + }; +}; + +/* RPM controlled regulators: */ + +&rpm_bus { + rpm-regulator-smpb1 { + status = "okay"; + pm8841_s1: regulator-s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8841_s1_ao: regulator-s1-ao { + regulator-name = "8841_s1_ao"; + qcom,set = <1>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + compatible = "qcom,rpm-regulator-smd"; + }; + pm8841_s1_so: regulator-s1-so { + regulator-name = "8841_s1_so"; + qcom,set = <2>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <675000>; + status = "okay"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpb2 { + status = "okay"; + pm8841_s2: regulator-s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8841_s2_corner: regulator-s2-corner { + regulator-name = "8841_s2_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + compatible = "qcom,rpm-regulator-smd"; + qcom,consumer-supplies = "vdd_dig", ""; + }; + pm8841_s2_corner_ao: regulator-s2-corner-ao { + regulator-name = "8841_s2_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + compatible = "qcom,rpm-regulator-smd"; + }; + pm8841_s2_floor_corner: regulator-s2-floor-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8841_s2_floor_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-floor-corner; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-smpb3 { + status = "okay"; + pm8841_s3: regulator-s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1050000>; + status = "okay"; + }; + }; + + rpm-regulator-smpb4 { + status = "okay"; + pm8841_s4: regulator-s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + status = "okay"; + }; + pm8841_s4_corner: regulator-s4-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8841_s4_corner"; + qcom,set = <3>; + qcom,use-voltage-corner; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,init-voltage-corner = <3>; /* SVS SOC */ + }; + pm8841_s4_floor_corner: regulator-s4-floor-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8841_s4_floor_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-floor-corner; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-smpa1 { + status = "okay"; + pm8941_s1: regulator-s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa2 { + status = "okay"; + pm8941_s2: regulator-s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + qcom,init-voltage = <2150000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8941_s3: regulator-s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8941_l1: regulator-l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8941_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8941_l3: regulator-l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8941_l4: regulator-l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8941_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8941_l6: regulator-l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8941_l7: regulator-l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8941_l8: regulator-l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8941_l9: regulator-l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8941_l10: regulator-l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8941_l11: regulator-l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8941_l12: regulator-l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + pm8941_l12_ao: regulator-l12-ao { + regulator-name = "8941_l12_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8941_l13: regulator-l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8941_l14: regulator-l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8941_l15: regulator-l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8941_l16: regulator-l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <2700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8941_l17: regulator-l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8941_l18: regulator-l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8941_l19: regulator-l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + pm8941_l20: regulator-l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + pm8941_l21: regulator-l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8941_l22: regulator-l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + pm8941_l23: regulator-l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + pm8941_l24: regulator-l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-vsa1 { + status = "okay"; + pm8941_lvs1: regulator-lvs1 { + status = "okay"; + }; + }; + + rpm-regulator-vsa2 { + status = "okay"; + pm8941_lvs2: regulator-lvs2 { + status = "okay"; + }; + }; + + rpm-regulator-vsa3 { + status = "okay"; + pm8941_lvs3: regulator-lvs3 { + status = "okay"; + }; + }; +}; + +&soc { + krait_pdn: krait-pdn@f9011000 { + reg = <0xf9011000 0x1000>, + <0xfc4b80b0 8>; + reg-names = "apcs_gcc", "phase-scaling-efuse"; + compatible = "qcom,krait-pdn"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + qcom,pfm-threshold = <73>; + + krait0_vreg: regulator@f9088000 { + compatible = "qcom,krait-regulator"; + regulator-name = "krait0"; + reg = <0xf9088000 0x1000>, /* APCS_ALIAS0_KPSS_ACS */ + <0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */ + reg-names = "acs", "mdd"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,headroom-voltage = <150000>; + qcom,retention-voltage = <675000>; + qcom,ldo-default-voltage = <750000>; + qcom,ldo-threshold-voltage = <850000>; + qcom,ldo-delta-voltage = <50000>; + qcom,cpu-num = <0>; + }; + + krait1_vreg: regulator@f9098000 { + compatible = "qcom,krait-regulator"; + regulator-name = "krait1"; + reg = <0xf9098000 0x1000>, /* APCS_ALIAS1_KPSS_ACS */ + <0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */ + reg-names = "acs", "mdd"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,headroom-voltage = <150000>; + qcom,retention-voltage = <675000>; + qcom,ldo-default-voltage = <750000>; + qcom,ldo-threshold-voltage = <850000>; + qcom,ldo-delta-voltage = <50000>; + qcom,cpu-num = <1>; + }; + + krait2_vreg: regulator@f90a8000 { + compatible = "qcom,krait-regulator"; + regulator-name = "krait2"; + reg = <0xf90a8000 0x1000>, /* APCS_ALIAS2_KPSS_ACS */ + <0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */ + reg-names = "acs", "mdd"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,headroom-voltage = <150000>; + qcom,retention-voltage = <675000>; + qcom,ldo-default-voltage = <750000>; + qcom,ldo-threshold-voltage = <850000>; + qcom,ldo-delta-voltage = <50000>; + qcom,cpu-num = <2>; + }; + + krait3_vreg: regulator@f90b8000 { + compatible = "qcom,krait-regulator"; + regulator-name = "krait3"; + reg = <0xf90b8000 0x1000>, /* APCS_ALIAS3_KPSS_ACS */ + <0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */ + reg-names = "acs", "mdd"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,headroom-voltage = <150000>; + qcom,retention-voltage = <675000>; + qcom,ldo-default-voltage = <750000>; + qcom,ldo-threshold-voltage = <850000>; + qcom,ldo-delta-voltage = <50000>; + qcom,cpu-num = <3>; + }; + }; + + spi_eth_vreg: spi_eth_phy_vreg { + compatible = "regulator-fixed"; + regulator-name = "ethernet_phy"; + gpio = <&pm8941_mpps 5 0>; + enable-active-high; + }; + + /* + * vph_pwr_vreg represents the unregulated battery voltage supply + * VPH_PWR that is present whenever the device is powered on. + */ + vph_pwr_vreg: vph_pwr_vreg { + compatible = "regulator-fixed"; + status = "disabled"; + regulator-name = "vph_pwr"; + regulator-always-on; + }; +}; + +&pm8941_chg { + otg-parent-supply = <&pm8941_boost>; +}; + +&pm8941_chg_boost { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "8941_smbb_boost"; +}; + +&pm8941_chg_otg { + regulator-name = "8941_smbb_otg"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-rumi.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-rumi.dtsi new file mode 100644 index 000000000..c01a4e509 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-rumi.dtsi @@ -0,0 +1,146 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm8974-leds.dtsi" +/include/ "msm8974-camera-sensor-cdp.dtsi" + +&soc { + timer { + clock-frequency = <5000000>; + }; + + serial@f995e000 { + status = "ok"; + }; + + usb@f9a55000 { + status = "disable"; + }; + + qcom,sdcc@f9824000 { + qcom,clk-rates = <400000 19200000>; + }; + + qcom,sdcc@f98a4000 { + qcom,clk-rates = <400000 19200000>; + }; + + qcom,sps@f998000 { + status = "disable"; + }; + + spi@f9924000 { + status = "disable"; + }; + + spi@f9923000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 0>; + spi-max-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 3 0>, /* CLK */ + <&msmgpio 1 0>, /* MISO */ + <&msmgpio 0 0>; /* MOSI */ + cs-gpios = <&msmgpio 9 0>; + + ethernet-switch@2 { + compatible = "simtec,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <90 0>; + spi-max-frequency = <5000000>; + }; + }; + + i2c@f9966000 { + status = "disable"; + }; + + i2c@f9967000 { + cell-index = <0>; + compatible = "qcom,i2c-qup"; + reg = <0Xf9967000 0x1000>; + reg-names = "qup_phys_addr"; + interrupts = <0 105 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + gpios = <&msmgpio 83 0>, /* DAT */ + <&msmgpio 84 0>; /* CLK */ + }; + + slim@fe12f000 { + status = "disable"; + }; + + qcom,mdss_dsi@fd922800 { + status = "disable"; + }; + + qcom,spmi@fc4c0000 { + status = "disable"; + }; + + qcom,ssusb@F9200000 { + status = "disable"; + }; + + qcom,lpass@fe200000 { + status = "disable"; + }; + + qcom,pronto@fb21b000 { + status = "disable"; + }; + + qcom,mss@fc880000 { + status = "disable"; + }; + + qcom,kgsl-3d0@fdb00000 { + status = "disabled"; + }; +}; + +&gdsc_venus { + status = "disabled"; +}; + +&gdsc_mdss { + status = "disabled"; +}; + +&gdsc_jpeg { + status = "disabled"; +}; + +&gdsc_vfe { + status = "disabled"; +}; + +&gdsc_oxili_gx { + status = "disabled"; +}; + +&gdsc_oxili_cx { + status = "disabled"; +}; + +&gdsc_usb_hsic { + status = "disabled"; +}; + +&rpm_bus { + rpm-standalone; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-sim.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-sim.dtsi new file mode 100644 index 000000000..24b8d18be --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-sim.dtsi @@ -0,0 +1,93 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-sim-video.dtsi" +/include/ "msm8974-leds.dtsi" +/include/ "msm8974-camera-sensor-cdp.dtsi" + +&soc { + qcom,mdss_dsi@fd922800 { + qcom,mdss_dsi_sim_video { + status = "ok"; + }; + }; + + serial@f991f000 { + status = "ok"; + }; + + serial@f995e000 { + status = "ok"; + }; +}; + +&jpeg_iommu { + qcom,iommu-ctx@fda6c000 { + interrupts = <0 69 0>; + }; + + qcom,iommu-ctx@fda6d000 { + interrupts = <0 70 0>; + }; + + qcom,iommu-ctx@fda6e000 { + interrupts = <0 71 0>; + }; +}; + +&mdp_iommu { + qcom,iommu-ctx@fd930000 { + interrupts = <0 46 0>; + }; + + qcom,iommu-ctx@fd931000 { + interrupts = <0 47 0>; + }; +}; + +&venus_iommu { + qcom,iommu-ctx@fdc8c000 { + interrupts = <0 43 0>; + }; + + qcom,iommu-ctx@fdc8d000 { + interrupts = <0 42 0>; + }; + + qcom,iommu-ctx@fdc8e000 { + interrupts = <0 41 0>; + }; +}; + +&kgsl_iommu { + qcom,iommu-ctx@fdb18000 { + interrupts = <0 240 0>; + }; + + qcom,iommu-ctx@fdb19000 { + interrupts = <0 241 0>; + }; +}; + +&vfe_iommu { + qcom,iommu-ctx@fda4c000 { + interrupts = <0 64 0>; + }; + + qcom,iommu-ctx@fda4d000 { + interrupts = <0 65 0>; + }; + + qcom,iommu-ctx@fda4e000 { + interrupts = <0 66 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-smp2p.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-smp2p.dtsi new file mode 100644 index 000000000..3921a686a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-smp2p.dtsi @@ -0,0 +1,225 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-wcnss { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <4>; + qcom,irq-bitmask = <0x40000>; + interrupts = <0 143 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + /* SMP2P SSR Driver for inbound entry from lpass. */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* SMP2P SSR Driver for outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_4_in: qcom,smp2pgpio-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_in { + compatible = "qcom,smp2pgpio_test_smp2p_4_in"; + gpios = <&smp2pgpio_smp2p_4_in 0 0>; + }; + + smp2pgpio_smp2p_4_out: qcom,smp2pgpio-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_in: qcom,smp2pgpio-ssr-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_out: qcom,smp2pgpio-ssr-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_out { + compatible = "qcom,smp2pgpio_test_smp2p_4_out"; + gpios = <&smp2pgpio_smp2p_4_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-cdp.dts new file mode 100644 index 000000000..c3fd98d2b --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-cdp.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8974 CDP"; + compatible = "qcom,msm8974-cdp", "qcom,msm8974", "qcom,cdp"; + qcom,msm-id = <126 1 0>, + <185 1 0>, + <186 1 0>; +}; + +&ehci { + status = "ok"; + vbus-supply = <&usb2_otg_sw>; +}; + +&hsic_host { + qcom,phy-sof-workaround; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-fluid.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-fluid.dts new file mode 100644 index 000000000..2b96ecbd2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-fluid.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-fluid.dtsi" + +/ { + model = "Qualcomm MSM 8974 FLUID"; + compatible = "qcom,msm8974-fluid", "qcom,msm8974", "qcom,fluid"; + qcom,msm-id = <126 3 0>, + <185 3 0>, + <186 3 0>; + +}; + +&pm8941_chg { + qcom,charging-disabled; +}; + +&sdcc1 { + qcom,bus-width = <4>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-iommu-domains.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-iommu-domains.dtsi new file mode 100644 index 000000000..25fca2a54 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-iommu-domains.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,iommu-domains { + compatible = "qcom,iommu-domains"; + + venus_domain_ns: qcom,iommu-domain1 { + label = "venus_ns"; + qcom,iommu-contexts = <&venus_ns>; + qcom,virtual-addr-pool = <0x40000000 0x3f000000 + 0x7f000000 0x1000000>; + }; + + venus_domain_cp: qcom,iommu-domain2 { + label = "venus_cp"; + qcom,iommu-contexts = <&venus_cp>; + qcom,virtual-addr-pool = <0x1000000 0x3f000000>; + qcom,secure-domain; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-iommu.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-iommu.dtsi new file mode 100644 index 000000000..56369dce3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-iommu.dtsi @@ -0,0 +1,40 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm-iommu-v1.dtsi" + +&jpeg_iommu { + status = "ok"; + vdd-supply = <&gdsc_jpeg>; +}; + +&mdp_iommu { + status = "ok"; + vdd-supply = <&gdsc_mdss>; +}; + +&venus_iommu { + status = "ok"; + vdd-supply = <&gdsc_venus>; +}; + +&kgsl_iommu { + status = "ok"; + qcom,needs-alt-core-clk; + vdd-supply = <&gdsc_oxili_cx>; + qcom,alt-vdd-supply = <&gdsc_oxili_gx>; +}; + +&vfe_iommu { + status = "ok"; + vdd-supply = <&gdsc_vfe>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-liquid.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-liquid.dts new file mode 100644 index 000000000..29d6150ba --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-liquid.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-liquid.dtsi" + +/ { + model = "Qualcomm MSM 8974 LIQUID"; + compatible = "qcom,msm8974-liquid", "qcom,msm8974", "qcom,liquid"; + qcom,msm-id = <126 9 0>, + <185 9 0>, + <186 9 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-mtp.dts new file mode 100644 index 000000000..8cbcca05a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-mtp.dts @@ -0,0 +1,28 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8974 MTP"; + compatible = "qcom,msm8974-mtp", "qcom,msm8974", "qcom,mtp"; + qcom,msm-id = <126 8 0>, + <185 8 0>, + <186 8 0>; +}; + +&pm8941_chg { + qcom,charging-disabled; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-pm.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-pm.dtsi new file mode 100644 index 000000000..56a819ecc --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-pm.dtsi @@ -0,0 +1,456 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f9099000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,core-id = <1>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f90a9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,core-id = <2>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f90b9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,core-id = <3>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f9012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9012000 0x1000>; + qcom,core-id = <0xffff>; /* L2/APCS SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-pmic-data0 = <0x02030080>; + qcom,saw2-pmic-data1 = <0x00030000>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + qcom,saw2-spm-cmd-ret = [1f 00 20 03 22 00 0f]; + qcom,saw2-spm-cmd-gdhs = [00 20 32 42 07 44 22 50 02 32 50 0f]; + qcom,saw2-spm-cmd-pc = [00 10 32 b0 11 42 07 01 b0 12 44 + 50 02 32 50 0f]; + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x62706d73>; /* "smpb" */ + qcom,id = <0x02>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <6>; /* Super Turbo */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x62706d73>; /* "smpb" */ + qcom,id = <0x01>; + qcom,key = <0x7675>; /* "uv" */ + qcom,init-value = <1050000>; /* Super Turbo */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + + qcom,lpm-resources@3 { + reg = <0x3>; + qcom,name = "l2"; + qcom,local-resource-type; + qcom,init-value = "l2_cache_retention"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,use-qtimer; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <1>; + qcom,ss-power = <784>; + qcom,energy-overhead = <190000>; + qcom,time-overhead = <100>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "retention"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <75>; + qcom,ss-power = <735>; + qcom,energy-overhead = <77341>; + qcom,time-overhead = <105>; + }; + + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <95>; + qcom,ss-power = <725>; + qcom,energy-overhead = <99500>; + qcom,time-overhead = <130>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_gdhs"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <2000>; + qcom,ss-power = <138>; + qcom,energy-overhead = <1208400>; + qcom,time-overhead = <3200>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3000>; + qcom,ss-power = <110>; + qcom,energy-overhead = <1250300>; + qcom,time-overhead = <3500>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_gdhs"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <3000>; + qcom,ss-power = <68>; + qcom,energy-overhead = <1350200>; + qcom,time-overhead = <4000>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <10300>; + qcom,ss-power = <63>; + qcom,energy-overhead = <2128000>; + qcom,time-overhead = <18200>; + }; + + qcom,lpm-level@7 { + reg = <0x7>; + qcom,mode= "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,latency-us = <18000>; + qcom,ss-power = <10>; + qcom,energy-overhead = <3202600>; + qcom,time-overhead = <27000>; + }; + + qcom,lpm-level@8 { + reg = <0x8>; + qcom,mode= "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <675000>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <20000>; + qcom,ss-power = <2>; + qcom,energy-overhead = <4252000>; + qcom,time-overhead = <32000>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <2 216>, /* tsens_upper_lower_int */ + <47 165>, /* usb30_hs_phy_irq */ + <50 172>, /* usb1_hs_async_wakeup_irq */ + <53 104>, /* mdss_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_low */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr + + <0xff 188>, /* lpass_irq_out_apcs(0) */ + <0xff 189>, /* lpass_irq_out_apcs(1) */ + <0xff 190>, /* lpass_irq_out_apcs(2) */ + <0xff 191>, /* lpass_irq_out_apcs(3) */ + <0xff 192>, /* lpass_irq_out_apcs(4) */ + <0xff 193>, /* lpass_irq_out_apcs(5) */ + <0xff 194>, /* lpass_irq_out_apcs(6) */ + <0xff 195>, /* lpass_irq_out_apcs(7) */ + <0xff 196>, /* lpass_irq_out_apcs(8) */ + <0xff 197>, /* lpass_irq_out_apcs(9) */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <3 102>, + <4 1 >, + <5 5 >, + <6 9 >, + <7 18>, + <8 20>, + <9 24>, + <10 27>, + <11 28>, + <12 34>, + <13 35>, + <14 37>, + <15 42>, + <16 44>, + <17 46>, + <18 50>, + <19 54>, + <20 59>, + <21 61>, + <22 62>, + <23 64>, + <24 65>, + <25 66>, + <26 67>, + <27 68>, + <28 71>, + <29 72>, + <30 73>, + <31 74>, + <32 75>, + <33 77>, + <34 79>, + <35 80>, + <36 82>, + <37 86>, + <38 92>, + <39 93>, + <40 95>, + <41 144>; + }; + + qcom,pm-8x60@fe805664 { + compatible = "qcom,pm-8x60"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfe805664 0x40>; + qcom,pc-mode = "tz_l2_int"; + qcom,use-sync-timer; + }; + + qcom,cpu-sleep-status@f9088008 { + compatible = "qcom,cpu-sleep-status"; + reg = <0xf9088008 0x4>; + qcom,cpu-alias-addr = <0x10000>; + qcom,sleep-status-mask= <0x80000>; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-rumi.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-rumi.dts new file mode 100644 index 000000000..85aab17b1 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-rumi.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-rumi.dtsi" + +/ { + model = "Qualcomm MSM 8974 RUMI"; + compatible = "qcom,msm8974-rumi", "qcom,msm8974", "qcom,rumi"; + qcom,msm-id = <126 15 0>, + <185 15 0>, + <186 15 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-sim.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-sim.dts new file mode 100644 index 000000000..fc9858de7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1-sim.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-sim.dtsi" + +/ { + model = "Qualcomm MSM 8974 Simulator"; + compatible = "qcom,msm8974-sim", "qcom,msm8974", "qcom,sim"; + qcom,msm-id = <126 16 0>, + <185 16 0>, + <186 16 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1.dtsi new file mode 100644 index 000000000..caec2dc1b --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v1.dtsi @@ -0,0 +1,134 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8974.dtsi file. + */ + +/include/ "msm8974.dtsi" +/include/ "msm8974-v1-iommu.dtsi" +/include/ "msm8974-v1-iommu-domains.dtsi" +/include/ "msm8974-v1-pm.dtsi" + +&soc { + android_usb@fc42b0c8 { + compatible = "qcom,android-usb"; + reg = <0xfc42b0c8 0xc8>; + qcom,android-usb-swfi-latency = <1>; + }; + + qcom,msm-imem@fc42b000 { + compatible = "qcom,msm-imem"; + reg = <0xfc42b000 0x1000>; /* Address and size of IMEM */ + }; +}; + +&tsens { + qcom,calibration-less-mode; +}; + +/* I2C clock frequency overrides */ +&i2c_0 { + qcom,i2c-src-freq = <19200000>; +}; + +&i2c_2 { + qcom,i2c-src-freq = <19200000>; +}; + +/* CoreSight */ +&tmc_etr { + qcom,reset-flush-race; +}; + +&stm { + qcom,write-64bit; +}; + +&mdss_mdp { + qcom,mdss-pingpong-off = <0x00021B00 0x00021C00 0x00021D00>; +}; + +&msm_vidc { + qcom,vidc-cp-map = <0x1000000 0x3f000000>; + qcom,vidc-ns-map = <0x40000000 0x40000000>; + qcom,load-freq-tbl = <979200 410000000>, + <783360 410000000>, + <489600 266670000>, + <244800 133330000>; + qcom,reg-presets = <0x80004 0x1>, + <0x80178 0x00001FFF>, + <0x8017c 0x1FFF1FFF>, + <0x800b0 0x10101001>, + <0x800b4 0x10101010>, + <0x800b8 0x10101010>, + <0x800bc 0x00000010>, + <0x800c0 0x1010100f>, + <0x800c4 0x10101010>, + <0x800c8 0x10101010>, + <0x800cc 0x00000010>, + <0x800d0 0x00001010>, + <0x800d4 0x00001010>, + <0x800f0 0x00000030>, + <0x800d8 0x00000707>, + <0x800dc 0x00000707>, + <0x80124 0x00000001>, + <0xE0020 0x5555556>, + <0xE0024 0x0>; + qcom,bus-ports = <1>; + qcom,enc-ocmem-ab-ib = <0 0>, + <138200 1222000>, + <414700 1222000>, + <940000 2444000>, + <1880000 2444000>, + <3008000 3910400>, + <3760000 4888000>; + qcom,dec-ocmem-ab-ib = <0 0>, + <176900 1556640>, + <456200 1556640>, + <864800 1556640>, + <1729600 3113280>, + <2767360 4981248>, + <3459200 6226560>; + qcom,enc-ddr-ab-ib = <0 0>, + <60000 664950>, + <181000 664950>, + <403000 664950>, + <806000 1329900>, + <1289600 2127840>, + <161200 6400000>; + qcom,dec-ddr-ab-ib = <0 0>, + <110000 909000>, + <268000 909000>, + <505000 909000>, + <1010000 1818000>, + <1616000 2908800>, + <2020000 6400000>; + qcom,iommu-groups = <&venus_domain_ns &venus_domain_cp>; + qcom,iommu-group-buffer-types = <0xfff 0x1ff>; + qcom,buffer-type-tz-usage-table = <0x1 0x1>, + <0x1fe 0x2>; +}; + +&sfpb_spinlock { + status = "disable"; +}; + +&ldrex_spinlock { + status = "ok"; +}; + +&usb_otg { + qcom,hsusb-otg-pnoc-errata-fix; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-cdp.dts new file mode 100644 index 000000000..85d478b73 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-cdp.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v2.dtsi" +/include/ "msm8974-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8974v2 CDP"; + compatible = "qcom,msm8974-cdp", "qcom,msm8974", "qcom,cdp"; + qcom,msm-id = <126 1 0x20000>, + <185 1 0x20000>, + <186 1 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-fluid.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-fluid.dts new file mode 100644 index 000000000..d83d13048 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-fluid.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v2.dtsi" +/include/ "msm8974-fluid.dtsi" + +/ { + model = "Qualcomm MSM 8974v2 FLUID"; + compatible = "qcom,msm8974-fluid", "qcom,msm8974", "qcom,fluid"; + qcom,msm-id = <126 3 0x20000>, + <185 3 0x20000>, + <186 3 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-iommu-domains.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-iommu-domains.dtsi new file mode 100644 index 000000000..01c94d0ec --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-iommu-domains.dtsi @@ -0,0 +1,45 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,iommu-domains { + compatible = "qcom,iommu-domains"; + + venus_domain_ns: qcom,iommu-domain1 { + label = "venus_ns"; + qcom,iommu-contexts = <&venus_ns>; + qcom,virtual-addr-pool = <0x5dc00000 0x7f000000 + 0xdcc00000 0x1000000>; + }; + + venus_domain_sec_bitstream: qcom,iommu-domain2 { + label = "venus_sec_bitstream"; + qcom,iommu-contexts = <&venus_sec_bitstream>; + qcom,virtual-addr-pool = <0x4b000000 0x12c00000>; + qcom,secure-domain; + }; + + venus_domain_sec_pixel: qcom,iommu-domain3 { + label = "venus_sec_pixel"; + qcom,iommu-contexts = <&venus_sec_pixel>; + qcom,virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-domain; + }; + + venus_domain_sec_non_pixel: qcom,iommu-domain4 { + label = "venus_sec_non_pixel"; + qcom,iommu-contexts = <&venus_sec_non_pixel>; + qcom,virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-domain; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-iommu.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-iommu.dtsi new file mode 100644 index 000000000..03f7e807e --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-iommu.dtsi @@ -0,0 +1,256 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm-iommu-v1.dtsi" + +&venus_iommu { + status = "ok"; + vdd-supply = <&gdsc_venus>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020 + 0x2024 + 0x2028 + 0x202c + 0x2030 + 0x2034 + 0x2038>; + + qcom,iommu-bfb-data = <0xFFFFFFFF + 0xFFFFFFFF + 0x00000004 + 0x00000008 + 0x00000000 + 0x00013205 + 0x00004000 + 0x00014020 + 0x0 + 0x94 + 0x114 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; + + venus_ns: qcom,iommu-ctx@fdc8c000 { + qcom,iommu-ctx-sids = <0 1 2 3 4 5 7>; + }; + + venus_sec_bitstream: qcom,iommu-ctx@fdc8d000 { + qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84>; + label = "venus_sec_bitstream"; + }; + + venus_sec_pixel: qcom,iommu-ctx@fdc8f000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc8f000 0x1000>; + interrupts = <0 42 0>, <0 43 0>; + qcom,iommu-ctx-sids = <0x85>; + label = "venus_sec_pixel"; + qcom,secure-context; + }; + + venus_sec_non_pixel: qcom,iommu-ctx@fdc90000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc90000 0x1000>; + interrupts = <0 42 0>, <0 43 0>; + qcom,iommu-ctx-sids = <0x87 0xA0>; + label = "venus_sec_non_pixel"; + qcom,secure-context; + }; +}; + +&jpeg_iommu { + status = "ok"; + vdd-supply = <&gdsc_jpeg>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014>; + + qcom,iommu-bfb-data = <0x3FFF + 0x00000000 + 0x4 + 0x4 + 0x0 + 0x0 + 0x10 + 0x50 + 0x0 + 0x00002804 + 0x00009614 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&mdp_iommu { + status = "ok"; + vdd-supply = <&gdsc_mdss>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xFFFFF + 0x00000000 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00006800 + 0x00006221 + 0x00016231 + 0x0 + 0x34 + 0x74 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&kgsl_iommu { + status = "ok"; + vdd-supply = <&gdsc_oxili_cx>; + qcom,alt-vdd-supply = <&gdsc_oxili_gx>; + qcom,iommu-enable-halt; + qcom,needs-alt-core-clk; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008>; + + qcom,iommu-bfb-data = <0x00000003 + 0x0 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000020 + 0x0 + 0x1 + 0x81 + 0x0>; +}; + +&vfe_iommu { + status = "ok"; + vdd-supply = <&gdsc_vfe>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x00000000 + 0x4 + 0x8 + 0x0 + 0x0 + 0x20 + 0x78 + 0x0 + 0x00003c08 + 0x0000b41e + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-liquid.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-liquid.dts new file mode 100644 index 000000000..53983dc1c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-liquid.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v2.dtsi" +/include/ "msm8974-liquid.dtsi" + +/ { + model = "Qualcomm MSM 8974v2 LIQUID"; + compatible = "qcom,msm8974-liquid", "qcom,msm8974", "qcom,liquid"; + qcom,msm-id = <126 9 0x20000>, + <185 9 0x20000>, + <186 9 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-mtp.dts new file mode 100644 index 000000000..792a78cbd --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-mtp.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v2.dtsi" +/include/ "msm8974-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8974v2 MTP"; + compatible = "qcom,msm8974-mtp", "qcom,msm8974", "qcom,mtp"; + qcom,msm-id = <126 8 0x20000>, + <185 8 0x20000>, + <186 8 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; + +&pm8941_chg { + qcom,bpd-detection = "bpd_thm"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-pm.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-pm.dtsi new file mode 100644 index 000000000..8a46724ae --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2-pm.dtsi @@ -0,0 +1,452 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f9099000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,core-id = <1>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f90a9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,core-id = <2>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f90b9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,core-id = <3>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f9012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9012000 0x1000>; + qcom,core-id = <0xffff>; /* L2/APCS SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-pmic-data0 = <0x02030080>; + qcom,saw2-pmic-data1 = <0x00030000>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + qcom,saw2-spm-cmd-ret = [1f 00 03 00 0f]; + qcom,saw2-spm-cmd-gdhs = [00 32 42 07 44 50 02 32 50 0f]; + qcom,saw2-spm-cmd-pc = [00 32 b0 11 42 07 01 b0 44 + 50 02 32 50 0f]; + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x62706d73>; /* "smpb" */ + qcom,id = <0x02>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <6>; /* Super Turbo */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x62706d73>; /* "smpb" */ + qcom,id = <0x01>; + qcom,key = <0x7675>; /* "uv" */ + qcom,init-value = <1050000>; /* Super Turbo */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + + qcom,lpm-resources@3 { + reg = <0x3>; + qcom,name = "l2"; + qcom,local-resource-type; + qcom,init-value = "l2_cache_retention"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,use-qtimer; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <1>; + qcom,ss-power = <715>; + qcom,energy-overhead = <17700>; + qcom,time-overhead = <2>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "retention"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <35>; + qcom,ss-power = <542>; + qcom,energy-overhead = <34920>; + qcom,time-overhead = <40>; + }; + + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <300>; + qcom,ss-power = <476>; + qcom,energy-overhead = <225300>; + qcom,time-overhead = <350>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_gdhs"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <2817>; + qcom,ss-power = <163>; + qcom,energy-overhead = <1577736>; + qcom,time-overhead = <5067>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3922>; + qcom,ss-power = <83>; + qcom,energy-overhead = <2274420>; + qcom,time-overhead = <6605>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <4922>; + qcom,ss-power = <68>; + qcom,energy-overhead = <2568180>; + qcom,time-overhead = <8812>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode= "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,latency-us = <5890>; + qcom,ss-power = <60>; + qcom,energy-overhead = <2675900>; + qcom,time-overhead = <10140>; + }; + + qcom,lpm-level@7 { + reg = <0x7>; + qcom,mode= "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <675000>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <8500>; + qcom,ss-power = <18>; + qcom,energy-overhead = <3286600>; + qcom,time-overhead = <15760>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <2 216>, /* tsens_upper_lower_int */ + <47 165>, /* usb30_hs_phy_irq */ + <50 172>, /* usb1_hs_async_wakeup_irq */ + <53 104>, /* mdss_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_low */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr + + <0xff 188>, /* lpass_irq_out_apcs(0) */ + <0xff 189>, /* lpass_irq_out_apcs(1) */ + <0xff 190>, /* lpass_irq_out_apcs(2) */ + <0xff 191>, /* lpass_irq_out_apcs(3) */ + <0xff 192>, /* lpass_irq_out_apcs(4) */ + <0xff 193>, /* lpass_irq_out_apcs(5) */ + <0xff 194>, /* lpass_irq_out_apcs(6) */ + <0xff 195>, /* lpass_irq_out_apcs(7) */ + <0xff 196>, /* lpass_irq_out_apcs(8) */ + <0xff 197>, /* lpass_irq_out_apcs(9) */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <3 102>, + <4 1 >, + <5 5 >, + <6 9 >, + <7 18>, + <8 20>, + <9 24>, + <10 27>, + <11 28>, + <12 34>, + <13 35>, + <14 37>, + <15 42>, + <16 44>, + <17 46>, + <18 50>, + <19 54>, + <20 59>, + <21 61>, + <22 62>, + <23 64>, + <24 65>, + <25 66>, + <26 67>, + <27 68>, + <28 71>, + <29 72>, + <30 73>, + <31 74>, + <32 75>, + <33 77>, + <34 79>, + <35 80>, + <36 82>, + <37 86>, + <38 92>, + <39 93>, + <40 95>, + <41 144>; + }; + + qcom,pm-8x60@fe805664 { + compatible = "qcom,pm-8x60"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfe805664 0x40>; + qcom,pc-mode = "tz_l2_int"; + qcom,use-sync-timer; + + qcom,pm-snoc-client { + compatible = "qcom,pm-snoc-client"; + qcom,msm-bus,name = "ocimem_snoc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <54 585 0 0>, + <54 585 0 800000>; + }; + }; + + qcom,cpu-sleep-status@f9088008{ + compatible = "qcom,cpu-sleep-status"; + reg = <0xf9088008 0x100>; + qcom,cpu-alias-addr = <0x10000>; + qcom,sleep-status-mask= <0x80000>; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2.dtsi new file mode 100644 index 000000000..96e78ac28 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974-v2.dtsi @@ -0,0 +1,138 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8974.dtsi file. + */ + +/include/ "msm8974.dtsi" +/include/ "msm8974-v2-iommu.dtsi" +/include/ "msm8974-v2-iommu-domains.dtsi" +/include/ "msm8974-v2-pm.dtsi" + +&soc { + android_usb@fe8050c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8050c8 0xc8>; + qcom,android-usb-swfi-latency = <1>; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; +}; + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x03030001>; + + /* Updated bus bandwidth requirements */ + qcom,msm-bus,vectors-KBps = + /* Off */ + <26 512 0 0>, <89 604 0 0>, + /* SVS */ + <26 512 0 2400000>, <89 604 0 3000000>, + /* Nominal / SVS */ + <26 512 0 4656000>, <89 604 0 3000000>, + /* Nominal */ + <26 512 0 4656000>, <89 604 0 5120000>, + /* Turbo / Nominal */ + <26 512 0 7464000>, <89 604 0 5120000>, + /* Turbo */ + <26 512 0 7464000>, <89 604 0 6400000>; +}; + +&mdss_mdp { + qcom,vbif-settings = <0x0004 0x00000001>; + + qcom,mdss-wb-off = <0x00011100 0x00011500 + 0x00011900 0x00011D00 0x00012100>; + qcom,mdss-intf-off = <0x00012500 0x00012700 + 0x00012900 0x00012b00>; + qcom,mdss-pingpong-off = <0x00012D00 0x00012E00 0x00012F00>; + qcom,mdss-has-bwc; + qcom,mdss-has-decimation; + qcom,mdss-ad-off = <0x0013100 0x00013300>; +}; + +&mdss_hdmi_tx { + reg = <0xfd922100 0x370>, + <0xfd922500 0x7C>, + <0xfc4b8000 0x60F0>; + reg-names = "core_physical", "phy_physical", "qfprom_physical"; +}; + +&msm_vidc { + qcom,vidc-ns-map = <0x40000000 0x40000000>; + qcom,load-freq-tbl = <979200 465000000>, + <783360 465000000>, + <489600 266670000>, + <244800 133330000>; + qcom,reg-presets = <0x80004 0x1>, + <0x80070 0x11FFF>, + <0x80074 0xA4>, + <0x800A8 0x1FFF>, + <0x80124 0x3>, + <0xE0020 0x5555556>, + <0xE0024 0x0>; + qcom,bus-ports = <1>; + qcom,enc-ocmem-ab-ib = <0 0>, + <138000 1034000>, + <414000 1034000>, + <940000 1034000>, + <1880000 2068000>, + <3008000 3309000>, + <3760000 4136000>, + <4468000 2457000>; + qcom,dec-ocmem-ab-ib = <0 0>, + <176000 519000>, + <456000 519000>, + <864000 519000>, + <1728000 1038000>, + <2766000 1661000>, + <3456000 2076000>, + <3662000 2198000>; + qcom,enc-ddr-ab-ib = <0 0>, + <120000 302000>, + <364000 302000>, + <804000 302000>, + <1608000 604000>, + <2576000 967000>, + <4680000 1404000>, + <49880000 1496000>; + qcom,dec-ddr-ab-ib = <0 0>, + <208000 303000>, + <536000 303000>, + <1012000 303000>, + <2024000 606000>, + <3240000 970000>, + <4048000 1212000>, + <4264000 1279000>; + qcom,iommu-groups = <&venus_domain_ns &venus_domain_sec_bitstream + &venus_domain_sec_pixel &venus_domain_sec_non_pixel>; + qcom,iommu-group-buffer-types = <0xfff 0x91 0x42 0x120>; + qcom,buffer-type-tz-usage-table = <0x91 0x1>, + <0x42 0x2>, + <0x120 0x3>; +}; + +&krait_pdn { + qcom,use-phase-switching; +}; + +&tspp { + vdd_cx-supply = <&pm8841_s2_corner>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974.dtsi new file mode 100644 index 000000000..6f164912e --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm8974.dtsi @@ -0,0 +1,1745 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM 8974"; + compatible = "qcom,msm8974"; + interrupt-parent = <&intc>; + + aliases { + spi0 = &spi_0; + spi7 = &spi_7; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + sdhc3 = &sdhc_3; /* SDC3 SDIO slot */ + sdhc4 = &sdhc_4; /* SDC4 SDIO slot */ + + /* smdtty devices */ + smd1 = &smdtty_apps_fm; + smd2 = &smdtty_apps_riva_bt_acl; + smd3 = &smdtty_apps_riva_bt_cmd; + smd4 = &smdtty_mbalbridge; + smd5 = &smdtty_apps_riva_ant_cmd; + smd6 = &smdtty_apps_riva_ant_data; + smd7 = &smdtty_data1; + smd11 = &smdtty_data11; + smd21 = &smdtty_data21; + smd27 = &smdtty_gps_nmea; + smd36 = &smdtty_loopback; + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0x0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0x1>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0x2>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0x3>; + }; + }; + + memory { + secure_mem: secure_region { + linux,contiguous-region; + reg = <0 0xFC00000>; + label = "secure_mem"; + }; + + adsp_mem: adsp_region { + linux,contiguous-region; + reg = <0 0x2F00000>; + label = "adsp_mem"; + }; + + qsecom_mem: qsecom_region { + linux,contiguous-region; + reg = <0 0x1100000>; + label = "qseecom_mem"; + }; + + }; + + soc: soc { }; +}; + +/include/ "msm8974-camera.dtsi" +/include/ "msm8974-coresight.dtsi" +/include/ "msm-gdsc.dtsi" +/include/ "msm8974-ion.dtsi" +/include/ "msm8974-gpu.dtsi" +/include/ "msm8974-mdss.dtsi" +/include/ "msm8974-smp2p.dtsi" +/include/ "msm8974-bus.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@F9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <146>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + wcd9xxx_intc: wcd9xxx-irq { + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&msmgpio>; + interrupts = <72 0>; + interrupt-names = "cdc-int"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + + qcom,mpm2-sleep-counter@fc4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xfc4a3000 0x1000>; + clock-frequency = <32768>; + }; + + msm_vidc: qcom,vidc@fdc00000 { + compatible = "qcom,msm-vidc"; + reg = <0xfdc00000 0xff000>; + interrupts = <0 44 0>; + qcom,hfi = "venus"; + qcom,has-ocmem; + qcom,max-hw-load = <1224450>; /* 4k @ 30 + 1080p @ 30*/ + }; + + qcom,vidc { + compatible = "qcom,msm-vidc"; + qcom,hfi = "q6"; + qcom,max-hw-load = <108000>; /* 720p @ 30 */ + }; + + qcom,wfd { + compatible = "qcom,msm-wfd"; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + serial@f995e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf995e000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + }; + + serial@f991e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991e000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + + qcom,msm-bus,name = "serial_uart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + }; + + usb_otg: usb@f9a55000 { + compatible = "qcom,hsusb-otg"; + status = "disabled"; + + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0 0 140 0>; + interrupt-names = "core_irq", "async_irq"; + HSUSB_VDDCX-supply = <&pm8841_s2_corner>; + HSUSB_1p8-supply = <&pm8941_l6>; + HSUSB_3p3-supply = <&pm8941_l24>; + qcom,vdd-voltage-level = <1 5 7>; + + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-phy-init-seq = <0x63 0x81 0xffffffff>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <1>; + qcom,hsusb-otg-disable-reset; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 60000 960000>; + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>, + <0xf9824800 0x100>, + <0xf9804000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 123 0>, <0 137 0>; + interrupt-names = "core_irq", "bam_irq"; + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <8>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + qcom,msm-bus,name = "sdcc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1600 3200>, /* 400 KB/s*/ + <78 512 80000 160000>, /* 20 MB/s */ + <78 512 100000 200000>, /* 25 MB/s */ + <78 512 200000 400000>, /* 50 MB/s */ + <78 512 400000 800000>, /* 100 MB/s */ + <78 512 800000 1600000>, /* 200 MB/s */ + <78 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + qcom,dat1-mpm-int = <42>; + status = "disable"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>, + <0xf98a4800 0x100>, + <0xf9884000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 125 0>, <0 220 0>; + interrupt-names = "core_irq", "bam_irq"; + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <4>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + qcom,msm-bus,name = "sdcc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1600 3200>, /* 400 KB/s*/ + <81 512 80000 160000>, /* 20 MB/s */ + <81 512 100000 200000>, /* 25 MB/s */ + <81 512 200000 400000>, /* 50 MB/s */ + <81 512 400000 800000>, /* 100 MB/s */ + <81 512 800000 1600000>, /* 200 MB/s */ + <81 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + qcom,dat1-mpm-int = <44>; + status = "disable"; + }; + + sdcc3: qcom,sdcc@f9864000 { + cell-index = <3>; /* SDC3 SDIO slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9864000 0x800>, + <0xf9864800 0x100>, + <0xf9844000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + #address-cells = <0>; + interrupt-parent = <&sdcc3>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 127 0 + 1 &intc 0 223 0 + 2 &msmgpio 37 0x8>; + interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq"; + + gpios = <&msmgpio 40 0>, /* CLK */ + <&msmgpio 39 0>, /* CMD */ + <&msmgpio 38 0>, /* DATA0 */ + <&msmgpio 37 0>, /* DATA1 */ + <&msmgpio 36 0>, /* DATA2 */ + <&msmgpio 35 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>; + qcom,sup-voltages = <1800 1800>; + qcom,bus-width = <4>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50"; + + qcom,msm-bus,name = "sdcc3"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */ + <79 512 1600 3200>, /* 400 KB/s*/ + <79 512 80000 160000>, /* 20 MB/s */ + <79 512 100000 200000>, /* 25 MB/s */ + <79 512 200000 400000>, /* 50 MB/s */ + <79 512 400000 800000>, /* 100 MB/s */ + <79 512 800000 1600000>, /* 200 MB/s */ + <79 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdcc4: qcom,sdcc@f98e4000 { + cell-index = <4>; /* SDC4 SDIO slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98e4000 0x800>, + <0xf98e4800 0x100>, + <0xf98c4000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + #address-cells = <0>; + interrupt-parent = <&sdcc4>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 129 0 + 1 &intc 0 226 0 + 2 &msmgpio 95 0x8>; + interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq"; + + gpios = <&msmgpio 93 0>, /* CLK */ + <&msmgpio 91 0>, /* CMD */ + <&msmgpio 96 0>, /* DATA0 */ + <&msmgpio 95 0>, /* DATA1 */ + <&msmgpio 94 0>, /* DATA2 */ + <&msmgpio 92 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>; + qcom,sup-voltages = <1800 1800>; + qcom,bus-width = <4>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50"; + + qcom,msm-bus,name = "sdcc4"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <80 512 0 0>, /* No vote */ + <80 512 1600 3200>, /* 400 KB/s*/ + <80 512 80000 160000>, /* 20 MB/s */ + <80 512 100000 200000>, /* 25 MB/s */ + <80 512 200000 400000>, /* 50 MB/s */ + <80 512 400000 800000>, /* 100 MB/s */ + <80 512 800000 1600000>, /* 200 MB/s */ + <80 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdhc_1: sdhci@f9824900 { + qcom,bus-width = <8>; + compatible = "qcom,sdhci-msm"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,cpu-dma-latency-us = <200>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1600 3200>, /* 400 KB/s*/ + <78 512 80000 160000>, /* 20 MB/s */ + <78 512 100000 200000>, /* 25 MB/s */ + <78 512 200000 400000>, /* 50 MB/s */ + <78 512 400000 800000>, /* 100 MB/s */ + <78 512 800000 1600000>, /* 200 MB/s */ + <78 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <200>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1600 3200>, /* 400 KB/s*/ + <81 512 80000 160000>, /* 20 MB/s */ + <81 512 100000 200000>, /* 25 MB/s */ + <81 512 200000 400000>, /* 50 MB/s */ + <81 512 400000 800000>, /* 100 MB/s */ + <81 512 800000 1600000>, /* 200 MB/s */ + <81 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdhc_3: sdhci@f9864900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 127 0>, <0 224 0>; + interrupt-names = "hc_irq", "pwr_irq"; + gpios = <&msmgpio 40 0>, /* CLK */ + <&msmgpio 39 0>, /* CMD */ + <&msmgpio 38 0>, /* DATA0 */ + <&msmgpio 37 0>, /* DATA1 */ + <&msmgpio 36 0>, /* DATA2 */ + <&msmgpio 35 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <200>; + + qcom,msm-bus,name = "sdhc3"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */ + <79 512 1600 3200>, /* 400 KB/s*/ + <79 512 80000 160000>, /* 20 MB/s */ + <79 512 100000 200000>, /* 25 MB/s */ + <79 512 200000 400000>, /* 50 MB/s */ + <79 512 400000 800000>, /* 100 MB/s */ + <79 512 800000 1600000>, /* 200 MB/s */ + <79 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdhc_4: sdhci@f98e4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf98e4900 0x11c>, <0xf98e4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 129 0>, <0 227 0>; + interrupt-names = "hc_irq", "pwr_irq"; + gpios = <&msmgpio 93 0>, /* CLK */ + <&msmgpio 91 0>, /* CMD */ + <&msmgpio 96 0>, /* DATA0 */ + <&msmgpio 95 0>, /* DATA1 */ + <&msmgpio 94 0>, /* DATA2 */ + <&msmgpio 92 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <200>; + + qcom,msm-bus,name = "sdhc4"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <80 512 0 0>, /* No vote */ + <80 512 1600 3200>, /* 400 KB/s*/ + <80 512 80000 160000>, /* 20 MB/s */ + <80 512 100000 200000>, /* 25 MB/s */ + <80 512 200000 400000>, /* 50 MB/s */ + <80 512 400000 800000>, /* 100 MB/s */ + <80 512 800000 1600000>, /* 200 MB/s */ + <80 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + qcom,sps@f9980000 { + compatible = "qcom,msm_sps"; + reg = <0xf9984000 0x15000>, + <0xf9999000 0xb000>; + interrupts = <0 94 0>; + + qcom,bam-dma-res-pipes = <6>; + }; + + spi_7: spi_epm: spi@f9966000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9966000 0x1000>; + interrupts = <0 104 0>; + spi-max-frequency = <19200000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 56 0>, /* CLK */ + <&msmgpio 54 0>, /* MISO */ + <&msmgpio 53 0>; /* MOSI */ + cs-gpios = <&msmgpio 55 0>; + qcom,master-id = <84>; + }; + + tspp: msm_tspp@f99d8000 { + compatible = "qcom,msm_tspp"; + cell-index = <0>; + reg = <0xf99d8000 0x1000>, /* MSM_TSIF0_PHYS */ + <0xf99d9000 0x1000>, /* MSM_TSIF1_PHYS */ + <0xf99da000 0x1000>, /* MSM_TSPP_PHYS */ + <0xf99c4000 0x14000>; /* MSM_TSPP_BAM_PHYS */ + reg-names = "MSM_TSIF0_PHYS", + "MSM_TSIF1_PHYS", + "MSM_TSPP_PHYS", + "MSM_TSPP_BAM_PHYS"; + interrupts = <0 153 0>, /* TSIF_TSPP_IRQ */ + <0 151 0>, /* TSIF0_IRQ */ + <0 152 0>, /* TSIF1_IRQ */ + <0 154 0>; /* TSIF_BAM_IRQ */ + interrupt-names = "TSIF_TSPP_IRQ", + "TSIF0_IRQ", + "TSIF1_IRQ", + "TSIF_BAM_IRQ"; + qcom,tsif-pclk = "iface_clk"; + qcom,tsif-ref-clk = "ref_clk"; + gpios = <&msmgpio 89 0>, /* TSIF0 CLK */ + <&msmgpio 90 0>, /* TSIF0 EN */ + <&msmgpio 91 0>, /* TSIF0 DATA */ + <&msmgpio 92 0>, /* TSIF0 SYNC */ + <&msmgpio 93 0>, /* TSIF1 CLK */ + <&msmgpio 94 0>, /* TSIF1 EN */ + <&msmgpio 95 0>, /* TSIF1 DATA */ + <&msmgpio 96 0>; /* TSIF1 SYNC */ + qcom,gpio-names = "tsif_clk", + "tsif_en", + "tsif_data", + "tsif_sync", + "tsif_clk", + "tsif_en", + "tsif_data", + "tsif_sync"; + qcom,gpios-func = <1>; + + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <82 512 0 0>, /* No vote */ + <82 512 12288 24576>; /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ + }; + + slim_msm: slim@fe12f000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xfe12f000 0x35000>, + <0xfe104000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0 0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + + taiko_codec { + compatible = "qcom,taiko-slim-pgd"; + elemental-addr = [00 01 A0 00 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,cdc-reset-gpio = <&msmgpio 63 0>; + + cdc-vdd-buck-supply = <&pm8941_s2>; + qcom,cdc-vdd-buck-voltage = <2150000 2150000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-vdd-tx-h-supply = <&pm8941_s3>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8941_s3>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pm8941_s3>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-a-1p2v-supply = <&pm8941_l1>; + qcom,cdc-vdd-a-1p2v-voltage = <1225000 1225000>; + qcom,cdc-vdd-a-1p2v-current = <10000>; + + cdc-vddcx-1-supply = <&pm8941_l1>; + qcom,cdc-vddcx-1-voltage = <1225000 1225000>; + qcom,cdc-vddcx-1-current = <10000>; + + cdc-vddcx-2-supply = <&pm8941_l1>; + qcom,cdc-vddcx-2-voltage = <1225000 1225000>; + qcom,cdc-vddcx-2-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1", + "cdc-vdd-a-1p2v", + "cdc-vddcx-1", + "cdc-vddcx-2"; + + qcom,cdc-micbias-ldoh-v = <0x3>; + qcom,cdc-micbias-cfilt1-mv = <1800>; + qcom,cdc-micbias-cfilt2-mv = <2700>; + qcom,cdc-micbias-cfilt3-mv = <1800>; + qcom,cdc-micbias1-cfilt-sel = <0x0>; + qcom,cdc-micbias2-cfilt-sel = <0x1>; + qcom,cdc-micbias3-cfilt-sel = <0x2>; + qcom,cdc-micbias4-cfilt-sel = <0x2>; + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "taiko-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 00 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + }; + }; + + sound { + compatible = "qcom,msm8974-audio-taiko"; + qcom,model = "msm8974-taiko-snd-card"; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "AIF4 MAD", "MCLK", + "AMIC1", "MIC BIAS1 Internal1", + "MIC BIAS1 Internal1", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC2", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic2", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4", + "DMIC5", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic5", + "DMIC6", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic6"; + + qcom,cdc-mclk-gpios = <&pm8941_gpios 15 0>; + qcom,taiko-mclk-clk-freq = <9600000>; + qcom,prim-auxpcm-gpio-clk = <&msmgpio 65 0>; + qcom,prim-auxpcm-gpio-sync = <&msmgpio 66 0>; + qcom,prim-auxpcm-gpio-din = <&msmgpio 67 0>; + qcom,prim-auxpcm-gpio-dout = <&msmgpio 68 0>; + qcom,prim-auxpcm-gpio-set = "prim-gpio-prim"; + qcom,sec-auxpcm-gpio-clk = <&msmgpio 79 0>; + qcom,sec-auxpcm-gpio-sync = <&msmgpio 80 0>; + qcom,sec-auxpcm-gpio-din = <&msmgpio 81 0>; + qcom,sec-auxpcm-gpio-dout = <&msmgpio 82 0>; + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0 0 187 0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + i2c_0: i2c@f9967000 { /* BLSP#11 */ + cell-index = <0>; + compatible = "qcom,i2c-qup"; + reg = <0Xf9967000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 105 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <50000000>; + qcom,master-id = <84>; + }; + + i2c_1: i2c@f9923000 { + cell-index = <1>; + compatible = "qcom,i2c-qup"; + reg = <0xf9923000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 95 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + qcom,scl-gpio = <&msmgpio 3 0>; + qcom,sda-gpio = <&msmgpio 2 0>; + qcom,master-id = <86>; + status = "disabled"; + }; + + i2c_2: i2c@f9924000 { + cell-index = <2>; + compatible = "qcom,i2c-qup"; + reg = <0xf9924000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 96 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <50000000>; + qcom,master-id = <86>; + }; + + spi_0: spi@f9923000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 0>; + spi-max-frequency = <19200000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 3 0>, /* CLK */ + <&msmgpio 1 0>, /* MISO */ + <&msmgpio 0 0>; /* MOSI */ + cs-gpios = <&msmgpio 9 0>; + qcom,master-id = <86>; + }; + + qcom,acpuclk@f9000000 { + compatible = "qcom,acpuclk-8974"; + krait0-supply = <&krait0_vreg>; + krait1-supply = <&krait1_vreg>; + krait2-supply = <&krait2_vreg>; + krait3-supply = <&krait3_vreg>; + krait0_mem-supply = <&pm8841_s1_ao>; + krait1_mem-supply = <&pm8841_s1_ao>; + krait2_mem-supply = <&pm8841_s1_ao>; + krait3_mem-supply = <&pm8841_s1_ao>; + krait0_dig-supply = <&pm8841_s2_corner_ao>; + krait1_dig-supply = <&pm8841_s2_corner_ao>; + krait2_dig-supply = <&pm8841_s2_corner_ao>; + krait3_dig-supply = <&pm8841_s2_corner_ao>; + krait0_hfpll-supply = <&pm8941_l12_ao>; + krait1_hfpll-supply = <&pm8941_l12_ao>; + krait2_hfpll-supply = <&pm8941_l12_ao>; + krait3_hfpll-supply = <&pm8941_l12_ao>; + l2_hfpll-supply = <&pm8941_l12_ao>; + }; + + usb3: qcom,ssusb@f9200000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xf9200000 0xfc000>, + <0xfd4ab000 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupts = <0 133 0>; + interrupt-names = "hs_phy_irq"; + ssusb_vdd_dig-supply = <&pm8841_s2_corner>; + SSUSB_1p8-supply = <&pm8941_l6>; + hsusb_vdd_dig-supply = <&pm8841_s2_corner>; + HSUSB_1p8-supply = <&pm8941_l6>; + HSUSB_3p3-supply = <&pm8941_l24>; + vbus_dwc3-supply = <&pm8941_mvs1>; + qcom,dwc-usb3-msm-dbm-eps = <4>; + qcom,vdd-voltage-level = <1 5 7>; + qcom,dwc-hsphy-init = <0x00D195A4>; + + qcom,msm-bus,name = "usb3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <61 512 0 0>, + <61 512 240000 960000>; + dwc3@f9200000 { + compatible = "synopsys,dwc3"; + reg = <0xf9200000 0xfc000>; + interrupt-parent = <&intc>; + interrupts = <0 131 0>, <0 179 0>; + interrupt-names = "irq", "otg_irq"; + tx-fifo-resize; + }; + }; + + ehci: qcom,ehci-host@f9a55000 { + compatible = "qcom,ehci-host"; + status = "disabled"; + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0>, <0 140 0>; + interrupt-names = "core_irq", "async_irq"; + HSUSB_VDDCX-supply = <&pm8841_s2>; + HSUSB_1p8-supply = <&pm8941_l6>; + HSUSB_3p3-supply = <&pm8941_l24>; + qcom,usb2-enable-hsphy2; + qcom,usb2-power-budget = <500>; + }; + + gdsc_oxili_gx: qcom,gdsc@fd8c4024 { + parent-supply = <&pm8841_s4_corner>; + }; + + qcom,lpass@fe200000 { + compatible = "qcom,pil-q6v5-lpass"; + reg = <0xfe200000 0x00100>, + <0xfd485100 0x00010>, + <0xfc4016c0 0x00004>; + reg-names = "qdsp6_base", "halt_base", "restart_reg"; + vdd_cx-supply = <&pm8841_s2_corner>; + interrupts = <0 162 1>; + + qcom,firmware-name = "adsp"; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + }; + + qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + }; + + qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + qcom,msm-pcm-lpa { + compatible = "qcom,msm-pcm-lpa"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + }; + + qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + qcom,msm-dai-q6-hdmi { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <8>; + }; + + qcom,msm-lsm-client { + compatible = "qcom,msm-lsm-client"; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + qcom,msm-dai-q6-sb-0-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16384>; + }; + + qcom,msm-dai-q6-sb-0-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16385>; + }; + + qcom,msm-dai-q6-sb-1-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16386>; + }; + + qcom,msm-dai-q6-sb-1-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16387>; + }; + + qcom,msm-dai-q6-sb-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16388>; + }; + + qcom,msm-dai-q6-sb-2-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16389>; + }; + + qcom,msm-dai-q6-sb-3-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16390>; + }; + + qcom,msm-dai-q6-sb-3-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16391>; + }; + + qcom,msm-dai-q6-sb-4-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16392>; + }; + + qcom,msm-dai-q6-sb-4-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16393>; + }; + + qcom,msm-dai-q6-sb-5-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16395>; + }; + + qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + qcom,msm-auxpcm { + compatible = "qcom,msm-auxpcm-resource"; + qcom,msm-cpudai-auxpcm-clk = "pcm_clk"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-slot = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + + qcom,msm-prim-auxpcm-rx { + qcom,msm-auxpcm-dev-id = <4106>; + compatible = "qcom,msm-auxpcm-dev"; + }; + + qcom,msm-prim-auxpcm-tx { + qcom,msm-auxpcm-dev-id = <4107>; + compatible = "qcom,msm-auxpcm-dev"; + }; + + qcom,msm-sec-auxpcm-rx { + qcom,msm-auxpcm-dev-id = <4108>; + compatible = "qcom,msm-auxpcm-dev"; + }; + + qcom,msm-sec-auxpcm-tx { + qcom,msm-auxpcm-dev-id = <4109>; + compatible = "qcom,msm-auxpcm-dev"; + }; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + qcom,msm-dai-q6-mi2s-quat { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <3>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <2>; + }; + }; + + qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + qcom,msm-ocmem-audio { + compatible = "qcom,msm-ocmem-audio"; + qcom,msm-bus,name = "audio-ocmem"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <11 604 0 0>, + <11 604 32506 32506>; + }; + + qcom,msm-adsp-sensors { + compatible = "qcom,msm-adsp-sensors"; + qcom,src-id = <11>; + qcom,dst-id = <604>; + qcom,ab = <32505856>; + qcom,ib = <32505856>; + }; + + qcom,mss@fc880000 { + compatible = "qcom,pil-q6v5-mss"; + reg = <0xfc880000 0x100>, + <0xfd485000 0x400>, + <0xfc820000 0x020>, + <0xfc401680 0x004>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg"; + + interrupts = <0 24 1>; + vdd_mss-supply = <&pm8841_s3>; + vdd_cx-supply = <&pm8841_s2_corner>; + vdd_mx-supply = <&pm8841_s1>; + vdd_pll-supply = <&pm8941_l12>; + qcom,vdd_pll = <1800000>; + qcom,firmware-name = "mba"; + qcom,pil-self-auth; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + qcom,pronto@fb21b000 { + compatible = "qcom,pil-pronto"; + reg = <0xfb21b000 0x3000>, + <0xfc401700 0x4>, + <0xfd485300 0xc>; + reg-names = "pmu_base", "clk_base", "halt_base"; + interrupts = <0 149 1>; + vdd_pronto_pll-supply = <&pm8941_l12>; + + qcom,firmware-name = "wcnss"; + + /* GPIO inputs from wcnss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>; + + /* GPIO output to wcnss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>; + }; + + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + + qcom,wcnss-wlan@fb000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xfb000000 0x280000>, + <0xf9011008 0x04>; + reg-names = "wcnss_mmio", "wcnss_fiq"; + interrupts = <0 145 0 0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8841_s1>; + qcom,pronto-vddcx-supply = <&pm8841_s2>; + qcom,pronto-vddpx-supply = <&pm8941_s3>; + qcom,iris-vddxo-supply = <&pm8941_l6>; + qcom,iris-vddrfa-supply = <&pm8941_l11>; + qcom,iris-vddpa-supply = <&pm8941_l19>; + qcom,iris-vdddig-supply = <&pm8941_l3>; + + gpios = <&msmgpio 36 0>, <&msmgpio 37 0>, <&msmgpio 38 0>, <&msmgpio 39 0>, <&msmgpio 40 0>; + qcom,has-48mhz-xo; + qcom,has-pronto-hw; + }; + + qcom,ocmem@fdd00000 { + compatible = "qcom,msm-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfdd02000 0x2000>, + <0xfe039000 0x400>, + <0xfec00000 0x180000>; + reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical"; + interrupts = <0 76 0 0 77 0>; + interrupt-names = "ocmem_irq", "dm_irq"; + qcom,ocmem-num-regions = <0x3>; + qcom,ocmem-num-macros = <0x18>; + qcom,resource-type = <0x706d636f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfec00000 0x180000>; + + partition@0 { + reg = <0x0 0x100000>; + qcom,ocmem-part-name = "graphics"; + qcom,ocmem-part-min = <0x80000>; + }; + + partition@80000 { + reg = <0x100000 0x80000>; + qcom,ocmem-part-name = "lp_audio"; + qcom,ocmem-part-min = <0x80000>; + }; + + partition@100000 { + reg = <0x100000 0x80000>; + qcom,ocmem-part-name = "video"; + qcom,ocmem-part-min = <0x55000>; + }; + + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,msm-rng@f9bff000 { + compatible = "qcom,msm-rng"; + reg = <0xf9bff000 0x200>; + }; + + qseecom: qcom,qseecom@7f00000 { + compatible = "qcom,qseecom"; + reg = <0x7f00000 0x500000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <1>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + }; + + qcom,tz-log@fe805720 { + compatible = "qcom,tz-log"; + reg = <0xfe805720 0x1000>; + }; + + qcom,venus@fdce0000 { + compatible = "qcom,pil-venus"; + reg = <0xfdce0000 0x4000>, + <0xfdc80000 0x400>; + reg-names = "wrapper_base", "vbif_base"; + vdd-supply = <&gdsc_venus>; + + qcom,firmware-name = "venus"; + }; + + qcom,cache_erp@f9012000 { + reg = <0xf9012000 0x80>, + <0xf9089000 0x80>, + <0xf9099000 0x80>, + <0xf90a9000 0x80>, + <0xf90b9000 0x80>, + <0xf9088000 0x40>, + <0xf9098000 0x40>, + <0xf90a8000 0x40>, + <0xf90b8000 0x40>; + + reg-names = "l2_saw", + "krait0_saw", + "krait1_saw", + "krait2_saw", + "krait3_saw", + "krait0_acs", + "krait1_acs", + "krait2_acs", + "krait3_acs"; + + compatible = "qcom,cache_erp"; + interrupts = <1 9 0>, <0 2 0>; + interrupt-names = "l1_irq", "l2_irq"; + }; + + qcom,cache_dump { + compatible = "qcom,cache_dump"; + qcom,l1-dump-size = <0x100000>; + qcom,l2-dump-size = <0x500000>; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x600000>; /* 6M EBI1 buffer */ + }; + + tsens: tsens@fc4a8000 { + compatible = "qcom,msm-tsens"; + reg = <0xfc4a8000 0x2000>, + <0xfc4b8000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + qcom,sensors = <11>; + qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200 + 3200 3200>; + qcom,calib-mode = "fuse_map1"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + qcom,msm-contig-mem { + compatible = "qcom,msm-contig-mem"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x280000>; /* 2.5M EBI1 buffer */ + }; + + qcom,qcedev@fd440000 { + compatible = "qcom,qcedev"; + reg = <0xfd440000 0x20000>, + <0xfd444000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 236 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <1>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <56 512 0 0>, + <56 512 3936000 393600>; + }; + + qcom,qcrypto@fd444000 { + compatible = "qcom,qcrypto"; + reg = <0xfd440000 0x20000>, + <0xfd444000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 236 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <1>; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <56 512 0 0>, + <56 512 3936000 393600>; + }; + + qcom,usbbam@f9304000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xf9304000 0x5000>, + <0xf9a44000 0x11000>, + <0xf92f880c 0x4>; + reg-names = "ssusb", "hsusb", "qscratch_ram1_reg"; + interrupts = <0 132 0 0 135 0>; + interrupt-names = "ssusb", "hsusb"; + qcom,usb-bam-num-pipes = <16>; + qcom,usb-bam-fifo-baseaddr = <0xf9200000>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <1>; + qcom,bam-type = <0>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37C000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9304000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0xf0000>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0xf4000>; + qcom,descriptor-fifo-size = <0x1400>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe1 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <1>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37c000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0xf4000>; + qcom,data-fifo-size = <0x1000>; + qcom,descriptor-fifo-offset = <0xf5000>; + qcom,descriptor-fifo-size = <0x400>; + }; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <5>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-control-mask = <0xf>; + qcom,core-limit-temp = <80>; + qcom,core-temp-hysteresis = <10>; + qcom,core-control-mask = <0xe>; + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + qcom,pmic-sw-mode-temp = <85>; + qcom,pmic-sw-mode-temp-hysteresis = <75>; + qcom,pmic-sw-mode-regs = "vdd_dig"; + vdd_dig-supply = <&pm8841_s2_floor_corner>; + vdd_gfx-supply = <&pm8841_s4_floor_corner>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd_dig"; + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + qcom,vdd-gfx-rstr{ + qcom,vdd-rstr-reg = "vdd_gfx"; + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + qcom,vdd-apps-rstr{ + qcom,vdd-rstr-reg = "vdd_apps"; + qcom,levels = <1881600 1958400 2265600>; + qcom,freq-req; + }; + }; + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + qcom,rx-ring-size = <64>; + }; + + memory_hole: qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x7f00000 0x8000000>; /* Address and Size of Hole */ + }; + + uart7: uart@f995d000 { /*BLSP #2, UART #7 */ + compatible = "qcom,msm-hsuart-v14"; + status = "disabled"; + reg = <0xf995d000 0x1000>, + <0xf9944000 0x19000>; + reg-names = "core_mem", "bam_mem"; + interrupts = <0 113 0>, <0 239 0>; + interrupt-names = "core_irq", "bam_irq"; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,msm-bus,name = "uart7"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <84 512 0 0>, + <84 512 500 800>; + }; + + qcom,smem@fa00000 { + compatible = "qcom,smem"; + reg = <0xfa00000 0x200000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1000>; + qcom,pil-string = "modem"; + interrupts = <0 25 1>; + }; + + qcom,smsm-modem { + compatible = "qcom,smsm"; + qcom,smsm-edge = <0>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x2000>; + interrupts = <0 26 1>; + }; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-wcnss { + compatible = "qcom,smd"; + qcom,smd-edge = <6>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x20000>; + qcom,pil-string = "wcnss"; + interrupts = <0 142 1>; + }; + + qcom,smsm-wcnss { + compatible = "qcom,smsm"; + qcom,smsm-edge = <6>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x80000>; + interrupts = <0 144 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; + + qcom,bcl { + compatible = "qcom,bcl"; + }; + + qcom,ssm { + compatible = "qcom,ssm"; + qcom,channel-name = "SSM_RTR"; + }; + + sfpb_spinlock: qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + ldrex_spinlock: qcom,ipc-spinlock@fa00000 { + compatible = "qcom,ipc-spinlock-ldrex"; + reg = <0xfa00000 0x200000>; + status = "disable"; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + qcom,irq-is-percpu; + interrupts = <1 7 0xf00>; + }; + + l2-pmu { + compatible = "qcom,l2-pmu"; + interrupts = <0 1 0>; + }; + + qcom,smdtty { + compatible = "qcom,smdtty"; + + smdtty_apps_fm: qcom,smdtty-apps-fm { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_FM"; + }; + + smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; + }; + + smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; + }; + + smdtty_mbalbridge: qcom,smdtty-mbalbridge { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "MBALBRIDGE"; + }; + + smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; + }; + + smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; + }; + + smdtty_data1: qcom,smdtty-data1 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA1"; + }; + + smdtty_data11: qcom,smdtty-data11 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA11"; + }; + + smdtty_data21: qcom,smdtty-data21 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA21"; + }; + + smdtty_gps_nmea: smdtty-gpsnmea { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "GPSNMEA"; + }; + + smdtty_loopback: smdtty-loopback { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "LOOPBACK"; + qcom,smdtty-dev-name = "LOOPBACK_TTY"; + }; + }; +}; + +&gdsc_venus { + qcom,clock-names = "core_clk"; + qcom,skip-logic-collapse; + status = "ok"; +}; + +&gdsc_mdss { + qcom,clock-names = "core_clk", "lut_clk"; + qcom,retain-periph; + status = "ok"; +}; + +&gdsc_jpeg { + qcom,clock-names = "core0_clk", "core1_clk", "core2_clk"; + status = "ok"; +}; + +&gdsc_vfe { + qcom,clock-names = "core0_clk", "core1_clk", "csi0_clk", "csi1_clk", + "cpp_clk"; + status = "ok"; +}; + +&gdsc_oxili_gx { + qcom,clock-names = "core_clk"; + qcom,retain-mem; + qcom,retain-periph; + status = "ok"; +}; + +&gdsc_oxili_cx { + status = "ok"; +}; + +&gdsc_usb_hsic { + status = "ok"; +}; + +/include/ "msm-pm8x41-rpm-regulator.dtsi" +/include/ "msm-pm8841.dtsi" +/include/ "msm-pm8941.dtsi" +/include/ "msm8974-regulator.dtsi" +/include/ "msm8974-clock.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-cdp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-cdp.dtsi new file mode 100644 index 000000000..6ddb50b82 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-cdp.dtsi @@ -0,0 +1,100 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm9625-display.dtsi" +/include/ "qpic-panel-ili-qvga.dtsi" + +&soc { + i2c@f9925000 { + charger@57 { + compatible = "summit,smb137c"; + reg = <0x57>; + summit,chg-current-ma = <1500>; + summit,term-current-ma = <50>; + summit,pre-chg-current-ma = <100>; + summit,float-voltage-mv = <4200>; + summit,thresh-voltage-mv = <3000>; + summit,recharge-thresh-mv = <75>; + summit,system-voltage-mv = <4250>; + summit,charging-timeout = <382>; + summit,pre-charge-timeout = <48>; + summit,therm-current-ua = <10>; + summit,temperature-min = <4>; /* 0 C */ + summit,temperature-max = <3>; /* 45 C */ + }; + }; + + wlan0: qca,wlan { + cell-index = <0>; + compatible = "qca,ar6004-hsic"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; + + qca,wlan_ar6003 { + cell-index = <0>; + compatible = "qca,ar6003-sdio"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; +}; + +/* PM8019 GPIO and MPP configuration */ +&pm8019_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + /* ext_2p95v regulator enable config */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS */ + qcom,invert = <0>; /* Output low */ + qcom,out-strength = <1>; /* Low */ + qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */ + qcom,src-sel = <0>; /* Constant */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; +}; + +&pm8019_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-coresight.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-coresight.dtsi new file mode 100644 index 000000000..3c00ae8c2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-coresight.dtsi @@ -0,0 +1,259 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@fc322000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc322000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x20000>; /* 128K EBI1 buffer */ + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + }; + + tpiu: tpiu@fc318000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc318000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + vdd-supply = <&ext_2p95v>; + }; + + replicator: replicator@fc31c000 { + compatible = "qcom,coresight-replicator"; + reg = <0xfc31c000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + }; + + tmc_etf: tmc@fc307000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc307000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + }; + + funnel_merg: funnel@fc31b000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31b000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc319000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc319000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + funnel_in1: funnel@fc31a000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31a000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <6>; + coresight-name = "coresight-funnel-in1"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <1>; + }; + + stm: stm@fc321000 { + compatible = "arm,coresight-stm"; + reg = <0xfc321000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <7>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc332000 { + compatible = "arm,coresight-etm"; + reg = <0xfc332000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <8>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <4>; + + qcom,round-robin; + }; + + csr: csr@fc302000 { + compatible = "qcom,coresight-csr"; + reg = <0xfc302000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <9>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <1>; + }; + + cti0: cti@fc308000 { + compatible = "arm,coresight-cti"; + reg = <0xfc308000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <10>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + }; + + cti1: cti@fc309000 { + compatible = "arm,coresight-cti"; + reg = <0xfc309000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <11>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + cti2: cti@fc30a000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30a000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <12>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + }; + + cti3: cti@fc30b000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30b000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <13>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + }; + + cti4: cti@fc30c000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30c000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <14>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + }; + + cti5: cti@fc30d000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30d000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + }; + + cti6: cti@fc30e000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30e000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + }; + + cti7: cti@fc30f000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30f000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + }; + + cti8: cti@fc310000 { + compatible = "arm,coresight-cti"; + reg = <0xfc310000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <18>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + }; + + cti_cpu: cti@fc333000 { + compatible = "arm,coresight-cti"; + reg = <0xfc333000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <19>; + coresight-name = "coresight-cti-cpu"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@f9011038 { + compatible = "qcom,coresight-hwevent"; + reg = <0xf9011038 0x8>, + <0xfd4ab160 0x80>; + reg-names = "apcs-mux", "ppss-mux"; + + coresight-id = <20>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-display.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-display.dtsi new file mode 100644 index 000000000..287a63aef --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-display.dtsi @@ -0,0 +1,20 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm_qpic@f9ac0000 { + compatible = "qcom,mdss_qpic"; + reg = <0xf9ac0000 0x24000>; + reg-names = "qpic_base"; + interrupts = <0 251 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-ion.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-ion.dtsi new file mode 100644 index 000000000..6f9bb535d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-ion.dtsi @@ -0,0 +1,35 @@ +/* Copyright (c) 2012-2013, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + qcom,ion-heap@28 { /* AUDIO HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <28>; + qcom,heap-align = <0x1000>; + qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */ + qcom,memory-reservation-size = <0xE9000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-mtp.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-mtp.dtsi new file mode 100755 index 000000000..b2908c42b --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-mtp.dtsi @@ -0,0 +1,111 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + i2c@f9925000 { + }; + + wlan0: qca,wlan { + cell-index = <0>; + compatible = "qca,ar6004-hsic"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; + + qca,wlan_ar6003 { + cell-index = <0>; + compatible = "qca,ar6003-sdio"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; + + mp2617 { + cell-index = <0>; + compatible = "mps,mp2617"; + mps,chg-current-ma = <1000>; + mps,chg-vbat-div = <3>; /* Divided by 3 before input */ + mps,chg-en-gpio = <&msmgpio 13 0>; /* refer to board-9625-gpiomux.c */ + mps,chg-ok-gpio = <&msmgpio 71 0>; + mps,chg-m0-gpio = <&msmgpio 12 0>; + mps,chg-m1-gpio = <&msmgpio 17 0>; + }; +}; + +/* PM8019 GPIO and MPP configuration */ +&pm8019_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + /* ext_2p95v regulator enable config */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS */ + qcom,invert = <0>; /* Output low */ + qcom,out-strength = <1>; /* Low */ + qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */ + qcom,src-sel = <0>; /* Constant */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; +}; + +&pm8019_mpps { + mpp@a000 { /* MPP 1 */ + }; + + /* [linyunfeng] Detect battery voltage */ + mpp@a100 { /* MPP 2 */ + /* channel 17 */ + qcom,mode = <4>; + qcom,ain-route = <1>; /* AMUX 6 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + /* VADC channel 19 */ + qcom,mode = <4>; + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + /* channel 21 */ + qcom,mode = <4>; + qcom,ain-route = <1>; /* AMUX 6 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-pm.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-pm.dtsi new file mode 100644 index 000000000..673b64053 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-pm.dtsi @@ -0,0 +1,299 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9009000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9009000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x101>; + qcom,saw2-spm-dly= <0>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [04 03 04 0f]; + qcom,saw2-spm-cmd-spc = [34 04 44 14 24 54 03 54 44 14 04 24 + 3e 0f]; + qcom,saw2-spm-cmd-pc = [34 04 44 14 24 54 07 54 44 14 04 24 + 3e 0f]; + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x616F646C>; /* "ldoa" */ + qcom,id = <0x0A>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <5>; /* Super Turbo */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x616F646C>; /* "ldoa" */ + qcom,id = <0x0C>; + qcom,key = <0x7675>; /* "uv" */ + qcom,init-value = <1050000>; /* Super Turbo */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,use-qtimer; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <100>; + qcom,ss-power = <8000>; + qcom,energy-overhead = <100000>; + qcom,time-overhead = <1>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <2000>; + qcom,ss-power = <5000>; + qcom,energy-overhead = <60100000>; + qcom,time-overhead = <3000>; + }; + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_gdhs"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3500>; + qcom,ss-power = <5000>; + qcom,energy-overhead = <60350000>; + qcom,time-overhead = <6300>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <4500>; + qcom,ss-power = <5000>; + qcom,energy-overhead = <60350000>; + qcom,time-overhead = <7300>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,latency-us = <6800>; + qcom,ss-power = <2000>; + qcom,energy-overhead = <71850000>; + qcom,time-overhead = <13300>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,latency-us = <8000>; + qcom,ss-power = <1800>; + qcom,energy-overhead = <71950000>; + qcom,time-overhead = <15300>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <675000>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <9800>; + qcom,ss-power = <0>; + qcom,energy-overhead = <76350000>; + qcom,time-overhead = <28300>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <2 216>, /* tsens_upper_lower_int */ + <47 172>, /* usb2_hsic_async_wakeup_irq */ + <41 180>, /* usb_async_wakeup_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_lo */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr */ + <0xff 188>, /* q6ss_irq_out(4) */ + <0xff 189>, /* q6ss_irq_out(5) */ + <0xff 190>, /* q6ss_irq_out(6) */ + <0xff 191>, /* q6ss_irq_out(7) */ + <0xff 192>, /* audio_out0_irq */ + <0xff 193>, /* midi_arm_irq */ + <0xff 194>, /* q6ss_wdog_exp_irq */ + <0xff 195>, /* slimbus_core_ee1_irq */ + <0xff 196>, /* bam_irq(1) */ + <0xff 197>, /* qdss_irq_out(7) */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <4 0>, + <5 1>, + <6 2>, + <7 3>, + <8 4>, + <9 5>, + <10 6>, + <11 7>, + <12 8>, + <13 9>, + <14 10>, + <15 11>, + <16 12>, + <17 13>, + <18 14>, + <19 15>, + <20 16>, + <21 17>, + <22 18>, + <23 19>, + <24 20>, + <25 21>, + <26 24>, + <27 25>, + <28 51>, + <29 61>, + <30 62>, + <31 63>, + <32 64>, + <33 65>, + <34 66>, + <35 67>, + <36 69>, + <37 71>; + }; + + qcom,pm-8x60 { + compatible = "qcom,pm-8x60"; + qcom,pc-mode = "tz_l2_ext"; + qcom,use-sync-timer; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-regulator.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-regulator.dtsi new file mode 100644 index 000000000..eb56d1c6a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-regulator.dtsi @@ -0,0 +1,284 @@ +/* Copyright (c) 2012-2013, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa1 { + status = "okay"; + pm8019_s1: regulator-s1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1050000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa2 { + status = "okay"; + pm8019_s2: regulator-s2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + qcom,init-voltage = <1250000>; + qcom,init-current = <100>; + qcom,system-load = <100000>; + regulator-always-on; + status = "okay"; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8019_s3: regulator-s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + qcom,init-voltage = <1100000>; + qcom,init-current = <100>; + qcom,system-load = <100000>; + regulator-always-on; + status = "okay"; + }; + pm8019_s3_ao: regulator-s3-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_s3_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8019_s4: regulator-s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2075000>; + qcom,init-voltage = <2075000>; + qcom,init-current = <100>; + qcom,system-load = <100000>; + regulator-always-on; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8019_l1: regulator-l1 { + parent-supply = <&pm8019_s2>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8019_l2: regulator-l2 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8019_l3: regulator-l3 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8019_l4: regulator-l4 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8019_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8019_l6: regulator-l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8019_l7: regulator-l7 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8019_l8: regulator-l8 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8019_l9: regulator-l9 { + parent-supply = <&pm8019_s2>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-current = <10>; + qcom,system-load = <10000>; + regulator-always-on; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8019_l10: regulator-l10 { + parent-supply = <&pm8019_s3>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8019_l10_corner: regulator-l10-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l10_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + status = "okay"; + qcom,consumer-supplies = "vdd_dig", ""; + }; + pm8019_l10_corner_ao: regulator-l10-corner-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l10_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + status = "okay"; + }; + pm8019_l10_floor_corner: regulator-l10-floor-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l10_floor_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-floor-corner; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8019_l11: regulator-l11 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-current = <10>; + qcom,system-load = <10000>; + regulator-always-on; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8019_l12: regulator-l12 { + parent-supply = <&pm8019_s3>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8019_l12_ao: regulator-l12-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l12_ao"; + qcom,set = <1>; + parent-supply = <&pm8019_s3_ao>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8019_l12_so: regulator-l12-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l12_so"; + qcom,set = <2>; + parent-supply = <&pm8019_s3>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <675000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8019_l13: regulator-l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8019_l14: regulator-l14 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <2700000>; + status = "okay"; + }; + }; +}; + +&soc { + ext_2p95v: regulator-isl80101 { + compatible = "regulator-fixed"; + regulator-name = "ext_2p95v"; + gpio = <&pm8019_gpios 4 0>; + enable-active-high; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-smp2p.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-smp2p.dtsi new file mode 100644 index 000000000..f8ad351a4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-smp2p.dtsi @@ -0,0 +1,142 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-cdp.dts new file mode 100644 index 000000000..d7537eb35 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-cdp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v1.dtsi" +/include/ "msm9625-cdp.dtsi" + +/ { + model = "Qualcomm MSM 9625V1 CDP"; + compatible = "qcom,msm9625-cdp", "qcom,msm9625", "qcom,cdp"; + qcom,msm-id = <134 1 0>, <152 1 0>, <149 1 0>, <150 1 0>, + <151 1 0>, <148 1 0>, <173 1 0>, <174 1 0>, + <175 1 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-mtp.dts new file mode 100644 index 000000000..a70ec1aa7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-mtp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v1.dtsi" +/include/ "msm9625-mtp.dtsi" + +/ { + model = "Qualcomm MSM 9625V1 MTP"; + compatible = "qcom,msm9625-mtp", "qcom,msm9625", "qcom,mtp"; + qcom,msm-id = <134 7 0>, <152 7 0>, <149 7 0>, <150 7 0>, + <151 7 0>, <148 7 0>, <173 7 0>, <174 7 0>, + <175 7 0>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-rumi.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-rumi.dts new file mode 100644 index 000000000..ef0068143 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1-rumi.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v1.dtsi" + +/ { + model = "Qualcomm MSM 9625V1 RUMI"; + compatible = "qcom,msm9625-rumi", "qcom,msm9625", "qcom,rumi"; + qcom,msm-id = <134 15 0>; + + chosen{ + bootargs = "root=/dev/ram rw init=/init console=ttyHSL0,115200n8 initrd=0x00000000,0x00000000 mem=29M@0x00200000 mem=10M@0x07600000"; + + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1.dtsi new file mode 100644 index 000000000..b238ba549 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v1.dtsi @@ -0,0 +1,67 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm9625.dtsi file. + */ + +/include/ "msm9625.dtsi" + +&soc { + qcom,msm-imem@fc42a800 { + compatible = "qcom,msm-imem"; + reg = <0xfc42a800 0x1000>; /* Address and size of IMEM */ + }; + + android_usb@fc42a8c8 { + compatible = "qcom,android-usb"; + reg = <0xfc42a8c8 0xc8>; + qcom,android-usb-swfi-latency = <100>; + }; + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + }; +}; + +&hsic_host { + qcom,disable-park-mode; +}; + +&ipa_hw { + qcom,ipa-hw-ver = <1>; /* IPA h-w revision */ +}; + +/* CoreSight */ +&tmc_etr { + qcom,reset-flush-race; +}; + +&stm { + qcom,write-64bit; +}; + +&sfpb_spinlock { + status = "disable"; +}; + +&ldrex_spinlock { + status = "ok"; +}; + +&hsic_host { + qcom,phy-sof-workaround; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2-cdp.dts new file mode 100644 index 000000000..9fbe5ec8a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2-cdp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v2.dtsi" +/include/ "msm9625-cdp.dtsi" + +/ { + model = "Qualcomm MSM 9625V2 CDP"; + compatible = "qcom,msm9625-cdp", "qcom,msm9625", "qcom,cdp"; + qcom,msm-id = <134 1 0x20000>, <152 1 0x20000>, <149 1 0x20000>, + <150 1 0x20000>, <151 1 0x20000>, <148 1 0x20000>, + <173 1 0x20000>, <174 1 0x20000>, <175 1 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2-mtp.dts new file mode 100644 index 000000000..27d00664a --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2-mtp.dts @@ -0,0 +1,122 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v2.dtsi" +/include/ "msm9625-mtp.dtsi" + +/ { + model = "Qualcomm MSM 9625V2 MTP"; + compatible = "qcom,msm9625-mtp", "qcom,msm9625", "qcom,mtp"; + qcom,msm-id = <134 7 0x20000>, <152 7 0x20000>, <149 7 0x20000>, + <150 7 0x20000>, <151 7 0x20000>, <148 7 0x20000>, + <173 7 0x20000>, <174 7 0x20000>, <175 7 0x20000>; +}; + +&soc { + i2c@f9925000 { + charger@57 { + compatible = "summit,smb137c"; + reg = <0x57>; + summit,chg-current-ma = <1500>; + summit,term-current-ma = <50>; + summit,pre-chg-current-ma = <100>; + summit,float-voltage-mv = <4200>; + summit,thresh-voltage-mv = <3000>; + summit,recharge-thresh-mv = <75>; + summit,system-voltage-mv = <4250>; + summit,charging-timeout = <382>; + summit,pre-charge-timeout = <48>; + summit,therm-current-ua = <10>; + summit,temperature-min = <4>; /* 0 C */ + summit,temperature-max = <3>; /* 45 C */ + }; + }; + + wlan0: qca,wlan { + cell-index = <0>; + compatible = "qca,ar6004-hsic"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; + + qca,wlan_ar6003 { + cell-index = <0>; + compatible = "qca,ar6003-sdio"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; +}; + +/* PM8019 GPIO and MPP configuration */ +&pm8019_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + /* ext_2p95v regulator enable config */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS */ + qcom,invert = <0>; /* Output low */ + qcom,out-strength = <1>; /* Low */ + qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */ + qcom,src-sel = <0>; /* Constant */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; +}; + +&pm8019_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + /* VADC channel 19 */ + qcom,mode = <4>; + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + /* channel 21 */ + qcom,mode = <4>; + qcom,ain-route = <1>; /* AMUX 6 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1-cdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1-cdp.dts new file mode 100644 index 000000000..b64359381 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1-cdp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v2.1.dtsi" +/include/ "msm9625-cdp.dtsi" + +/ { + model = "Qualcomm MSM 9625V2.1 CDP"; + compatible = "qcom,msm9625-cdp", "qcom,msm9625", "qcom,cdp"; + qcom,msm-id = <134 1 0x20001>, <152 1 0x20001>, <149 1 0x20001>, + <150 1 0x20001>, <151 1 0x20001>, <148 1 0x20001>, + <173 1 0x20001>, <174 1 0x20001>, <175 1 0x20001>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1-mtp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1-mtp.dts new file mode 100644 index 000000000..8bbcc0d55 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1-mtp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v2.1.dtsi" +/include/ "msm9625-mtp.dtsi" + +/ { + model = "Qualcomm MSM 9625V2.1 MTP"; + compatible = "qcom,msm9625-mtp", "qcom,msm9625", "qcom,mtp"; + qcom,msm-id = <134 7 0x20001>, <152 7 0x20001>, <149 7 0x20001>, + <150 7 0x20001>, <151 7 0x20001>, <148 7 0x20001>, + <173 7 0x20001>, <174 7 0x20001>, <175 7 0x20001>; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1.dtsi new file mode 100644 index 000000000..5720700e3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.1.dtsi @@ -0,0 +1,40 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm9625.dtsi file. + */ + +/include/ "msm9625.dtsi" + +&soc { + qcom,msm-imem@fe807800 { + compatible = "qcom,msm-imem"; + reg = <0xfe807800 0x1000>; /* Address and size of IMEM */ + }; + + android_usb@fe8078c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8078c8 0xc8>; + qcom,android-usb-swfi-latency = <100>; + }; +}; + +&ipa_hw { + qcom,ipa-hw-ver = <2>; /* IPA h-w revision */ +}; + +&hsusb_otg { + qcom,hsusb-l1-supported; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.dtsi new file mode 100644 index 000000000..3eda3f896 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625-v2.dtsi @@ -0,0 +1,54 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm9625.dtsi file. + */ + +/include/ "msm9625.dtsi" + +&soc { + qcom,msm-imem@fe807800 { + compatible = "qcom,msm-imem"; + reg = <0xfe807800 0x1000>; /* Address and size of IMEM */ + }; + + android_usb@fe8078c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8078c8 0xc8>; + qcom,android-usb-swfi-latency = <100>; + }; +}; + +&ipa_hw { + qcom,ipa-hw-ver = <2>; /* IPA h-w revision */ +}; + +&hsic_host { + qcom,disable-park-mode; + qcom,phy-susp-sof-workaround; + qcom,phy-reset-sof-workaround; +}; + +&sfpb_spinlock { + status = "disable"; +}; + +&ldrex_spinlock { + status = "ok"; +}; + +&hsusb_otg { + qcom,hsusb-l1-supported; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625.dtsi new file mode 100755 index 000000000..e57b976e8 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msm9625.dtsi @@ -0,0 +1,895 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM 9625"; + compatible = "qcom,msm9625"; + interrupt-parent = <&intc>; + + aliases { + spi0 = &spi_0; + }; + + soc: soc { }; +}; + +/include/ "msm9625-ion.dtsi" +/include/ "msm9625-pm.dtsi" +/include/ "msm9625-coresight.dtsi" +/include/ "msm9625-smp2p.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@F9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + l2: cache-controller@f9040000 { + compatible = "arm,pl310-cache"; + reg = <0xf9040000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <76>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + qcom,mpm2-sleep-counter@fc4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xfc4a3000 0x1000>; + clock-frequency = <32768>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + + frame@f9029000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0xf9029000 0x1000>; + status = "disabled"; + }; + }; + + qcom,sps@f9980000 { + compatible = "qcom,msm_sps"; + reg = <0xf9984000 0x15000>, + <0xf9999000 0xb000>, + <0xfe803000 0x4800>; + interrupts = <0 94 0>; + qcom,device-type = <2>; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + qcom,msm-bus,name = "blsp1_uart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + }; + + hsusb_otg: usb@f9a55000 { + compatible = "qcom,hsusb-otg"; + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0 0 140 0>; + interrupt-names = "core_irq", "async_irq"; + HSUSB_VDDCX-supply = <&pm8019_l12>; + HSUSB_1p8-supply = <&pm8019_l2>; + HSUSB_3p3-supply = <&pm8019_l4>; + vbus_otg-supply = <&usb_vbus>; + + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <1>; + qcom,hsusb-otg-disable-reset; + qcom,hsusb-otg-delay-lpm-hndshk-on-disconnect; + qcom,hsusb-otg-delay-lpm; + qcom,hsusb-otg-mpm-dpsehv-int = <49>; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 40000 640000>; + qcom,hsusb-log2-itc = <4>; + }; + + hsic_host: hsic@f9a15000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a15000 0x400>; + interrupts = <0 136 0>, <0 148 0>; + interrupt-names = "core_irq", "async_irq"; + HSIC_VDDCX-supply = <&pm8019_l12>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 640000>; + qcom,pool-64-bit-align; + qcom,enable-hbm; + hsic,consider-ipa-handshake; + qcom,ahb-async-bridge-bypass; + hsic,disable-cerr; + qcom,disable-internal-clk-gating; + }; + + qcom,usbbam@f9a44000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xf9a44000 0x11000>, + <0xf9a04000 0x11000>; + reg-names = "hsusb", "hsic"; + interrupts = <0 135 0 0 255 0>; + interrupt-names = "hsusb", "hsic"; + qcom,usb-bam-num-pipes = <16>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + + qcom,pipe0 { + label = "hsusb-ipa-out-0"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <0>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a44000>; + qcom,src-bam-pipe-index = <1>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + qcom,pipe1 { + label = "hsusb-ipa-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + qcom,pipe2 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <0>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37c000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x4100>; + qcom,data-fifo-size = <0x700>; + qcom,descriptor-fifo-offset = <0x4000>; + qcom,descriptor-fifo-size = <0x100>; + }; + qcom,pipe3 { + label = "hsic-ipa-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a04000>; + qcom,dst-bam-pipe-index = <3>; + qcom,data-fifo-size = <0xF800>; + qcom,descriptor-fifo-size = <0x3A58>; + qcom,reset-bam-on-connect; + }; + qcom,pipe4 { + label = "hsic-ipa-in-1"; + qcom,bam-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <1>; + qcom,peer-bam = <2>; + qcom,usb-bam-mem-type = <2>; + qcom,dst-bam-physical-address = <0xf9a04000>; + qcom,dst-bam-pipe-index = <4>; + qcom,data-fifo-size = <0xF800>; + qcom,descriptor-fifo-size = <0x3A58>; + qcom,reset-bam-on-connect; + }; + qcom,pipe5 { + label = "hsic-ipa-in-2"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <2>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a04000>; + qcom,dst-bam-pipe-index = <5>; + qcom,data-fifo-size = <0xF800>; + qcom,descriptor-fifo-size = <0x3A58>; + qcom,reset-bam-on-connect; + }; + qcom,pipe6 { + label = "hsic-ipa-in-3"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <3>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a04000>; + qcom,dst-bam-pipe-index = <6>; + qcom,data-fifo-size = <0xF800>; + qcom,descriptor-fifo-size = <0x3A58>; + qcom,reset-bam-on-connect; + }; + qcom,pipe7 { + label = "hsic-ipa-out-0"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <2>; + qcom,dir = <0>; + qcom,pipe-num = <0>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a04000>; + qcom,src-bam-pipe-index = <7>; + qcom,data-fifo-size = <0xDFE>; + qcom,descriptor-fifo-size = <0xB30>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe8 { + label = "hsusb-ipa-out-1"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <1>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a44000>; + qcom,src-bam-pipe-index = <5>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe9 { + label = "hsusb-ipa-in-1"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <1>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <4>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe10 { + label = "hsusb-ipa-out-2"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <2>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a44000>; + qcom,src-bam-pipe-index = <7>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe11 { + label = "hsusb-ipa-in-2"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <2>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <6>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe12 { + label = "hsusb-ipa-out-3"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <3>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a44000>; + qcom,src-bam-pipe-index = <8>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe13 { + label = "hsusb-ipa-in-3"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <3>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <9>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + }; + + qcom,nand@f9ac0000 { + compatible = "qcom,msm-nand"; + reg = <0xf9ac0000 0x1000>, + <0xf9ac4000 0x8000>; + reg-names = "nand_phys", + "bam_phys"; + interrupts = <0 247 0>; + interrupt-names = "bam_irq"; + }; + + spi_0: spi@f9924000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9924000 0x1000>; + interrupts = <0 96 0>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 7 0>, /* CLK */ + <&msmgpio 5 0>, /* MISO */ + <&msmgpio 4 0>; /* MOSI */ + + cs-gpios = <&msmgpio 6 0>; + + qcom-spi-oled@1 { + compatible = "tplink,oleds90319"; + reg = <1>; + spi-max-frequency = <9600000>; + }; + + }; + + oled { + compatible = "tp,oled_pt"; + qcom,oled_s90319 { + compatible = "qcom,oled_s90319_pt"; + qcom,oled-cs-gpio = <&msmgpio 6 0>; /* refer to board-9625-gpiomux.c */ + qcom,oled-rsx-gpio = <&msmgpio 21 0>; + qcom,oled-reset-gpio = <&msmgpio 20 0>; + qcom,oled-vdd0-gpio = <&msmgpio 22 0>; + qcom,oled-vdd1-gpio = <&msmgpio 23 0>; + qcom,oled-boost-en-gpio = <&msmgpio 61 0>; + }; + }; + + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <1 2 0>, <1 1 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0 0 187 0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>, + <0xf98a4800 0x100>, + <0xf9884000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + + vdd-supply = <&ext_2p95v>; + + vdd-io-supply = <&pm8019_l13>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; + qcom,pad-pull-off = <0x0 0x3 0x3>; + qcom,pad-drv-on = <0x4 0x4 0x4>; + qcom,pad-drv-off = <0x0 0x0 0x0>; + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <4>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + interrupt-parent = <&sdcc2>; + #address-cells = <0>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 66 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + }; + + ipa_hw: qcom,ipa@fd4c0000 { + compatible = "qcom,ipa"; + reg = <0xfd4c0000 0x26000>, + <0xfd4c4000 0x14818>, + <0xfc834000 0x7000>; + reg-names = "ipa-base", "bam-base", "a2-bam-base"; + interrupts = <0 252 0>, + <0 253 0>, + <0 29 1>; + interrupt-names = "ipa-irq", "bam-irq", "a2-bam-irq"; + + qcom,pipe1 { + label = "a2-to-ipa"; + qcom,src-bam-physical-address = <0xfc834000>; + qcom,ipa-bam-mem-type = <0>; + qcom,src-bam-pipe-index = <1>; + qcom,dst-bam-physical-address = <0xfd4c0000>; + qcom,dst-bam-pipe-index = <6>; + qcom,data-fifo-offset = <0x1000>; + qcom,data-fifo-size = <0xd00>; + qcom,descriptor-fifo-offset = <0x1d00>; + qcom,descriptor-fifo-size = <0x300>; + }; + + qcom,pipe2 { + label = "ipa-to-a2"; + qcom,src-bam-physical-address = <0xfd4c0000>; + qcom,ipa-bam-mem-type = <0>; + qcom,src-bam-pipe-index = <7>; + qcom,dst-bam-physical-address = <0xfc834000>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x00>; + qcom,data-fifo-size = <0xd00>; + qcom,descriptor-fifo-offset = <0xd00>; + qcom,descriptor-fifo-size = <0x300>; + }; + }; + + qcom,acpuclk@f9010000 { + compatible = "qcom,acpuclk-9625"; + reg = <0xf9010008 0x10>, + <0xf9008004 0x4>; + reg-names = "rcg_base", "pwr_base"; + a5_cpu-supply = <&pm8019_l10_corner_ao>; + a5_mem-supply = <&pm8019_l12_ao>; + }; + + gdsc_usb_hsic: qcom,gdsc@fc400404 { + compatible = "qcom,gdsc"; + reg = <0xfc400404 0x4>; + regulator-name = "gdsc_usb_hsic"; + }; + + tsens@fc4a8000 { + compatible = "qcom,msm-tsens"; + reg = <0xfc4a8000 0x2000>, + <0xfc4b8000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + qcom,sensors = <5>; + qcom,slope = <3200 3200 3200 3200 3200>; + qcom,calib-mode = "fuse_map1"; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <0>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-control-mask = <0x0>; + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + vdd-dig-supply = <&pm8019_l10_floor_corner>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd-dig"; + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + }; + + qcom,msm-rng@f9bff000 { + compatible = "qcom,msm-rng"; + reg = <0xf9bff000 0x200>; + qcom,msm-rng-iface-clk; + }; + + i2c@f9925000 { + cell-index = <3>; + compatible = "qcom,i2c-qup"; + reg = <0xf9925000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 97 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <400000>; + qcom,i2c-src-freq = <19200000>; + }; + + qcom,mss { + compatible = "qcom,pil-q6v5-mss"; + interrupts = <0 24 1>; + qcom,is-not-loadable; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + qcom,smem@0 { + compatible = "qcom,smem"; + reg = <0x0 0x100000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1000>; + qcom,pil-string = "modem"; + interrupts = <0 25 1>; + }; + + qcom,smsm-modem { + compatible = "qcom,smsm"; + qcom,smsm-edge = <0>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x2000>; + interrupts = <0 26 1>; + }; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; + + qcom,qcedev@fd400000 { + compatible = "qcom,qcedev"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + }; + + qcom,qcrypto@fd440000 { + compatible = "qcom,qcrypto"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + }; + + jtag_mm: jtagmm@fc332000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc332000 0x1000>, + <0xfc330000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x1000>; /* 4K EBI1 buffer */ + }; + + qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x1c00000 0x4800000>; /* Address and Size of Hole */ + }; + + sfpb_spinlock: qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + ldrex_spinlock: qcom,ipc-spinlock@fa00000 { + compatible = "qcom,ipc-spinlock-ldrex"; + reg = <0xfa00000 0x200000>; + status = "disable"; + }; + + cpu-pmu { + compatible = "arm,cortex-a5-pmu"; + qcom,irq-is-percpu; + interrupts = <1 7 0x00>; + }; + + l2-pmu { + compatible = "qcom,l2-pmu"; + interrupts = <0 1 0>; + }; + + /* [houjihai start] gpio keys */ + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + input-name = "gpio-keys"; + key-up { + label = "WPS"; + linux,code = <103>; + gpios = <&msmgpio 14 1>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + key-back { + label = "RESET"; + linux,code = <158>; + gpios = <&msmgpio 15 1>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + /* [houjihai end] */ + +}; + +/include/ "msm-pm8019-rpm-regulator.dtsi" +/include/ "msm-pm8019.dtsi" +/include/ "msm9625-regulator.dtsi" + +&pm8019_vadc { + chan@31 { + label = "batt_id_therm"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + /* [linyunfeng] Detect battery voltage */ + chan@11 { + label = "vbat"; + reg = <0x11>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@33 { + label = "pa_therm0"; + reg = <0x33>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@34 { + label = "pa_therm1"; + reg = <0x34>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@32 { + label = "xo_therm"; + reg = <0x32>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@3c { + label = "xo_therm_amux"; + reg = <0x3c>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@13 { + label = "case_therm"; + reg = <0x13>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@15 { + label = "ambient_therm"; + reg = <0x15>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8019_adc_tm { + /* Channel Node */ + chan@33 { + label = "pa_therm0"; + reg = <0x33>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x48>; + qcom,thermal-node; + }; + + chan@34 { + label = "pa_therm1"; + reg = <0x34>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msmkrypton-sim.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msmkrypton-sim.dts new file mode 100644 index 000000000..1872a36b9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msmkrypton-sim.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msmkrypton.dtsi" + +/ { + model = "Qualcomm MSM KRYPTON SIM"; + compatible = "qcom,msmkrypton-sim", "qcom,msmkrypton", "qcom,sim"; + qcom,msm-id = <187 16 0>; +}; + +&uartdm3{ + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msmkrypton.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msmkrypton.dtsi new file mode 100644 index 000000000..4b032d86d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msmkrypton.dtsi @@ -0,0 +1,120 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM KRYPTON"; + compatible = "qcom,msmkrypton"; + interrupt-parent = <&intc>; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <89>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + + frame@f9029000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0xf9029000 0x1000>; + status = "disabled"; + }; + }; + + uartdm3: serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-ion.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-ion.dtsi new file mode 100644 index 000000000..ea954b89c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-ion.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-rumi.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-rumi.dts new file mode 100644 index 000000000..9a679a4fd --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-rumi.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msmsamarium.dtsi" + +/ { + model = "Qualcomm MSM SAMARIUM RUMI"; + compatible = "qcom,msmsamarium-rumi", "qcom,msmsamarium", "qcom,rumi"; + qcom,msm-id = <195 0 0>; +}; + +&uartblsp0dm2{ + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-sim.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-sim.dts new file mode 100644 index 000000000..4acffae18 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium-sim.dts @@ -0,0 +1,55 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msmsamarium.dtsi" + +/ { + model = "Qualcomm MSM SAMARIUM SIM"; + compatible = "qcom,msmsamarium-sim", "qcom,msmsamarium", "qcom,sim"; + qcom,msm-id = <195 0 0>; +}; + +&uartblsp0dm2{ + status = "ok"; +}; + +&sdcc1 { + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + status = "ok"; +}; + +&sdcc2 { + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium.dtsi new file mode 100644 index 000000000..81699b689 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/msmsamarium.dtsi @@ -0,0 +1,90 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM SAMARIUM"; + compatible = "qcom,msmsamarium"; + interrupt-parent = <&intc>; + soc: soc { }; +}; + +/include/ "msmsamarium-ion.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <145>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + uartblsp0dm2: serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>; + reg-names = "core_mem"; + interrupts = <0 123 0>; + interrupt-names = "core_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>; + reg-names = "core_mem"; + interrupts = <0 125 0>; + interrupt-names = "core_irq"; + + qcom,bus-width = <4>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/omap2.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/omap2.dtsi new file mode 100644 index 000000000..f2ab4ea7c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/omap2.dtsi @@ -0,0 +1,67 @@ +/* + * Device Tree Source for OMAP2 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + cpus { + cpu@0 { + compatible = "arm,arm1136jf-s"; + }; + }; + + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap2-mpu"; + ti,hwmods = "mpu"; + }; + }; + + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@1 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@4806e000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/omap3-beagle.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/omap3-beagle.dts new file mode 100644 index 000000000..9f72cd4cf --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/omap3-beagle.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TI OMAP3 BeagleBoard"; + compatible = "ti,omap3-beagle", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/omap3-evm.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/omap3-evm.dts new file mode 100644 index 000000000..2eee16ec5 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/omap3-evm.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; + compatible = "ti,omap3-evm", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/omap3.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/omap3.dtsi new file mode 100644 index 000000000..c6121357c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/omap3.dtsi @@ -0,0 +1,117 @@ +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,omap3430", "ti,omap3"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + + iva { + compatible = "ti,iva2.2"; + ti,hwmods = "iva"; + + dsp { + compatible = "ti,omap3-c64"; + }; + }; + }; + + /* + * XXX: Use a flat representation of the OMAP3 interconnect. + * The real OMAP interconnect network is quite complex. + * Since that will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <96>; + reg = <0x48200000 0x1000>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@49020000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + i2c1: i2c@48070000 { + compatible = "ti,omap3-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap3-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap3-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/omap4-panda.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/omap4-panda.dts new file mode 100644 index 000000000..9755ad591 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/omap4-panda.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap4.dtsi" + +/ { + model = "TI OMAP4 PandaBoard"; + compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/omap4-sdp.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/omap4-sdp.dts new file mode 100644 index 000000000..63c6b2b2b --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/omap4-sdp.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap4.dtsi" + +/ { + model = "TI OMAP4 SDP board"; + compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/omap4.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/omap4.dtsi new file mode 100644 index 000000000..3d35559e7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/omap4.dtsi @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Carveout for multimedia usecases + * It should be the last 48MB of the first 512MB memory part + * In theory, it should not even exist. That zone should be reserved + * dynamically during the .reserve callback. + */ +/memreserve/ 0x9d000000 0x03000000; + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,omap4430", "ti,omap4"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap4-mpu"; + ti,hwmods = "mpu"; + }; + + dsp { + compatible = "ti,omap3-c64"; + ti,hwmods = "dsp"; + }; + + iva { + compatible = "ti,ivahd"; + ti,hwmods = "iva"; + }; + }; + + /* + * XXX: Use a flat representation of the OMAP4 interconnect. + * The real OMAP interconnect network is quite complex. + * + * MPU -+-- MPU_PRIVATE - GIC, L2 + * | + * +----------------+----------+ + * | | | + * + +- EMIF - DDR | + * | | | + * | + +--------+ + * | | | + * | +- L4_ABE - AESS, MCBSP, TIMERs... + * | | + * +- L3_MAIN --+- L4_CORE - IPs... + * | + * +- L4_PER - IPs... + * | + * +- L4_CFG -+- L4_WKUP - IPs... + * | | + * | +- IPs... + * +- IPU ----+ + * | | + * +- DSP ----+ + * | | + * +- DSS ----+ + * + * Since that will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp { + compatible = "ti,omap4-l3-noc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; + + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@48020000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@4806e000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + i2c1: i2c@48070000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + + i2c4: i2c@48350000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c4"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc3x2.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc3x2.dtsi new file mode 100644 index 000000000..f0a8c2068 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc3x2.dtsi @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2011 Picochip, Jamie Iles + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/include/ "skeleton.dtsi" +/ { + model = "Picochip picoXcell PC3X2"; + compatible = "picochip,pc3x2"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,1176jz-s"; + clock-frequency = <400000000>; + reg = <0>; + d-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-line-size = <32>; + i-cache-size = <32768>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pclk: clock@0 { + compatible = "fixed-clock"; + clock-outputs = "bus", "pclk"; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + }; + + paxi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80000000 0x400000>; + + emac: gem@30000 { + compatible = "cadence,gem"; + reg = <0x30000 0x10000>; + interrupts = <31>; + }; + + dmac1: dmac@40000 { + compatible = "snps,dw-dmac"; + reg = <0x40000 0x10000>; + interrupts = <25>; + }; + + dmac2: dmac@50000 { + compatible = "snps,dw-dmac"; + reg = <0x50000 0x10000>; + interrupts = <26>; + }; + + vic0: interrupt-controller@60000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x60000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@64000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x64000 0x1000>; + #interrupt-cells = <1>; + }; + + fuse: picoxcell-fuse@80000 { + compatible = "picoxcell,fuse-pc3x2"; + reg = <0x80000 0x10000>; + }; + + ssi: picoxcell-spi@90000 { + compatible = "picoxcell,spi"; + reg = <0x90000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <10>; + }; + + ipsec: spacc@100000 { + compatible = "picochip,spacc-ipsec"; + reg = <0x100000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <24>; + ref-clock = <&pclk>, "ref"; + }; + + srtp: spacc@140000 { + compatible = "picochip,spacc-srtp"; + reg = <0x140000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <23>; + }; + + l2_engine: spacc@180000 { + compatible = "picochip,spacc-l2"; + reg = <0x180000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <22>; + ref-clock = <&pclk>, "ref"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x80000>; + + rtc0: rtc@00000 { + compatible = "picochip,pc3x2-rtc"; + clock-freq = <200000000>; + reg = <0x00000 0xf>; + interrupt-parent = <&vic1>; + interrupts = <8>; + }; + + timer0: timer@10000 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <4>; + clock-freq = <200000000>; + reg = <0x10000 0x14>; + }; + + timer1: timer@10014 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <5>; + clock-freq = <200000000>; + reg = <0x10014 0x14>; + }; + + timer2: timer@10028 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <6>; + clock-freq = <200000000>; + reg = <0x10028 0x14>; + }; + + timer3: timer@1003c { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <7>; + clock-freq = <200000000>; + reg = <0x1003c 0x14>; + }; + + gpio: gpio@20000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-io-width = <4>; + + banka: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <8>; + + regoffset-dat = <0x50>; + regoffset-set = <0x00>; + regoffset-dirout = <0x04>; + }; + + bankb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <8>; + + regoffset-dat = <0x54>; + regoffset-set = <0x0c>; + regoffset-dirout = <0x10>; + }; + }; + + uart0: uart@30000 { + compatible = "snps,dw-apb-uart"; + reg = <0x30000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <10>; + clock-frequency = <3686400>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: uart@40000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <9>; + clock-frequency = <3686400>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + wdog: watchdog@50000 { + compatible = "snps,dw-apb-wdg"; + reg = <0x50000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <11>; + bus-clock = <&pclk>, "bus"; + }; + }; + }; + + rwid-axi { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + ebi@50000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x08000000 + 1 0 0x48000000 0x08000000 + 2 0 0x50000000 0x08000000 + 3 0 0x58000000 0x08000000>; + }; + + axi2pico@c0000000 { + compatible = "picochip,axi2pico-pc3x2"; + reg = <0xc0000000 0x10000>; + interrupts = <13 14 15 16 17 18 19 20 21>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc3x3.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc3x3.dtsi new file mode 100644 index 000000000..daa962d19 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc3x3.dtsi @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2011 Picochip, Jamie Iles + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/include/ "skeleton.dtsi" +/ { + model = "Picochip picoXcell PC3X3"; + compatible = "picochip,pc3x3"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,1176jz-s"; + cpu-clock = <&arm_clk>, "cpu"; + reg = <0>; + d-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-line-size = <32>; + i-cache-size = <32768>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clkgate: clkgate@800a0048 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x800a0048 4>; + compatible = "picochip,pc3x3-clk-gate"; + + tzprot_clk: clock@0 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <0>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + spi_clk: clock@1 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <1>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + dmac0_clk: clock@2 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <2>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + dmac1_clk: clock@3 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <3>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + ebi_clk: clock@4 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <4>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + ipsec_clk: clock@5 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <5>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + l2_clk: clock@6 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <6>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + trng_clk: clock@7 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <7>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + fuse_clk: clock@8 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <8>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + otp_clk: clock@9 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <9>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + }; + + arm_clk: clock@11 { + compatible = "picochip,pc3x3-pll"; + reg = <0x800a0050 0x8>; + picochip,min-freq = <140000000>; + picochip,max-freq = <700000000>; + ref-clock = <&ref_clk>, "ref"; + clock-outputs = "cpu"; + }; + + pclk: clock@12 { + compatible = "fixed-clock"; + clock-outputs = "bus", "pclk"; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + }; + + paxi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80000000 0x400000>; + + emac: gem@30000 { + compatible = "cadence,gem"; + reg = <0x30000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <31>; + }; + + dmac1: dmac@40000 { + compatible = "snps,dw-dmac"; + reg = <0x40000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <25>; + }; + + dmac2: dmac@50000 { + compatible = "snps,dw-dmac"; + reg = <0x50000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <26>; + }; + + vic0: interrupt-controller@60000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x60000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@64000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x64000 0x1000>; + #interrupt-cells = <1>; + }; + + fuse: picoxcell-fuse@80000 { + compatible = "picoxcell,fuse-pc3x3"; + reg = <0x80000 0x10000>; + }; + + ssi: picoxcell-spi@90000 { + compatible = "picoxcell,spi"; + reg = <0x90000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <10>; + }; + + ipsec: spacc@100000 { + compatible = "picochip,spacc-ipsec"; + reg = <0x100000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <24>; + ref-clock = <&ipsec_clk>, "ref"; + }; + + srtp: spacc@140000 { + compatible = "picochip,spacc-srtp"; + reg = <0x140000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <23>; + }; + + l2_engine: spacc@180000 { + compatible = "picochip,spacc-l2"; + reg = <0x180000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <22>; + ref-clock = <&l2_clk>, "ref"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x80000>; + + rtc0: rtc@00000 { + compatible = "picochip,pc3x2-rtc"; + clock-freq = <200000000>; + reg = <0x00000 0xf>; + interrupt-parent = <&vic0>; + interrupts = <8>; + }; + + timer0: timer@10000 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <4>; + clock-freq = <200000000>; + reg = <0x10000 0x14>; + }; + + timer1: timer@10014 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <5>; + clock-freq = <200000000>; + reg = <0x10014 0x14>; + }; + + gpio: gpio@20000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-io-width = <4>; + + banka: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <8>; + + regoffset-dat = <0x50>; + regoffset-set = <0x00>; + regoffset-dirout = <0x04>; + }; + + bankb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <16>; + + regoffset-dat = <0x54>; + regoffset-set = <0x0c>; + regoffset-dirout = <0x10>; + }; + + bankd: gpio-controller@2 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <30>; + + regoffset-dat = <0x5c>; + regoffset-set = <0x24>; + regoffset-dirout = <0x28>; + }; + }; + + uart0: uart@30000 { + compatible = "snps,dw-apb-uart"; + reg = <0x30000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <10>; + clock-frequency = <3686400>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: uart@40000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <9>; + clock-frequency = <3686400>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + wdog: watchdog@50000 { + compatible = "snps,dw-apb-wdg"; + reg = <0x50000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <11>; + bus-clock = <&pclk>, "bus"; + }; + + timer2: timer@60000 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <6>; + clock-freq = <200000000>; + reg = <0x60000 0x14>; + }; + + timer3: timer@60014 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <7>; + clock-freq = <200000000>; + reg = <0x60014 0x14>; + }; + }; + }; + + rwid-axi { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + ebi@50000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x08000000 + 1 0 0x48000000 0x08000000 + 2 0 0x50000000 0x08000000 + 3 0 0x58000000 0x08000000>; + }; + + axi2pico@c0000000 { + compatible = "picochip,axi2pico-pc3x3"; + reg = <0xc0000000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <13 14 15 16 17 18 19 20 21>; + }; + + otp@ffff8000 { + compatible = "picochip,otp-pc3x3"; + reg = <0xffff8000 0x8000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc7302-pc3x2.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc7302-pc3x2.dts new file mode 100644 index 000000000..1297414dd --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc7302-pc3x2.dts @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2011 Picochip, Jamie Iles + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "picoxcell-pc3x2.dtsi" +/ { + model = "Picochip PC7302 (PC3X2)"; + compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2"; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + linux,stdout-path = &uart0; + }; + + clocks { + ref_clk: clock@1 { + compatible = "fixed-clock"; + clock-outputs = "ref"; + clock-frequency = <20000000>; + }; + }; + + rwid-axi { + ebi@50000000 { + nand: gpio-nand@2,0 { + compatible = "gpio-control-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <2 0x0000 0x1000>; + bus-clock = <&pclk>, "bus"; + gpio-control-nand,io-sync-reg = + <0x00000000 0x80220000>; + + gpios = <&banka 1 0 /* rdy */ + &banka 2 0 /* nce */ + &banka 3 0 /* ale */ + &banka 4 0 /* cle */ + 0 /* nwp */>; + + boot@100000 { + label = "Boot"; + reg = <0x100000 0x80000>; + }; + + redundant-boot@200000 { + label = "Redundant Boot"; + reg = <0x200000 0x80000>; + }; + + boot-env@300000 { + label = "Boot Evironment"; + reg = <0x300000 0x20000>; + }; + + redundant-boot-env@320000 { + label = "Redundant Boot Environment"; + reg = <0x300000 0x20000>; + }; + + kernel@380000 { + label = "Kernel"; + reg = <0x380000 0x800000>; + }; + + fs@b80000 { + label = "File System"; + reg = <0xb80000 0xf480000>; + }; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc7302-pc3x3.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc7302-pc3x3.dts new file mode 100644 index 000000000..9e317a4f4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/picoxcell-pc7302-pc3x3.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2011 Picochip, Jamie Iles + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "picoxcell-pc3x3.dtsi" +/ { + model = "Picochip PC7302 (PC3X3)"; + compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3"; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + linux,stdout-path = &uart0; + }; + + clocks { + ref_clk: clock@10 { + compatible = "fixed-clock"; + clock-outputs = "ref"; + clock-frequency = <20000000>; + }; + + clkgate: clkgate@800a0048 { + clock@4 { + picochip,clk-no-disable; + }; + }; + }; + + rwid-axi { + ebi@50000000 { + nand: gpio-nand@2,0 { + compatible = "gpio-control-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <2 0x0000 0x1000>; + bus-clock = <&ebi_clk>, "bus"; + gpio-control-nand,io-sync-reg = + <0x00000000 0x80220000>; + + gpios = <&banka 1 0 /* rdy */ + &banka 2 0 /* nce */ + &banka 3 0 /* ale */ + &banka 4 0 /* cle */ + 0 /* nwp */>; + + boot@100000 { + label = "Boot"; + reg = <0x100000 0x80000>; + }; + + redundant-boot@200000 { + label = "Redundant Boot"; + reg = <0x200000 0x80000>; + }; + + boot-env@300000 { + label = "Boot Evironment"; + reg = <0x300000 0x20000>; + }; + + redundant-boot-env@320000 { + label = "Redundant Boot Environment"; + reg = <0x300000 0x20000>; + }; + + kernel@380000 { + label = "Kernel"; + reg = <0x380000 0x800000>; + }; + + fs@b80000 { + label = "File System"; + reg = <0xb80000 0xf480000>; + }; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/prima2-cb.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/prima2-cb.dts new file mode 100644 index 000000000..34ae3a64b --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/prima2-cb.dts @@ -0,0 +1,424 @@ +/dts-v1/; +/ { + model = "SiRF Prima2 eVB"; + compatible = "sirf,prima2-cb", "sirf,prima2"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + memory { + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1"; + linux,stdout-path = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* from bootloader */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0x80000000>; + + l2-cache-controller@80040000 { + compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; + reg = <0x80040000 0x1000>; + interrupts = <59>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0 0x40000000>; + }; + + intc: interrupt-controller@80020000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "sirf,prima2-intc"; + reg = <0x80020000 0x1000>; + }; + + sys-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x88000000 0x88000000 0x40000>; + + clock-controller@88000000 { + compatible = "sirf,prima2-clkc"; + reg = <0x88000000 0x1000>; + interrupts = <3>; + }; + + reset-controller@88010000 { + compatible = "sirf,prima2-rstc"; + reg = <0x88010000 0x1000>; + }; + + rsc-controller@88020000 { + compatible = "sirf,prima2-rsc"; + reg = <0x88020000 0x1000>; + }; + }; + + mem-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90000000 0x90000000 0x10000>; + + memory-controller@90000000 { + compatible = "sirf,prima2-memc"; + reg = <0x90000000 0x10000>; + interrupts = <27>; + }; + }; + + disp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90010000 0x90010000 0x30000>; + + display@90010000 { + compatible = "sirf,prima2-lcd"; + reg = <0x90010000 0x20000>; + interrupts = <30>; + }; + + vpp@90020000 { + compatible = "sirf,prima2-vpp"; + reg = <0x90020000 0x10000>; + interrupts = <31>; + }; + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x8000000>; + + graphics@98000000 { + compatible = "powervr,sgx531"; + reg = <0x98000000 0x8000000>; + interrupts = <6>; + }; + }; + + multimedia-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa0000000 0xa0000000 0x8000000>; + + multimedia@a0000000 { + compatible = "sirf,prima2-video-codec"; + reg = <0xa0000000 0x8000000>; + interrupts = <5>; + }; + }; + + dsp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa8000000 0xa8000000 0x2000000>; + + dspif@a8000000 { + compatible = "sirf,prima2-dspif"; + reg = <0xa8000000 0x10000>; + interrupts = <9>; + }; + + gps@a8010000 { + compatible = "sirf,prima2-gps"; + reg = <0xa8010000 0x10000>; + interrupts = <7>; + }; + + dsp@a9000000 { + compatible = "sirf,prima2-dsp"; + reg = <0xa9000000 0x1000000>; + interrupts = <8>; + }; + }; + + peri-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0xb0000000 0x180000>; + + timer@b0020000 { + compatible = "sirf,prima2-tick"; + reg = <0xb0020000 0x1000>; + interrupts = <0>; + }; + + nand@b0030000 { + compatible = "sirf,prima2-nand"; + reg = <0xb0030000 0x10000>; + interrupts = <41>; + }; + + audio@b0040000 { + compatible = "sirf,prima2-audio"; + reg = <0xb0040000 0x10000>; + interrupts = <35>; + }; + + uart0: uart@b0050000 { + cell-index = <0>; + compatible = "sirf,prima2-uart"; + reg = <0xb0050000 0x10000>; + interrupts = <17>; + }; + + uart1: uart@b0060000 { + cell-index = <1>; + compatible = "sirf,prima2-uart"; + reg = <0xb0060000 0x10000>; + interrupts = <18>; + }; + + uart2: uart@b0070000 { + cell-index = <2>; + compatible = "sirf,prima2-uart"; + reg = <0xb0070000 0x10000>; + interrupts = <19>; + }; + + usp0: usp@b0080000 { + cell-index = <0>; + compatible = "sirf,prima2-usp"; + reg = <0xb0080000 0x10000>; + interrupts = <20>; + }; + + usp1: usp@b0090000 { + cell-index = <1>; + compatible = "sirf,prima2-usp"; + reg = <0xb0090000 0x10000>; + interrupts = <21>; + }; + + usp2: usp@b00a0000 { + cell-index = <2>; + compatible = "sirf,prima2-usp"; + reg = <0xb00a0000 0x10000>; + interrupts = <22>; + }; + + dmac0: dma-controller@b00b0000 { + cell-index = <0>; + compatible = "sirf,prima2-dmac"; + reg = <0xb00b0000 0x10000>; + interrupts = <12>; + }; + + dmac1: dma-controller@b0160000 { + cell-index = <1>; + compatible = "sirf,prima2-dmac"; + reg = <0xb0160000 0x10000>; + interrupts = <13>; + }; + + vip@b00C0000 { + compatible = "sirf,prima2-vip"; + reg = <0xb00C0000 0x10000>; + }; + + spi0: spi@b00d0000 { + cell-index = <0>; + compatible = "sirf,prima2-spi"; + reg = <0xb00d0000 0x10000>; + interrupts = <15>; + }; + + spi1: spi@b0170000 { + cell-index = <1>; + compatible = "sirf,prima2-spi"; + reg = <0xb0170000 0x10000>; + interrupts = <16>; + }; + + i2c0: i2c@b00e0000 { + cell-index = <0>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00e0000 0x10000>; + interrupts = <24>; + }; + + i2c1: i2c@b00f0000 { + cell-index = <1>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00f0000 0x10000>; + interrupts = <25>; + }; + + tsc@b0110000 { + compatible = "sirf,prima2-tsc"; + reg = <0xb0110000 0x10000>; + interrupts = <33>; + }; + + gpio: gpio-controller@b0120000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,prima2-gpio-pinmux"; + reg = <0xb0120000 0x10000>; + gpio-controller; + interrupt-controller; + }; + + pwm@b0130000 { + compatible = "sirf,prima2-pwm"; + reg = <0xb0130000 0x10000>; + }; + + efusesys@b0140000 { + compatible = "sirf,prima2-efuse"; + reg = <0xb0140000 0x10000>; + }; + + pulsec@b0150000 { + compatible = "sirf,prima2-pulsec"; + reg = <0xb0150000 0x10000>; + interrupts = <48>; + }; + + pci-iobg { + compatible = "sirf,prima2-pciiobg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x56000000 0x1b00000>; + + sd0: sdhci@56000000 { + cell-index = <0>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56000000 0x100000>; + interrupts = <38>; + }; + + sd1: sdhci@56100000 { + cell-index = <1>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56100000 0x100000>; + interrupts = <38>; + }; + + sd2: sdhci@56200000 { + cell-index = <2>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56200000 0x100000>; + interrupts = <23>; + }; + + sd3: sdhci@56300000 { + cell-index = <3>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56300000 0x100000>; + interrupts = <23>; + }; + + sd4: sdhci@56400000 { + cell-index = <4>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56400000 0x100000>; + interrupts = <39>; + }; + + sd5: sdhci@56500000 { + cell-index = <5>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56500000 0x100000>; + interrupts = <39>; + }; + + pci-copy@57900000 { + compatible = "sirf,prima2-pcicp"; + reg = <0x57900000 0x100000>; + interrupts = <40>; + }; + + rom-interface@57a00000 { + compatible = "sirf,prima2-romif"; + reg = <0x57a00000 0x100000>; + }; + }; + }; + + rtc-iobg { + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80030000 0x10000>; + + gpsrtc@1000 { + compatible = "sirf,prima2-gpsrtc"; + reg = <0x1000 0x1000>; + interrupts = <55 56 57>; + }; + + sysrtc@2000 { + compatible = "sirf,prima2-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <52 53 54>; + }; + + pwrc@3000 { + compatible = "sirf,prima2-pwrc"; + reg = <0x3000 0x1000>; + interrupts = <32>; + }; + }; + + uus-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb8000000 0xb8000000 0x40000>; + + usb0: usb@b00e0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8000000 0x10000>; + interrupts = <10>; + }; + + usb1: usb@b00f0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8010000 0x10000>; + interrupts = <11>; + }; + + sata@b00f0000 { + compatible = "synopsys,dwc-ahsata"; + reg = <0xb8020000 0x10000>; + interrupts = <37>; + }; + + security@b00f0000 { + compatible = "sirf,prima2-security"; + reg = <0xb8030000 0x10000>; + interrupts = <42>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/pxa168-aspenite.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/pxa168-aspenite.dts new file mode 100644 index 000000000..e762facb3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/pxa168-aspenite.dts @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "pxa168.dtsi" + +/ { + model = "Marvell PXA168 Aspenite Development Board"; + compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + }; + + memory { + reg = <0x00000000 0x04000000>; + }; + + soc { + apb@d4000000 { + uart1: uart@d4017000 { + status = "okay"; + }; + twsi1: i2c@d4011000 { + status = "okay"; + }; + rtc: rtc@d4010000 { + status = "okay"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/pxa168.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/pxa168.dtsi new file mode 100644 index 000000000..d32d5128f --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/pxa168.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + i2c0 = &twsi1; + i2c1 = &twsi2; + }; + + intc: intc-interrupt-controller@d4282000 { + compatible = "mrvl,mmp-intc", "mrvl,intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + apb@d4000000 { /* APB */ + compatible = "mrvl,apb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + uart1: uart@d4017000 { + compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + reg = <0xd4017000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + uart2: uart@d4018000 { + compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + reg = <0xd4018000 0x1000>; + interrupts = <28>; + status = "disabled"; + }; + + uart3: uart@d4026000 { + compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + reg = <0xd4026000 0x1000>; + interrupts = <29>; + status = "disabled"; + }; + + gpio: gpio@d4019000 { + compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio"; + reg = <0xd4019000 0x1000>; + interrupts = <49>; + interrupt-names = "gpio_mux"; + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; + reg = <0xd4011000 0x1000>; + interrupts = <7>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4025000 { + compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; + reg = <0xd4025000 0x1000>; + interrupts = <58>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <5 6>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/qpic-panel-ili-qvga.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/qpic-panel-ili-qvga.dtsi new file mode 100644 index 000000000..089f1125d --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/qpic-panel-ili-qvga.dtsi @@ -0,0 +1,27 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_lcdc_ili9341_qvga { + compatible = "qcom,mdss-qpic-panel"; + label = "ili qvga lcdc panel"; + vdd-supply = <&pm8019_l11>; + avdd-supply = <&pm8019_l14>; + qcom,cs-gpio = <&msmgpio 21 0>; + qcom,te-gpio = <&msmgpio 22 0>; + qcom,rst-gpio = <&msmgpio 23 0>; + qcom,ad8-gpio = <&msmgpio 20 0>; + qcom,mdss-pan-res = <240 320>; + qcom,mdss-pan-bpp = <18>; + qcom,refresh_rate = <60>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/skeleton.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/skeleton.dtsi new file mode 100644 index 000000000..f9988cd78 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/skeleton.dtsi @@ -0,0 +1,18 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { + #address-cells = <1>; + #size-cells = <1>; + device_type = "memory"; + reg = <0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/skeleton64.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/skeleton64.dtsi new file mode 100644 index 000000000..5bf6a82f0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/skeleton64.dtsi @@ -0,0 +1,18 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + chosen { }; + aliases { }; + memory { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + reg = <0 0 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/snowball.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/snowball.dts new file mode 100644 index 000000000..359c6d679 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/snowball.dts @@ -0,0 +1,139 @@ +/* + * Copyright 2011 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "db8500.dtsi" + +/ { + model = "Calao Systems Snowball platform with device tree"; + compatible = "calaosystems,snowball-a9500"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <2>; + label = "userpb"; + gpios = <&gpio1 0>; + }; + button@2 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <3>; + label = "userpb"; + gpios = <&gpio4 23>; + }; + button@3 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <4>; + label = "userpb"; + gpios = <&gpio4 23>; + }; + button@4 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <5>; + label = "userpb"; + gpios = <&gpio5 1>; + }; + button@5 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <6>; + label = "userpb"; + gpios = <&gpio5 2>; + }; + }; + + leds { + compatible = "gpio-leds"; + used-led { + label = "user_led"; + gpios = <&gpio4 14>; + }; + }; + + soc-u9500 { + + external-bus@50000000 { + compatible = "simple-bus"; + reg = <0x50000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ethernet@50000000 { + compatible = "smsc,9111"; + reg = <0x50000000 0x10000>; + interrupts = <12>; + interrupt-parent = <&gpio4>; + }; + }; + + sdi@80126000 { + status = "enabled"; + cd-gpios = <&gpio6 26>; + }; + + sdi@80114000 { + status = "enabled"; + }; + + uart@80120000 { + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; + + i2c@80004000 { + tc3589x@42 { + //compatible = "tc3589x"; + reg = <0x42>; + interrupts = <25>; + interrupt-parent = <&gpio6>; + }; + tps61052@33 { + //compatible = "tps61052"; + reg = <0x33>; + }; + }; + + i2c@80128000 { + lp5521@0x33 { + // compatible = "lp5521"; + reg = <0x33>; + }; + lp5521@0x34 { + // compatible = "lp5521"; + reg = <0x34>; + }; + bh1780@0x29 { + // compatible = "rohm,bh1780gli"; + reg = <0x33>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/spear600-evb.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/spear600-evb.dts new file mode 100644 index 000000000..636292e18 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/spear600-evb.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2012 Stefan Roese + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear600.dtsi" + +/ { + model = "ST SPEAr600 Evaluation Board"; + compatible = "st,spear600-evb", "st,spear600"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0 0x10000000>; + }; + + ahb { + gmac: ethernet@e0800000 { + phy-mode = "gmii"; + status = "okay"; + }; + + apb { + serial@d0000000 { + status = "okay"; + }; + + serial@d0080000 { + status = "okay"; + }; + + i2c@d0200000 { + clock-frequency = <400000>; + status = "okay"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/spear600.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/spear600.dtsi new file mode 100644 index 000000000..ebe0885a2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/spear600.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright 2012 Stefan Roese + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "st,spear600"; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + vic0: interrupt-controller@f1100000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1100000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@f1000000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1000000 0x1000>; + #interrupt-cells = <1>; + }; + + gmac: ethernet@e0800000 { + compatible = "st,spear600-gmac"; + reg = <0xe0800000 0x8000>; + interrupt-parent = <&vic1>; + interrupts = <24 23>; + interrupt-names = "macirq", "eth_wake_irq"; + status = "disabled"; + }; + + fsmc: flash@d1800000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd1800000 0x1000 /* FSMC Register */ + 0xd2000000 0x4000>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + st,ale-off = <0x20000>; + st,cle-off = <0x10000>; + status = "disabled"; + }; + + smi: flash@fc000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xfc000000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <12>; + status = "disabled"; + }; + + ehci@e1800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe1800000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <27>; + status = "disabled"; + }; + + ehci@e2000000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe2000000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <29>; + status = "disabled"; + }; + + ohci@e1900000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe1900000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <26>; + status = "disabled"; + }; + + ohci@e2100000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe2100000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <28>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + serial@d0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0000000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <24>; + status = "disabled"; + }; + + serial@d0080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0080000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <25>; + status = "disabled"; + }; + + /* local/cpu GPIO */ + gpio0: gpio@f0100000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xf0100000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <18>; + }; + + /* basic GPIO */ + gpio1: gpio@fc980000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfc980000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <19>; + }; + + /* appl GPIO */ + gpio2: gpio@d8100000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xd8100000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <4>; + }; + + i2c@d0200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xd0200000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <28>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-cardhu.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-cardhu.dts new file mode 100644 index 000000000..ac3fb7558 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-cardhu.dts @@ -0,0 +1,70 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = < 0x80000000 0x40000000 >; + }; + + serial@70006000 { + clock-frequency = < 408000000 >; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + + i2c@7000c000 { + clock-frequency = <100000>; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + }; + + i2c@7000c700 { + clock-frequency = <100000>; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + }; + + sdhci@78000000 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + }; + + sdhci@78000200 { + status = "disable"; + }; + + sdhci@78000400 { + status = "disable"; + }; + + sdhci@78000400 { + support-8bit; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-harmony.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-harmony.dts new file mode 100644 index 000000000..6e8447dc0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-harmony.dts @@ -0,0 +1,115 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Harmony evaluation board"; + compatible = "nvidia,harmony", "nvidia,tegra20"; + + memory@0 { + reg = < 0x00000000 0x40000000 >; + }; + + pmc@7000f400 { + nvidia,invert-interrupt; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = < 187 0x04 >; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + i2s@70002a00 { + status = "disable"; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-harmony", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Harmony"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ + nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + support-8bit; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-paz00.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-paz00.dts new file mode 100644 index 000000000..6c02abb46 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-paz00.dts @@ -0,0 +1,134 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + memory@0 { + reg = <0x00000000 0x20000000>; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + alc5632: alc5632@1e { + compatible = "realtek,alc5632"; + reg = <0x1e>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "disable"; + }; + + nvec@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,nvec"; + reg = <0x7000C500 0x100>; + interrupts = <0 92 0x04>; + clock-frequency = <80000>; + request-gpios = <&gpio 170 0>; + slave-addr = <138>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + + adt7461@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + + i2s@70002a00 { + status = "disable"; + }; + + sound { + compatible = "nvidia,tegra-audio-alc5632-paz00", + "nvidia,tegra-audio-alc5632"; + + nvidia,model = "Compal PAZ00"; + + nvidia,audio-routing = + "Int Spk", "SPKOUT", + "Int Spk", "SPKOUTN", + "Headset Mic", "MICBIAS1", + "MIC1", "Headset Mic", + "Headset Stereophone", "HPR", + "Headset Stereophone", "HPL", + "DMICDAT", "Digital Mic"; + + nvidia,audio-codec = <&alc5632>; + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + clock-frequency = <216000000>; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + cd-gpios = <&gpio 173 0>; /* gpio PV5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 169 0>; /* gpio PV1 */ + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + support-8bit; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio 79 1>; /* gpio PJ7, active low */ + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wifi { + label = "wifi-led"; + gpios = <&gpio 24 0>; + linux,default-trigger = "rfkill0"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-seaboard.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-seaboard.dts new file mode 100644 index 000000000..dbf1c5a17 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-seaboard.dts @@ -0,0 +1,175 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Seaboard"; + compatible = "nvidia,seaboard", "nvidia,tegra20"; + + memory { + device_type = "memory"; + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = < 187 0x04 >; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + + adt7461@4c { + compatible = "adt7461"; + reg = <0x4c>; + }; + }; + + i2s@70002a00 { + status = "disable"; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-seaboard", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Seaboard"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1R", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; + + sdhci@c8000600 { + support-8bit; + }; + + usb@c5000000 { + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + dr_mode = "otg"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio 170 1>; /* gpio PV2, active low */ + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + lid { + label = "Lid"; + gpios = <&gpio 23 0>; /* gpio PC7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; + + emc@7000f400 { + emc-table@190000 { + reg = < 190000 >; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 190000 >; + nvidia,emc-registers = < 0x0000000c 0x00000026 + 0x00000009 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x0000059f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000b 0x000000c8 + 0x00000003 0x00000007 0x00000004 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xa06204ae + 0x007dc010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 >; + }; + + emc-table@380000 { + reg = < 380000 >; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 380000 >; + nvidia,emc-registers = < 0x00000017 0x0000004b + 0x00000012 0x00000006 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000b5f + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe044048b + 0x007d8010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 >; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-trimslice.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-trimslice.dts new file mode 100644 index 000000000..252476867 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-trimslice.dts @@ -0,0 +1,77 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + memory@0 { + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "disable"; + }; + + i2s@70002800 { + status = "disable"; + }; + + i2s@70002a00 { + status = "disable"; + }; + + das@70000c00 { + status = "disable"; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 121 0>; + wp-gpios = <&gpio 122 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-ventana.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-ventana.dts new file mode 100644 index 000000000..2dcff8728 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra-ventana.dts @@ -0,0 +1,108 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; + + memory { + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = < 187 0x04 >; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + i2s@70002a00 { + status = "disable"; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-ventana", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Ventana"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ + nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; + + sdhci@c8000600 { + support-8bit; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/tegra20.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra20.dtsi new file mode 100644 index 000000000..108e894a8 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra20.dtsi @@ -0,0 +1,210 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra20"; + interrupt-parent = <&intc>; + + pmc@7000f400 { + compatible = "nvidia,tegra20-pmc"; + reg = <0x7000e400 0x400>; + }; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 56 0x04 + 0 57 0x04>; + }; + + apbdma: dma@6000a000 { + compatible = "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1200>; + interrupts = < 0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 0 38 0x04 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 0 84 0x04 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 0 92 0x04 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c-dvc"; + reg = <0x7000D000 0x200>; + interrupts = < 0 53 0x04 >; + }; + + tegra_i2s1: i2s@70002800 { + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002800 0x200>; + interrupts = < 0 13 0x04 >; + nvidia,dma-request-selector = < &apbdma 2 >; + }; + + tegra_i2s2: i2s@70002a00 { + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002a00 0x200>; + interrupts = < 0 3 0x04 >; + nvidia,dma-request-selector = < &apbdma 1 >; + }; + + das@70000c00 { + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 >; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = < 0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8 >; /* Pad control registers */ + }; + + serial@70006000 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 0 36 0x04 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 0 37 0x04 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 0 46 0x04 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 0 90 0x04 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 0 91 0x04 >; + }; + + emc@7000f400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f400 0x200>; + }; + + sdhci@c8000000 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000000 0x200>; + interrupts = < 0 14 0x04 >; + }; + + sdhci@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = < 0 15 0x04 >; + }; + + sdhci@c8000400 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000400 0x200>; + interrupts = < 0 19 0x04 >; + }; + + sdhci@c8000600 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000600 0x200>; + interrupts = < 0 31 0x04 >; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 0 20 0x04 >; + phy_type = "utmi"; + nvidia,has-legacy-mode; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 0 21 0x04 >; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 0 97 0x04 >; + phy_type = "utmi"; + }; +}; + diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/tegra30.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra30.dtsi new file mode 100644 index 000000000..62a7b39f1 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/tegra30.dtsi @@ -0,0 +1,186 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra30"; + interrupt-parent = <&intc>; + + pmc@7000f400 { + compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; + reg = <0x7000e400 0x400>; + }; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 144 0x04 + 0 145 0x04 + 0 146 0x04 + 0 147 0x04>; + }; + + apbdma: dma@6000a000 { + compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1400>; + interrupts = < 0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04 + 0 128 0x04 + 0 129 0x04 + 0 130 0x04 + 0 131 0x04 + 0 132 0x04 + 0 133 0x04 + 0 134 0x04 + 0 135 0x04 + 0 136 0x04 + 0 137 0x04 + 0 138 0x04 + 0 139 0x04 + 0 140 0x04 + 0 141 0x04 + 0 142 0x04 + 0 143 0x04 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 0 38 0x04 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 0 84 0x04 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 0 92 0x04 >; + }; + + i2c@7000c700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = < 0 120 0x04 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x100>; + interrupts = < 0 53 0x04 >; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04 >; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 0 36 0x04 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 0 37 0x04 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 0 46 0x04 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 0 90 0x04 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 0 91 0x04 >; + }; + + sdhci@78000000 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000000 0x200>; + interrupts = < 0 14 0x04 >; + }; + + sdhci@78000200 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000200 0x200>; + interrupts = < 0 15 0x04 >; + }; + + sdhci@78000400 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000400 0x200>; + interrupts = < 0 19 0x04 >; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000600 0x200>; + interrupts = < 0 31 0x04 >; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra30-pinmux"; + reg = < 0x70000868 0xd0 /* Pad control registers */ + 0x70003000 0x3e0 >; /* Mux registers */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/testcases/tests-phandle.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/testcases/tests-phandle.dtsi new file mode 100644 index 000000000..0007d3cd7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/testcases/tests-phandle.dtsi @@ -0,0 +1,39 @@ + +/ { + testcase-data { + phandle-tests { + provider0: provider0 { + #phandle-cells = <0>; + }; + + provider1: provider1 { + #phandle-cells = <1>; + }; + + provider2: provider2 { + #phandle-cells = <2>; + }; + + provider3: provider3 { + #phandle-cells = <3>; + }; + + consumer-a { + phandle-list = <&provider1 1>, + <&provider2 2 0>, + <0>, + <&provider3 4 4 3>, + <&provider2 5 100>, + <&provider0>, + <&provider1 7>; + phandle-list-names = "first", "second", "third"; + + phandle-list-bad-phandle = <12345678 0 0>; + phandle-list-bad-args = <&provider2 1 0>, + <&provider3 0>; + empty-property; + unterminated-string = [40 41 42 43]; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/testcases/tests.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/testcases/tests.dtsi new file mode 100644 index 000000000..a7c506762 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/testcases/tests.dtsi @@ -0,0 +1 @@ +/include/ "tests-phandle.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/usb_a9g20-dab-mmx.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/usb_a9g20-dab-mmx.dtsi new file mode 100644 index 000000000..ad3eca17c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/usb_a9g20-dab-mmx.dtsi @@ -0,0 +1,96 @@ +/* + * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ + +/ { + ahb { + apb { + usart1: serial@fffb4000 { + status = "okay"; + }; + + usart3: serial@fffd0000 { + status = "okay"; + }; + }; + }; + + i2c-gpio@0 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "user_led1"; + gpios = <&pioB 20 1>; + }; + +/* +* led already used by mother board but active as high +* user_led2 { +* label = "user_led2"; +* gpios = <&pioB 21 1>; +* }; +*/ + user_led3 { + label = "user_led3"; + gpios = <&pioB 22 1>; + }; + + user_led4 { + label = "user_led4"; + gpios = <&pioB 23 1>; + }; + + red { + label = "red"; + gpios = <&pioB 24 1>; + }; + + orange { + label = "orange"; + gpios = <&pioB 30 1>; + }; + + green { + label = "green"; + gpios = <&pioB 31 1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb1 { + label = "user_pb1"; + gpios = <&pioB 25 1>; + linux,code = <0x100>; + }; + + user_pb2 { + label = "user_pb2"; + gpios = <&pioB 13 1>; + linux,code = <0x101>; + }; + + user_pb3 { + label = "user_pb3"; + gpios = <&pioA 26 1>; + linux,code = <0x102>; + }; + + user_pb4 { + label = "user_pb4"; + gpios = <&pioC 9 1>; + linux,code = <0x103>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/usb_a9g20.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/usb_a9g20.dts new file mode 100644 index 000000000..7c2399c53 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/usb_a9g20.dts @@ -0,0 +1,130 @@ +/* + * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "at91sam9g20.dtsi" + +/ { + model = "Calao USB A9G20"; + compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 0>; + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xa0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4a0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7ca0000 0x8360000>; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led { + label = "user_led"; + gpios = <&pioB 21 1>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb { + label = "user_pb"; + gpios = <&pioB 10 1>; + linux,code = <28>; + gpio-key,wakeup; + }; + }; + + i2c@0 { + status = "okay"; + + rv3029c2@56 { + compatible = "rv3029c2"; + reg = <0x56>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/versatile-ab.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/versatile-ab.dts new file mode 100644 index 000000000..e2fe3195c --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/versatile-ab.dts @@ -0,0 +1,192 @@ +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "ARM Versatile AB"; + compatible = "arm,versatile-ab"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + }; + + memory { + reg = <0x0 0x08000000>; + }; + + flash@34000000 { + compatible = "arm,versatile-flash"; + reg = <0x34000000 0x4000000>; + bank-width = <4>; + }; + + i2c0: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + net@10010000 { + compatible = "smsc,lan91c111"; + reg = <0x10010000 0x10000>; + interrupts = <25>; + }; + + lcd@10008000 { + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: intc@10140000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10140000 0x1000>; + }; + + sic: intc@10003000 { + compatible = "arm,versatile-sic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10003000 0x1000>; + interrupt-parent = <&vic>; + interrupts = <31>; /* Cascaded to vic */ + }; + + dma@10130000 { + compatible = "arm,pl081", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupts = <17>; + }; + + uart0: uart@101f1000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f1000 0x1000>; + interrupts = <12>; + }; + + uart1: uart@101f2000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f2000 0x1000>; + interrupts = <13>; + }; + + uart2: uart@101f3000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f3000 0x1000>; + interrupts = <14>; + }; + + smc@10100000 { + compatible = "arm,primecell"; + reg = <0x10100000 0x1000>; + }; + + mpmc@10110000 { + compatible = "arm,primecell"; + reg = <0x10110000 0x1000>; + }; + + display@10120000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x10120000 0x1000>; + interrupts = <16>; + }; + + sctl@101e0000 { + compatible = "arm,primecell"; + reg = <0x101e0000 0x1000>; + }; + + watchdog@101e1000 { + compatible = "arm,primecell"; + reg = <0x101e1000 0x1000>; + interrupts = <0>; + }; + + gpio0: gpio@101e4000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e4000 0x1000>; + gpio-controller; + interrupts = <6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@101e5000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e5000 0x1000>; + interrupts = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rtc@101e8000 { + compatible = "arm,pl030", "arm,primecell"; + reg = <0x101e8000 0x1000>; + interrupts = <10>; + }; + + sci@101f0000 { + compatible = "arm,primecell"; + reg = <0x101f0000 0x1000>; + interrupts = <15>; + }; + + ssp@101f4000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x101f4000 0x1000>; + interrupts = <11>; + }; + + fpga { + compatible = "arm,versatile-fpga", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10000000 0x10000>; + + aaci@4000 { + compatible = "arm,primecell"; + reg = <0x4000 0x1000>; + interrupts = <24>; + }; + mmc@5000 { + compatible = "arm,primecell"; + reg = < 0x5000 0x1000>; + interrupts = <22 34>; + }; + kmi@6000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x6000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <3>; + }; + kmi@7000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x7000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <4>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/versatile-pb.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/versatile-pb.dts new file mode 100644 index 000000000..7e8175269 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/versatile-pb.dts @@ -0,0 +1,50 @@ +/include/ "versatile-ab.dts" + +/ { + model = "ARM Versatile PB"; + compatible = "arm,versatile-pb"; + + amba { + gpio2: gpio@101e6000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e6000 0x1000>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@101e7000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e7000 0x1000>; + interrupts = <9>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + fpga { + uart@9000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x9000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <6>; + }; + sci@a000 { + compatible = "arm,primecell"; + reg = <0xa000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <5>; + }; + mmc@b000 { + compatible = "arm,primecell"; + reg = <0xb000 0x1000>; + interrupts = <23 34>; + }; + }; + }; +}; + +/include/ "testcases/tests.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2m-rs1.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2m-rs1.dtsi new file mode 100644 index 000000000..16076e2d0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2m-rs1.dtsi @@ -0,0 +1,201 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * RS1 memory map ("ARM Cortex-A Series memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * original variant (vexpress-v2m.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m.dtsi! + */ + +/ { + aliases { + arm,v2m_timer = &v2m_timer01; + }; + + motherboard { + compatible = "simple-bus"; + arm,v2m-memory-map = "rs1"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@1,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <1 0x00000000 0x02000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + }; + + usb@2,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <2 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + }; + + sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@030000 { + compatible = "arm,versatile-i2c"; + reg = <0x030000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@160000 { + compatible = "arm,versatile-i2c"; + reg = <0x160000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + }; + + compact-flash@1a0000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a0000 0x100 + 0x1a0100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2m.dtsi b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2m.dtsi new file mode 100644 index 000000000..a6c9c7c82 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2m.dtsi @@ -0,0 +1,200 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * Original memory map ("Legacy memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m-rs1.dtsi! + */ + +/ { + aliases { + arm,v2m_timer = &v2m_timer01; + }; + + motherboard { + compatible = "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <1 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@2,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <2 0x00000000 0x02000000>; + bank-width = <4>; + }; + + vram@3,00000000 { + compatible = "arm,vexpress-vram"; + reg = <3 0x00000000 0x00800000>; + }; + + ethernet@3,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <3 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + }; + + usb@3,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <3 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@7,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 7 0 0x20000>; + + sysreg@00000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + }; + + sysctl@01000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x01000 0x1000>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@02000 { + compatible = "arm,versatile-i2c"; + reg = <0x02000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@04000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x04000 0x1000>; + interrupts = <11>; + }; + + mmci@05000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x05000 0x1000>; + interrupts = <9 10>; + }; + + kmi@06000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x06000 0x1000>; + interrupts = <12>; + }; + + kmi@07000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x07000 0x1000>; + interrupts = <13>; + }; + + v2m_serial0: uart@09000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000 0x1000>; + interrupts = <5>; + }; + + v2m_serial1: uart@0a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a000 0x1000>; + interrupts = <6>; + }; + + v2m_serial2: uart@0b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b000 0x1000>; + interrupts = <7>; + }; + + v2m_serial3: uart@0c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c000 0x1000>; + interrupts = <8>; + }; + + wdt@0f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f000 0x1000>; + interrupts = <0>; + }; + + v2m_timer01: timer@11000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x11000 0x1000>; + interrupts = <2>; + }; + + v2m_timer23: timer@12000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x12000 0x1000>; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@16000 { + compatible = "arm,versatile-i2c"; + reg = <0x16000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@17000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x17000 0x1000>; + interrupts = <4>; + }; + + compact-flash@1a000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a000 0x100 + 0x1a100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f000 0x1000>; + interrupts = <14>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca15-tc1.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca15-tc1.dts new file mode 100644 index 000000000..941b161ab --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca15-tc1.dts @@ -0,0 +1,157 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A15x2 (version with Test Chip 1) + * Cortex-A15 MPCore (V2P-CA15) + * + * HBI-0237A + */ + +/dts-v1/; + +/ { + model = "V2P-CA15"; + arm,hbi = <0x237>; + compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + hdlcd@2b000000 { + compatible = "arm,hdlcd"; + reg = <0x2b000000 0x1000>; + interrupts = <0 85 4>; + }; + + memory-controller@2b0a0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x2b0a0000 0x1000>; + }; + + wdt@2b060000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x2b060000 0x1000>; + interrupts = <98>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x100>; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x7ffd0000 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + }; + + dma@7ffb0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x7ffb0000 0x1000>; + interrupts = <0 92 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; + interrupts = <0 68 4>, + <0 69 4>; + }; + + motherboard { + ranges = <0 0 0x08000000 0x04000000>, + <1 0 0x14000000 0x04000000>, + <2 0 0x18000000 0x04000000>, + <3 0 0x1c000000 0x04000000>, + <4 0 0x0c000000 0x04000000>, + <5 0 0x10000000 0x04000000>; + + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + }; +}; + +/include/ "vexpress-v2m-rs1.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca5s.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca5s.dts new file mode 100644 index 000000000..6905e66d4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca5s.dts @@ -0,0 +1,162 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A5x2 + * Cortex-A5 MPCore (V2P-CA5s) + * + * HBI-0225B + */ + +/dts-v1/; + +/ { + model = "V2P-CA5s"; + arm,hbi = <0x225>; + compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + hdlcd@2a110000 { + compatible = "arm,hdlcd"; + reg = <0x2a110000 0x1000>; + interrupts = <0 85 4>; + }; + + memory-controller@2a150000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x2a150000 0x1000>; + }; + + memory-controller@2a190000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x2a190000 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + }; + + scu@2c000000 { + compatible = "arm,cortex-a5-scu"; + reg = <0x2c000000 0x58>; + }; + + timer@2c000600 { + compatible = "arm,cortex-a5-twd-timer"; + reg = <0x2c000600 0x38>; + interrupts = <1 2 0x304>, + <1 3 0x304>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c000100 0x100>; + }; + + L2: cache-controller@2c0f0000 { + compatible = "arm,pl310-cache"; + reg = <0x2c0f0000 0x1000>; + interrupts = <0 84 4>; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; + interrupts = <0 68 4>, + <0 69 4>; + }; + + motherboard { + ranges = <0 0 0x08000000 0x04000000>, + <1 0 0x14000000 0x04000000>, + <2 0 0x18000000 0x04000000>, + <3 0 0x1c000000 0x04000000>, + <4 0 0x0c000000 0x04000000>, + <5 0 0x10000000 0x04000000>; + + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + }; +}; + +/include/ "vexpress-v2m-rs1.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca9.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca9.dts new file mode 100644 index 000000000..da778693b --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/vexpress-v2p-ca9.dts @@ -0,0 +1,192 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A9x4 + * Cortex-A9 MPCore (V2P-CA9) + * + * HBI-0191B + */ + +/dts-v1/; + +/ { + model = "V2P-CA9"; + arm,hbi = <0x191>; + compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupts = <0 44 4>; + }; + + memory-controller@100e0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x100e0000 0x1000>; + }; + + memory-controller@100e1000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x100e1000 0x1000>; + interrupts = <0 45 4>, + <0 46 4>; + }; + + timer@100e4000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x100e4000 0x1000>; + interrupts = <0 48 4>, + <0 49 4>; + }; + + watchdog@100e5000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x100e5000 0x1000>; + interrupts = <0 51 4>; + }; + + scu@1e000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000000 0x58>; + }; + + timer@1e000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e000600 0x20>; + interrupts = <1 2 0xf04>, + <1 3 0xf04>; + }; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000100 0x100>; + }; + + L2: cache-controller@1e00a000 { + compatible = "arm,pl310-cache"; + reg = <0x1e00a000 0x1000>; + interrupts = <0 43 4>; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + motherboard { + ranges = <0 0 0x40000000 0x04000000>, + <1 0 0x44000000 0x04000000>, + <2 0 0x48000000 0x04000000>, + <3 0 0x4c000000 0x04000000>, + <7 0 0x10000000 0x00020000>; + + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + }; +}; + +/include/ "vexpress-v2m.dtsi" diff --git a/kernel/arch/arm/boot/dts/m7350-un-v3/zynq-ep107.dts b/kernel/arch/arm/boot/dts/m7350-un-v3/zynq-ep107.dts new file mode 100644 index 000000000..37ca192fb --- /dev/null +++ b/kernel/arch/arm/boot/dts/m7350-un-v3/zynq-ep107.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/ { + model = "Xilinx Zynq EP107"; + compatible = "xlnx,zynq-ep107"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk"; + linux,stdout-path = &uart0; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f8f01000 { + interrupt-controller; + compatible = "arm,gic"; + reg = <0xF8F01000 0x1000>; + #interrupt-cells = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + reg = <0xE0000000 0x1000>; + interrupts = <59 0>; + clock = <50000000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/msm9625.dtsi b/kernel/arch/arm/boot/dts/msm9625.dtsi index b1f722d95..e57b976e8 100755 --- a/kernel/arch/arm/boot/dts/msm9625.dtsi +++ b/kernel/arch/arm/boot/dts/msm9625.dtsi @@ -720,7 +720,7 @@ qcom,msm-mem-hole { compatible = "qcom,msm-mem-hole"; - qcom,memblock-remove = <0x1c00000 0x4c00000>; /* Address and Size of Hole */ + qcom,memblock-remove = <0x1c00000 0x4800000>; /* Address and Size of Hole */ }; sfpb_spinlock: qcom,ipc-spinlock@fd484000 { diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/am3517_mt_ventoux.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/am3517_mt_ventoux.dts new file mode 100644 index 000000000..5eb26d7d9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/am3517_mt_ventoux.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011 Ilya Yanok, EmCraft Systems + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TeeJet Mt.Ventoux"; + compatible = "teejet,mt_ventoux", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* AM35xx doesn't have IVA */ + soc { + iva { + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026-mtp.dts new file mode 100644 index 000000000..e14a68568 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/include/ "apq8026.dtsi" +/include/ "msm8226-mtp.dtsi" + +/ { + model = "Qualcomm APQ 8026 MTP"; + compatible = "qcom,apq8026-mtp", "qcom,apq8026", "qcom,mtp"; + qcom,msm-id = <199 8 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026-xpm.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026-xpm.dts new file mode 100644 index 000000000..67152af2d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026-xpm.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/include/ "apq8026.dtsi" +/include/ "msm8226-cdp.dtsi" + +/ { + model = "Qualcomm APQ 8026 XPM"; + compatible = "qcom,apq8026-xpm", "qcom,apq8026", "qcom,xpm"; + qcom,msm-id = <199 14 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026.dtsi new file mode 100644 index 000000000..db6576a0d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8026.dtsi @@ -0,0 +1,24 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Only 8026-specific property overrides should be placed inside this + * file. Device definitions should be placed inside the msm8226.dtsi + * file. + */ + +/include/ "msm8226.dtsi" + +/ { + model = "Qualcomm APQ 8026"; + compatible = "qcom,apq8026"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-dragonboard.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-dragonboard.dtsi new file mode 100644 index 000000000..6b4d1d339 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-dragonboard.dtsi @@ -0,0 +1,654 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-sharp-qhd-video.dtsi" +/include/ "msm8974-camera-sensor-dragonboard.dtsi" +/include/ "msm8974-leds.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_dsi_sharp_qhd_video { + status = "ok"; + }; + + qcom,hdmi_tx@fd922100 { + status = "ok"; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + general { + label = "general"; + gpios = <&pm8941_gpios 23 0x1>; + linux,input-type = <1>; + linux,code = <102>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + bt_ar3002 { + compatible = "qca,ar3002"; + qca,bt-reset-gpio = <&pm8941_gpios 34 0>; + }; + + hsic_hub { + compatible = "qcom,hsic-smsc-hub"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + smsc,reset-gpio = <&pm8941_gpios 8 0x00>; + + hsic_host: hsic@f9a00000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a00000 0x400>; + #address-cells = <0>; + interrupt-parent = <&hsic_host>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 136 0 + 1 &intc 0 148 0 + 2 &msmgpio 144 0x8>; + interrupt-names = "core_irq", "async_irq", "wakeup"; + HSIC_VDDCX-supply = <&pm8841_s2>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + hsic,strobe-gpio = <&msmgpio 144 0x00>; + hsic,data-gpio = <&msmgpio 145 0x00>; + hsic,ignore-cal-pad-config; + hsic,strobe-pad-offset = <0x2050>; + hsic,data-pad-offset = <0x2054>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>; + }; + }; + + i2c@f9923000 { + status = "ok"; + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l18>; + vcc_i2c-supply = <&pm8941_s3>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 566 1067>; + atmel,display-coords = <0 0 540 960>; + atmel,i2c-pull-up; + atmel,cfg_1 { + atmel,family-id = <0x81>; + atmel,variant-id = <0x19>; + atmel,version = <0x10>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 38, Instance = 0 */ + 0F 02 00 17 04 0C 00 00 + /* Object 7, Instance = 0 */ + 30 FF 19 + /* Object 8, Instance = 0 */ + 1B 00 05 01 00 00 08 08 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 13 0B 00 10 23 01 03 + 0A 0F 01 0B 04 05 28 0A 2B 04 + 36 02 00 00 00 00 8F 28 8F 50 + 12 0F 32 32 02 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 + /* Object 23, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 00 00 00 00 + /* Object 42, Instance = 0 */ + 00 00 00 00 00 00 00 00 + /* Object 46, Instance = 0 */ + 00 03 10 30 00 00 01 00 00 + /* Object 47, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + /* Object 48, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <540>; + qcom,disp-maxy = <960>; + qcom,panel-maxx = <566>; + qcom,panel-maxy = <1067>; + qcom,key-codes = <158 139 102 217>; + }; + + sound { + qcom,model = "apq8074-taiko-db-snd-card"; + qcom,hdmi-audio-rx; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "AMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic4", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic6", + "AMIC6", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic7", + "DMIC1", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic1", + "DMIC2", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic2", + "DMIC3", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4", + "DMIC5", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic5", + "DMIC6", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic6"; + }; + + qcom,pronto@fb21b000 { + status = "disabled"; + }; + + qcom,iris-fm { + status = "disabled"; + }; + + qcom,wcnss-wlan@fb000000 { + status = "disabled"; + }; + + qcom,smd-wcnss { + status = "disabled"; + }; + + qcom,smsm-wcnss { + status = "disabled"; + }; +}; + +&mdss_fb0 { + qcom,memory-reservation-size = <0x1000000>; /* size 16MB */ +}; + +&sdcc3 { + qcom,sup-voltages = <2000 2000>; + status = "ok"; +}; + +&pm8941_l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + regulator-always-on; +}; + +&pm8941_l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + regulator-always-on; +}; + +&uart7 { + status = "ok"; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; +}; + +&usb_otg { + status = "ok"; + qcom,hsusb-otg-otg-control = <2>; + qcom,hsusb-otg-mode = <3>; + vbus_otg-supply = <&pm8941_mvs1>; + qcom,usb2-enable-hsphy2; + qcom,dp-manual-pullup; + + #address-cells = <0>; + interrupt-parent = <&usb_otg>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 134 0 + 1 &intc 0 140 0 + 2 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "core_irq", "async_irq", "pmic_id_irq"; +}; + +&usb3 { + qcom,charging-disabled; + vbus_dwc3-supply = <0>; + dwc3@f9200000 { + host-only-mode; + }; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias2-ext-cap; + qcom,cdc-micbias3-ext-cap; + }; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c500 { /* GPIO 6 */ + /* TUSB3_HUB-RESET */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <0>; /* QPNP_PIN_PULL_30 */ + qcom,vin-sel = <0>; /* QPNP_PIN_VIN0 VPH */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; /* Keep it out of reset */ + qcom,master-en = <1>; + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + /* HSIC_HUB-RESET */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,pull = <5>; /* PULL_NO */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,master-en = <1>; + }; + + gpio@c800 { /* GPIO 9 */ + /* GbE_RST_N */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <0>; /* QPNP_PIN_PULL_30 */ + qcom,vin-sel = <0>; /* QPNP_PIN_VIN0 VPH */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; /* Keep it out of reset */ + qcom,master-en = <1>; + }; + + gpio@c900 { /* GPIO 10 */ + /* SATA_RST_N */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <0>; /* QPNP_PIN_PULL_30 */ + qcom,vin-sel = <0>; /* QPNP_PIN_VIN0 VPH */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; /* Keep it out of reset */ + qcom,master-en = <1>; + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; + + gpio@d600 { /* GPIO 23 */ + }; + + gpio@d700 { /* GPIO 24 */ + }; + + gpio@d800 { /* GPIO 25 */ + }; + + gpio@d900 { /* GPIO 26 */ + }; + + gpio@da00 { /* GPIO 27 */ + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,pull = <0>; /* set to default pull */ + qcom,master-en = <1>; + qcom,vin-sel = <2>; /* select 1.8 V source */ + }; + + gpio@dd00 { /* GPIO 30 */ + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + }; + + gpio@e000 { /* GPIO 33 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; + qcom,master-en = <1>; + }; + + gpio@e100 { /* GPIO 34 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <0>; + qcom,master-en = <1>; + }; + + gpio@e200 { /* GPIO 35 */ + }; + + gpio@e300 { /* GPIO 36 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <3>; /* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */ + qcom,master-en = <1>; + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3*/ + }; + + mpp@a300 { /* MPP 4*/ + }; +}; + +&spi_epm { + epm-adc@0 { + compatible = "cy,epm-adc-cy8c5568lti-114"; + reg = <0>; + interrupt-parent = <&msmgpio>; + spi-max-frequency = <960000>; + qcom,channels = <31>; + qcom,gain = <50 50 50 50 50 100 50 50 50 50 + 50 50 50 50 100 50 50 50 50 100 + 50 50 50 100 50 50 50 1 1 1 + 1>; + qcom,rsense = <40 10 10 25 10 1000 75 25 10 25 + 33 500 200 10 500 100 33 200 25 100 + 75 500 50 200 5 5 3 1 1 1 + 1>; + qcom,channel-type = <0xf0000000>; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d000 { + qcom,rgb_2 { + status = "ok"; + qcom,default-state = "on"; + qcom,turn-off-delay-ms = <1000>; + }; + }; + + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <20>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <1>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + }; +}; + +&pm8941_chg { + status = "ok"; + + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v1.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v1.dtsi new file mode 100644 index 000000000..c4e7b7c3c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v1.dtsi @@ -0,0 +1,48 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8974.dtsi file. + */ + +/include/ "msm8974-v1.dtsi" + +&soc { + qcom,qseecom@a700000 { + compatible = "qcom,qseecom"; + reg = <0x0a700000 0x500000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <1>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; +}; + +&memory_hole { + qcom,memblock-remove = <0x0a700000 0x5800000>; /* Address and size of the hole */ +}; + +&qseecom { + status = "disabled"; +}; + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2-dragonboard.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2-dragonboard.dts new file mode 100644 index 000000000..5a6f5f3bf --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2-dragonboard.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "apq8074-v2.dtsi" +/include/ "apq8074-dragonboard.dtsi" + +/ { + model = "Qualcomm APQ 8074v2 DRAGONBOARD"; + compatible = "qcom,apq8074-dragonboard", "qcom,apq8074", "qcom,dragonboard"; + qcom,msm-id = <184 10 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2-liquid.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2-liquid.dts new file mode 100644 index 000000000..4ec1cdd17 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2-liquid.dts @@ -0,0 +1,34 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "apq8074-v2.dtsi" +/include/ "msm8974-liquid.dtsi" + +/ { + model = "Qualcomm APQ 8074v2 LIQUID"; + compatible = "qcom,apq8074-liquid", "qcom,apq8074", "qcom,liquid"; + qcom,msm-id = <184 9 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2.dtsi new file mode 100644 index 000000000..76eb14b96 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8074-v2.dtsi @@ -0,0 +1,52 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8974.dtsi file. + */ + +/include/ "msm8974-v2.dtsi" + +&soc { + qcom,qseecom@a700000 { + compatible = "qcom,qseecom"; + reg = <0x0a700000 0x500000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <1>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; + + sound { + compatible = "qcom,apq8074-audio-taiko"; + }; +}; + +&memory_hole { + qcom,memblock-remove = <0x0a700000 0x5800000>; /* Address and size of the hole */ +}; + +&qseecom { + status = "disabled"; +}; + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-ion.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-ion.dtsi new file mode 100644 index 000000000..ea954b89c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-ion.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-regulator.dtsi new file mode 100644 index 000000000..998b46906 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-regulator.dtsi @@ -0,0 +1,377 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* QPNP controlled regulators: */ + +&spmi_bus { + qcom,pma8084@1 { + pma8084_s1: regulator@1400 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + /* PMA8084 S2 + S12 = 2 phase VDD_CX supply */ + pma8084_s2: regulator@1700 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s3: regulator@1a00 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s4: regulator@1d00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s5: regulator@2000 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + /* PMA8084 S6 + S7 = 2 phase VDD_GFX supply */ + pma8084_s6: regulator@2300 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + /* PMA8084 S8 + S9 + S10 + S11 = 4 phase VDD_APC supply */ + pma8084_s8: regulator@2900 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + /* Output of PMA8084 L1 and L11 is tied together. */ + pma8084_l1: regulator@4000 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <10000>; + status = "okay"; + }; + + pma8084_l2: regulator@4100 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l3: regulator@4200 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l4: regulator@4300 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l6: regulator@4500 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l8: regulator@4700 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l9: regulator@4800 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l10: regulator@4900 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l12: regulator@4b00 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l13: regulator@4c00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l14: regulator@4d00 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l15: regulator@4e00 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l16: regulator@4f00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l17: regulator@5000 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l18: regulator@5100 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l19: regulator@5200 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l20: regulator@5300 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l21: regulator@5400 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l22: regulator@5500 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l23: regulator@5600 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l24: regulator@5700 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l25: regulator@5800 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l26: regulator@5900 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l27: regulator@5a00 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs1: regulator@8000 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs2: regulator@8100 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs3: regulator@8200 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs4: regulator@8300 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_mvs1: regulator@8400 { + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + }; +}; + +&rpm_bus { + rpm-regulator-smpb1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + + pma8084_s1_ao: regulator-s1-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8084_s1_ao"; + qcom,set = <1>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + }; + + rpm-regulator-smpb2 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + + pma8084_s2_corner_ao: regulator-s2-corner-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8084_s2_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + + pma8084_l12_ao: regulator-l12-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8084_l12_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-sim.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-sim.dts new file mode 100644 index 000000000..e206d4dd0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-sim.dts @@ -0,0 +1,173 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "apq8084.dtsi" + +/ { + model = "Qualcomm APQ 8084 Simulator"; + compatible = "qcom,apq8084-sim", "qcom,apq8084", "qcom,sim"; + qcom,msm-id = <178 0 0>; + + aliases { + serial0 = &uart0; + }; +}; + +&soc { + uart0: serial@f991f000 { + status = "ok"; + }; +}; + +&sdcc1 { + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdcc2 { + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + qcom,vdd-io-lpm-sup; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + status = "ok"; +}; + +&pma8084_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + }; + + gpio@cf00 { /* GPIO 16 */ + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; +}; + +&pma8084_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&usb3 { + qcom,skip-charger-detection; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-smp2p.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-smp2p.dtsi new file mode 100644 index 000000000..b1d21ffd7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084-smp2p.dtsi @@ -0,0 +1,82 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084.dtsi new file mode 100644 index 000000000..b39f5690a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/apq8084.dtsi @@ -0,0 +1,276 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton64.dtsi" + +/ { + model = "Qualcomm APQ 8084"; + compatible = "qcom,apq8084"; + interrupt-parent = <&intc>; + soc: soc { }; +}; + +/include/ "apq8084-ion.dtsi" +/include/ "apq8084-smp2p.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <146>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + qcom,cache_erp { + compatible = "qcom,cache_erp"; + interrupts = <1 9 0>, <0 2 0>; + interrupt-names = "l1_irq", "l2_irq"; + }; + + qcom,cache_dump { + compatible = "qcom,cache_dump"; + qcom,l1-dump-size = <0x100000>; + qcom,l2-dump-size = <0x500000>; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x600000>; /* 6M EBI1 buffer */ + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + rpm-standalone; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>; + reg-names = "core_mem"; + interrupts = <0 123 0>; + interrupt-names = "core_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>; + reg-names = "core_mem"; + interrupts = <0 125 0>; + interrupt-names = "core_irq"; + + + qcom,bus-width = <4>; + status = "disabled"; + }; + + qcom,sps@f9980000 { + compatible = "qcom,msm_sps"; + reg = <0xf9984000 0x15000>, + <0xf9999000 0xb000>; + interrupts = <0 94 0>; + qcom,pipe-attr-ee; + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0>, <0 187 0>; + qcom,not-wakeup; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + i2c_0: i2c@f9925000 { /* BLSP1 QUP3 */ + cell-index = <0>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9925000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 97 0>; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <50000000>; + qcom,sda-gpio = <&msmgpio 10 0>; + qcom,scl-gpio = <&msmgpio 11 0>; + }; + + usb3: qcom,ssusb@f9200000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xf9200000 0xfc000>, + <0xfd4ab000 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupts = <0 133 0>; + interrupt-names = "hs_phy_irq"; + ssusb_vdd_dig-supply = <&pma8084_s1>; + SSUSB_1p8-supply = <&pma8084_l6>; + hsusb_vdd_dig-supply = <&pma8084_s1>; + HSUSB_1p8-supply = <&pma8084_l6>; + HSUSB_3p3-supply = <&pma8084_l24>; + qcom,dwc-usb3-msm-dbm-eps = <4>; + qcom,vdd-voltage-level = <0 900000 1050000>; + + dwc3@f9200000 { + compatible = "synopsys,dwc3"; + reg = <0xf9200000 0xfc000>; + interrupt-parent = <&intc>; + interrupts = <0 131 0>, <0 179 0>; + interrupt-names = "irq", "otg_irq"; + tx-fifo-resize; + }; + }; + + android_usb { + compatible = "qcom,android-usb"; + }; + + qcom,ocmem@fdd00000 { + compatible = "qcom,msm-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfdd02000 0x2000>, + <0xfe039000 0x400>, + <0xfec00000 0x200000>; + reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical"; + interrupts = <0 76 0 0 77 0>; + interrupt-names = "ocmem_irq", "dm_irq"; + qcom,ocmem-num-regions = <0x4>; + qcom,ocmem-num-macros = <0x20>; + qcom,resource-type = <0x706d636f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfec00000 0x200000>; + + partition@0 { + reg = <0x0 0x180000>; + qcom,ocmem-part-name = "graphics"; + qcom,ocmem-part-min = <0x80000>; + }; + + partition@80000 { + reg = <0x180000 0x80000>; + qcom,ocmem-part-name = "lp_audio"; + qcom,ocmem-part-min = <0x80000>; + }; + + partition@100000 { + reg = <0x180000 0x80000>; + qcom,ocmem-part-name = "video"; + qcom,ocmem-part-min = <0x55000>; + }; + + }; + + memory_hole: qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x0dc00000 0x2000000>; /* Address and Size of Hole */ + }; + + qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + qcom,smem@fa00000 { + compatible = "qcom,smem"; + reg = <0xfa00000 0x200000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; +}; + +/include/ "msm-pma8084.dtsi" +/include/ "apq8084-regulator.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g20.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g20.dtsi new file mode 100644 index 000000000..773ef4840 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g20.dtsi @@ -0,0 +1,238 @@ +/* + * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre , + * 2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Atmel AT91SAM9G20 family SoC"; + compatible = "atmel,at91sam9g20"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + serial5 = &usart4; + serial6 = &usart5; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + reg = <0x20000000 0x08000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <2>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 4>; + }; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffa0000 0x100>; + interrupts = <17 4 18 4 19 4>; + }; + + tcb1: timer@fffdc000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffdc000 0x100>; + interrupts = <26 4 27 4 28 4>; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <4 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 4>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + interrupts = <6 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + interrupts = <7 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart2: serial@fffb8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + interrupts = <8 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart3: serial@fffd0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd0000 0x200>; + interrupts = <23 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart4: serial@fffd4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd4000 0x200>; + interrupts = <24 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart5: serial@fffd8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffd8000 0x200>; + interrupts = <25 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + macb0: ethernet@fffc4000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffc4000 0x100>; + interrupts = <21 4>; + status = "disabled"; + }; + + usb1: gadget@fffa4000 { + compatible = "atmel,at91rm9200-udc"; + reg = <0xfffa4000 0x4000>; + interrupts = <10 4>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe800 0x200 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + gpios = <&pioC 13 0 + &pioC 14 0 + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <20 4>; + status = "disabled"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioA 23 0 /* sda */ + &pioA 24 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g25ek.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g25ek.dts new file mode 100644 index 000000000..7829a4d0c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g25ek.dts @@ -0,0 +1,49 @@ +/* + * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "at91sam9x5.dtsi" +/include/ "at91sam9x5cm.dtsi" + +/ { + model = "Atmel AT91SAM9G25-EK"; + compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@f801c000 { + status = "okay"; + }; + + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + }; + + usb0: ohci@00600000 { + status = "okay"; + num-ports = <2>; + atmel,vbus-gpio = <&pioD 19 1 + &pioD 20 1 + >; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g45.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g45.dtsi new file mode 100644 index 000000000..c8042147e --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9g45.dtsi @@ -0,0 +1,247 @@ +/* + * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC + * applies to AT91SAM9G45, AT91SAM9M10, + * AT91SAM9G46, AT91SAM9M11 SoC + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Atmel AT91SAM9G45 family SoC"; + compatible = "atmel,at91sam9g45"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + reg = <0x70000000 0x10000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <2>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + }; + + ramc0: ramc@ffffe400 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe400 0x200 + 0xffffe600 0x200>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffd00 0x10>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 4>; + }; + + + shdwc@fffffd10 { + compatible = "atmel,at91sam9rl-shdwc"; + reg = <0xfffffd10 0x10>; + }; + + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfff7c000 0x100>; + interrupts = <18 4>; + }; + + tcb1: timer@fffd4000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffd4000 0x100>; + interrupts = <18 4>; + }; + + dma: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <21 4>; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <4 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <5 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <5 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; + interrupts = <1 4>; + status = "disabled"; + }; + + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x200>; + interrupts = <7 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart1: serial@fff90000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff90000 0x200>; + interrupts = <8 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart2: serial@fff94000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff94000 0x200>; + interrupts = <9 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart3: serial@fff98000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff98000 0x200>; + interrupts = <10 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + macb0: ethernet@fffbc000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; + interrupts = <25 4>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe200 0x200 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + gpios = <&pioC 8 0 + &pioC 14 0 + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00700000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00700000 0x100000>; + interrupts = <22 4>; + status = "disabled"; + }; + + usb1: ehci@00800000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00800000 0x100000>; + interrupts = <22 4>; + status = "disabled"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioA 20 0 /* sda */ + &pioA 21 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <5>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9m10g45ek.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9m10g45ek.dts new file mode 100644 index 000000000..a3633bd13 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9m10g45ek.dts @@ -0,0 +1,156 @@ +/* + * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "at91sam9g45.dtsi" + +/ { + model = "Atmel AT91SAM9M10G45-EK"; + compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2"; + }; + + memory { + reg = <0x70000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + usart1: serial@fff90000 { + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + boot@0 { + label = "bootstrap/uboot/kernel"; + reg = <0x0 0x400000>; + }; + + rootfs@400000 { + label = "rootfs"; + reg = <0x400000 0x3C00000>; + }; + + data@4000000 { + label = "data"; + reg = <0x4000000 0xC000000>; + }; + }; + + usb0: ohci@00700000 { + status = "okay"; + num-ports = <2>; + atmel,vbus-gpio = <&pioD 1 1 + &pioD 3 1>; + }; + + usb1: ehci@00800000 { + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + d8 { + label = "d8"; + gpios = <&pioD 30 0>; + linux,default-trigger = "heartbeat"; + }; + + d6 { + label = "d6"; + gpios = <&pioD 0 1>; + linux,default-trigger = "nand-disk"; + }; + + d7 { + label = "d7"; + gpios = <&pioD 31 1>; + linux,default-trigger = "mmc0"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + left_click { + label = "left_click"; + gpios = <&pioB 6 1>; + linux,code = <272>; + gpio-key,wakeup; + }; + + right_click { + label = "right_click"; + gpios = <&pioB 7 1>; + linux,code = <273>; + gpio-key,wakeup; + }; + + left { + label = "Joystick Left"; + gpios = <&pioB 14 1>; + linux,code = <105>; + }; + + right { + label = "Joystick Right"; + gpios = <&pioB 15 1>; + linux,code = <106>; + }; + + up { + label = "Joystick Up"; + gpios = <&pioB 16 1>; + linux,code = <103>; + }; + + down { + label = "Joystick Down"; + gpios = <&pioB 17 1>; + linux,code = <108>; + }; + + enter { + label = "Joystick Press"; + gpios = <&pioB 18 1>; + linux,code = <28>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9x5.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9x5.dtsi new file mode 100644 index 000000000..dd4ed7484 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9x5.dtsi @@ -0,0 +1,263 @@ +/* + * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC + * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, + * AT91SAM9X25, AT91SAM9X35 SoC + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Atmel AT91SAM9x5 family SoC"; + compatible = "atmel,at91sam9x5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <2>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + }; + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + + rstc@fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + }; + + shdwc@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <1 4>; + }; + + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8008000 0x100>; + interrupts = <17 4>; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; + interrupts = <17 4>; + }; + + dma0: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <20 4>; + }; + + dma1: dma-controller@ffffee00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffee00 0x200>; + interrupts = <21 4>; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 4>; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x200>; + interrupts = <5 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x200>; + interrupts = <6 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x200>; + interrupts = <7 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + macb0: ethernet@f802c000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <24 4>; + status = "disabled"; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf8030000 0x100>; + interrupts = <27 4>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + gpios = <&pioD 5 0 + &pioD 4 0 + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <22 4>; + status = "disabled"; + }; + + usb1: ehci@00700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <22 4>; + status = "disabled"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = <&pioA 30 0 /* sda */ + &pioA 31 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@1 { + compatible = "i2c-gpio"; + gpios = <&pioC 0 0 /* sda */ + &pioC 1 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@2 { + compatible = "i2c-gpio"; + gpios = <&pioB 4 0 /* sda */ + &pioB 5 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9x5cm.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9x5cm.dtsi new file mode 100644 index 000000000..31e7be237 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/at91sam9x5cm.dtsi @@ -0,0 +1,74 @@ +/* + * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/ { + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pb18 { + label = "pb18"; + gpios = <&pioB 18 1>; + linux,default-trigger = "heartbeat"; + }; + + pd21 { + label = "pd21"; + gpios = <&pioD 21 0>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/db8500.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/db8500.dtsi new file mode 100644 index 000000000..14bc30705 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/db8500.dtsi @@ -0,0 +1,274 @@ +/* + * Copyright 2012 Linaro Ltd + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + soc-u9500 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500"; + interrupt-parent = <&intc>; + ranges; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = <0 13 4>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 7 0x4>; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = <1 13 0x304>; + }; + + rtc@80154000 { + compatible = "stericsson,db8500-rtc"; + reg = <0x80154000 0x1000>; + interrupts = <0 18 0x4>; + }; + + gpio0: gpio@8012e000 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8012e000 0x80>; + interrupts = <0 119 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio1: gpio@8012e080 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8012e080 0x80>; + interrupts = <0 120 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio2: gpio@8000e000 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8000e000 0x80>; + interrupts = <0 121 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio3: gpio@8000e080 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8000e080 0x80>; + interrupts = <0 122 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio4: gpio@8000e100 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8000e100 0x80>; + interrupts = <0 123 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio5: gpio@8000e180 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8000e180 0x80>; + interrupts = <0 124 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio6: gpio@8011e000 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8011e000 0x80>; + interrupts = <0 125 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio7: gpio@8011e080 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0x8011e080 0x80>; + interrupts = <0 126 0x4>; + supports-sleepmode; + gpio-controller; + }; + + gpio8: gpio@a03fe000 { + compatible = "stericsson,db8500-gpio", + "stmicroelectronics,nomadik-gpio"; + reg = <0xa03fe000 0x80>; + interrupts = <0 127 0x4>; + supports-sleepmode; + gpio-controller; + }; + + usb@a03e0000 { + compatible = "stericsson,db8500-musb", + "mentor,musb"; + reg = <0xa03e0000 0x10000>; + interrupts = <0 23 0x4>; + }; + + dma-controller@801C0000 { + compatible = "stericsson,db8500-dma40", + "stericsson,dma40"; + reg = <0x801C0000 0x1000 0x40010000 0x800>; + interrupts = <0 25 0x4>; + }; + + prcmu@80157000 { + compatible = "stericsson,db8500-prcmu"; + reg = <0x80157000 0x1000>; + interrupts = <46 47>; + #address-cells = <1>; + #size-cells = <0>; + + ab8500@5 { + compatible = "stericsson,ab8500"; + reg = <5>; /* mailbox 5 is i2c */ + interrupts = <0 40 0x4>; + }; + }; + + i2c@80004000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x80004000 0x1000>; + interrupts = <0 21 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80122000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x80122000 0x1000>; + interrupts = <0 22 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80128000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x80128000 0x1000>; + interrupts = <0 55 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80110000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x80110000 0x1000>; + interrupts = <0 12 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@8012a000 { + compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c"; + reg = <0x8012a000 0x1000>; + interrupts = <0 51 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + ssp@80002000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <80002000 0x1000>; + interrupts = <0 14 0x4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + // Add one of these for each child device + cs-gpios = <&gpio0 31 &gpio4 14 &gpio4 16 &gpio6 22 &gpio7 0>; + + }; + + uart@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <0 11 0x4>; + status = "disabled"; + }; + uart@80121000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80121000 0x1000>; + interrupts = <0 19 0x4>; + status = "disabled"; + }; + uart@80007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80007000 0x1000>; + interrupts = <0 26 0x4>; + status = "disabled"; + }; + + sdi@80126000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80126000 0x1000>; + interrupts = <0 60 0x4>; + status = "disabled"; + }; + sdi@80118000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80118000 0x1000>; + interrupts = <0 50 0x4>; + status = "disabled"; + }; + sdi@80005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80005000 0x1000>; + interrupts = <0 41 0x4>; + status = "disabled"; + }; + sdi@80119000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80119000 0x1000>; + interrupts = <0 59 0x4>; + status = "disabled"; + }; + sdi@80114000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = <0 99 0x4>; + status = "disabled"; + }; + sdi@80008000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = <0 100 0x4>; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-nt35590-720p-cmd.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-nt35590-720p-cmd.dtsi new file mode 100644 index 000000000..7942567cc --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-nt35590-720p-cmd.dtsi @@ -0,0 +1,530 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + qcom,mdss_dsi_nt35590_720p_cmd { + compatible = "qcom,mdss-dsi-panel"; + label = "nt35590 720p command mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,rst-gpio = <&msmgpio 25 0>; + qcom,te-gpio = <&msmgpio 24 0>; + qcom,mdss-pan-res = <720 1280>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <164 8 140 1 1 6>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-bl-levels = <1 4095>; + qcom,mdss-pan-dsi-mode = <1>; + qcom,mdss-vsync-enable = <1>; + qcom,mdss-hw-vsync-mode = <1>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <2>; + qcom,mdss-pan-dsi-dst-format = <8>; + qcom,mdss-pan-insert-dcs-cmd = <1>; + qcom,mdss-pan-wr-mem-continue = <0x3c>; + qcom,mdss-pan-wr-mem-start = <0x2c>; + qcom,mdss-pan-te-sel = <1>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 1 1>; /* 4 lanes */ + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x2c 0x20>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [07 09 03 00 /* Regualotor settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 00 00 00 00 00 00 01 97 /* lane0 config */ + 00 00 00 00 05 00 00 01 97 /* lane1 config */ + 00 00 00 00 0a 00 00 01 97 /* lane2 config */ + 00 00 00 00 0f 00 00 01 97 /* lane3 config */ + 00 c0 00 00 00 00 00 01 bb]; /* Clk ln config */ + qcom,panel-on-cmds = [29 01 00 00 00 02 FF EE + 29 01 00 00 00 02 26 08 + 29 01 00 00 00 02 26 00 + 29 01 00 00 10 02 FF 00 + 29 01 00 00 00 02 BA 03 + 29 01 00 00 00 02 C2 08 + 29 01 00 00 00 02 FF 01 + 29 01 00 00 00 02 FB 01 + 29 01 00 00 00 02 00 4A + 29 01 00 00 00 02 01 33 + 29 01 00 00 00 02 02 53 + 29 01 00 00 00 02 03 55 + 29 01 00 00 00 02 04 55 + 29 01 00 00 00 02 05 33 + 29 01 00 00 00 02 06 22 + 29 01 00 00 00 02 08 56 + 29 01 00 00 00 02 09 8F + 29 01 00 00 00 02 36 73 + 29 01 00 00 00 02 0B 9F + 29 01 00 00 00 02 0C 9F + 29 01 00 00 00 02 0D 2F + 29 01 00 00 00 02 0E 24 + 29 01 00 00 00 02 11 83 + 29 01 00 00 00 02 12 03 + 29 01 00 00 00 02 71 2C + 29 01 00 00 00 02 6F 03 + 29 01 00 00 00 02 0F 0A + 29 01 00 00 00 02 FF 05 + 29 01 00 00 00 02 FB 01 + 29 01 00 00 00 02 01 00 + 29 01 00 00 00 02 02 8B + 29 01 00 00 00 02 03 82 + 29 01 00 00 00 02 04 82 + 29 01 00 00 00 02 05 30 + 29 01 00 00 00 02 06 33 + 29 01 00 00 00 02 07 01 + 29 01 00 00 00 02 08 00 + 29 01 00 00 00 02 09 46 + 29 01 00 00 00 02 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01 00 00 00 02 D0 59 + 29 01 00 00 00 02 D1 02 + 29 01 00 00 00 02 D2 94 + 29 01 00 00 00 02 D3 02 + 29 01 00 00 00 02 D4 B4 + 29 01 00 00 00 02 D5 02 + 29 01 00 00 00 02 D6 E1 + 29 01 00 00 00 02 D7 03 + 29 01 00 00 00 02 D8 01 + 29 01 00 00 00 02 D9 03 + 29 01 00 00 00 02 DA 28 + 29 01 00 00 00 02 DB 03 + 29 01 00 00 00 02 DC 30 + 29 01 00 00 00 02 DD 03 + 29 01 00 00 00 02 DE 37 + 29 01 00 00 00 02 DF 03 + 29 01 00 00 00 02 E0 3B + 29 01 00 00 00 02 E1 03 + 29 01 00 00 00 02 E2 40 + 29 01 00 00 00 02 E3 03 + 29 01 00 00 00 02 E4 50 + 29 01 00 00 00 02 E5 03 + 29 01 00 00 00 02 E6 6D + 29 01 00 00 00 02 E7 03 + 29 01 00 00 00 02 E8 80 + 29 01 00 00 00 02 E9 03 + 29 01 00 00 00 02 EA CB + 29 01 00 00 00 02 FF 01 + 29 01 00 00 00 02 FB 01 + 29 01 00 00 00 02 FF 02 + 29 01 00 00 00 02 FB 01 + 29 01 00 00 00 02 FF 04 + 29 01 00 00 00 02 FB 01 + 29 01 00 00 00 02 FF 00 + 29 01 00 00 64 02 11 00 + 29 01 00 00 00 02 FF EE + 29 01 00 00 00 02 12 50 + 29 01 00 00 00 02 13 02 + 29 01 00 00 00 02 6A 60 + 29 01 00 00 00 02 FF 00 + 29 01 00 00 78 02 29 00]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 32 02 28 00 + 05 01 00 00 78 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_HS_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-nt35590-720p-video.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-nt35590-720p-video.dtsi new file mode 100644 index 000000000..7bc748d59 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-nt35590-720p-video.dtsi @@ -0,0 +1,524 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_dsi_nt35590_720p_video { + compatible = "qcom,mdss-dsi-panel"; + label = "nt35590 720p video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,rst-gpio = <&msmgpio 25 0>; + qcom,mdss-pan-res = <720 1280>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <164 8 140 1 1 6>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-bl-levels = <1 4095>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <2>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 1 1>; /* 4 lanes */ + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x2c 0x20>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [07 09 03 00 /* Regualotor settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 00 00 00 00 00 00 01 97 /* lane0 config */ + 00 00 00 00 05 00 00 01 97 /* lane1 config */ + 00 00 00 00 0a 00 00 01 97 /* lane2 config */ + 00 00 00 00 0f 00 00 01 97 /* lane3 config */ + 00 c0 00 00 00 00 00 01 bb]; /* Clk ln config */ + qcom,panel-on-cmds = [29 01 00 00 00 00 02 FF EE + 29 01 00 00 00 00 02 26 08 + 29 01 00 00 00 00 02 26 00 + 29 01 00 00 10 00 02 FF 00 + 29 01 00 00 00 00 02 BA 03 + 29 01 00 00 00 00 02 C2 03 + 29 01 00 00 00 00 02 FF 01 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 00 4A + 29 01 00 00 00 00 02 01 33 + 29 01 00 00 00 00 02 02 53 + 29 01 00 00 00 00 02 03 55 + 29 01 00 00 00 00 02 04 55 + 29 01 00 00 00 00 02 05 33 + 29 01 00 00 00 00 02 06 22 + 29 01 00 00 00 00 02 08 56 + 29 01 00 00 00 00 02 09 8F + 29 01 00 00 00 00 02 36 73 + 29 01 00 00 00 00 02 0B 9F + 29 01 00 00 00 00 02 0C 9F + 29 01 00 00 00 00 02 0D 2F + 29 01 00 00 00 00 02 0E 24 + 29 01 00 00 00 00 02 11 83 + 29 01 00 00 00 00 02 12 03 + 29 01 00 00 00 00 02 71 2C + 29 01 00 00 00 00 02 6F 03 + 29 01 00 00 00 00 02 0F 0A + 29 01 00 00 00 00 02 FF 05 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 01 00 + 29 01 00 00 00 00 02 02 8B + 29 01 00 00 00 00 02 03 82 + 29 01 00 00 00 00 02 04 82 + 29 01 00 00 00 00 02 05 30 + 29 01 00 00 00 00 02 06 33 + 29 01 00 00 00 00 02 07 01 + 29 01 00 00 00 00 02 08 00 + 29 01 00 00 00 00 02 09 46 + 29 01 00 00 00 00 02 0A 46 + 29 01 00 00 00 00 02 0D 0B + 29 01 00 00 00 00 02 0E 1D + 29 01 00 00 00 00 02 0F 08 + 29 01 00 00 00 00 02 10 53 + 29 01 00 00 00 00 02 11 00 + 29 01 00 00 00 00 02 12 00 + 29 01 00 00 00 00 02 14 01 + 29 01 00 00 00 00 02 15 00 + 29 01 00 00 00 00 02 16 05 + 29 01 00 00 00 00 02 17 00 + 29 01 00 00 00 00 02 19 7F + 29 01 00 00 00 00 02 1A FF + 29 01 00 00 00 00 02 1B 0F + 29 01 00 00 00 00 02 1C 00 + 29 01 00 00 00 00 02 1D 00 + 29 01 00 00 00 00 02 1E 00 + 29 01 00 00 00 00 02 1F 07 + 29 01 00 00 00 00 02 20 00 + 29 01 00 00 00 00 02 21 06 + 29 01 00 00 00 00 02 22 55 + 29 01 00 00 00 00 02 23 4D + 29 01 00 00 00 00 02 2D 02 + 29 01 00 00 00 00 02 28 01 + 29 01 00 00 00 00 02 2F 02 + 29 01 00 00 00 00 02 83 01 + 29 01 00 00 00 00 02 9E 58 + 29 01 00 00 00 00 02 9F 6A + 29 01 00 00 00 00 02 A0 01 + 29 01 00 00 00 00 02 A2 10 + 29 01 00 00 00 00 02 BB 0A + 29 01 00 00 00 00 02 BC 0A + 29 01 00 00 00 00 02 32 08 + 29 01 00 00 00 00 02 33 B8 + 29 01 00 00 00 00 02 36 01 + 29 01 00 00 00 00 02 37 00 + 29 01 00 00 00 00 02 43 00 + 29 01 00 00 00 00 02 4B 21 + 29 01 00 00 00 00 02 4C 03 + 29 01 00 00 00 00 02 50 21 + 29 01 00 00 00 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00 02 D0 59 + 29 01 00 00 00 00 02 D1 02 + 29 01 00 00 00 00 02 D2 94 + 29 01 00 00 00 00 02 D3 02 + 29 01 00 00 00 00 02 D4 B4 + 29 01 00 00 00 00 02 D5 02 + 29 01 00 00 00 00 02 D6 E1 + 29 01 00 00 00 00 02 D7 03 + 29 01 00 00 00 00 02 D8 01 + 29 01 00 00 00 00 02 D9 03 + 29 01 00 00 00 00 02 DA 28 + 29 01 00 00 00 00 02 DB 03 + 29 01 00 00 00 00 02 DC 30 + 29 01 00 00 00 00 02 DD 03 + 29 01 00 00 00 00 02 DE 37 + 29 01 00 00 00 00 02 DF 03 + 29 01 00 00 00 00 02 E0 3B + 29 01 00 00 00 00 02 E1 03 + 29 01 00 00 00 00 02 E2 40 + 29 01 00 00 00 00 02 E3 03 + 29 01 00 00 00 00 02 E4 50 + 29 01 00 00 00 00 02 E5 03 + 29 01 00 00 00 00 02 E6 6D + 29 01 00 00 00 00 02 E7 03 + 29 01 00 00 00 00 02 E8 80 + 29 01 00 00 00 00 02 E9 03 + 29 01 00 00 00 00 02 EA CB + 29 01 00 00 00 00 02 FF 01 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 FF 02 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 FF 04 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 FF 00 + 29 01 00 00 64 00 02 11 00 + 29 01 00 00 00 00 02 FF EE + 29 01 00 00 00 00 02 12 50 + 29 01 00 00 00 00 02 13 02 + 29 01 00 00 00 00 02 6A 60 + 29 01 00 00 00 00 02 FF 00 + 29 01 00 00 78 00 02 29 00]; + + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_HS_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-orise-720p-video.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-orise-720p-video.dtsi new file mode 100644 index 000000000..478541fb1 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-orise-720p-video.dtsi @@ -0,0 +1,60 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_dsi_orise_720p_video { + compatible = "qcom,mdss-dsi-panel"; + label = "orise 720p video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi1>; + qcom,mdss-pan-res = <720 1280>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_2"; + qcom,mdss-pan-porch-values = <32 12 144 3 4 9>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-levels = <1 255>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <0>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <1>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 1 1>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [03 01 01 00 /* Regualotor settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [69 29 1f 00 55 55 + 19 2a 2a 03 04 00]; + qcom,panel-phy-strengthCtrl = [77 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 c2 45 00 00 00 00 01 75 /* lane0 config */ + 00 c2 45 00 00 00 00 01 75 /* lane1 config */ + 00 c2 45 00 00 00 00 01 75 /* lane2 config */ + 00 c2 45 00 00 00 00 01 75 /* lane3 config */ + 00 02 45 00 00 00 00 01 97]; /* Clk ln config */ + + qcom,panel-on-cmds = [05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_LP_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-sharp-qhd-video.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-sharp-qhd-video.dtsi new file mode 100644 index 000000000..45d396cdc --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-sharp-qhd-video.dtsi @@ -0,0 +1,67 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_dsi_sharp_qhd_video { + compatible = "qcom,mdss-dsi-panel"; + label = "sharp QHD LS043T1LE01 video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,enable-gpio = <&msmgpio 58 0>; + qcom,rst-gpio = <&pm8941_gpios 19 0>; + qcom,mdss-pan-res = <540 960>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <80 32 48 15 10 3>; /* HBP, HPW, HFP, VBP, VPW, VFP */ + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-bl-levels = <1 4095>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <0>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <2>; + qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x1c 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x04>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [07 09 03 00 /* Regulator settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [46 1d 20 00 39 3a + 21 21 32 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 00 00 00 00 00 00 01 97 /* lane0 config */ + 00 00 00 00 05 00 00 01 97 /* lane1 config */ + 00 00 00 00 0a 00 00 01 97 /* lane2 config */ + 00 00 00 00 0f 00 00 01 97 /* lane3 config */ + 00 c0 00 00 00 00 00 01 bb]; /* Clk ln config */ + qcom,panel-on-cmds = [05 01 00 00 32 00 02 01 00 /* sw reset */ + 05 01 00 00 0a 00 02 11 00 /* exit sleep */ + 15 01 00 00 0a 00 02 53 2c /* backlight on */ + 15 01 00 00 0a 00 02 51 ff /* brightness max */ + 05 01 00 00 0a 00 02 29 00 /* display on */ + 15 01 00 00 0a 00 02 ae 03 /* set num of lanes */ + 15 01 00 00 0a 00 02 3a 77 /* rgb_888 */]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 0a 00 02 28 00 /* display off */ + 05 01 00 00 78 00 02 10 00 /* enter sleep */]; + qcom,off-cmds-dsi-state = "DSI_HS_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-sim-video.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-sim-video.dtsi new file mode 100644 index 000000000..271e37316 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-sim-video.dtsi @@ -0,0 +1,46 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + qcom,mdss_dsi_sim_video { + compatible = "qcom,mdss-dsi-panel"; + label = "simulator video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,mdss-pan-res = <640 480>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <6 2 6 6 2 6>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-levels = <1 15>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <1 1 1>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <0>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x24 0x03>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x04>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-on-cmds = [32 01 00 00 00 00 02 00 00]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [22 01 00 00 00 00 02 00 00]; + qcom,off-cmds-dsi-state = "DSI_LP_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-toshiba-720p-video.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-toshiba-720p-video.dtsi new file mode 100644 index 000000000..5c37cf8dc --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-panel-toshiba-720p-video.dtsi @@ -0,0 +1,124 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + qcom,mdss_dsi_toshiba_720p_video { + compatible = "qcom,mdss-dsi-panel"; + label = "toshiba 720p video mode dsi panel"; + status = "disable"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,enable-gpio = <&msmgpio 58 0>; + qcom,rst-gpio = <&pm8941_gpios 19 0>; + qcom,mdss-pan-res = <720 1280>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <32 12 144 3 4 9>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-bl-levels = <1 4095>; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <0>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <1>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 1 1>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>; + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings = [07 09 03 00 /* Regualotor settings */ + 20 00 01]; + qcom,panel-phy-timingSettings = [b0 23 1b 00 94 93 + 1e 25 15 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [00 00 b1 ff /* BIST Ctrl settings */ + 00 00]; + qcom,panel-phy-laneConfig = [00 00 00 00 00 00 00 01 97 /* lane0 config */ + 00 00 00 00 05 00 00 01 97 /* lane1 config */ + 00 00 00 00 0a 00 00 01 97 /* lane2 config */ + 00 00 00 00 0f 00 00 01 97 /* lane3 config */ + 00 c0 00 00 00 00 00 01 bb]; /* Clk ln config */ + + qcom,panel-on-cmds = [23 01 00 00 0a 00 02 b0 00 + 23 01 00 00 0a 00 02 b2 00 + 23 01 00 00 0a 00 02 b3 0c + 23 01 00 00 0a 00 02 b4 02 + 29 01 00 00 00 00 06 + c0 40 02 7f c8 08 + 29 01 00 00 00 00 10 + c1 00 a8 00 00 00 + 00 00 9d 08 27 00 + 00 00 00 00 + 29 01 00 00 00 00 06 + c2 00 00 09 00 00 + 23 01 00 00 0a 00 02 c3 04 + 29 01 00 00 00 00 04 + c4 4d 83 00 + 29 01 00 00 00 00 0b + c6 12 00 08 71 00 + 00 00 80 00 04 + 23 01 00 00 0a 00 02 c7 22 + 29 01 00 00 00 00 05 + c8 4c 0c 0c 0c + 29 01 00 00 00 00 0e + c9 00 40 00 16 32 + 2e 3a 43 3e 3c 45 + 79 3f + 29 01 00 00 00 00 0e + ca 00 46 1a 23 21 + 1c 25 31 2d 49 5f + 7f 3f + 29 01 00 00 00 00 0e + cb 00 4c 20 3a 42 + 40 47 4b 42 3e 46 + 7e 3f + 29 01 00 00 00 00 0e + cc 00 41 19 21 1d + 14 18 1f 1d 25 3f + 73 3f + 29 01 00 00 00 00 0e + cd 23 79 5a 5f 57 + 4c 51 51 45 3f 4b + 7f 3f + 29 01 00 00 00 00 0e + ce 00 40 14 20 1a + 0e 0e 13 08 00 05 + 46 1c + 29 01 00 00 00 00 04 + d0 6a 64 01 + 29 01 00 00 00 00 03 d1 77 d4 + 23 01 00 00 0a 00 02 d3 33 + 29 01 00 00 00 00 03 d5 0f 0f + 29 01 00 00 00 00 07 + d8 34 64 23 25 62 + 32 + 29 01 00 00 00 00 0c + de 10 7b 11 0a 00 + 00 00 00 00 00 00 + 29 01 00 00 00 00 09 + fd 04 55 53 00 70 + ff 10 73 + 23 01 00 00 0a 00 02 e2 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-off-cmds = [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_HS_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-v2-panel-hx8379a-wvga-video.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-v2-panel-hx8379a-wvga-video.dtsi new file mode 100644 index 000000000..b9ed0506a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-v2-panel-hx8379a-wvga-video.dtsi @@ -0,0 +1,117 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + qcom,dsi_v2_hx8379a_wvga_video { + compatible = "qcom,dsi-panel-v2"; + label = "HX8379A WVGA video mode dsi panel"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,rst-gpio = <&msmgpio 41 0>; + vdda-supply = <&pm8110_l19>; + vddio-supply=<&pm8110_l14>; + qcom,mdss-pan-res = <480 800>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <90 17 90 2 3 11>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-levels = <1 255>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <1>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <2>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>; + qcom,mdss-pan-dsi-dlane-swap = <1>; + qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>;/*todo*/ + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings =[09 08 05 00 20 03]; + qcom,panel-phy-timingSettings = [5D 12 0C 00 33 39 + 10 16 15 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [03 03 00 00 0f 00]; + qcom,panel-phy-laneConfig = + [80 45 00 00 01 66 /*lane0**/ + 80 45 00 00 01 66 /*lane1*/ + 80 45 00 00 01 66 /*lane2*/ + 80 45 00 00 01 66 /*lane3*/ + 40 67 00 00 01 88]; /*Clk*/ + + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-on-cmds = [ + 29 01 00 00 01 04 + B9 FF 83 79 + 23 01 00 00 01 02 + BA 51 + 29 01 00 00 01 14 + B1 00 50 44 + EA 8D 08 11 + 0F 0F 24 2C + 9A 1A 42 0B + 6E F1 00 E6 + 29 01 00 00 01 0e + B2 00 00 3C + 08 04 19 22 + 00 FF 08 04 + 19 20 + 29 01 00 00 01 20 + B4 80 08 00 + 32 10 03 32 + 13 70 32 10 + 08 37 01 28 + 05 37 08 3C + 20 44 44 08 + 00 40 08 28 + 08 30 30 04 + 23 01 00 00 01 02 + cc 02 + 29 01 00 00 01 30 + D5 00 00 08 + 00 01 05 00 + 03 00 88 88 + 88 88 23 01 + 67 45 02 13 + 88 88 88 88 + 88 88 88 88 + 88 88 54 76 + 10 32 31 20 + 88 88 88 88 + 88 88 00 00 + 00 00 00 00 + 29 01 00 00 01 24 + E0 79 00 00 + 02 1C 1F 33 + 28 3E 07 0E + 0F 15 17 16 + 16 13 19 00 + 00 02 1C 1F + 33 28 3E 07 + 0E 0F 15 17 + 16 16 13 19 + 29 01 00 00 01 05 + B6 00 A6 00 A6 + 05 01 00 00 96 02 + 11 00 + 05 01 00 00 78 02 + 29 00 + ]; + qcom,panel-off-cmds = [05 01 00 00 32 02 28 00 + 05 01 00 00 78 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_LP_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-v2-panel-truly-wvga-video.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-v2-panel-truly-wvga-video.dtsi new file mode 100644 index 000000000..891eac3ad --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/dsi-v2-panel-truly-wvga-video.dtsi @@ -0,0 +1,120 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + qcom,dsi_v2_truly_wvga_video { + compatible = "qcom,dsi-panel-v2"; + label = "Truly WVGA video mode dsi panel"; + qcom,dsi-ctrl-phandle = <&mdss_dsi0>; + qcom,rst-gpio = <&msmgpio 41 0>; + qcom,mode-selection-gpio = <&msmgpio 7 0>; + vdda-supply = <&pm8110_l19>; + vddio-supply=<&pm8110_l14>; + qcom,mdss-pan-res = <480 800>; + qcom,mdss-pan-bpp = <24>; + qcom,mdss-pan-dest = "display_1"; + qcom,mdss-pan-porch-values = <40 8 160 10 2 12>; + qcom,mdss-pan-underflow-clr = <0xff>; + qcom,mdss-pan-bl-levels = <1 255>; + qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled"; + qcom,mdss-pan-dsi-mode = <0>; + qcom,mdss-pan-dsi-h-pulse-mode = <0>; + qcom,mdss-pan-dsi-h-power-stop = <0 0 0>; + qcom,mdss-pan-dsi-bllp-power-stop = <1 1>; + qcom,mdss-pan-dsi-traffic-mode = <1>; + qcom,mdss-pan-dsi-dst-format = <3>; + qcom,mdss-pan-dsi-vc = <0>; + qcom,mdss-pan-dsi-rgb-swap = <0>; + qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>; + qcom,mdss-pan-dsi-dlane-swap = <0>; + qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>; + qcom,mdss-pan-dsi-stream = <0>; + qcom,mdss-pan-dsi-mdp-tr = <0x0>;/*todo*/ + qcom,mdss-pan-dsi-dma-tr = <0x04>; + qcom,mdss-pan-dsi-frame-rate = <60>; + qcom,panel-phy-regulatorSettings =[09 08 05 00 20 03]; + qcom,panel-phy-timingSettings = [5D 12 0C 00 33 38 + 10 16 1E 03 04 00]; + qcom,panel-phy-strengthCtrl = [ff 06]; + qcom,panel-phy-bistCtrl = [03 03 00 00 0f 00]; + qcom,panel-phy-laneConfig = + [80 45 00 00 01 66 /*lane0**/ + 80 45 00 00 01 66 /*lane1*/ + 80 45 00 00 01 66 /*lane2*/ + 80 45 00 00 01 66 /*lane3*/ + 40 67 00 00 01 88]; /*Clk*/ + + qcom,on-cmds-dsi-state = "DSI_LP_MODE"; + qcom,panel-on-cmds = [ + 05 01 00 00 00 02 + 01 00 + 23 01 00 00 00 02 + b0 04 + 29 01 00 00 00 03 + b3 02 00 + 23 01 00 00 00 02 + bd 00 + 29 01 00 00 00 03 + c0 18 66 + 29 01 00 00 00 10 + c1 23 31 99 21 20 00 30 28 0c 0c + 00 00 00 21 01 + 29 01 00 00 00 07 + c2 10 06 06 01 03 00 + 29 01 00 00 00 19 + c8 04 10 18 20 2e 46 3c 28 1f 18 + 10 04 04 10 18 20 2e 46 3c 28 1f 18 10 04 + 29 01 00 00 00 19 + c9 04 10 18 20 2e 46 3c 28 1f 18 + 10 04 04 10 18 20 2e 46 3c 28 1f 18 10 04 + 29 01 00 00 00 19 + ca 04 10 18 20 2e 46 3c 28 1f 18 + 10 04 04 10 18 20 2e 46 3c 28 1f 18 10 04 + 29 01 00 00 00 11 + d0 29 03 ce a6 00 43 20 10 01 00 + 01 01 00 03 01 00 + 29 01 00 00 00 08 + d1 18 0C 23 03 75 02 50 + 23 01 00 00 00 02 + d3 11 + 29 01 00 00 00 03 + d5 2a 2a + 29 01 00 00 00 03 + de 01 41 + 23 01 00 00 00 02 + e6 51 + 23 01 00 00 00 02 + fa 03 + 23 01 00 00 64 02 + d6 28 + 39 01 00 00 00 05 + 2a 00 00 01 df + 39 01 00 00 00 05 + 2b 00 00 03 1f + 15 01 00 00 00 02 + 35 00 + 39 01 00 00 00 03 + 44 00 50 + 15 01 00 00 00 02 + 36 c1 + 15 01 00 00 00 02 + 3a 77 + 05 01 00 00 7D 02 + 11 00 + 05 01 00 00 14 02 + 29 00 + ]; + qcom,panel-off-cmds = [05 01 00 00 32 02 28 00 + 05 01 00 00 78 02 10 00]; + qcom,off-cmds-dsi-state = "DSI_LP_MODE"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210-origen.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210-origen.dts new file mode 100644 index 000000000..b8c476384 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210-origen.dts @@ -0,0 +1,137 @@ +/* + * Samsung's Exynos4210 based Origen board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Insignal's Origen board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x40000000>; + }; + + chosen { + bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; + }; + + sdhci@12530000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; + }; + + sdhci@12510000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk0 2 2 3 3>; + gpios = <&gpk0 0 2 0 3>, + <&gpk0 1 2 0 3>, + <&gpk0 3 2 3 3>, + <&gpk0 4 2 3 3>, + <&gpk0 5 2 3 3>, + <&gpk0 6 2 3 3>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + up { + label = "Up"; + gpios = <&gpx2 0 0 0 2>; + linux,code = <103>; + }; + + down { + label = "Down"; + gpios = <&gpx2 1 0 0 2>; + linux,code = <108>; + }; + + back { + label = "Back"; + gpios = <&gpx1 7 0 0 2>; + linux,code = <158>; + }; + + home { + label = "Home"; + gpios = <&gpx1 6 0 0 2>; + linux,code = <102>; + }; + + menu { + label = "Menu"; + gpios = <&gpx1 5 0 0 2>; + linux,code = <139>; + }; + }; + + keypad@100A0000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + i2c@13860000 { + status = "disabled"; + }; + + i2c@13870000 { + status = "disabled"; + }; + + i2c@13880000 { + status = "disabled"; + }; + + i2c@13890000 { + status = "disabled"; + }; + + i2c@138A0000 { + status = "disabled"; + }; + + i2c@138B0000 { + status = "disabled"; + }; + + i2c@138C0000 { + status = "disabled"; + }; + + i2c@138D0000 { + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210-smdkv310.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210-smdkv310.dts new file mode 100644 index 000000000..27afc8e53 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210-smdkv310.dts @@ -0,0 +1,182 @@ +/* + * Samsung's Exynos4210 based SMDKV310 board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Samsung's SMDKV310 board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Samsung smdkv310 evaluation board based on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; + }; + + sdhci@12530000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; + }; + + keypad@100A0000 { + samsung,keypad-num-rows = <2>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + + row-gpios = <&gpx2 0 3 3 0>, + <&gpx2 1 3 3 0>; + + col-gpios = <&gpx1 0 3 0 0>, + <&gpx1 1 3 0 0>, + <&gpx1 2 3 0 0>, + <&gpx1 3 3 0 0>, + <&gpx1 4 3 0 0>, + <&gpx1 5 3 0 0>, + <&gpx1 6 3 0 0>, + <&gpx1 7 3 0 0>; + + key_1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = <2>; + }; + + key_2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = <3>; + }; + + key_3 { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <4>; + }; + + key_4 { + keypad,row = <0>; + keypad,column = <6>; + linux,code = <5>; + }; + + key_5 { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <6>; + }; + + key_a { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <30>; + }; + + key_b { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <48>; + }; + + key_c { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <46>; + }; + + key_d { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <32>; + }; + + key_e { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <18>; + }; + }; + + i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpd1 0 2 3 0>, + <&gpd1 1 2 3 0>; + + eeprom@50 { + compatible = "samsung,24ad0xd1"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "samsung,24ad0xd1"; + reg = <0x52>; + }; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + i2c@13870000 { + status = "disabled"; + }; + + i2c@13880000 { + status = "disabled"; + }; + + i2c@13890000 { + status = "disabled"; + }; + + i2c@138A0000 { + status = "disabled"; + }; + + i2c@138B0000 { + status = "disabled"; + }; + + i2c@138C0000 { + status = "disabled"; + }; + + i2c@138D0000 { + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210.dtsi new file mode 100644 index 000000000..a1dd2ee83 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos4210.dtsi @@ -0,0 +1,398 @@ +/* + * Samsung's Exynos4210 SoC device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,exynos4210"; + interrupt-parent = <&gic>; + + gic:interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + cpu-offset = <0x8000>; + reg = <0x10490000 0x1000>, <0x10480000 0x100>; + }; + + watchdog@10060000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x10060000 0x100>; + interrupts = <0 43 0>; + }; + + rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 44 0>, <0 45 0>; + }; + + keypad@100A0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100A0000 0x100>; + interrupts = <0 109 0>; + }; + + sdhci@12510000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12510000 0x100>; + interrupts = <0 73 0>; + }; + + sdhci@12520000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12520000 0x100>; + interrupts = <0 74 0>; + }; + + sdhci@12530000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12530000 0x100>; + interrupts = <0 75 0>; + }; + + sdhci@12540000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12540000 0x100>; + interrupts = <0 76 0>; + }; + + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 52 0>; + }; + + serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 53 0>; + }; + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 54 0>; + }; + + serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = <0 55 0>; + }; + + i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 59 0>; + }; + + i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@138A0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@138B0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@138C0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 64 0>; + }; + + i2c@138D0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 65 0>; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 35 0>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 36 0>; + }; + }; + + gpio-controllers { + #address-cells = <1>; + #size-cells = <1>; + gpio-controller; + ranges; + + gpa0: gpio-controller@11400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400000 0x20>; + #gpio-cells = <4>; + }; + + gpa1: gpio-controller@11400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400020 0x20>; + #gpio-cells = <4>; + }; + + gpb: gpio-controller@11400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400040 0x20>; + #gpio-cells = <4>; + }; + + gpc0: gpio-controller@11400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400060 0x20>; + #gpio-cells = <4>; + }; + + gpc1: gpio-controller@11400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400080 0x20>; + #gpio-cells = <4>; + }; + + gpd0: gpio-controller@114000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000A0 0x20>; + #gpio-cells = <4>; + }; + + gpd1: gpio-controller@114000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000C0 0x20>; + #gpio-cells = <4>; + }; + + gpe0: gpio-controller@114000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000E0 0x20>; + #gpio-cells = <4>; + }; + + gpe1: gpio-controller@11400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400100 0x20>; + #gpio-cells = <4>; + }; + + gpe2: gpio-controller@11400120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400120 0x20>; + #gpio-cells = <4>; + }; + + gpe3: gpio-controller@11400140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400140 0x20>; + #gpio-cells = <4>; + }; + + gpe4: gpio-controller@11400160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400160 0x20>; + #gpio-cells = <4>; + }; + + gpf0: gpio-controller@11400180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400180 0x20>; + #gpio-cells = <4>; + }; + + gpf1: gpio-controller@114001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001A0 0x20>; + #gpio-cells = <4>; + }; + + gpf2: gpio-controller@114001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001C0 0x20>; + #gpio-cells = <4>; + }; + + gpf3: gpio-controller@114001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001E0 0x20>; + #gpio-cells = <4>; + }; + + gpj0: gpio-controller@11000000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000000 0x20>; + #gpio-cells = <4>; + }; + + gpj1: gpio-controller@11000020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000020 0x20>; + #gpio-cells = <4>; + }; + + gpk0: gpio-controller@11000040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000040 0x20>; + #gpio-cells = <4>; + }; + + gpk1: gpio-controller@11000060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000060 0x20>; + #gpio-cells = <4>; + }; + + gpk2: gpio-controller@11000080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000080 0x20>; + #gpio-cells = <4>; + }; + + gpk3: gpio-controller@110000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000A0 0x20>; + #gpio-cells = <4>; + }; + + gpl0: gpio-controller@110000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000C0 0x20>; + #gpio-cells = <4>; + }; + + gpl1: gpio-controller@110000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000E0 0x20>; + #gpio-cells = <4>; + }; + + gpl2: gpio-controller@11000100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000100 0x20>; + #gpio-cells = <4>; + }; + + gpy0: gpio-controller@11000120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000120 0x20>; + #gpio-cells = <4>; + }; + + gpy1: gpio-controller@11000140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000140 0x20>; + #gpio-cells = <4>; + }; + + gpy2: gpio-controller@11000160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000160 0x20>; + #gpio-cells = <4>; + }; + + gpy3: gpio-controller@11000180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000180 0x20>; + #gpio-cells = <4>; + }; + + gpy4: gpio-controller@110001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001A0 0x20>; + #gpio-cells = <4>; + }; + + gpy5: gpio-controller@110001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001C0 0x20>; + #gpio-cells = <4>; + }; + + gpy6: gpio-controller@110001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001E0 0x20>; + #gpio-cells = <4>; + }; + + gpx0: gpio-controller@11000C00 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C00 0x20>; + #gpio-cells = <4>; + }; + + gpx1: gpio-controller@11000C20 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C20 0x20>; + #gpio-cells = <4>; + }; + + gpx2: gpio-controller@11000C40 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C40 0x20>; + #gpio-cells = <4>; + }; + + gpx3: gpio-controller@11000C60 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C60 0x20>; + #gpio-cells = <4>; + }; + + gpz: gpio-controller@03860000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x03860000 0x20>; + #gpio-cells = <4>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos5250-smdk5250.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos5250-smdk5250.dts new file mode 100644 index 000000000..399d17b23 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos5250-smdk5250.dts @@ -0,0 +1,26 @@ +/* + * SAMSUNG SMDK5250 board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos5250.dtsi" + +/ { + model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; + compatible = "samsung,smdk5250", "samsung,exynos5250"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos5250.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos5250.dtsi new file mode 100644 index 000000000..dfc433599 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/exynos5250.dtsi @@ -0,0 +1,413 @@ +/* + * SAMSUNG EXYNOS5250 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. + * EXYNOS5250 based board files can include this file and provide + * values for board specfic bindings. + * + * Note: This file does not include device nodes for all the controllers in + * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, + * additional nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,exynos5250"; + interrupt-parent = <&gic>; + + gic:interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10490000 0x1000>, <0x10480000 0x100>; + }; + + watchdog { + compatible = "samsung,s3c2410-wdt"; + reg = <0x101D0000 0x100>; + interrupts = <0 42 0>; + }; + + rtc { + compatible = "samsung,s3c6410-rtc"; + reg = <0x101E0000 0x100>; + interrupts = <0 43 0>, <0 44 0>; + }; + + sdhci@12200000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12200000 0x100>; + interrupts = <0 75 0>; + }; + + sdhci@12210000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12210000 0x100>; + interrupts = <0 76 0>; + }; + + sdhci@12220000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12220000 0x100>; + interrupts = <0 77 0>; + }; + + sdhci@12230000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12230000 0x100>; + interrupts = <0 78 0>; + }; + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + }; + + serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + interrupts = <0 54 0>; + }; + + i2c@12C60000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C60000 0x100>; + interrupts = <0 56 0>; + }; + + i2c@12C70000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C70000 0x100>; + interrupts = <0 57 0>; + }; + + i2c@12C80000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C80000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@12C90000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C90000 0x100>; + interrupts = <0 59 0>; + }; + + i2c@12CA0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CA0000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@12CB0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CB0000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@12CC0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CC0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@12CD0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x12CD0000 0x100>; + interrupts = <0 63 0>; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@121A0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <0 34 0>; + }; + + pdma1: pdma@121B0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <0 35 0>; + }; + + mdma0: pdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <0 33 0>; + }; + + mdma1: pdma@11C10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <0 124 0>; + }; + }; + + gpio-controllers { + #address-cells = <1>; + #size-cells = <1>; + gpio-controller; + ranges; + + gpa0: gpio-controller@11400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400000 0x20>; + #gpio-cells = <4>; + }; + + gpa1: gpio-controller@11400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400020 0x20>; + #gpio-cells = <4>; + }; + + gpa2: gpio-controller@11400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400040 0x20>; + #gpio-cells = <4>; + }; + + gpb0: gpio-controller@11400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400060 0x20>; + #gpio-cells = <4>; + }; + + gpb1: gpio-controller@11400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400080 0x20>; + #gpio-cells = <4>; + }; + + gpb2: gpio-controller@114000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000A0 0x20>; + #gpio-cells = <4>; + }; + + gpb3: gpio-controller@114000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000C0 0x20>; + #gpio-cells = <4>; + }; + + gpc0: gpio-controller@114000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000E0 0x20>; + #gpio-cells = <4>; + }; + + gpc1: gpio-controller@11400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400100 0x20>; + #gpio-cells = <4>; + }; + + gpc2: gpio-controller@11400120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400120 0x20>; + #gpio-cells = <4>; + }; + + gpc3: gpio-controller@11400140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400140 0x20>; + #gpio-cells = <4>; + }; + + gpd0: gpio-controller@11400160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400160 0x20>; + #gpio-cells = <4>; + }; + + gpd1: gpio-controller@11400180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400180 0x20>; + #gpio-cells = <4>; + }; + + gpy0: gpio-controller@114001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001A0 0x20>; + #gpio-cells = <4>; + }; + + gpy1: gpio-controller@114001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001C0 0x20>; + #gpio-cells = <4>; + }; + + gpy2: gpio-controller@114001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001E0 0x20>; + #gpio-cells = <4>; + }; + + gpy3: gpio-controller@11400200 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400200 0x20>; + #gpio-cells = <4>; + }; + + gpy4: gpio-controller@11400220 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400220 0x20>; + #gpio-cells = <4>; + }; + + gpy5: gpio-controller@11400240 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400240 0x20>; + #gpio-cells = <4>; + }; + + gpy6: gpio-controller@11400260 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400260 0x20>; + #gpio-cells = <4>; + }; + + gpx0: gpio-controller@11400C00 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C00 0x20>; + #gpio-cells = <4>; + }; + + gpx1: gpio-controller@11400C20 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C20 0x20>; + #gpio-cells = <4>; + }; + + gpx2: gpio-controller@11400C40 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C40 0x20>; + #gpio-cells = <4>; + }; + + gpx3: gpio-controller@11400C60 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C60 0x20>; + #gpio-cells = <4>; + }; + + gpe0: gpio-controller@13400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400000 0x20>; + #gpio-cells = <4>; + }; + + gpe1: gpio-controller@13400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400020 0x20>; + #gpio-cells = <4>; + }; + + gpf0: gpio-controller@13400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400040 0x20>; + #gpio-cells = <4>; + }; + + gpf1: gpio-controller@13400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400060 0x20>; + #gpio-cells = <4>; + }; + + gpg0: gpio-controller@13400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400080 0x20>; + #gpio-cells = <4>; + }; + + gpg1: gpio-controller@134000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000A0 0x20>; + #gpio-cells = <4>; + }; + + gpg2: gpio-controller@134000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000C0 0x20>; + #gpio-cells = <4>; + }; + + gph0: gpio-controller@134000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000E0 0x20>; + #gpio-cells = <4>; + }; + + gph1: gpio-controller@13400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400100 0x20>; + #gpio-cells = <4>; + }; + + gpv0: gpio-controller@10D10000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10000 0x20>; + #gpio-cells = <4>; + }; + + gpv1: gpio-controller@10D10020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10020 0x20>; + #gpio-cells = <4>; + }; + + gpv2: gpio-controller@10D10040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10040 0x20>; + #gpio-cells = <4>; + }; + + gpv3: gpio-controller@10D10060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10060 0x20>; + #gpio-cells = <4>; + }; + + gpv4: gpio-controller@10D10080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10080 0x20>; + #gpio-cells = <4>; + }; + + gpz: gpio-controller@03860000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x03860000 0x20>; + #gpio-cells = <4>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900-rumi.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900-rumi.dts new file mode 100644 index 000000000..2b380c7b3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900-rumi.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "fsm9900.dtsi" + +/ { + model = "Qualcomm FSM9900 Rumi"; + compatible = "qcom,fsm9900-rumi", "qcom,fsm9900", "qcom-sim"; + qcom,msm-id = <188 0 0>; + + aliases { + serial0 = &uart0; + }; +}; + +&soc { + uart0: serial@f9960000 { + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900-sim.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900-sim.dts new file mode 100644 index 000000000..050929e60 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900-sim.dts @@ -0,0 +1,32 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "fsm9900.dtsi" + +/ { + model = "Qualcomm FSM9900 Simulator"; + compatible = "qcom,fsm9900-sim", "qcom,fsm9900", "qcom-sim"; + qcom,msm-id = <188 0 0>; + + aliases { + serial0 = &uart0; + }; +}; + +&soc { + uart0: serial@f9960000 { + interrupts = <0 116 0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900.dtsi new file mode 100644 index 000000000..766db368d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/fsm9900.dtsi @@ -0,0 +1,94 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton64.dtsi" + +/ { + model = "Qualcomm FSM9900"; + compatible = "qcom,fsm9900"; + interrupt-parent = <&intc>; + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <142>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <5>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + serial@f9960000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf9960000 0x1000>; + interrupts = <0 104 0>; + status = "disabled"; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + qcom,irq-is-percpu; + interrupts = <1 7 0xf00>; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + qcom,cache_erp { + compatible = "qcom,cache_erp"; + interrupts = <1 9 0>, <0 2 0>; + interrupt-names = "l1_irq", "l2_irq"; + }; + + qcom,cache_dump { + compatible = "qcom,cache_dump"; + qcom,l1-dump-size = <0x100000>; + qcom,l2-dump-size = <0x500000>; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x600000>; /* 6M EBI1 buffer */ + }; + + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/highbank.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/highbank.dts new file mode 100644 index 000000000..83e72294a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/highbank.dts @@ -0,0 +1,209 @@ +/* + * Copyright 2011 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/dts-v1/; + +/* First 4KB has pen for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; + +/ { + model = "Calxeda Highbank"; + compatible = "calxeda,highbank"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x00000000 0xff900000>; + }; + + chosen { + bootargs = "console=ttyAMA0"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + timer@fff10600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfff10600 0x20>; + interrupts = <1 13 0xf01>; + }; + + watchdog@fff10620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xfff10620 0x20>; + interrupts = <1 14 0xf01>; + }; + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + interrupts = <0 70 4>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; + }; + + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x10000>; + interrupts = <0 83 4>; + }; + + sdhci@ffe0e000 { + compatible = "calxeda,hb-sdhci"; + reg = <0xffe0e000 0x1000>; + interrupts = <0 90 4>; + }; + + ipc@fff20000 { + compatible = "arm,pl320", "arm,primecell"; + reg = <0xfff20000 0x1000>; + interrupts = <0 7 4>; + }; + + gpioe: gpio@fff30000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff30000 0x1000>; + interrupts = <0 14 4>; + }; + + gpiof: gpio@fff31000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff31000 0x1000>; + interrupts = <0 15 4>; + }; + + gpiog: gpio@fff32000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff32000 0x1000>; + interrupts = <0 16 4>; + }; + + gpioh: gpio@fff33000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfff33000 0x1000>; + interrupts = <0 17 4>; + }; + + timer { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xfff34000 0x1000>; + interrupts = <0 18 4>; + }; + + rtc@fff35000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0xfff35000 0x1000>; + interrupts = <0 19 4>; + }; + + serial@fff36000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xfff36000 0x1000>; + interrupts = <0 20 4>; + }; + + smic@fff3a000 { + compatible = "ipmi-smic"; + device_type = "ipmi"; + reg = <0xfff3a000 0x1000>; + interrupts = <0 24 4>; + reg-size = <4>; + reg-spacing = <4>; + }; + + sregs@fff3c000 { + compatible = "calxeda,hb-sregs"; + reg = <0xfff3c000 0x1000>; + }; + + dma@fff3d000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xfff3d000 0x1000>; + interrupts = <0 92 4>; + }; + + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4 0 78 4 0 79 4>; + }; + + ethernet@fff51000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff51000 0x1000>; + interrupts = <0 80 4 0 81 4 0 82 4>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx27-phytec-phycore.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx27-phytec-phycore.dts new file mode 100644 index 000000000..a51a08fc2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx27-phytec-phycore.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx27.dtsi" + +/ { + model = "Phytec pcm038"; + compatible = "phytec,imx27-pcm038", "fsl,imx27"; + + memory { + reg = <0x0 0x0>; + }; + + soc { + aipi@10000000 { /* aipi */ + + wdog@10002000 { + status = "okay"; + }; + + uart@1000a000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + uart@1000b000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + uart@1000c000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + fec@1002b000 { + status = "okay"; + }; + + i2c@1001d000 { + clock-frequency = <400000>; + status = "okay"; + at24@4c { + compatible = "at,24c32"; + pagesize = <32>; + reg = <0x52>; + }; + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + lm75@4a { + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + }; + }; + + nor_flash@c0000000 { + compatible = "cfi-flash"; + bank-width = <2>; + reg = <0xc0000000 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx27.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx27.dtsi new file mode 100644 index 000000000..bc5e7d5dd --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx27.dtsi @@ -0,0 +1,217 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + }; + + avic: avic-interrupt-controller@e0000000 { + compatible = "fsl,imx27-avic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10040000 0x1000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc26m { + compatible = "fsl,imx-osc26m", "fixed-clock"; + clock-frequency = <26000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&avic>; + ranges; + + aipi@10000000 { /* AIPI1 */ + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10000000 0x10000000>; + ranges; + + wdog@10002000 { + compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; + reg = <0x10002000 0x4000>; + interrupts = <27>; + status = "disabled"; + }; + + uart1: uart@1000a000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000a000 0x1000>; + interrupts = <20>; + status = "disabled"; + }; + + uart2: uart@1000b000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000b000 0x1000>; + interrupts = <19>; + status = "disabled"; + }; + + uart3: uart@1000c000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000c000 0x1000>; + interrupts = <18>; + status = "disabled"; + }; + + uart4: uart@1000d000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000d000 0x1000>; + interrupts = <17>; + status = "disabled"; + }; + + cspi1: cspi@1000e000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x1000e000 0x1000>; + interrupts = <16>; + status = "disabled"; + }; + + cspi2: cspi@1000f000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x1000f000 0x1000>; + interrupts = <15>; + status = "disabled"; + }; + + i2c1: i2c@10012000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-i2c", "fsl,imx1-i2c"; + reg = <0x10012000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + + gpio1: gpio@10015000 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015000 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@10015100 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015100 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@10015200 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015200 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@10015300 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015300 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio5: gpio@10015400 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015400 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio6: gpio@10015500 { + compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; + reg = <0x10015500 0x100>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + cspi3: cspi@10017000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-cspi"; + reg = <0x10017000 0x1000>; + interrupts = <6>; + status = "disabled"; + }; + + uart5: uart@1001b000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1001b000 0x1000>; + interrupts = <49>; + status = "disabled"; + }; + + uart6: uart@1001c000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1001c000 0x1000>; + interrupts = <48>; + status = "disabled"; + }; + + i2c2: i2c@1001d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx27-i2c", "fsl,imx1-i2c"; + reg = <0x1001d000 0x1000>; + interrupts = <1>; + status = "disabled"; + }; + + fec: fec@1002b000 { + compatible = "fsl,imx27-fec"; + reg = <0x1002b000 0x4000>; + interrupts = <50>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx51-babbage.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx51-babbage.dts new file mode 100644 index 000000000..9949e6060 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx51-babbage.dts @@ -0,0 +1,221 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx51.dtsi" + +/ { + model = "Freescale i.MX51 Babbage Board"; + compatible = "fsl,imx51-babbage", "fsl,imx51"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x90000000 0x20000000>; + }; + + soc { + aips@70000000 { /* aips-1 */ + spba@70000000 { + esdhc@70004000 { /* ESDHC1 */ + fsl,cd-internal; + fsl,wp-internal; + status = "okay"; + }; + + esdhc@70008000 { /* ESDHC2 */ + cd-gpios = <&gpio1 6 0>; + wp-gpios = <&gpio1 5 0>; + status = "okay"; + }; + + uart3: uart@7000c000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + ecspi@70010000 { /* ECSPI1 */ + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; + status = "okay"; + + pmic: mc13892@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mc13892"; + spi-max-frequency = <6000000>; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8>; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + }; + + flash: at45db321d@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0x3c0000>; + }; + }; + }; + }; + + wdog@73f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@73fa8000 { + compatible = "fsl,imx51-iomuxc-babbage"; + reg = <0x73fa8000 0x4000>; + }; + + uart1: uart@73fbc000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + uart2: uart@73fc0000 { + status = "okay"; + }; + }; + + aips@80000000 { /* aips-2 */ + sdma@83fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; + }; + + i2c@83fc4000 { /* I2C2 */ + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + }; + + fec@83fec000 { + phy-mode = "mii"; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power Button"; + gpios = <&gpio2 21 0>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx51.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx51.dtsi new file mode 100644 index 000000000..6663986fe --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx51.dtsi @@ -0,0 +1,246 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + tzic: tz-interrupt-controller@e0000000 { + compatible = "fsl,imx51-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xe0000000 0x4000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + aips@70000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x70000000 0x10000000>; + ranges; + + spba@70000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x70000000 0x40000>; + ranges; + + esdhc@70004000 { /* ESDHC1 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70004000 0x4000>; + interrupts = <1>; + status = "disabled"; + }; + + esdhc@70008000 { /* ESDHC2 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70008000 0x4000>; + interrupts = <2>; + status = "disabled"; + }; + + uart3: uart@7000c000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x7000c000 0x4000>; + interrupts = <33>; + status = "disabled"; + }; + + ecspi@70010000 { /* ECSPI1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ecspi"; + reg = <0x70010000 0x4000>; + interrupts = <36>; + status = "disabled"; + }; + + esdhc@70020000 { /* ESDHC3 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70020000 0x4000>; + interrupts = <3>; + status = "disabled"; + }; + + esdhc@70024000 { /* ESDHC4 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70024000 0x4000>; + interrupts = <4>; + status = "disabled"; + }; + }; + + gpio1: gpio@73f84000 { + compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; + reg = <0x73f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@73f88000 { + compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; + reg = <0x73f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@73f8c000 { + compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; + reg = <0x73f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@73f90000 { + compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; + reg = <0x73f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + wdog@73f98000 { /* WDOG1 */ + compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; + reg = <0x73f98000 0x4000>; + interrupts = <58>; + status = "disabled"; + }; + + wdog@73f9c000 { /* WDOG2 */ + compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; + reg = <0x73f9c000 0x4000>; + interrupts = <59>; + status = "disabled"; + }; + + uart1: uart@73fbc000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fbc000 0x4000>; + interrupts = <31>; + status = "disabled"; + }; + + uart2: uart@73fc0000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fc0000 0x4000>; + interrupts = <32>; + status = "disabled"; + }; + }; + + aips@80000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x10000000>; + ranges; + + ecspi@83fac000 { /* ECSPI2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ecspi"; + reg = <0x83fac000 0x4000>; + interrupts = <37>; + status = "disabled"; + }; + + sdma@83fb0000 { + compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; + reg = <0x83fb0000 0x4000>; + interrupts = <6>; + }; + + cspi@83fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; + reg = <0x83fc0000 0x4000>; + interrupts = <38>; + status = "disabled"; + }; + + i2c@83fc4000 { /* I2C2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; + reg = <0x83fc4000 0x4000>; + interrupts = <63>; + status = "disabled"; + }; + + i2c@83fc8000 { /* I2C1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; + reg = <0x83fc8000 0x4000>; + interrupts = <62>; + status = "disabled"; + }; + + fec@83fec000 { + compatible = "fsl,imx51-fec", "fsl,imx27-fec"; + reg = <0x83fec000 0x4000>; + interrupts = <87>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-ard.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-ard.dts new file mode 100644 index 000000000..2dccce46e --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-ard.dts @@ -0,0 +1,113 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Automotive Reference Design Board"; + compatible = "fsl,imx53-ard", "fsl,imx53"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x70000000 0x40000000>; + }; + + soc { + aips@50000000 { /* AIPS1 */ + spba@50000000 { + esdhc@50004000 { /* ESDHC1 */ + cd-gpios = <&gpio1 1 0>; + wp-gpios = <&gpio1 9 0>; + status = "okay"; + }; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-ard"; + reg = <0x53fa8000 0x4000>; + }; + + uart1: uart@53fbc000 { + status = "okay"; + }; + }; + + aips@60000000 { /* AIPS2 */ + sdma@63fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + }; + }; + + eim-cs1@f4000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eim-bus", "simple-bus"; + reg = <0xf4000000 0x3ff0000>; + ranges; + + lan9220@f4000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0xf4000000 0x2000000>; + phy-mode = "mii"; + interrupt-parent = <&gpio2>; + interrupts = <31>; + reg-io-width = <4>; + smsc,irq-push-pull; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + home { + label = "Home"; + gpios = <&gpio5 10 0>; + linux,code = <102>; /* KEY_HOME */ + gpio-key,wakeup; + }; + + back { + label = "Back"; + gpios = <&gpio5 11 0>; + linux,code = <158>; /* KEY_BACK */ + gpio-key,wakeup; + }; + + program { + label = "Program"; + gpios = <&gpio5 12 0>; + linux,code = <362>; /* KEY_PROGRAM */ + gpio-key,wakeup; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio5 13 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 0 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-evk.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-evk.dts new file mode 100644 index 000000000..5bac4aa48 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-evk.dts @@ -0,0 +1,119 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Evaluation Kit"; + compatible = "fsl,imx53-evk", "fsl,imx53"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x70000000 0x80000000>; + }; + + soc { + aips@50000000 { /* AIPS1 */ + spba@50000000 { + esdhc@50004000 { /* ESDHC1 */ + cd-gpios = <&gpio3 13 0>; + wp-gpios = <&gpio3 14 0>; + status = "okay"; + }; + + ecspi@50010000 { /* ECSPI1 */ + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; + status = "okay"; + + flash: at45db321d@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0x3c0000>; + }; + }; + }; + + esdhc@50020000 { /* ESDHC3 */ + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; + status = "okay"; + }; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-evk"; + reg = <0x53fa8000 0x4000>; + }; + + uart1: uart@53fbc000 { + status = "okay"; + }; + }; + + aips@60000000 { /* AIPS2 */ + sdma@63fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + i2c@63fc4000 { /* I2C2 */ + status = "okay"; + + pmic: mc13892@08 { + compatible = "fsl,mc13892", "fsl,mc13xxx"; + reg = <0x08>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + }; + + fec@63fec000 { + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + green { + label = "Heartbeat"; + gpios = <&gpio7 7 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-qsb.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-qsb.dts new file mode 100644 index 000000000..5c57c8672 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-qsb.dts @@ -0,0 +1,125 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Quick Start Board"; + compatible = "fsl,imx53-qsb", "fsl,imx53"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x70000000 0x40000000>; + }; + + soc { + aips@50000000 { /* AIPS1 */ + spba@50000000 { + esdhc@50004000 { /* ESDHC1 */ + cd-gpios = <&gpio3 13 0>; + status = "okay"; + }; + + esdhc@50020000 { /* ESDHC3 */ + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; + status = "okay"; + }; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-qsb"; + reg = <0x53fa8000 0x4000>; + }; + + uart1: uart@53fbc000 { + status = "okay"; + }; + }; + + aips@60000000 { /* AIPS2 */ + sdma@63fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + i2c@63fc4000 { /* I2C2 */ + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + }; + + i2c@63fc8000 { /* I2C1 */ + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + pmic: dialog@48 { + compatible = "dialog,da9053", "dialog,da9052"; + reg = <0x48>; + }; + }; + + fec@63fec000 { + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power Button"; + gpios = <&gpio1 8 0>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 14 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio2 15 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio7 7 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-smd.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-smd.dts new file mode 100644 index 000000000..c7ee86c2d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53-smd.dts @@ -0,0 +1,168 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx53.dtsi" + +/ { + model = "Freescale i.MX53 Smart Mobile Reference Design Board"; + compatible = "fsl,imx53-smd", "fsl,imx53"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait"; + }; + + memory { + reg = <0x70000000 0x40000000>; + }; + + soc { + aips@50000000 { /* AIPS1 */ + spba@50000000 { + esdhc@50004000 { /* ESDHC1 */ + cd-gpios = <&gpio3 13 0>; + wp-gpios = <&gpio4 11 0>; + status = "okay"; + }; + + esdhc@50008000 { /* ESDHC2 */ + fsl,card-wired; + status = "okay"; + }; + + uart3: uart@5000c000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + ecspi@50010000 { /* ECSPI1 */ + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; + status = "okay"; + + zigbee: mc1323@0 { + compatible = "fsl,mc1323"; + spi-max-frequency = <8000000>; + reg = <0>; + }; + + flash: m25p32@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "st,m25p"; + spi-max-frequency = <20000000>; + reg = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0x3c0000>; + }; + }; + }; + + esdhc@50020000 { /* ESDHC3 */ + fsl,card-wired; + status = "okay"; + }; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-smd"; + reg = <0x53fa8000 0x4000>; + }; + + uart1: uart@53fbc000 { + status = "okay"; + }; + + uart2: uart@53fc0000 { + status = "okay"; + }; + }; + + aips@60000000 { /* AIPS2 */ + sdma@63fb0000 { + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + i2c@63fc4000 { /* I2C2 */ + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + }; + + magnetometer: mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + }; + + touchkey: mpr121@5a { + compatible = "fsl,mpr121"; + reg = <0x5a>; + }; + }; + + i2c@63fc8000 { /* I2C1 */ + status = "okay"; + + accelerometer: mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + camera: ov5642@3c { + compatible = "ovti,ov5642"; + reg = <0x3c>; + }; + + pmic: dialog@48 { + compatible = "dialog,da9053", "dialog,da9052"; + reg = <0x48>; + }; + }; + + fec@63fec000 { + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio2 14 0>; + linux,code = <115>; /* KEY_VOLUMEUP */ + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio2 15 0>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53.dtsi new file mode 100644 index 000000000..5dd91b942 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx53.dtsi @@ -0,0 +1,301 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + tzic: tz-interrupt-controller@0fffc000 { + compatible = "fsl,imx53-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x0fffc000 0x4000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + aips@50000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x10000000>; + ranges; + + spba@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x40000>; + ranges; + + esdhc@50004000 { /* ESDHC1 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50004000 0x4000>; + interrupts = <1>; + status = "disabled"; + }; + + esdhc@50008000 { /* ESDHC2 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50008000 0x4000>; + interrupts = <2>; + status = "disabled"; + }; + + uart3: uart@5000c000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + status = "disabled"; + }; + + ecspi@50010000 { /* ECSPI1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + status = "disabled"; + }; + + esdhc@50020000 { /* ESDHC3 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50020000 0x4000>; + interrupts = <3>; + status = "disabled"; + }; + + esdhc@50024000 { /* ESDHC4 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50024000 0x4000>; + interrupts = <4>; + status = "disabled"; + }; + }; + + gpio1: gpio@53f84000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@53f88000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@53f8c000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@53f90000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + wdog@53f98000 { /* WDOG1 */ + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + status = "disabled"; + }; + + wdog@53f9c000 { /* WDOG2 */ + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f9c000 0x4000>; + interrupts = <59>; + status = "disabled"; + }; + + uart1: uart@53fbc000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + status = "disabled"; + }; + + uart2: uart@53fc0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + status = "disabled"; + }; + + gpio5: gpio@53fdc000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fdc000 0x4000>; + interrupts = <103 104>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio6: gpio@53fe0000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fe0000 0x4000>; + interrupts = <105 106>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio7: gpio@53fe4000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fe4000 0x4000>; + interrupts = <107 108>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + i2c@53fec000 { /* I2C3 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x53fec000 0x4000>; + interrupts = <64>; + status = "disabled"; + }; + + uart4: uart@53ff0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + status = "disabled"; + }; + }; + + aips@60000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x60000000 0x10000000>; + ranges; + + uart5: uart@63f90000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + status = "disabled"; + }; + + ecspi@63fac000 { /* ECSPI2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + status = "disabled"; + }; + + sdma@63fb0000 { + compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; + reg = <0x63fb0000 0x4000>; + interrupts = <6>; + }; + + cspi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + status = "disabled"; + }; + + i2c@63fc4000 { /* I2C2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x63fc4000 0x4000>; + interrupts = <63>; + status = "disabled"; + }; + + i2c@63fc8000 { /* I2C1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x63fc8000 0x4000>; + interrupts = <62>; + status = "disabled"; + }; + + fec@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q-arm2.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q-arm2.dts new file mode 100644 index 000000000..ce1c8238c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q-arm2.dts @@ -0,0 +1,76 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; + + chosen { + bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait"; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + soc { + aips-bus@02100000 { /* AIPS2 */ + enet@02188000 { + phy-mode = "rgmii"; + local-mac-address = [00 04 9F 01 1B 61]; + status = "okay"; + }; + + usdhc@02198000 { /* uSDHC3 */ + cd-gpios = <&gpio6 11 0>; + wp-gpios = <&gpio6 14 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + usdhc@0219c000 { /* uSDHC4 */ + fsl,card-wired; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + uart4: uart@021f0000 { + status = "okay"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + leds { + compatible = "gpio-leds"; + + debug-led { + label = "Heartbeat"; + gpios = <&gpio3 25 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q-sabrelite.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q-sabrelite.dts new file mode 100644 index 000000000..4663a4e5a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q-sabrelite.dts @@ -0,0 +1,83 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Lite Board"; + compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + soc { + aips-bus@02100000 { /* AIPS2 */ + enet@02188000 { + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; + status = "okay"; + }; + + usdhc@02198000 { /* uSDHC3 */ + cd-gpios = <&gpio7 0 0>; + wp-gpios = <&gpio7 1 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + usdhc@0219c000 { /* uSDHC4 */ + cd-gpios = <&gpio2 6 0>; + wp-gpios = <&gpio2 7 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + uart2: uart@021e8000 { + status = "okay"; + }; + + i2c@021a0000 { /* I2C1 */ + status = "okay"; + clock-frequency = <100000>; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q.dtsi new file mode 100644 index 000000000..4905f51a1 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/imx6q.dtsi @@ -0,0 +1,575 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + timer@00a00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x00a00600 0x20>; + interrupts = <1 13 0xf01>; + }; + + L2: l2-cache@00a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = <0 92 0x04>; + cache-unified; + cache-level = <2>; + }; + + aips-bus@02000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif@02004000 { + reg = <0x02004000 0x4000>; + interrupts = <0 52 0x04>; + }; + + ecspi@02008000 { /* eCSPI1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <0 31 0x04>; + status = "disabled"; + }; + + ecspi@0200c000 { /* eCSPI2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <0 32 0x04>; + status = "disabled"; + }; + + ecspi@02010000 { /* eCSPI3 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <0 33 0x04>; + status = "disabled"; + }; + + ecspi@02014000 { /* eCSPI4 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <0 34 0x04>; + status = "disabled"; + }; + + ecspi@02018000 { /* eCSPI5 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02018000 0x4000>; + interrupts = <0 35 0x04>; + status = "disabled"; + }; + + uart1: uart@02020000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <0 26 0x04>; + status = "disabled"; + }; + + esai@02024000 { + reg = <0x02024000 0x4000>; + interrupts = <0 51 0x04>; + }; + + ssi@02028000 { /* SSI1 */ + reg = <0x02028000 0x4000>; + interrupts = <0 46 0x04>; + }; + + ssi@0202c000 { /* SSI2 */ + reg = <0x0202c000 0x4000>; + interrupts = <0 47 0x04>; + }; + + ssi@02030000 { /* SSI3 */ + reg = <0x02030000 0x4000>; + interrupts = <0 48 0x04>; + }; + + asrc@02034000 { + reg = <0x02034000 0x4000>; + interrupts = <0 50 0x04>; + }; + + spba@0203c000 { + reg = <0x0203c000 0x4000>; + }; + }; + + vpu@02040000 { + reg = <0x02040000 0x3c000>; + interrupts = <0 3 0x04 0 12 0x04>; + }; + + aipstz@0207c000 { /* AIPSTZ1 */ + reg = <0x0207c000 0x4000>; + }; + + pwm@02080000 { /* PWM1 */ + reg = <0x02080000 0x4000>; + interrupts = <0 83 0x04>; + }; + + pwm@02084000 { /* PWM2 */ + reg = <0x02084000 0x4000>; + interrupts = <0 84 0x04>; + }; + + pwm@02088000 { /* PWM3 */ + reg = <0x02088000 0x4000>; + interrupts = <0 85 0x04>; + }; + + pwm@0208c000 { /* PWM4 */ + reg = <0x0208c000 0x4000>; + interrupts = <0 86 0x04>; + }; + + flexcan@02090000 { /* CAN1 */ + reg = <0x02090000 0x4000>; + interrupts = <0 110 0x04>; + }; + + flexcan@02094000 { /* CAN2 */ + reg = <0x02094000 0x4000>; + interrupts = <0 111 0x04>; + }; + + gpt@02098000 { + compatible = "fsl,imx6q-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <0 55 0x04>; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <0 66 0x04 0 67 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <0 68 0x04 0 69 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <0 70 0x04 0 71 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <0 72 0x04 0 73 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <0 74 0x04 0 75 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio6: gpio@020b0000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = <0 76 0x04 0 77 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio7: gpio@020b4000 { + compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; + reg = <0x020b4000 0x4000>; + interrupts = <0 78 0x04 0 79 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + kpp@020b8000 { + reg = <0x020b8000 0x4000>; + interrupts = <0 82 0x04>; + }; + + wdog@020bc000 { /* WDOG1 */ + compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <0 80 0x04>; + status = "disabled"; + }; + + wdog@020c0000 { /* WDOG2 */ + compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <0 81 0x04>; + status = "disabled"; + }; + + ccm@020c4000 { + compatible = "fsl,imx6q-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 0x04 0 88 0x04>; + }; + + anatop@020c8000 { + compatible = "fsl,imx6q-anatop"; + reg = <0x020c8000 0x1000>; + interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; + }; + + usbphy@020c9000 { /* USBPHY1 */ + reg = <0x020c9000 0x1000>; + interrupts = <0 44 0x04>; + }; + + usbphy@020ca000 { /* USBPHY2 */ + reg = <0x020ca000 0x1000>; + interrupts = <0 45 0x04>; + }; + + snvs@020cc000 { + reg = <0x020cc000 0x4000>; + interrupts = <0 19 0x04 0 20 0x04>; + }; + + epit@020d0000 { /* EPIT1 */ + reg = <0x020d0000 0x4000>; + interrupts = <0 56 0x04>; + }; + + epit@020d4000 { /* EPIT2 */ + reg = <0x020d4000 0x4000>; + interrupts = <0 57 0x04>; + }; + + src@020d8000 { + compatible = "fsl,imx6q-src"; + reg = <0x020d8000 0x4000>; + interrupts = <0 91 0x04 0 96 0x04>; + }; + + gpc@020dc000 { + compatible = "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = <0 89 0x04 0 90 0x04>; + }; + + iomuxc@020e0000 { + reg = <0x020e0000 0x4000>; + }; + + dcic@020e4000 { /* DCIC1 */ + reg = <0x020e4000 0x4000>; + interrupts = <0 124 0x04>; + }; + + dcic@020e8000 { /* DCIC2 */ + reg = <0x020e8000 0x4000>; + interrupts = <0 125 0x04>; + }; + + sdma@020ec000 { + compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = <0 2 0x04>; + }; + }; + + aips-bus@02100000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + caam@02100000 { + reg = <0x02100000 0x40000>; + interrupts = <0 105 0x04 0 106 0x04>; + }; + + aipstz@0217c000 { /* AIPSTZ2 */ + reg = <0x0217c000 0x4000>; + }; + + enet@02188000 { + compatible = "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupts = <0 118 0x04 0 119 0x04>; + status = "disabled"; + }; + + mlb@0218c000 { + reg = <0x0218c000 0x4000>; + interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; + }; + + usdhc@02190000 { /* uSDHC1 */ + compatible = "fsl,imx6q-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <0 22 0x04>; + status = "disabled"; + }; + + usdhc@02194000 { /* uSDHC2 */ + compatible = "fsl,imx6q-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <0 23 0x04>; + status = "disabled"; + }; + + usdhc@02198000 { /* uSDHC3 */ + compatible = "fsl,imx6q-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = <0 24 0x04>; + status = "disabled"; + }; + + usdhc@0219c000 { /* uSDHC4 */ + compatible = "fsl,imx6q-usdhc"; + reg = <0x0219c000 0x4000>; + interrupts = <0 25 0x04>; + status = "disabled"; + }; + + i2c@021a0000 { /* I2C1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <0 36 0x04>; + status = "disabled"; + }; + + i2c@021a4000 { /* I2C2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <0 37 0x04>; + status = "disabled"; + }; + + i2c@021a8000 { /* I2C3 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <0 38 0x04>; + status = "disabled"; + }; + + romcp@021ac000 { + reg = <0x021ac000 0x4000>; + }; + + mmdc@021b0000 { /* MMDC0 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + mmdc@021b4000 { /* MMDC1 */ + reg = <0x021b4000 0x4000>; + }; + + weim@021b8000 { + reg = <0x021b8000 0x4000>; + interrupts = <0 14 0x04>; + }; + + ocotp@021bc000 { + reg = <0x021bc000 0x4000>; + }; + + ocotp@021c0000 { + reg = <0x021c0000 0x4000>; + interrupts = <0 21 0x04>; + }; + + tzasc@021d0000 { /* TZASC1 */ + reg = <0x021d0000 0x4000>; + interrupts = <0 108 0x04>; + }; + + tzasc@021d4000 { /* TZASC2 */ + reg = <0x021d4000 0x4000>; + interrupts = <0 109 0x04>; + }; + + audmux@021d8000 { + reg = <0x021d8000 0x4000>; + }; + + mipi@021dc000 { /* MIPI-CSI */ + reg = <0x021dc000 0x4000>; + }; + + mipi@021e0000 { /* MIPI-DSI */ + reg = <0x021e0000 0x4000>; + }; + + vdoa@021e4000 { + reg = <0x021e4000 0x4000>; + interrupts = <0 18 0x04>; + }; + + uart2: uart@021e8000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = <0 27 0x04>; + status = "disabled"; + }; + + uart3: uart@021ec000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = <0 28 0x04>; + status = "disabled"; + }; + + uart4: uart@021f0000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = <0 29 0x04>; + status = "disabled"; + }; + + uart5: uart@021f4000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = <0 30 0x04>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/kirkwood-dreamplug.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/kirkwood-dreamplug.dts new file mode 100644 index 000000000..a5376b842 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/kirkwood-dreamplug.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +/include/ "kirkwood.dtsi" + +/ { + model = "Globalscale Technologies Dreamplug"; + compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + serial@12000 { + clock-frequency = <200000000>; + status = "ok"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/kirkwood.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/kirkwood.dtsi new file mode 100644 index 000000000..3474ef890 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/kirkwood.dtsi @@ -0,0 +1,36 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "mrvl,kirkwood"; + + ocp@f1000000 { + compatible = "simple-bus"; + ranges = <0 0xf1000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <33>; + /* set clock-frequency in board dts */ + status = "disabled"; + }; + + serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <34>; + /* set clock-frequency in board dts */ + status = "disabled"; + }; + + rtc@10300 { + compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-iommu.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-iommu.dtsi new file mode 100644 index 000000000..56369dce3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-iommu.dtsi @@ -0,0 +1,40 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm-iommu-v1.dtsi" + +&jpeg_iommu { + status = "ok"; + vdd-supply = <&gdsc_jpeg>; +}; + +&mdp_iommu { + status = "ok"; + vdd-supply = <&gdsc_mdss>; +}; + +&venus_iommu { + status = "ok"; + vdd-supply = <&gdsc_venus>; +}; + +&kgsl_iommu { + status = "ok"; + qcom,needs-alt-core-clk; + vdd-supply = <&gdsc_oxili_cx>; + qcom,alt-vdd-supply = <&gdsc_oxili_gx>; +}; + +&vfe_iommu { + status = "ok"; + vdd-supply = <&gdsc_vfe>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-ion.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-ion.dtsi new file mode 100644 index 000000000..f9f59850a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-ion.dtsi @@ -0,0 +1,33 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + }; +}; + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-regulator.dtsi new file mode 100644 index 000000000..63896e922 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-regulator.dtsi @@ -0,0 +1,324 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* QPNP controlled regulators: */ + +&spmi_bus { + + qcom,pma8084@1 { + pma8084_s1: regulator@1400 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s3: regulator@1a00 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s4: regulator@1d00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_s5: regulator@2000 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_s6: regulator@2300 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_s8: regulator@2900 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_s12: regulator@3500 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + qcom,enable-time = <500>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_l1: regulator@4000 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + qcom,system-load = <10000>; + status = "okay"; + }; + + pma8084_l2: regulator@4100 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l3: regulator@4200 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l4: regulator@4300 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l6: regulator@4500 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l9: regulator@4800 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l10: regulator@4900 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l11: regulator@4a00 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l12: regulator@4b00 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l13: regulator@4c00 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l14: regulator@4d00 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l15: regulator@4e00 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l16: regulator@4f00 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l17: regulator@5000 { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + qcom,system-load = <100000>; + status = "okay"; + }; + + pma8084_l18: regulator@5100 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l19: regulator@5200 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l20: regulator@5300 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l21: regulator@5400 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l22: regulator@5500 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l23: regulator@5600 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_l24: regulator@5700 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + regulator-always-on; + status = "okay"; + }; + + pma8084_l25: regulator@5800 { + parent-supply = <&pma8084_s5>; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + pma8084_l26: regulator@5900 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + pma8084_l27: regulator@5A00 { + parent-supply = <&pma8084_s3>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs1: regulator@8000 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs2: regulator@8100 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs3: regulator@8200 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_lvs4: regulator@8300 { + parent-supply = <&pma8084_s4>; + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + + pma8084_mvs1: regulator@8400 { + qcom,enable-time = <200>; + qcom,pull-down-enable = <1>; + status = "okay"; + }; + }; +}; + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-rumi.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-rumi.dts new file mode 100644 index 000000000..1abaf5596 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-rumi.dts @@ -0,0 +1,28 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "mpq8092.dtsi" +/include/ "mpq8092-rumi.dtsi" + +/ { + model = "Qualcomm MPQ8092 RUMI"; + compatible = "qcom,mpq8092-rumi", "qcom,mpq8092", "qcom,rumi"; + qcom,msm-id = <146 16 0>; +}; + +&soc { + serial@f9922000 { + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-rumi.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-rumi.dtsi new file mode 100644 index 000000000..201699882 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-rumi.dtsi @@ -0,0 +1,134 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + timer { + clock-frequency = <5000000>; + }; + + timer@f9020000 { + clock-frequency = <5000000>; + }; + + usb@f9a55000 { + status = "disable"; + }; + + qcom,sdcc@f9824000 { + status = "disabled"; + qcom,clk-rates = <400000 19200000>; + }; + + qcom,sdcc@f98a4000 { + status = "disabled"; + qcom,clk-rates = <400000 19200000>; + }; + + qcom,sps@f998000 { + status = "disable"; + }; + + spi@f9924000 { + status = "disable"; + }; + + spi@f9923000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 0>; + spi-max-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 3 0>, /* CLK */ + <&msmgpio 1 0>, /* MISO */ + <&msmgpio 0 0>; /* MOSI */ + cs-gpios = <&msmgpio 9 0>; + + ethernet-switch@2 { + compatible = "simtec,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <90 0>; + spi-max-frequency = <5000000>; + }; + }; + + i2c@f9966000 { + status = "disable"; + }; + + i2c@f9967000 { + status = "disable"; + cell-index = <0>; + compatible = "qcom,i2c-qup"; + reg = <0Xf9967000 0x1000>; + reg-names = "qup_phys_addr"; + interrupts = <0 105 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + gpios = <&msmgpio 83 0>,/* DAT */ + <&msmgpio 84 0>;/* CLK */ + }; + + slim@fe12f000 { + status = "disable"; + }; + + qcom,mdss_dsi@fd922800 { + status = "disable"; + }; + + qcom,spmi@fc4c0000 { + status = "disable"; + }; + + qcom,ssusb@F9200000 { + status = "disable"; + }; + + qcom,lpass@fe200000 { + status = "disable"; + }; + + qcom,pronto@fb21b000 { + status = "disable"; + }; + + qcom,mss@fc880000 { + status = "disable"; + }; + + qcom,kgsl-3d0@fdb00000 { + status = "disabled"; + }; +}; + +&gdsc_venus { + status = "disabled"; +}; + +&gdsc_jpeg { + status = "disabled"; +}; + +&gdsc_oxili_gx { + status = "disabled"; +}; + +&gdsc_oxili_cx { + status = "disabled"; +}; + +&gdsc_usb_hsic { + status = "disabled"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-sim.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-sim.dts new file mode 100644 index 000000000..676ef3b17 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092-sim.dts @@ -0,0 +1,125 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "mpq8092.dtsi" + +/ { + model = "Qualcomm MPQ8092 Simulator"; + compatible = "qcom,mpq8092-sim", "qcom,mpq8092", "qcom,sim"; + qcom,msm-id = <126 16 0>; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; + + serial@f995e000 { + status = "ok"; + }; +}; + +&pma8084_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + }; + + gpio@cf00 { /* GPIO 16 */ + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; +}; + +&pma8084_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092.dtsi new file mode 100644 index 000000000..e8674a055 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/mpq8092.dtsi @@ -0,0 +1,240 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MPQ8092"; + compatible = "qcom,mpq8092"; + interrupt-parent = <&intc>; + + soc: soc { }; +}; + +/include/ "mpq8092-iommu.dtsi" +/include/ "msm-gdsc.dtsi" +/include/ "mpq8092-ion.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <146>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0>, <1 3 0>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + serial@f9922000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf9922000 0x1000>; + interrupts = <0 112 0>; + status = "disabled"; + }; + + serial@f995e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf995e000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0 0 187 0>; + qcom,not-wakeup; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>; + reg-names = "core_mem"; + interrupts = <0 123 0>; + interrupt-names = "core_irq"; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <8>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>; + reg-names = "core_mem"; + interrupts = <0 125 0>; + interrupt-names = "core_irq"; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <4>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + }; + + sata: sata@fc580000 { + compatible = "qcom,msm-ahci"; + reg = <0xfc580000 0x17c>; + interrupts = <0 243 0>; + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + }; +}; + +&gdsc_venus { + status = "ok"; +}; + +&gdsc_mdss { + status = "ok"; +}; + +&gdsc_jpeg { + status = "ok"; +}; + +&gdsc_oxili_gx { + status = "ok"; +}; + +&gdsc_oxili_cx { + status = "ok"; +}; + +&gdsc_usb_hsic { + status = "ok"; +}; + +/include/ "msm-pma8084.dtsi" +/include/ "mpq8092-regulator.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-gdsc.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-gdsc.dtsi new file mode 100644 index 000000000..78234e858 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-gdsc.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + gdsc_venus: qcom,gdsc@fd8c1024 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus"; + reg = <0xfd8c1024 0x4>; + status = "disabled"; + }; + + gdsc_mdss: qcom,gdsc@fd8c2304 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_mdss"; + reg = <0xfd8c2304 0x4>; + status = "disabled"; + }; + + gdsc_jpeg: qcom,gdsc@fd8c35a4 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_jpeg"; + reg = <0xfd8c35a4 0x4>; + status = "disabled"; + }; + + gdsc_vfe: qcom,gdsc@fd8c36a4 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe"; + reg = <0xfd8c36a4 0x4>; + status = "disabled"; + }; + + gdsc_oxili_gx: qcom,gdsc@fd8c4024 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_gx"; + reg = <0xfd8c4024 0x4>; + status = "disabled"; + }; + + gdsc_oxili_cx: qcom,gdsc@fd8c4034 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_cx"; + reg = <0xfd8c4034 0x4>; + status = "disabled"; + }; + + gdsc_usb_hsic: qcom,gdsc@fc400404 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_usb_hsic"; + reg = <0xfc400404 0x4>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-iommu-v0.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-iommu-v0.dtsi new file mode 100644 index 000000000..2cfc5cf07 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-iommu-v0.dtsi @@ -0,0 +1,333 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + lpass_iommu: qcom,iommu@fd000000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd000000 0x10000>; + interrupts = <0 248 0>; + qcom,glb-offset = <0xF000>; + label = "lpass_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "lpass_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <11 512 0 0>, + <11 512 0 1000>; + status = "disabled"; + + lpass_q6_fw: qcom,iommu-ctx@fd000000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd000000 0x1000>; + interrupts = <0 250 0>; + qcom,iommu-ctx-mids = <0 15>; + label = "q6_fw"; + }; + + lpass_audio_shared: qcom,iommu-ctx@fd001000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd001000 0x1000>; + interrupts = <0 250 0>; + qcom,iommu-ctx-mids = <1>; + label = "audio_shared"; + }; + + lpass_video_shared: qcom,iommu-ctx@fd002000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd002000 0x1000>; + interrupts = <0 250 0>; + qcom,iommu-ctx-mids = <2>; + label = "video_shared"; + }; + + lpass_q6_spare: qcom,iommu-ctx@fd003000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd003000 0x1000>; + interrupts = <0 250 0>; + qcom,iommu-ctx-mids = <3 4 5 6 7 8 9 10 11 12 13 14>; + label = "q6_spare"; + }; + }; + + copss_iommu: qcom,iommu@fd010000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd010000 0x10000>; + interrupts = <0 252 0>; + qcom,glb-offset = <0xF000>; + label = "copss_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "copss_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <88 512 0 0>, + <88 512 0 1000>; + + status = "disabled"; + + qcom,iommu-ctx@fd010000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd010000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <0>; + label = "copss_0"; + }; + + qcom,iommu-ctx@fd011000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd011000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <1>; + label = "copss_1"; + }; + + qcom,iommu-ctx@fd012000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd012000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <2>; + label = "copss_2"; + }; + + qcom,iommu-ctx@fd013000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd013000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <3>; + label = "copss_3"; + }; + + qcom,iommu-ctx@fd014000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd014000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <4>; + label = "copss_4"; + }; + + qcom,iommu-ctx@fd015000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd015000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <5>; + label = "copss_5"; + }; + + qcom,iommu-ctx@fd016000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd016000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <6>; + label = "copss_6"; + }; + + qcom,iommu-ctx@fd017000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd017000 0x1000>; + interrupts = <0 254 0>; + qcom,iommu-ctx-mids = <7>; + label = "copss_7"; + }; + }; + + mdpe_iommu: qcom,iommu@fd860000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd860000 0x10000>; + interrupts = <0 245 0>; + qcom,glb-offset = <0xF000>; + label = "mdpe_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "mdpe_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <92 512 0 0>, + <92 512 0 1000>; + status = "disabled"; + + qcom,iommu-ctx@fd860000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd860000 0x1000>; + interrupts = <0 247 0>; + qcom,iommu-ctx-mids = <0 1 3>; + label = "mdpe_0"; + }; + + qcom,iommu-ctx@fd861000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd861000 0x1000>; + interrupts = <0 247 0>; + qcom,iommu-ctx-mids = <2>; + label = "mdpe_1"; + }; + }; + + mdps_iommu: qcom,iommu@fd870000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd870000 0x10000>; + interrupts = <0 73 0>; + qcom,glb-offset = <0xF000>; + label = "mdps_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "mdps_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + status = "disabled"; + + qcom,iommu-ctx@fd870000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd870000 0x1000>; + interrupts = <0 47 0>; + qcom,iommu-ctx-mids = <0>; + label = "mdps_0"; + }; + + qcom,iommu-ctx@fd871000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd871000 0x1000>; + interrupts = <0 47 0>; + qcom,iommu-ctx-mids = <1>; + label = "mdps_1"; + }; + }; + + gfx_iommu: qcom,iommu@fd880000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd880000 0x10000>; + interrupts = <0 38 0>; + qcom,glb-offset = <0xF000>; + qcom,needs-alt-core-clk; + label = "gfx_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "gfx_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 1000>; + status = "disabled"; + + qcom,iommu-ctx@fd880000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd880000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-mids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 + 14 15>; + label = "gfx3d_user"; + }; + + qcom,iommu-ctx@fd881000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd881000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-mids = <16 17 18 19 20 21 22 23 24 25 + 26 27 28 29 30 31>; + label = "gfx3d_priv"; + }; + + qcom,iommu-ctx@fd882000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd882000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-mids = <>; + label = "gfx3d_spare"; + }; + }; + + vfe_iommu: qcom,iommu@fd890000 { + compatible = "qcom,msm-smmu-v0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd890000 0x10000>; + interrupts = <0 62 0>; + qcom,glb-offset = <0xF000>; + label = "vfe_iommu"; + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <4>; + qcom,iommu-pmu-event-classes = <0x08 + 0x09 + 0x10 + 0x12 + 0x80>; + qcom,msm-bus,name = "vfe_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 0 1000>; + status = "disabled"; + + qcom,iommu-ctx@fd890000 { + compatible = "qcom,msm-smmu-v0-ctx"; + reg = <0xfd890000 0x1000>; + interrupts = <0 65 0>; + qcom,iommu-ctx-mids = <0 1 2 3 4 5 6 7 8 9>; + label = "vfe0"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-iommu-v1.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-iommu-v1.dtsi new file mode 100644 index 000000000..44920778e --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-iommu-v1.dtsi @@ -0,0 +1,514 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + jpeg_iommu: qcom,iommu@fda64000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfda64000 0x10000>; + reg-names = "iommu_base"; + interrupts = <0 67 0>; + qcom,needs-alt-core-clk; + label = "jpeg_iommu"; + status = "disabled"; + qcom,msm-bus,name = "jpeg_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <62 512 0 0>, + <62 512 0 1000>; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014>; + + qcom,iommu-bfb-data = <0x0000ffff + 0x0 + 0x4 + 0x4 + 0x0 + 0x0 + 0x10 + 0x50 + 0x0 + 0x10 + 0x20 + 0x0 + 0x0 + 0x0 + 0x0>; + + qcom,iommu-ctx@fda6c000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda6c000 0x1000>; + interrupts = <0 70 0>; + qcom,iommu-ctx-sids = <0>; + label = "jpeg_enc0"; + }; + + qcom,iommu-ctx@fda6d000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda6d000 0x1000>; + interrupts = <0 70 0>; + qcom,iommu-ctx-sids = <1>; + label = "jpeg_enc1"; + }; + + qcom,iommu-ctx@fda6e000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda6e000 0x1000>; + interrupts = <0 70 0>; + qcom,iommu-ctx-sids = <2>; + label = "jpeg_dec"; + }; + }; + + mdp_iommu: qcom,iommu@fd928000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfd928000 0x10000>; + reg-names = "iommu_base"; + interrupts = <0 73 0>; + qcom,iommu-secure-id = <1>; + label = "mdp_iommu"; + qcom,msm-bus,name = "mdp_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + status = "disabled"; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x0 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000034 + 0x00000044 + 0x0 + 0x34 + 0x74 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; + + qcom,iommu-ctx@fd930000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfd930000 0x1000>; + interrupts = <0 47 0>; + qcom,iommu-ctx-sids = <0>; + label = "mdp_0"; + }; + + qcom,iommu-ctx@fd931000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfd931000 0x1000>; + interrupts = <0 47 0>, <0 46 0>; + qcom,iommu-ctx-sids = <1>; + label = "mdp_1"; + qcom,secure-context; + }; + + qcom,iommu-ctx@fd932000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfd932000 0x1000>; + interrupts = <0 47 0>, <0 46 0>; + qcom,iommu-ctx-sids = <>; + label = "mdp_2"; + qcom,secure-context; + }; + }; + + venus_iommu: qcom,iommu@fdc84000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfdc84000 0x10000 + 0xfdce0004 0x4>; + reg-names = "iommu_base", "clk_base"; + interrupts = <0 45 0>; + qcom,iommu-secure-id = <0>; + qcom,needs-alt-core-clk; + label = "venus_iommu"; + qcom,msm-bus,name = "venus_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 1000>; + status = "disabled"; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020 + 0x2024 + 0x2028 + 0x202c + 0x2030 + 0x2034 + 0x2038>; + + qcom,iommu-bfb-data = <0xffffffff + 0xffffffff + 0x00000004 + 0x00000008 + 0x00000000 + 0x00000000 + 0x00000094 + 0x000000b4 + 0x0 + 0x94 + 0x114 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; + + venus_ns: qcom,iommu-ctx@fdc8c000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc8c000 0x1000>; + interrupts = <0 42 0>; + qcom,iommu-ctx-sids = <0 1 2 3 4 5>; + label = "venus_ns"; + }; + + venus_cp: qcom,iommu-ctx@fdc8d000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc8d000 0x1000>; + interrupts = <0 42 0>, <0 43 0>; + qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84 0x85>; + label = "venus_cp"; + qcom,secure-context; + }; + + venus_fw: qcom,iommu-ctx@fdc8e000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc8e000 0x1000>; + interrupts = <0 42 0>, <0 43 0>; + qcom,iommu-ctx-sids = <0xc0 0xc6>; + label = "venus_fw"; + qcom,secure-context; + }; + }; + + kgsl_iommu: qcom,iommu@fdb10000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfdb10000 0x10000>; + reg-names = "iommu_base"; + interrupts = <0 38 0>; + label = "kgsl_iommu"; + qcom,msm-bus,name = "kgsl_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 1000>; + status = "disabled"; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008>; + + qcom,iommu-bfb-data = <0x00000003 + 0x0 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000021 + 0x0 + 0x1 + 0x81 + 0x0>; + + qcom,iommu-ctx@fdb18000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdb18000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-sids = <0>; + label = "gfx3d_user"; + }; + + qcom,iommu-ctx@fdb19000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdb19000 0x1000>; + interrupts = <0 241 0>; + qcom,iommu-ctx-sids = <1>; + label = "gfx3d_priv"; + }; + }; + + vfe_iommu: qcom,iommu@fda44000 { + compatible = "qcom,msm-smmu-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfda44000 0x10000>; + reg-names = "iommu_base"; + interrupts = <0 62 0>; + qcom,needs-alt-core-clk; + label = "vfe_iommu"; + qcom,msm-bus,name = "vfe_ebi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 0 1000>; + status = "disabled"; + + qcom,iommu-pmu-ngroups = <1>; + qcom,iommu-pmu-ncounters = <8>; + qcom,iommu-pmu-event-classes = <0x00 + 0x01 + 0x08 + 0x09 + 0x0A + 0x10 + 0x11 + 0x12 + 0x80 + 0x81 + 0x82 + 0x83 + 0x90 + 0x91 + 0x92 + 0xb0 + 0xb1>; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x00000000 + 0x4 + 0x8 + 0x0 + 0x0 + 0x20 + 0x78 + 0x0 + 0x20 + 0x36 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; + + qcom,iommu-ctx@fda4c000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda4c000 0x1000>; + interrupts = <0 65 0>; + qcom,iommu-ctx-sids = <0>; + label = "vfe0"; + }; + + qcom,iommu-ctx@fda4d000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda4d000 0x1000>; + interrupts = <0 65 0>; + qcom,iommu-ctx-sids = <1>; + label = "vfe1"; + }; + + qcom,iommu-ctx@fda4e000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfda4e000 0x1000>; + interrupts = <0 65 0>; + qcom,iommu-ctx-sids = <2>; + label = "cpp"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8019-rpm-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8019-rpm-regulator.dtsi new file mode 100644 index 000000000..c48f67dca --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8019-rpm-regulator.dtsi @@ -0,0 +1,301 @@ +/* Copyright (c) 2012, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa1 { + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s1 { + regulator-name = "8019_s1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa2 { + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s2 { + regulator-name = "8019_s2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa3 { + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s3 { + regulator-name = "8019_s3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa4 { + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s4 { + regulator-name = "8019_s4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa1 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l1 { + regulator-name = "8019_l1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa2 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l2 { + regulator-name = "8019_l2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa3 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l3 { + regulator-name = "8019_l3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa4 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l4 { + regulator-name = "8019_l4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa5 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l5 { + regulator-name = "8019_l5"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa6 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l6 { + regulator-name = "8019_l6"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa7 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l7 { + regulator-name = "8019_l7"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa8 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l8 { + regulator-name = "8019_l8"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa9 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l9 { + regulator-name = "8019_l9"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa10 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l10 { + regulator-name = "8019_l10"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa11 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l11 { + regulator-name = "8019_l11"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa12 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l12 { + regulator-name = "8019_l12"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa13 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l13 { + regulator-name = "8019_l13"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa14 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l14 { + regulator-name = "8019_l14"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8019.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8019.dtsi new file mode 100755 index 000000000..6b5edf7ea --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8019.dtsi @@ -0,0 +1,415 @@ +/* Copyright (c) 2012-2013, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8019@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power_on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x2>; + interrupt-names = "cblpwr"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + + qcom,pon_1 { + qcom,pon-type = <2>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + }; + + clkdiv@5b00 { + reg = <0x5b00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + clkdiv@5c00 { + reg = <0x5c00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + clkdiv@5d00 { + reg = <0x5d00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8019_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm8019_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + + pm8019_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8019-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + }; + }; + + pm8019_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8019-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + + mpp@a400 { + reg = <0xa400 0x100>; + qcom,pin-num = <5>; + }; + + mpp@a500 { + reg = <0xa500 0x100>; + qcom,pin-num = <6>; + }; + }; + + pm8019_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,vadc-poll-eoc; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + pm8019_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + }; + }; + + qcom,pm8019@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8019_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8019_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8019_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8019_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@4000 { + regulator-name = "8019_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8019_l2"; + reg = <0x4100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8019_l3"; + reg = <0x4200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8019_l4"; + reg = <0x4300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8019_l5"; + reg = <0x4400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8019_l6"; + reg = <0x4500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8019_l7"; + reg = <0x4600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8019_l8"; + reg = <0x4700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8019_l9"; + reg = <0x4800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8019_l10"; + reg = <0x4900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4a00 { + regulator-name = "8019_l11"; + reg = <0x4a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8019_l12"; + reg = <0x4b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4c00 { + regulator-name = "8019_l13"; + reg = <0x4c00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8019_l14"; + reg = <0x4d00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8019_ldo_xo"; + reg = <0x4e00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8019_ldo_rfclk"; + reg = <0x4f00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8110-rpm-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8110-rpm-regulator.dtsi new file mode 100644 index 000000000..0de72b0de --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8110-rpm-regulator.dtsi @@ -0,0 +1,381 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l8"; + qcom,set = <1>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8110.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8110.dtsi new file mode 100644 index 000000000..1877f40d7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8110.dtsi @@ -0,0 +1,608 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8110@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0>, + <0x0 0x8 0x1>, + <0x0 0x8 0x4>; + interrupt-names = "kpdpwr", "resin", "resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + }; + + pm8110_chg: qcom,charger { + spmi-dev-container; + compatible = "qcom,qpnp-charger"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,vddmax-mv = <4200>; + qcom,vddsafe-mv = <4230>; + qcom,vinmin-mv = <4200>; + qcom,vbatdet-mv = <4100>; + qcom,ibatmax-ma = <1500>; + qcom,ibatterm-ma = <200>; + qcom,ibatsafe-ma = <1500>; + qcom,thermal-mitigation = <1500 700 600 325>; + qcom,vbatdet-delta-mv = <350>; + qcom,tchg-mins = <150>; + + qcom,chgr@1000 { + status = "disabled"; + reg = <0x1000 0x100>; + interrupts = <0x0 0x10 0x0>, + <0x0 0x10 0x1>, + <0x0 0x10 0x2>, + <0x0 0x10 0x3>, + <0x0 0x10 0x4>, + <0x0 0x10 0x5>, + <0x0 0x10 0x6>, + <0x0 0x10 0x7>; + + interrupt-names = "vbat-det-lo", + "vbat-det-hi", + "chgwdog", + "state-change", + "trkl-chg-on", + "fast-chg-on", + "chg-failed", + "chg-done"; + }; + + qcom,buck@1100 { + status = "disabled"; + reg = <0x1100 0x100>; + interrupts = <0x0 0x11 0x0>, + <0x0 0x11 0x1>, + <0x0 0x11 0x2>, + <0x0 0x11 0x3>, + <0x0 0x11 0x4>, + <0x0 0x11 0x5>, + <0x0 0x11 0x6>; + + interrupt-names = "vbat-ov", + "vreg-ov", + "overtemp", + "vchg-loop", + "ichg-loop", + "ibat-loop", + "vdd-loop"; + }; + + qcom,bat-if@1200 { + status = "disabled"; + reg = <0x1200 0x100>; + interrupts = <0x0 0x12 0x0>, + <0x0 0x12 0x1>, + <0x0 0x12 0x2>, + <0x0 0x12 0x3>, + <0x0 0x12 0x4>; + + interrupt-names = "batt-pres", + "bat-temp-ok", + "bat-fet-on", + "vcp-on", + "psi"; + }; + + qcom,usb-chgpth@1300 { + status = "disabled"; + reg = <0x1300 0x100>; + interrupts = <0 0x13 0x0>, + <0 0x13 0x1>, + <0x0 0x13 0x2>; + + interrupt-names = "coarse-det-usb", + "usbin-valid", + "chg-gone"; + }; + + qcom,chg-misc@1600 { + status = "disabled"; + reg = <0x1600 0x100>; + }; + }; + + pm8110_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8110-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + }; + + pm8110_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8110-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + }; + + pm8110_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + iadc@3600 { + compatible = "qcom,qpnp-iadc"; + reg = <0x3600 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x36 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <16>; + qcom,adc-vdd-reference = <1800>; + + chan@0 { + label = "internal_rsense"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + pm8110_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0>; + label = "pm8110_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + }; + + pm8110_bms: qcom,bms { + spmi-dev-container; + compatible = "qcom,qpnp-bms"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,r-sense-uohm = <10000>; + qcom,v-cutoff-uv = <3400000>; + qcom,max-voltage-uv = <4200000>; + qcom,r-conn-mohm = <0>; + qcom,shutdown-soc-valid-limit = <20>; + qcom,adjust-soc-low-threshold = <15>; + qcom,ocv-voltage-high-threshold-uv = <3750000>; + qcom,ocv-voltage-low-threshold-uv = <3650000>; + qcom,low-soc-calculate-soc-threshold = <15>; + qcom,low-soc-calculate-soc-ms = <5000>; + qcom,calculate-soc-ms = <20000>; + qcom,chg-term-ua = <100000>; + qcom,batt-type = <0>; + qcom,low-voltage-threshold = <3420000>; + qcom,tm-temp-margin = <5000>; + qcom,low-ocv-correction-limit-uv = <100>; + qcom,high-ocv-correction-limit-uv = <50>; + qcom,hold-soc-est = <3>; + + qcom,bms-iadc@3800 { + reg = <0x3800 0x100>; + }; + + qcom,bms-bms@4000 { + reg = <0x4000 0x100>; + interrupts = <0x0 0x40 0x0>, + <0x0 0x40 0x1>, + <0x0 0x40 0x2>, + <0x0 0x40 0x3>, + <0x0 0x40 0x4>, + <0x0 0x40 0x5>, + <0x0 0x40 0x6>, + <0x0 0x40 0x7>; + + interrupt-names = "vsense_for_r", + "vsense_avg", + "sw_cc_thr", + "ocv_thr", + "charge_begin", + "good_ocv", + "ocv_for_r", + "cc_thr"; + }; + }; + + qcom,pm8110_rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8110_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm8110_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + + qcom,leds@a100 { + compatible = "qcom,leds-qpnp"; + reg = <0xa100 0x100>; + label = "mpp"; + }; + + qcom,leds@a200 { + compatible = "qcom,leds-qpnp"; + reg = <0xa200 0x100>; + label = "mpp"; + }; + }; + + qcom,pm8110@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@4000 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l1"; + reg = <0x4000 0x100>; + status = "disabled"; + }; + + regulator@4100 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l2"; + reg = <0x4100 0x100>; + status = "disabled"; + }; + + regulator@4200 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l3"; + reg = <0x4200 0x100>; + status = "disabled"; + }; + + regulator@4300 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l4"; + reg = <0x4300 0x100>; + status = "disabled"; + }; + + regulator@4400 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l5"; + reg = <0x4400 0x100>; + status = "disabled"; + }; + + regulator@4500 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l6"; + reg = <0x4500 0x100>; + status = "disabled"; + }; + + regulator@4600 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l7"; + reg = <0x4600 0x100>; + status = "disabled"; + }; + + regulator@4700 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l8"; + reg = <0x4700 0x100>; + status = "disabled"; + }; + + regulator@4800 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l9"; + reg = <0x4800 0x100>; + status = "disabled"; + }; + + regulator@4900 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l10"; + reg = <0x4900 0x100>; + status = "disabled"; + }; + + regulator@4b00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l12"; + reg = <0x4b00 0x100>; + status = "disabled"; + }; + + regulator@4d00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l14"; + reg = <0x4d00 0x100>; + status = "disabled"; + }; + + regulator@4e00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l15"; + reg = <0x4e00 0x100>; + status = "disabled"; + }; + + regulator@4f00 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l16"; + reg = <0x4f00 0x100>; + status = "disabled"; + }; + + regulator@5000 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l17"; + reg = <0x5000 0x100>; + status = "disabled"; + }; + + regulator@5100 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l18"; + reg = <0x5100 0x100>; + status = "disabled"; + }; + + regulator@5200 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l19"; + reg = <0x5200 0x100>; + status = "disabled"; + }; + + regulator@5300 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l20"; + reg = <0x5300 0x100>; + status = "disabled"; + }; + + regulator@5400 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l21"; + reg = <0x5400 0x100>; + status = "disabled"; + }; + + regulator@5500 { + compatible = "qcom,qpnp-regulator"; + regulator-name = "8110_l22"; + reg = <0x5500 0x100>; + status = "disabled"; + }; + + qcom,vibrator@c000 { + compatible = "qcom,qpnp-vibrator"; + reg = <0xc000 0x100>; + label = "vibrator"; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8226-rpm-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8226-rpm-regulator.dtsi new file mode 100644 index 000000000..ded949489 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8226-rpm-regulator.dtsi @@ -0,0 +1,492 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l8"; + qcom,set = <1>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa24 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l24 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l24"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa26 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <26>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l26 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l26"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa27 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <27>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l27 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l27"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa28 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <28>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l28 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l28"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-vsa1 { + compatible = "qcom,rpm-regulator-smd-resource"; + qcom,resource-name = "vsa"; + qcom,resource-id = <1>; + qcom,regulator-type = <2>; + status = "disabled"; + + regulator-lvs1 { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_lvs1"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8226.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8226.dtsi new file mode 100644 index 000000000..d429f72b7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8226.dtsi @@ -0,0 +1,833 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8226@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0>, + <0x0 0x8 0x1>, + <0x0 0x8 0x4>; + interrupt-names = "kpdpwr", "resin", "resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <0>; + qcom,s2-timer = <2000>; + qcom,s2-type = <1>; + linux,code = <114>; + }; + }; + + pm8226_chg: qcom,charger { + spmi-dev-container; + compatible = "qcom,qpnp-charger"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,vddmax-mv = <4200>; + qcom,vddsafe-mv = <4230>; + qcom,vinmin-mv = <4200>; + qcom,vbatdet-delta-mv = <150>; + qcom,ibatmax-ma = <1500>; + qcom,ibatterm-ma = <100>; + qcom,ibatsafe-ma = <1500>; + qcom,thermal-mitigation = <1500 700 600 325>; + qcom,tchg-mins = <150>; + + qcom,chgr@1000 { + status = "disabled"; + reg = <0x1000 0x100>; + interrupts = <0x0 0x10 0x0>, + <0x0 0x10 0x1>, + <0x0 0x10 0x2>, + <0x0 0x10 0x3>, + <0x0 0x10 0x4>, + <0x0 0x10 0x5>, + <0x0 0x10 0x6>, + <0x0 0x10 0x7>; + + interrupt-names = "vbat-det-lo", + "vbat-det-hi", + "chgwdog", + "state-change", + "trkl-chg-on", + "fast-chg-on", + "chg-failed", + "chg-done"; + }; + + qcom,buck@1100 { + status = "disabled"; + reg = <0x1100 0x100>; + interrupts = <0x0 0x11 0x0>, + <0x0 0x11 0x1>, + <0x0 0x11 0x2>, + <0x0 0x11 0x3>, + <0x0 0x11 0x4>, + <0x0 0x11 0x5>, + <0x0 0x11 0x6>; + + interrupt-names = "vbat-ov", + "vreg-ov", + "overtemp", + "vchg-loop", + "ichg-loop", + "ibat-loop", + "vdd-loop"; + }; + + qcom,bat-if@1200 { + status = "disabled"; + reg = <0x1200 0x100>; + interrupts = <0x0 0x12 0x0>, + <0x0 0x12 0x1>, + <0x0 0x12 0x2>, + <0x0 0x12 0x3>, + <0x0 0x12 0x4>; + + interrupt-names = "batt-pres", + "bat-temp-ok", + "bat-fet-on", + "vcp-on", + "psi"; + + }; + + pm8226_chg_otg: qcom,usb-chgpth@1300 { + status = "disabled"; + reg = <0x1300 0x100>; + interrupts = <0 0x13 0x0>, + <0 0x13 0x1>, + <0x0 0x13 0x2>; + + interrupt-names = "coarse-det-usb", + "usbin-valid", + "chg-gone"; + }; + + pm8226_chg_boost: qcom,boost@1500 { + status = "disabled"; + reg = <0x1500 0x100>; + interrupts = <0x0 0x15 0x0>, + <0x0 0x15 0x1>; + + interrupt-names = "boost-pwr-ok", + "limit-error"; + }; + + qcom,chg-misc@1600 { + status = "disabled"; + reg = <0x1600 0x100>; + }; + }; + + pm8226_bms: qcom,bms { + spmi-dev-container; + compatible = "qcom,qpnp-bms"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,r-sense-uohm = <10000>; + qcom,v-cutoff-uv = <3400000>; + qcom,max-voltage-uv = <4200000>; + qcom,r-conn-mohm = <0>; + qcom,shutdown-soc-valid-limit = <20>; + qcom,adjust-soc-low-threshold = <15>; + qcom,ocv-voltage-high-threshold-uv = <3750000>; + qcom,ocv-voltage-low-threshold-uv = <3650000>; + qcom,low-soc-calculate-soc-threshold = <15>; + qcom,low-soc-calculate-soc-ms = <5000>; + qcom,calculate-soc-ms = <20000>; + qcom,chg-term-ua = <100000>; + qcom,batt-type = <0>; + qcom,tm-temp-margin = <5000>; + qcom,low-ocv-correction-limit-uv = <100>; + qcom,high-ocv-correction-limit-uv = <50>; + qcom,hold-soc-est = <3>; + qcom,low-voltage-threshold = <3420000>; + + qcom,bms-iadc@3800 { + reg = <0x3800 0x100>; + }; + + qcom,bms-bms@4000 { + reg = <0x4000 0x100>; + interrupts = <0x0 0x40 0x0>, + <0x0 0x40 0x1>, + <0x0 0x40 0x2>, + <0x0 0x40 0x3>, + <0x0 0x40 0x4>, + <0x0 0x40 0x5>, + <0x0 0x40 0x6>, + <0x0 0x40 0x7>; + + interrupt-names = "vsense_for_r", + "vsense_avg", + "sw_cc_thr", + "ocv_thr", + "charge_begin", + "good_ocv", + "ocv_for_r", + "cc_thr"; + }; + }; + + qcom,leds@a100 { + compatible = "qcom,leds-qpnp"; + reg = <0xa100 0x100>; + label = "mpp"; + }; + + qcom,leds@a300 { + compatible = "qcom,leds-qpnp"; + reg = <0xa300 0x100>; + label = "mpp"; + }; + + qcom,leds@a500 { + compatible = "qcom,leds-qpnp"; + reg = <0xa500 0x100>; + label = "mpp"; + }; + + pm8226_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8226-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + }; + }; + + pm8226_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8226-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + + mpp@a400 { + reg = <0xa400 0x100>; + qcom,pin-num = <5>; + }; + + mpp@a500 { + reg = <0xa500 0x100>; + qcom,pin-num = <6>; + }; + + mpp@a600 { + reg = <0xa600 0x100>; + qcom,pin-num = <7>; + }; + + mpp@a700 { + reg = <0xa700 0x100>; + qcom,pin-num = <8>; + }; + }; + + pm8226_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@c { + label = "ref_buf_625mv"; + reg = <0xc>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + iadc@3600 { + compatible = "qcom,qpnp-iadc"; + reg = <0x3600 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x36 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <16>; + qcom,adc-vdd-reference = <1800>; + + chan@0 { + label = "internal_rsense"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + pm8226_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0>; + label = "pm8226_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + }; + + qcom,pm8226_rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8226_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm8226_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + }; + + qcom,pm8226@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8226_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8226_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8226_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8226_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@2000 { + regulator-name = "8226_s5"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2000 0x300>; + status = "disabled"; + + qcom,ctl@2000 { + reg = <0x2000 0x100>; + }; + qcom,ps@2100 { + reg = <0x2100 0x100>; + }; + qcom,freq@2200 { + reg = <0x2200 0x100>; + }; + }; + + regulator@4000 { + regulator-name = "8226_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8226_l2"; + reg = <0x4100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8226_l3"; + reg = <0x4200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8226_l4"; + reg = <0x4300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8226_l5"; + reg = <0x4400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8226_l6"; + reg = <0x4500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8226_l7"; + reg = <0x4600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8226_l8"; + reg = <0x4700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8226_l9"; + reg = <0x4800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8226_l10"; + reg = <0x4900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8226_l12"; + reg = <0x4b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8226_l14"; + reg = <0x4d00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8226_l15"; + reg = <0x4e00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8226_l16"; + reg = <0x4f00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5000 { + regulator-name = "8226_l17"; + reg = <0x5000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5100 { + regulator-name = "8226_l18"; + reg = <0x5100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5200 { + regulator-name = "8226_l19"; + reg = <0x5200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5300 { + regulator-name = "8226_l20"; + reg = <0x5300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5400 { + regulator-name = "8226_l21"; + reg = <0x5400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5500 { + regulator-name = "8226_l22"; + reg = <0x5500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5600 { + regulator-name = "8226_l23"; + reg = <0x5600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5700 { + regulator-name = "8226_l24"; + reg = <0x5700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5900 { + regulator-name = "8226_l26"; + reg = <0x5900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5a00 { + regulator-name = "8226_l27"; + reg = <0x5a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5b00 { + regulator-name = "8226_l28"; + reg = <0x5b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + qcom,leds@d800 { + compatible = "qcom,leds-qpnp"; + reg = <0xd800 0x100>; + label = "wled"; + }; + + pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <0>; + }; + + pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <1>; + }; + + pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <2>; + }; + + pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <3>; + }; + + pwm@b500 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb500 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <4>; + }; + + pwm@b600 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb600 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <5>; + }; + + regulator@8000 { + regulator-name = "8226_lvs1"; + reg = <0x8000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + qcom,vibrator@c000 { + compatible = "qcom,qpnp-vibrator"; + reg = <0xc000 0x100>; + label = "vibrator"; + status = "disabled"; + }; + + qcom,leds@d300 { + compatible = "qcom,leds-qpnp"; + status = "okay"; + reg = <0xd300 0x100>; + label = "flash"; + flash_boost-supply = <&pm8226_chg_boost>; + pm8226_flash0: qcom,flash_0 { + qcom,max-current = <1000>; + qcom,default-state = "off"; + qcom,headroom = <0>; + qcom,duration = <1280>; + qcom,clamp-curr = <200>; + qcom,startup-dly = <1>; + qcom,safety-timer; + label = "flash"; + linux,default-trigger = + "flash0_trigger"; + qcom,id = <1>; + linux,name = "led:flash_0"; + qcom,current = <625>; + }; + + pm8226_flash1: qcom,flash_1 { + qcom,max-current = <1000>; + qcom,default-state = "off"; + qcom,headroom = <0>; + qcom,duration = <1280>; + qcom,clamp-curr = <200>; + qcom,startup-dly = <1>; + qcom,safety-timer; + linux,default-trigger = + "flash1_trigger"; + label = "flash"; + qcom,id = <2>; + linux,name = "led:flash_1"; + qcom,current = <625>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8841.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8841.dtsi new file mode 100644 index 000000000..a2d80ec05 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8841.dtsi @@ -0,0 +1,242 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8841@4 { + spmi-slave-container; + reg = <0x4>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,qpnp-revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x4 0x24 0x0>; + label = "pm8841_tz"; + qcom,threshold-set = <0>; + qcom,default-temp = <37000>; + }; + + pm8841_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8841-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + }; + }; + + qcom,pm8841@5 { + spmi-slave-container; + reg = <0x5>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8841_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8841_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8841_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8841_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@2000 { + regulator-name = "8841_s5"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2000 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@0 { + reg = <0x2000 0x100>; + }; + qcom,ps@100 { + reg = <0x2100 0x100>; + }; + qcom,freq@200 { + reg = <0x2200 0x100>; + }; + }; + + regulator@2300 { + regulator-name = "8841_s6"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2300 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@2300 { + reg = <0x2300 0x100>; + }; + qcom,ps@2400 { + reg = <0x2400 0x100>; + }; + qcom,freq@2500 { + reg = <0x2500 0x100>; + }; + }; + + regulator@2600 { + regulator-name = "8841_s7"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2600 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@2600 { + reg = <0x2600 0x100>; + }; + qcom,ps@2700 { + reg = <0x2700 0x100>; + }; + qcom,freq@2800 { + reg = <0x2800 0x100>; + }; + }; + + regulator@2900 { + regulator-name = "8841_s8"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2900 0x300>; + status = "disabled"; + qcom,force-type = <0x1c 0x08>; + + qcom,ctl@2900 { + reg = <0x2900 0x100>; + }; + qcom,ps@2a000 { + reg = <0x2a00 0x100>; + }; + qcom,freq@2b00 { + reg = <0x2b00 0x100>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8941.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8941.dtsi new file mode 100644 index 000000000..b4e557e16 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8941.dtsi @@ -0,0 +1,1384 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pm8941@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + pm8941_misc: qcom,misc@900 { + compatible = "qcom,qpnp-misc"; + reg = <0x900 0x100>; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0>; + label = "pm8941_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0>, + <0x0 0x8 0x1>, + <0x0 0x8 0x4>; + interrupt-names = "kpdpwr", "resin", "resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <0>; + qcom,s2-timer = <2000>; + qcom,s2-type = <1>; + linux,code = <114>; + }; + }; + + bif_ctrl: qcom,bsi@1b00 { + compatible = "qcom,qpnp-bsi"; + reg = <0x1b00 0x100>, + <0x1208 0x1>; + reg-names = "bsi-base", "batt-id-status"; + label = "pm8941-bsi"; + interrupts = <0x0 0x1b 0x0>, + <0x0 0x1b 0x1>, + <0x0 0x1b 0x2>, + <0x0 0x12 0x0>; + interrupt-names = "err", + "rx", + "tx", + "batt-present"; + qcom,channel-num = <0x31>; + qcom,pullup-ohms = <100000>; + qcom,vref-microvolts = <1800000>; + qcom,min-clock-period = <1000>; + qcom,max-clock-period = <160000>; + qcom,sample-rate = <4>; + }; + + pm8941_coincell: qcom,coincell@2800 { + compatible = "qcom,qpnp-coincell"; + reg = <0x2800 0x100>; + }; + + pm8941_bms: qcom,bms { + spmi-dev-container; + compatible = "qcom,qpnp-bms"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,r-sense-uohm = <10000>; + qcom,v-cutoff-uv = <3400000>; + qcom,max-voltage-uv = <4200000>; + qcom,r-conn-mohm = <0>; + qcom,shutdown-soc-valid-limit = <20>; + qcom,adjust-soc-low-threshold = <15>; + qcom,ocv-voltage-high-threshold-uv = <3750000>; + qcom,ocv-voltage-low-threshold-uv = <3650000>; + qcom,low-soc-calculate-soc-threshold = <15>; + qcom,low-soc-calculate-soc-ms = <5000>; + qcom,calculate-soc-ms = <20000>; + qcom,chg-term-ua = <100000>; + qcom,batt-type = <0>; + qcom,low-voltage-threshold = <3420000>; + qcom,tm-temp-margin = <5000>; + qcom,low-ocv-correction-limit-uv = <100>; + qcom,high-ocv-correction-limit-uv = <50>; + qcom,hold-soc-est = <3>; + + qcom,bms-iadc@3800 { + reg = <0x3800 0x100>; + }; + + qcom,bms-bms@4000 { + reg = <0x4000 0x100>; + interrupts = <0x0 0x40 0x0>, + <0x0 0x40 0x1>, + <0x0 0x40 0x2>, + <0x0 0x40 0x3>, + <0x0 0x40 0x4>, + <0x0 0x40 0x5>, + <0x0 0x40 0x6>, + <0x0 0x40 0x7>; + + interrupt-names = "vsense_for_r", + "vsense_avg", + "sw_cc_thr", + "ocv_thr", + "charge_begin", + "good_ocv", + "ocv_for_r", + "cc_thr"; + }; + }; + + clkdiv@5b00 { + reg = <0x5b00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + clkdiv@5c00 { + reg = <0x5c00 0x100>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + clkdiv@5d00 { + reg = <0x5d00 0x1000>; + compatible = "qcom,qpnp-clkdiv"; + qcom,cxo-freq = <19200000>; + }; + + pm8941_chg: qcom,charger { + spmi-dev-container; + compatible = "qcom,qpnp-charger"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,vddmax-mv = <4200>; + qcom,vddsafe-mv = <4230>; + qcom,vinmin-mv = <4300>; + qcom,ibatmax-ma = <1500>; + qcom,ibatterm-ma = <100>; + qcom,ibatsafe-ma = <1500>; + qcom,thermal-mitigation = <1500 700 600 325>; + qcom,cool-bat-decidegc = <100>; + qcom,cool-bat-mv = <4100>; + qcom,ibatmax-warm-ma = <350>; + qcom,warm-bat-decidegc = <450>; + qcom,warm-bat-mv = <4100>; + qcom,ibatmax-cool-ma = <350>; + qcom,vbatdet-delta-mv = <100>; + qcom,tchg-mins = <150>; + + qcom,chgr@1000 { + status = "disabled"; + reg = <0x1000 0x100>; + interrupts = <0x0 0x10 0x0>, + <0x0 0x10 0x1>, + <0x0 0x10 0x2>, + <0x0 0x10 0x3>, + <0x0 0x10 0x4>, + <0x0 0x10 0x5>, + <0x0 0x10 0x6>, + <0x0 0x10 0x7>; + + interrupt-names = "vbat-det-lo", + "vbat-det-hi", + "chgwdog", + "state-change", + "trkl-chg-on", + "fast-chg-on", + "chg-failed", + "chg-done"; + }; + + qcom,buck@1100 { + status = "disabled"; + reg = <0x1100 0x100>; + interrupts = <0x0 0x11 0x0>, + <0x0 0x11 0x1>, + <0x0 0x11 0x2>, + <0x0 0x11 0x3>, + <0x0 0x11 0x4>, + <0x0 0x11 0x5>, + <0x0 0x11 0x6>; + + interrupt-names = "vbat-ov", + "vreg-ov", + "overtemp", + "vchg-loop", + "ichg-loop", + "ibat-loop", + "vdd-loop"; + }; + + qcom,bat-if@1200 { + status = "disabled"; + reg = <0x1200 0x100>; + interrupts = <0x0 0x12 0x0>, + <0x0 0x12 0x1>, + <0x0 0x12 0x2>, + <0x0 0x12 0x3>, + <0x0 0x12 0x4>; + + interrupt-names = "batt-pres", + "bat-temp-ok", + "bat-fet-on", + "vcp-on", + "psi"; + + }; + + pm8941_chg_otg: qcom,usb-chgpth@1300 { + status = "disabled"; + reg = <0x1300 0x100>; + interrupts = <0 0x13 0x0>, + <0 0x13 0x1>, + <0x0 0x13 0x2>; + + interrupt-names = "coarse-det-usb", + "usbin-valid", + "chg-gone"; + }; + + qcom,dc-chgpth@1400 { + status = "disabled"; + reg = <0x1400 0x100>; + interrupts = <0x0 0x14 0x0>, + <0x0 0x14 0x1>; + + interrupt-names = "coarse-det-dc", + "dcin-valid"; + }; + + pm8941_chg_boost: qcom,boost@1500 { + status = "disabled"; + reg = <0x1500 0x100>; + interrupts = <0x0 0x15 0x0>, + <0x0 0x15 0x1>; + + interrupt-names = "boost-pwr-ok", + "limit-error"; + }; + + qcom,chg-misc@1600 { + status = "disabled"; + reg = <0x1600 0x100>; + }; + }; + + pm8941_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8941-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + }; + + gpio@cd00 { + reg = <0xcd00 0x100>; + qcom,pin-num = <14>; + }; + + gpio@ce00 { + reg = <0xce00 0x100>; + qcom,pin-num = <15>; + }; + + gpio@cf00 { + reg = <0xcf00 0x100>; + qcom,pin-num = <16>; + }; + + gpio@d000 { + reg = <0xd000 0x100>; + qcom,pin-num = <17>; + }; + + gpio@d100 { + reg = <0xd100 0x100>; + qcom,pin-num = <18>; + }; + + gpio@d200 { + reg = <0xd200 0x100>; + qcom,pin-num = <19>; + }; + + gpio@d300 { + reg = <0xd300 0x100>; + qcom,pin-num = <20>; + }; + + gpio@d400 { + reg = <0xd400 0x100>; + qcom,pin-num = <21>; + }; + + gpio@d500 { + reg = <0xd500 0x100>; + qcom,pin-num = <22>; + }; + + gpio@d600 { + reg = <0xd600 0x100>; + qcom,pin-num = <23>; + }; + + gpio@d700 { + reg = <0xd700 0x100>; + qcom,pin-num = <24>; + }; + + gpio@d800 { + reg = <0xd800 0x100>; + qcom,pin-num = <25>; + }; + + gpio@d900 { + reg = <0xd900 0x100>; + qcom,pin-num = <26>; + }; + + gpio@da00 { + reg = <0xda00 0x100>; + qcom,pin-num = <27>; + }; + + gpio@db00 { + reg = <0xdb00 0x100>; + qcom,pin-num = <28>; + }; + + gpio@dc00 { + reg = <0xdc00 0x100>; + qcom,pin-num = <29>; + }; + + gpio@dd00 { + reg = <0xdd00 0x100>; + qcom,pin-num = <30>; + }; + + gpio@de00 { + reg = <0xde00 0x100>; + qcom,pin-num = <31>; + }; + + gpio@df00 { + reg = <0xdf00 0x100>; + qcom,pin-num = <32>; + }; + + gpio@e000 { + reg = <0xe000 0x100>; + qcom,pin-num = <33>; + }; + + gpio@e100 { + reg = <0xe100 0x100>; + qcom,pin-num = <34>; + }; + + gpio@e200 { + reg = <0xe200 0x100>; + qcom,pin-num = <35>; + }; + + gpio@e300 { + reg = <0xe300 0x100>; + qcom,pin-num = <36>; + }; + }; + + pm8941_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8941-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + + mpp@a400 { + reg = <0xa400 0x100>; + qcom,pin-num = <5>; + }; + + mpp@a500 { + reg = <0xa500 0x100>; + qcom,pin-num = <6>; + }; + + mpp@a600 { + reg = <0xa600 0x100>; + qcom,pin-num = <7>; + }; + + mpp@a700 { + reg = <0xa700 0x100>; + qcom,pin-num = <8>; + }; + }; + + qcom,pm8941_rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8941_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm8941_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + + vadc@3100 { + compatible = "qcom,qpnp-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + chan@0 { + label = "usb_in"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@1 { + label = "dc_in"; + reg = <1>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@2 { + label = "vchg_sns"; + reg = <2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <3>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@3 { + label = "spare1_div3"; + reg = <3>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4 { + label = "usb_id_mv"; + reg = <4>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@31 { + label = "batt_id"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b2 { + label = "xo_therm_pu2"; + reg = <0xb2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b3 { + label = "msm_therm"; + reg = <0xb3>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b4 { + label = "emmc_therm"; + reg = <0xb4>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b5 { + label = "pa_therm0"; + reg = <0xb5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b7 { + label = "pa_therm1"; + reg = <0xb7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b8 { + label = "quiet_therm"; + reg = <0xb8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b9 { + label = "usb_id"; + reg = <0xb9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@39 { + label = "usb_id_nopull"; + reg = <0x39>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + }; + + iadc@3600 { + compatible = "qcom,qpnp-iadc"; + reg = <0x3600 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x36 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <16>; + qcom,adc-vdd-reference = <1800>; + + chan@0 { + label = "internal_rsense"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + qcom,vadc@3400 { + compatible = "qcom,qpnp-adc-tm"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + + /* Channel Node */ + chan@b9 { + label = "usb_id"; + reg = <0xb9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x48>; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x68>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x70>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x78>; + }; + + chan@b5 { + label = "pa_therm0"; + reg = <0xb5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x80>; + qcom,thermal-node; + }; + + chan@b7 { + label = "pa_therm1"; + reg = <0xb7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x88>; + qcom,thermal-node; + }; + + chan@b4 { + label = "emmc_therm"; + reg = <0xb4>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x90>; + qcom,thermal-node; + }; + + chan@b3 { + label = "msm_therm"; + reg = <0xb3>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x98>; + qcom,thermal-node; + }; + }; + }; + + qcom,pm8941@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8941_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8941_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8941_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@a000 { + regulator-name = "8941_boost"; + reg = <0xa000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4000 { + regulator-name = "8941_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8941_l2"; + reg = <0x4100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8941_l3"; + reg = <0x4200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8941_l4"; + reg = <0x4300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8941_l5"; + reg = <0x4400 0x100>; + compatible = "qcom,qpnp-regulator"; + qcom,force-type = <0x04 0x10>; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8941_l6"; + reg = <0x4500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8941_l7"; + reg = <0x4600 0x100>; + compatible = "qcom,qpnp-regulator"; + qcom,force-type = <0x04 0x10>; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8941_l8"; + reg = <0x4700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8941_l9"; + reg = <0x4800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8941_l10"; + reg = <0x4900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4a00 { + regulator-name = "8941_l11"; + reg = <0x4a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8941_l12"; + reg = <0x4b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4c00 { + regulator-name = "8941_l13"; + reg = <0x4c00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8941_l14"; + reg = <0x4d00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8941_l15"; + reg = <0x4e00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8941_l16"; + reg = <0x4f00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5000 { + regulator-name = "8941_l17"; + reg = <0x5000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5100 { + regulator-name = "8941_l18"; + reg = <0x5100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5200 { + regulator-name = "8941_l19"; + reg = <0x5200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5300 { + regulator-name = "8941_l20"; + reg = <0x5300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5400 { + regulator-name = "8941_l21"; + reg = <0x5400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5500 { + regulator-name = "8941_l22"; + reg = <0x5500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5600 { + regulator-name = "8941_l23"; + reg = <0x5600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5700 { + regulator-name = "8941_l24"; + reg = <0x5700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8000 { + regulator-name = "8941_lvs1"; + reg = <0x8000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8100 { + regulator-name = "8941_lvs2"; + reg = <0x8100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8200 { + regulator-name = "8941_lvs3"; + reg = <0x8200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8300 { + regulator-name = "8941_mvs1"; + reg = <0x8300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8400 { + regulator-name = "8941_mvs2"; + reg = <0x8400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + qcom,vibrator@c000 { + compatible = "qcom,qpnp-vibrator"; + reg = <0xc000 0x100>; + label = "vibrator"; + status = "disabled"; + }; + + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + }; + + qcom,leds@d100 { + compatible = "qcom,leds-qpnp"; + reg = <0xd100 0x100>; + label = "rgb"; + }; + + qcom,leds@d200 { + compatible = "qcom,leds-qpnp"; + reg = <0xd200 0x100>; + label = "rgb"; + }; + + qcom,leds@d300 { + compatible = "qcom,leds-qpnp"; + reg = <0xd300 0x100>; + label = "flash"; + flash_boost-supply = <&pm8941_chg_boost>; + }; + + qcom,leds@d400 { + compatible = "qcom,leds-qpnp"; + reg = <0xd400 0x100>; + label = "flash"; + }; + + qcom,leds@d500 { + compatible = "qcom,leds-qpnp"; + reg = <0xd500 0x100>; + label = "flash"; + }; + + qcom,leds@d600 { + compatible = "qcom,leds-qpnp"; + reg = <0xd600 0x100>; + label = "flash"; + }; + + qcom,leds@d700 { + compatible = "qcom,leds-qpnp"; + reg = <0xd700 0x100>; + label = "flash"; + }; + + qcom,leds@d800 { + compatible = "qcom,leds-qpnp"; + reg = <0xd800 0x100>; + label = "wled"; + }; + + qcom,leds@d900 { + compatible = "qcom,leds-qpnp"; + reg = <0xd900 0x100>; + label = "wled"; + }; + + qcom,leds@da00 { + compatible = "qcom,leds-qpnp"; + reg = <0xda00 0x100>; + label = "wled"; + }; + + qcom,leds@db00 { + compatible = "qcom,leds-qpnp"; + reg = <0xdb00 0x100>; + label = "wled"; + }; + + qcom,leds@dc00 { + compatible = "qcom,leds-qpnp"; + reg = <0xdc00 0x100>; + label = "wled"; + }; + + qcom,leds@dd00 { + compatible = "qcom,leds-qpnp"; + reg = <0xdd00 0x100>; + label = "wled"; + }; + + qcom,leds@de00 { + compatible = "qcom,leds-qpnp"; + reg = <0xde00 0x100>; + label = "wled"; + }; + + qcom,leds@df00 { + compatible = "qcom,leds-qpnp"; + reg = <0xdf00 0x100>; + label = "wled"; + }; + + qcom,leds@e000 { + compatible = "qcom,leds-qpnp"; + reg = <0xe000 0x100>; + label = "wled"; + }; + + qcom,leds@e100 { + compatible = "qcom,leds-qpnp"; + reg = <0xe100 0x100>; + label = "wled"; + }; + + pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <0>; + }; + + pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <1>; + }; + + pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <2>; + }; + + pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <3>; + }; + + pwm@b500 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb500 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <4>; + }; + + pwm@b600 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb600 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <5>; + }; + + pwm@b700 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb700 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <6>; + }; + + pwm@b800 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb800 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; + qcom,channel-id = <7>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8x41-rpm-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8x41-rpm-regulator.dtsi new file mode 100644 index 000000000..6e67dd85c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pm8x41-rpm-regulator.dtsi @@ -0,0 +1,585 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpb1 { + qcom,resource-name = "smpb"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s1 { + regulator-name = "8841_s1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpb2 { + qcom,resource-name = "smpb"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s2 { + regulator-name = "8841_s2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpb3 { + qcom,resource-name = "smpb"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s3 { + regulator-name = "8841_s3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpb4 { + qcom,resource-name = "smpb"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s4 { + regulator-name = "8841_s4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa1 { + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s1 { + regulator-name = "8941_s1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa2 { + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s2 { + regulator-name = "8941_s2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpa3 { + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-s3 { + regulator-name = "8941_s3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa1 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l1 { + regulator-name = "8941_l1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa2 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l2 { + regulator-name = "8941_l2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa3 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l3 { + regulator-name = "8941_l3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa4 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l4 { + regulator-name = "8941_l4"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa5 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l5 { + regulator-name = "8941_l5"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa6 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l6 { + regulator-name = "8941_l6"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa7 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l7 { + regulator-name = "8941_l7"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa8 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l8 { + regulator-name = "8941_l8"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa9 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l9 { + regulator-name = "8941_l9"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa10 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l10 { + regulator-name = "8941_l10"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa11 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l11 { + regulator-name = "8941_l11"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa12 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l12 { + regulator-name = "8941_l12"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa13 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l13 { + regulator-name = "8941_l13"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa14 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l14 { + regulator-name = "8941_l14"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa15 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l15 { + regulator-name = "8941_l15"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa16 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l16 { + regulator-name = "8941_l16"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa17 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l17 { + regulator-name = "8941_l17"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa18 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l18 { + regulator-name = "8941_l18"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa19 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l19 { + regulator-name = "8941_l19"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa20 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l20 { + regulator-name = "8941_l20"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa21 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l21 { + regulator-name = "8941_l21"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa22 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l22 { + regulator-name = "8941_l22"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa23 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l23 { + regulator-name = "8941_l23"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa24 { + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-l24 { + regulator-name = "8941_l24"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + /* TODO: find out correct resource names for LVS vs MVS */ + rpm-regulator-vsa1 { + qcom,resource-name = "vsa"; + qcom,resource-id = <1>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-lvs1 { + regulator-name = "8941_lvs1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-vsa2 { + qcom,resource-name = "vsa"; + qcom,resource-id = <2>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-lvs2 { + regulator-name = "8941_lvs2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-vsa3 { + qcom,resource-name = "vsa"; + qcom,resource-id = <3>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-lvs3 { + regulator-name = "8941_lvs3"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-vsa4 { + qcom,resource-name = "vsa"; + qcom,resource-id = <4>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-mvs1 { + regulator-name = "8941_mvs1"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-vsa5 { + qcom,resource-name = "vsa"; + qcom,resource-id = <5>; + qcom,regulator-type = <2>; + compatible = "qcom,rpm-regulator-smd-resource"; + status = "disabled"; + + regulator-mvs2 { + regulator-name = "8941_mvs2"; + qcom,set = <3>; + status = "disabled"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pma8084.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pma8084.dtsi new file mode 100644 index 000000000..30525aac0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm-pma8084.dtsi @@ -0,0 +1,666 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + qcom,pma8084@0 { + spmi-slave-container; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + pma8084_gpios: gpios { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pma8084-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + }; + + gpio@cd00 { + reg = <0xcd00 0x100>; + qcom,pin-num = <14>; + }; + + gpio@ce00 { + reg = <0xce00 0x100>; + qcom,pin-num = <15>; + }; + + gpio@cf00 { + reg = <0xcf00 0x100>; + qcom,pin-num = <16>; + }; + + gpio@d000 { + reg = <0xd000 0x100>; + qcom,pin-num = <17>; + }; + + gpio@d100 { + reg = <0xd100 0x100>; + qcom,pin-num = <18>; + }; + + gpio@d200 { + reg = <0xd200 0x100>; + qcom,pin-num = <19>; + }; + + gpio@d300 { + reg = <0xd300 0x100>; + qcom,pin-num = <20>; + }; + + gpio@d400 { + reg = <0xd400 0x100>; + qcom,pin-num = <21>; + }; + + gpio@d500 { + reg = <0xd500 0x100>; + qcom,pin-num = <22>; + }; + }; + + pma8084_mpps: mpps { + spmi-dev-container; + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pma8084-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + + mpp@a400 { + reg = <0xa400 0x100>; + qcom,pin-num = <5>; + }; + + mpp@a500 { + reg = <0xa500 0x100>; + qcom,pin-num = <6>; + }; + + mpp@a600 { + reg = <0xa600 0x100>; + qcom,pin-num = <7>; + }; + + mpp@a700 { + reg = <0xa700 0x100>; + qcom,pin-num = <8>; + }; + }; + }; + + qcom,pma8084@1 { + spmi-slave-container; + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8084_s1"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x300>; + status = "disabled"; + + qcom,ctl@1400 { + reg = <0x1400 0x100>; + }; + qcom,ps@1500 { + reg = <0x1500 0x100>; + }; + qcom,freq@1600 { + reg = <0x1600 0x100>; + }; + }; + + regulator@1700 { + regulator-name = "8084_s2"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8084_s3"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8084_s4"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + }; + + regulator@2000 { + regulator-name = "8084_s5"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2000 0x300>; + status = "disabled"; + + qcom,ctl@2000 { + reg = <0x2000 0x100>; + }; + qcom,ps@2100 { + reg = <0x2100 0x100>; + }; + qcom,freq@2200 { + reg = <0x2200 0x100>; + }; + }; + + regulator@2300 { + regulator-name = "8084_s6"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2300 0x300>; + status = "disabled"; + + qcom,ctl@2300 { + reg = <0x2300 0x100>; + }; + qcom,ps@2400 { + reg = <0x2400 0x100>; + }; + qcom,freq@2500 { + reg = <0x2500 0x100>; + }; + }; + + regulator@2600 { + regulator-name = "8084_s7"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2600 0x300>; + status = "disabled"; + + qcom,ctl@2600 { + reg = <0x2600 0x100>; + }; + qcom,ps@2700 { + reg = <0x2700 0x100>; + }; + qcom,freq@2800 { + reg = <0x2800 0x100>; + }; + }; + + regulator@2900 { + regulator-name = "8084_s8"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2900 0x300>; + status = "disabled"; + + qcom,ctl@2900 { + reg = <0x2900 0x100>; + }; + qcom,ps@2a00 { + reg = <0x2a00 0x100>; + }; + qcom,freq@2b00 { + reg = <0x2b00 0x100>; + }; + }; + + regulator@2c00 { + regulator-name = "8084_s9"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2c00 0x300>; + status = "disabled"; + + qcom,ctl@2c00 { + reg = <0x2c00 0x100>; + }; + qcom,ps@2d00 { + reg = <0x2d00 0x100>; + }; + qcom,freq@2e00 { + reg = <0x2e00 0x100>; + }; + }; + + regulator@2f00 { + regulator-name = "8084_s10"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x2f00 0x300>; + status = "disabled"; + + qcom,ctl@2f00 { + reg = <0x2f00 0x100>; + }; + qcom,ps@3000 { + reg = <0x3000 0x100>; + }; + qcom,freq@3100 { + reg = <0x3100 0x100>; + }; + }; + + regulator@3200 { + regulator-name = "8084_s11"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x3200 0x300>; + status = "disabled"; + + qcom,ctl@3200 { + reg = <0x3200 0x100>; + }; + qcom,ps@3300 { + reg = <0x3300 0x100>; + }; + qcom,freq@3400 { + reg = <0x3400 0x100>; + }; + }; + + regulator@3500 { + regulator-name = "8084_s12"; + spmi-dev-container; + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qpnp-regulator"; + reg = <0x3500 0x300>; + status = "disabled"; + + qcom,ctl@3500 { + reg = <0x3500 0x100>; + }; + qcom,ps@3600 { + reg = <0x3600 0x100>; + }; + qcom,freq@3700 { + reg = <0x3700 0x100>; + }; + }; + + regulator@4000 { + regulator-name = "8084_l1"; + reg = <0x4000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8084_l2"; + reg = <0x4100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8084_l3"; + reg = <0x4200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8084_l4"; + reg = <0x4300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8084_l5"; + reg = <0x4400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8084_l6"; + reg = <0x4500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8084_l7"; + reg = <0x4600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8084_l8"; + reg = <0x4700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8084_l9"; + reg = <0x4800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8084_l10"; + reg = <0x4900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4a00 { + regulator-name = "8084_l11"; + reg = <0x4a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8084_l12"; + reg = <0x4b00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4c00 { + regulator-name = "8084_l13"; + reg = <0x4c00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8084_l14"; + reg = <0x4d00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8084_l15"; + reg = <0x4e00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8084_l16"; + reg = <0x4f00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5000 { + regulator-name = "8084_l17"; + reg = <0x5000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5100 { + regulator-name = "8084_l18"; + reg = <0x5100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5200 { + regulator-name = "8084_l19"; + reg = <0x5200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5300 { + regulator-name = "8084_l20"; + reg = <0x5300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5400 { + regulator-name = "8084_l21"; + reg = <0x5400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5500 { + regulator-name = "8084_l22"; + reg = <0x5500 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5600 { + regulator-name = "8084_l23"; + reg = <0x5600 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5700 { + regulator-name = "8084_l24"; + reg = <0x5700 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5800 { + regulator-name = "8084_l25"; + reg = <0x5800 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5900 { + regulator-name = "8084_l26"; + reg = <0x5900 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@5a00 { + regulator-name = "8084_l27"; + reg = <0x5a00 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8000 { + regulator-name = "8084_lvs1"; + reg = <0x8000 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8100 { + regulator-name = "8084_lvs2"; + reg = <0x8100 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8200 { + regulator-name = "8084_lvs3"; + reg = <0x8200 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8300 { + regulator-name = "8084_lvs4"; + reg = <0x8300 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + + regulator@8400 { + regulator-name = "8084_mvs1"; + reg = <0x8400 0x100>; + compatible = "qcom,qpnp-regulator"; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-bus.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-bus.dtsi new file mode 100644 index 000000000..d87aa3ea5 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-bus.dtsi @@ -0,0 +1,1128 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm-mmss-noc@fc478000 { + compatible = "msm-bus-fabric"; + reg = <0xfc478000 0x00004000>; + cell-id = <2048>; + label = "msm_mmss_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-gfx3d { + cell-id = <26>; + label = "mas-gfx3d"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <2>; + qcom,mas-hw-id = <6>; + }; + + mas-jpeg { + cell-id = <62>; + label = "mas-jpeg"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <7>; + }; + + mas-mdp-port0 { + cell-id = <22>; + label = "mas-mdp-port0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,qport = <1>; + qcom,ws = <10000>; + qcom,mas-hw-id = <8>; + }; + + mas-video-p0 { + cell-id = <63>; + label = "mas-video-p0"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <4>; + qcom,mas-hw-id = <9>; + }; + + mas-vfe { + cell-id = <29>; + label = "mas-vfe"; + qcom,masterp = <16>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <6>; + qcom,mas-hw-id = <11>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,masterp = <0 1>; + qcom,buswidth = <16>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <4>; + }; + + fab-bimc { + cell-id = <0>; + label = "fab-bimc"; + qcom,gateway; + qcom,slavep = <16>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <16>; + }; + + slv-camera-cfg { + cell-id = <589>; + label = "slv-camera-cfg"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <3>; + }; + + slv-display-cfg { + cell-id = <590>; + label = "slv-display-cfg"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <4>; + }; + + slv-ocmem-cfg { + cell-id = <591>; + label = "slv-ocmem-cfg"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <5>; + }; + + slv-cpr-cfg { + cell-id = <592>; + label = "slv-cpr-cfg"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <6>; + }; + + slv-cpr-xpu-cfg { + cell-id = <593>; + label = "slv-cpr-xpu-cfg"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <7>; + }; + + slv-misc-cfg { + cell-id = <594>; + label = "slv-misc-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <8>; + }; + + slv-misc-xpu-cfg { + cell-id = <595>; + label = "slv-misc-xpu-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <9>; + }; + + slv-venus-cfg { + cell-id = <596>; + label = "slv-venus-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <10>; + }; + + slv-gfx3d-cfg { + cell-id = <598>; + label = "slv-gfx3d-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <11>; + }; + + slv-mmss-clk-cfg { + cell-id = <599>; + label = "slv-mmss-clk-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <12>; + }; + + slv-mmss-clk-xpu-cfg { + cell-id = <600>; + label = "slv-mmss-clk-xpu-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <13>; + }; + + slv-mnoc-mpu-cfg { + cell-id = <601>; + label = "slv-mnoc-mpu-cfg"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <14>; + }; + + slv-onoc-mpu-cfg { + cell-id = <602>; + label = "slv-onoc-mpu-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <15>; + }; + + slv-service-mnoc { + cell-id = <603>; + label = "slv-service-mnoc"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <17>; + }; + + }; + + msm-sys-noc@fc460000 { + compatible = "msm-bus-fabric"; + reg = <0xfc460000 0x00004000>; + cell-id = <1024>; + label = "msm_sys_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-lpass-ahb { + cell-id = <52>; + label = "mas-lpass-ahb"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,qport = <0>; + qcom,mas-hw-id = <18>; + qcom,mode = "Fixed"; + qcom,prio-rd = <2>; + qcom,prio-wr = <2>; + }; + + mas-qdss-bam { + cell-id = <53>; + label = "mas-qdss-bam"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <1>; + qcom,mas-hw-id = <19>; + }; + + mas-snoc-cfg { + cell-id = <54>; + label = "mas-snoc-cfg"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,mas-hw-id = <20>; + }; + + fab-bimc { + cell-id = <0>; + label= "fab-bimc"; + qcom,gateway; + qcom,slavep = <7>; + qcom,masterp = <3>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <21>; + qcom,slv-hw-id = <24>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,slavep = <8>; + qcom,masterp = <4>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <22>; + qcom,slv-hw-id = <25>; + }; + + fab-pnoc { + cell-id = <4096>; + label = "fab-pnoc"; + qcom,gateway; + qcom,slavep = <10>; + qcom,masterp = <10>; + qcom,buswidth = <8>; + qcom,qport = <8>; + qcom,mas-hw-id = <29>; + qcom,slv-hw-id = <28>; + qcom,mode = "Fixed"; + qcom,prio-rd = <2>; + qcom,prio-wr = <2>; + }; + + fab-ovnoc { + cell-id = <6144>; + label = "fab-ovnoc"; + qcom,gateway; + qcom,buswidth = <8>; + qcom,mas-hw-id = <53>; + qcom,slv-hw-id = <77>; + }; + + mas-crypto-core0 { + cell-id = <55>; + label = "mas-crypto-core0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,mode = "Fixed"; +/* qcom,qport = <2>;*/ + qcom,mas-hw-id = <23>; + qcom,hw-sel = "NoC"; + qcom,prio-rd = <1>; + qcom,prio-wr = <1>; + }; + + mas-lpass-proc { + cell-id = <11>; + label = "mas-lpass-proc"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,qport = <4>; + qcom,mas-hw-id = <25>; + qcom,mode = "Fixed"; + qcom,prio-rd = <2>; + qcom,prio-wr = <2>; + }; + + mas-mss { + cell-id = <38>; + label = "mas-mss"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,mas-hw-id = <26>; + }; + + mas-mss-nav { + cell-id = <57>; + label = "mas-mss-nav"; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,mas-hw-id = <27>; + }; + + mas-ocmem-dma { + cell-id = <58>; + label = "mas-ocmem-dma"; + qcom,masterp = <9>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <7>; + qcom,mas-hw-id = <28>; + }; + + mas-wcss { + cell-id = <59>; + label = "mas-wcss"; + qcom,masterp = <11>; + qcom,tier = <2>; + qcom,mas-hw-id = <30>; + }; + + mas-qdss-etr { + cell-id = <60>; + label = "mas-qdss-etr"; + qcom,masterp = <12>; + qcom,tier = <2>; + qcom,qport = <10>; + qcom,mode = "Fixed"; + qcom,mas-hw-id = <31>; + }; + + slv-ampss { + cell-id = <520>; + label = "slv-ampss"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <20>; + }; + + slv-lpass { + cell-id = <522>; + label = "slv-lpass"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <21>; + }; + + slv-wcss { + cell-id = <584>; + label = "slv-wcss"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <23>; + }; + + slv-ocimem { + cell-id = <585>; + label = "slv-ocimem"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <26>; + }; + + slv-service-snoc { + cell-id = <587>; + label = "slv-service-snoc"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <29>; + }; + + slv-qdss-stm { + cell-id = <588>; + label = "slv-qdss-stm"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <30>; + }; + + }; + + msm-periph-noc@fc468000 { + compatible = "msm-bus-fabric"; + reg = <0xfc468000 0x00004000>; + cell-id = <4096>; + label = "msm_periph_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-pnoc-cfg { + cell-id = <88>; + label = "mas-pnoc-cfg"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <43>; + }; + + mas-sdcc-1 { + cell-id = <78>; + label = "mas-sdcc-1"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <33>; + }; + + mas-sdcc-3 { + cell-id = <79>; + label = "mas-sdcc-3"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <34>; + }; + + mas-sdcc-2 { + cell-id = <81>; + label = "mas-sdcc-2"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <35>; + }; + + mas-bam-dma { + cell-id = <83>; + label = "mas-bam-dma"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <38>; + }; + + mas-usb-hsic { + cell-id = <85>; + label = "mas-usb-hsic"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <40>; + }; + + mas-blsp-1 { + cell-id = <86>; + label = "mas-blsp-1"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <41>; + }; + + mas-usb-hs { + cell-id = <87>; + label = "mas-usb-hs"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <42>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <12>; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <45>; + qcom,mas-hw-id = <44>; + }; + + slv-sdcc-1 { + cell-id = <606>; + label = "slv-sdcc-1"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <31>; + }; + + slv-sdcc-3 { + cell-id = <607>; + label = "slv-sdcc-3"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <32>; + }; + + slv-sdcc-2 { + cell-id = <608>; + label = "slv-sdcc-2"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <33>; + }; + + slv-bam-dma { + cell-id = <610>; + label = "slv-bam-dma"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <36>; + }; + + slv-usb-hsic { + cell-id = <612>; + label = "slv-usb-hsic"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <38>; + }; + + slv-blsp-1 { + cell-id = <613>; + label = "slv-blsp-1"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <39>; + }; + + slv-usb-hs { + cell-id = <614>; + label = "slv-usb-hs"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <40>; + }; + + slv-pdm { + cell-id = <615>; + label = "slv-pdm"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <41>; + }; + + slv-periph-apu-cfg { + cell-id = <616>; + label = "slv-periph-apu-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <42>; + }; + + slv-pnoc-mpu-cfg { + cell-id = <617>; + label = "slv-pnoc-mpu-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <43>; + }; + + slv-prng { + cell-id = <618>; + label = "slv-prng"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <44>; + }; + + slv-service-pnoc { + cell-id = <619>; + label = "slv-service-pnoc"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <46>; + }; + + }; + + msm-config-noc@fc480000 { + compatible = "msm-bus-fabric"; + reg = <0xfc480000 0x00004000>; + cell-id = <5120>; + label = "msm_config_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-rpm-inst { + cell-id = <72>; + label = "mas-rpm-inst"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <45>; + }; + + mas-rpm-data { + cell-id = <73>; + label = "mas-rpm-data"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <46>; + }; + + mas-rpm-sys { + cell-id = <74>; + label = "mas-rpm-sys"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <47>; + }; + + mas-dehr { + cell-id = <75>; + label = "mas-dehr"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <48>; + }; + + mas-qdss-dsp { + cell-id = <76>; + label = "mas-qdss-dap"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <49>; + }; + + mas-spdm { + cell-id = <36>; + label = "mas-spdm"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <50>; + }; + + mas-tic { + cell-id = <77>; + label = "mas-tic"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <51>; + }; + + slv-clk-ctl { + cell-id = <620>; + label = "slv-clk-ctl"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <47>; + }; + + slv-cnoc-mss { + cell-id = <621>; + label = "slv-cnoc-mss"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <48>; + }; + + slv-security { + cell-id = <622>; + label = "slv-security"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <49>; + }; + + slv-tcsr { + cell-id = <623>; + label = "slv-tcsr"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <50>; + }; + + slv-tlmm { + cell-id = <624>; + label = "slv-tlmm"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <51>; + }; + + slv-crypto-0-cfg { + cell-id = <625>; + label = "slv-crypto-0-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <52>; + }; + + slv-imem-cfg { + cell-id = <627>; + label = "slv-imem-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <54>; + }; + + slv-message-ram { + cell-id = <628>; + label = "slv-message-ram"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <55>; + }; + + slv-bimc-cfg { + cell-id = <629>; + label = "slv-bimc-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <56>; + }; + + slv-boot-rom { + cell-id = <630>; + label = "slv-boot-rom"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <57>; + }; + + slv-pmic-arb { + cell-id = <632>; + label = "slv-pmic-arb"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <59>; + }; + + slv-spdm-wrapper { + cell-id = <633>; + label = "slv-spdm-wrapper"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <60>; + }; + + slv-dehr-cfg { + cell-id = <634>; + label = "slv-dehr-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <61>; + }; + + slv-mpm { + cell-id = <536>; + label = "slv-mpm"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <62>; + }; + + slv-qdss-cfg { + cell-id = <635>; + label = "slv-qdss-cfg"; + qcom,slavep = <16>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <63>; + }; + + slv-rbcpr-cfg { + cell-id = <636>; + label = "slv-rbcpr-cfg"; + qcom,slavep = <17>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <64>; + }; + + slv-rbcpr-qdss-apu-cfg { + cell-id = <637>; + label = "slv-rbcpr-qdss-apu-cfg"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <65>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <26>; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <52>; + qcom,slv-hw-id = <75>; + }; + + slv-cnoc-mnoc-mmss-cfg { + cell-id = <631>; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <58>; + }; + + slv-cnoc-mnoc-cfg { + cell-id = <640>; + label = "slv-cnoc-mnoc-cfg"; + qcom,slavep = <19>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <66>; + }; + + slv-pnoc-cfg { + cell-id = <641>; + label = "slv-pnoc-cfg"; + qcom,slavep = <21>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <69>; + }; + + slv-snoc-mpu-cfg { + cell-id = <638>; + label = "slv-snoc-mpu-cfg"; + qcom,slavep = <20>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <67>; + }; + + slv-snoc-cfg { + cell-id = <642>; + label = "slv-snoc-cfg"; + qcom,slavep = <22>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <70>; + }; + + slv-phy-apu-cfg { + cell-id = <644>; + label = "slv-phy-apu-cfg"; + qcom,slavep = <23>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <72>; + }; + + slv-ebi1-phy-cfg { + cell-id = <645>; + label = "slv-ebi1-phy-cfg"; + qcom,slavep = <24>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <73>; + }; + + slv-rpm { + cell-id = <534>; + label = "slv-rpm"; + qcom,slavep = <25>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <74>; + }; + + slv-service-cnoc { + cell-id = <646>; + label = "slv-service-cnoc"; + qcom,slavep = <27>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <76>; + }; + + }; + + msm-bimc@0xfc380000 { + compatible = "msm-bus-fabric"; + reg = <0xfc380000 0x0006A000>; + cell-id = <0>; + label = "msm_bimc"; + qcom,fabclk-dual = "mem_clk"; + qcom,fabclk-active = "mem_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "BIMC"; + qcom,rpm-en; + + mas-ampss-m0 { + cell-id = <1>; + label = "mas-ampss-m0"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Fixed"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + }; + + mas-mss-proc { + cell-id = <65>; + label = "mas-mss-proc"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <1>; + }; + + fab-mmss-noc { + cell-id = <2048>; + label = "fab_mmss_noc"; + qcom,gateway; + qcom,masterp = <2>; + qcom,qport = <2>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Bypass"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <2>; + qcom,masterp = <4>; + qcom,qport = <4>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <3>; + qcom,slv-hw-id = <2>; + qcom,mode = "Bypass"; + qcom,hw-sel = "RPM"; + }; + + slv-ebi-ch0 { + cell-id = <512>; + label = "slv-ebi-ch0"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <0>; + qcom,mode = "Bypass"; + }; + + slv-ampss-l2 { + cell-id = <514>; + label = "slv-ampss-l2"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <1>; + }; + }; + + msm-ocmem-vnoc@6144 { + compatible = "msm-bus-fabric"; + reg = <0x6144 0x2>; + cell-id = <6144>; + label = "msm-ocmem-vnoc"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + qcom,virt; + + mas-v-ocmem-gfx3d { + cell-id = <89>; + label = "mas-v-ocmem-gfx3d"; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <55>; + }; + + slv-ocmem { + cell-id = <604>; + label = "slv-ocmem"; + qcom,slavep = <0 1>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,slv-hw-id = <18>; + qcom,slaveclk-dual = "ocmem_clk"; + qcom,slaveclk-active = "ocmem_a_clk"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,buswidth = <32>; + qcom,ws = <10000>; + qcom,mas-hw-id = <57>; + qcom,slv-hw-id = <80>; + }; + + fab-onoc { + cell-id = <3072>; + label = "fab-onoc"; + qcom,gateway; + qcom,buswidth = <16>; + qcom,ws = <10000>; + qcom,mas-hw-id = <56>; + qcom,slv-hw-id = <79>; + }; + + }; +}; + + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-cdp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-cdp.dtsi new file mode 100644 index 000000000..41d6b7e79 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-cdp.dtsi @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + led_flash0: qcom,camera-led-flash { + cell-index = <0>; + compatible = "qcom,camera-led-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pm8226_flash0 &pm8226_flash1>; + }; +}; + +&cci { + + actuator0: qcom,actuator@6e { + cell-index = <3>; + reg = <0x6c>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6f { + compatible = "qcom,ov8825"; + reg = <0x6f>; + qcom,slave-id = <0x6c 0x300a 0x8825>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "ov8825"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + cam_vaf-supply = <&pm8226_l15>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 36 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1f>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; + + qcom,camera@6d { + compatible = "qcom,ov9724"; + reg = <0x6d>; + qcom,slave-id = <0x20 0x0 0x9724>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <0>; + qcom,sensor-name = "ov9724"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-type = <0 1 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 28 0>, + <&msmgpio 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-mtp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-mtp.dtsi new file mode 100644 index 000000000..53860ac85 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-mtp.dtsi @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + led_flash0: qcom,camera-led-flash { + cell-index = <0>; + compatible = "qcom,camera-led-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pm8226_flash0 &pm8226_flash1>; + }; +}; + +&cci { + + actuator0: qcom,actuator@6e { + cell-index = <3>; + reg = <0x6c>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6f { + compatible = "qcom,ov8825"; + reg = <0x6f>; + qcom,slave-id = <0x6c 0x300a 0x8825>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "ov8825"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + cam_vaf-supply = <&pm8226_l15>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1f>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; + + qcom,camera@6d { + compatible = "qcom,ov9724"; + reg = <0x6d>; + qcom,slave-id = <0x20 0x0 0x9724>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <270>; + qcom,sensor-name = "ov9724"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-type = <0 1 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 28 0>, + <&msmgpio 36 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-qrd.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-qrd.dtsi new file mode 100644 index 000000000..3935dbb78 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera-sensor-qrd.dtsi @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + led_flash0: qcom,camera-led-flash { + cell-index = <0>; + compatible = "qcom,camera-led-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pm8226_flash0 &pm8226_flash1>; + }; +}; + +&cci { + + actuator0: qcom,actuator@6e { + cell-index = <3>; + reg = <0x6c>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6f { + compatible = "qcom,ov8825"; + reg = <0x6f>; + qcom,slave-id = <0x6c 0x300a 0x8825>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <270>; + qcom,sensor-name = "ov8825"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + cam_vaf-supply = <&pm8226_l15>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000 2800000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 36 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1f>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; + + qcom,camera@6d { + compatible = "qcom,ov9724"; + reg = <0x6d>; + qcom,slave-id = <0x20 0x0 0x9724>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <270>; + qcom,sensor-name = "ov9724"; + cam_vdig-supply = <&pm8226_l5>; + cam_vana-supply = <&pm8226_l19>; + cam_vio-supply = <&pm8226_lvs1>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-type = <0 1 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 28 0>, + <&msmgpio 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera.dtsi new file mode 100644 index 000000000..ec0092d43 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-camera.dtsi @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-cam@fd8c0000 { + compatible = "qcom,msm-cam"; + reg = <0xfd8c0000 0x10000>; + reg-names = "msm-cam"; + }; + + qcom,csiphy@fda0ac00 { + cell-index = <0>; + compatible = "qcom,csiphy"; + reg = <0xfda0ac00 0x200>, + <0xfda00030 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + }; + + qcom,csiphy@fda0b000 { + cell-index = <1>; + compatible = "qcom,csiphy"; + reg = <0xfda0b000 0x200>, + <0xfda00038 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + }; + + qcom,csid@fda08000 { + cell-index = <0>; + compatible = "qcom,csid"; + reg = <0xfda08000 0x100>; + reg-names = "csid"; + interrupts = <0 51 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8226_l4>; + }; + + qcom,csid@fda08400 { + cell-index = <1>; + compatible = "qcom,csid"; + reg = <0xfda08400 0x100>; + reg-names = "csid"; + interrupts = <0 52 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8226_l4>; + }; + + qcom,ispif@fda0a000 { + cell-index = <0>; + compatible = "qcom,ispif"; + reg = <0xfda0a000 0x500>, + <0xfda00020 0x10>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 55 0>; + interrupt-names = "ispif"; + }; + + qcom,vfe@fda10000 { + cell-index = <0>; + compatible = "qcom,vfe40"; + reg = <0xfda10000 0x1000>, + <0xfda40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 57 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + }; + + qcom,jpeg@fda1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0xfda1c000 0x400>; + reg-names = "jpeg"; + interrupts = <0 59 0>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + }; + + qcom,irqrouter@fda00000 { + cell-index = <0>; + compatible = "qcom,irqrouter"; + reg = <0xfda00000 0x100>; + reg-names = "irqrouter"; + }; + + qcom,cpp@fda04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xfda04000 0x100>, + <0xfda40000 0x200>, + <0xfda18000 0x008>; + reg-names = "cpp", "cpp_vbif", "cpp_hw"; + interrupts = <0 49 0>; + interrupt-names = "cpp"; + vdd-supply = <&gdsc_vfe>; + }; + + cci: qcom,cci@fda0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xfda0c000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 50 0>; + interrupt-names = "cci"; + gpios = <&msmgpio 29 0>, + <&msmgpio 30 0>; + qcom,gpio-tbl-num = <0 1>; + qcom,gpio-tbl-flags = <1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0"; + qcom,hw-thigh = <78>; + qcom,hw-tlow = <114>; + qcom,hw-tsu-sto = <28>; + qcom,hw-tsu-sta = <28>; + qcom,hw-thd-dat = <10>; + qcom,hw-thd-sta = <77>; + qcom,hw-tbuf = <118>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-cdp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-cdp.dtsi new file mode 100644 index 000000000..da9ad8c0a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-cdp.dtsi @@ -0,0 +1,393 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-nt35590-720p-video.dtsi" +/include/ "msm8226-camera-sensor-cdp.dtsi" + +&soc { + serial@f991f000 { + status = "ok"; + }; + + qcom,mdss_dsi_nt35590_720p_video { + status = "ok"; + }; + + i2c@f9927000 { /* BLSP1 QUP5 */ + synaptics@20 { + compatible = "synaptics,rmi4"; + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <17 0x2008>; + vdd-supply = <&pm8226_l19>; + vcc_i2c-supply = <&pm8226_lvs1>; + synaptics,reset-gpio = <&msmgpio 16 0x00>; + synaptics,irq-gpio = <&msmgpio 17 0x2008>; + synaptics,button-map = <139 102 158>; + synaptics,i2c-pull-up; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 108 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 107 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 106 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@3 { + compatible = "micrel,ks8851"; + reg = <3>; + interrupt-parent = <&msmgpio>; + interrupts = <0 115 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&msmgpio 114 0>; + vdd-io-supply = <&pm8226_lvs1>; + vdd-phy-supply = <&pm8226_lvs1>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "SPK_OUT", "MCLK", + "SPK_OUT", "EXT_VDD_SPKR", + "AMIC1", "MIC BIAS1 Internal1", + "MIC BIAS1 Internal1", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC5", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC2", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic2", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4"; + + qcom,cdc-mclk-gpios = <&pm8226_gpios 1 0>; + qcom,cdc-vdd-spkr-gpios = <&pm8226_gpios 2 0>; + qcom,headset-jack-type-NO; + }; +}; + +&sdcc1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdcc2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <600>; + + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "disabled"; +}; + +&sdhc_2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "ok"; +}; + +&spmi_bus { + qcom,pm8226@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "manual"; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + }; + }; + + qcom,leds@a300 { + status = "okay"; + qcom,led_mpp_4 { + label = "mpp"; + linux,name = "green"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,source-sel = <8>; + qcom,mode-ctrl = <0x60>; + qcom,pwm-channel = <0>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + + qcom,leds@a500 { + status = "okay"; + qcom,led_mpp_6 { + label = "mpp"; + linux,name = "red"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,mode-ctrl = <0x60>; + qcom,source-sel = <10>; + qcom,pwm-channel = <5>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + }; + + qcom,pm8226@1 { + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <20>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <0>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + }; +}; + +&pm8226_gpios { + gpio@c000 { /* GPIO 1 */ + /* XO_PMIC_CDC_MCLK enable for tapan codec */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS logic */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO*/ + qcom,vin-sel = <3>; /* QPNP_PIN_VIN3 */ + qcom,out-strength = <3>;/* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <3>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; +}; + +&pm8226_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&pm8226_chg { + qcom,charging-disabled; + qcom,use-default-batt-values; +}; + +&usb_otg_sw { + status = "okay"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-coresight.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-coresight.dtsi new file mode 100644 index 000000000..e11c963c6 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-coresight.dtsi @@ -0,0 +1,377 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@fc322000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc322000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + }; + + tpiu: tpiu@fc318000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc318000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + vdd-supply = <&pm8226_l18>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + }; + + replicator: replicator@fc31c000 { + compatible = "qcom,coresight-replicator"; + reg = <0xfc31c000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + }; + + tmc_etf: tmc@fc307000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc307000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + }; + + funnel_merg: funnel@fc31b000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31b000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc319000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc319000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + funnel_in1: funnel@fc31a000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31a000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <6>; + coresight-name = "coresight-funnel-in1"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <1>; + }; + + funnel_a7ss: funnel@fc345000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc345000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <7>; + coresight-name = "coresight-funnel-a7ss"; + coresight-nr-inports = <4>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <5>; + }; + + funnel_mmss: funnel@fc364000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc364000 0x1000>; + reg-names = "funnel-base"; + + + coresight-id = <8>; + coresight-name = "coresight-funnel-mmss"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <1>; + }; + + stm: stm@fc321000 { + compatible = "arm,coresight-stm"; + reg = <0xfc321000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <9>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc33c000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33c000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <10>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <0>; + + qcom,round-robin; + }; + + etm1: etm@fc33d000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33d000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <11>; + coresight-name = "coresight-etm1"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <1>; + + qcom,round-robin; + }; + + etm2: etm@fc33e000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33e000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <12>; + coresight-name = "coresight-etm2"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <2>; + + qcom,round-robin; + }; + + etm3: etm@fc33f000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33f000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <13>; + coresight-name = "coresight-etm3"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <3>; + + qcom,round-robin; + }; + + csr: csr@fc302000 { + compatible = "qcom,coresight-csr"; + reg = <0xfc302000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <14>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <1>; + }; + + cti0: cti@fc308000 { + compatible = "arm,coresight-cti"; + reg = <0xfc308000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + }; + + cti1: cti@fc309000 { + compatible = "arm,coresight-cti"; + reg = <0xfc309000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + cti2: cti@fc30a000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30a000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + }; + + cti3: cti@fc30b000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30b000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <18>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + }; + + cti4: cti@fc30c000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30c000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <19>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + }; + + cti5: cti@fc30d000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30d000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <20>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + }; + + cti6: cti@fc30e000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30e000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <21>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + }; + + cti7: cti@fc30f000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30f000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <22>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + }; + + cti8: cti@fc310000 { + compatible = "arm,coresight-cti"; + reg = <0xfc310000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <23>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + }; + + cti_l2: cti@fc340000 { + compatible = "arm,coresight-cti"; + reg = <0xfc340000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <24>; + coresight-name = "coresight-cti-l2"; + coresight-nr-inports = <0>; + }; + + cti_cpu0: cti@fc341000 { + compatible = "arm,coresight-cti"; + reg = <0xfc341000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <25>; + coresight-name = "coresight-cti-cpu0"; + coresight-nr-inports = <0>; + }; + + cti_cpu1: cti@fc342000 { + compatible = "arm,coresight-cti"; + reg = <0xfc342000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <26>; + coresight-name = "coresight-cti-cpu1"; + coresight-nr-inports = <0>; + }; + + cti_cpu2: cti@fc343000 { + compatible = "arm,coresight-cti"; + reg = <0xfc343000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <27>; + coresight-name = "coresight-cti-cpu2"; + coresight-nr-inports = <0>; + }; + + cti_cpu3: cti@fc344000 { + compatible = "arm,coresight-cti"; + reg = <0xfc344000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <28>; + coresight-name = "coresight-cti-cpu3"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@fd828018 { + compatible = "qcom,coresight-hwevent"; + reg = <0xfd828018 0x80>, + <0xf9011080 0x80>, + <0xfd4ab160 0x80>; + reg-names = "mmss-mux", "apcs-mux", "ppss-mux"; + + coresight-id = <29>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + + qcom,hwevent-clks = "core_mmss_clk"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-fluid.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-fluid.dts new file mode 100644 index 000000000..c58b43b4b --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-fluid.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226.dtsi" + +/ { + model = "Qualcomm MSM 8226 FLUID"; + compatible = "qcom,msm8226-fluid", "qcom,msm8226", "qcom,fluid"; + qcom,msm-id = <145 3 0>, + <158 3 0>, + <159 3 0>, + <198 3 0>; +}; + +&soc { + serial@f991f000 { + status = "disabled"; + }; +}; + +&pm8226_bms { + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-gpu.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-gpu.dtsi new file mode 100644 index 000000000..590f73395 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-gpu.dtsi @@ -0,0 +1,161 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + msm_gpu: qcom,kgsl-3d0@fdb00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0xfdb00000 0x10000 + 0xfdb20000 0x10000>; + reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03000510>; + + qcom,initial-pwrlevel = <1>; + + qcom,idle-timeout = <8>; // + qcom,strtstp-sleepwake; + qcom,clk-map = <0x00000016>; /* KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE */ + + /* Bus Scale Settings */ + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, <89 604 0 0>, + <26 512 0 1600000>, <89 604 0 3200000>, + <26 512 0 3200000>, <89 604 0 5120000>, + <26 512 0 4256000>, <89 604 0 6400000>; + + + /* GDSC oxili regulators */ + vddcx-supply = "\0"; + vdd-supply = <&gdsc_oxili_cx>; + + + /* IOMMU Data */ + iommu = <&kgsl_iommu>; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <450000000>; + qcom,bus-freq = <3>; + qcom,io-fraction = <0>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <1>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <19000000>; + qcom,bus-freq = <0>; + qcom,io-fraction = <0>; + }; + }; + + qcom,dcvs-core-info { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,dcvs-core-info"; + + qcom,num-cores = <1>; + qcom,sensors = <0>; + + qcom,core-core-type = <1>; + + qcom,algo-disable-pc-threshold = <0>; + qcom,algo-em-win-size-min-us = <100000>; + qcom,algo-em-win-size-max-us = <300000>; + qcom,algo-em-max-util-pct = <97>; + qcom,algo-group-id = <95>; + qcom,algo-max-freq-chg-time-us = <100000>; + qcom,algo-slack-mode-dynamic = <100000>; + qcom,algo-slack-weight-thresh-pct = <0>; + qcom,algo-slack-time-min-us = <39000>; + qcom,algo-slack-time-max-us = <39000>; + qcom,algo-ss-win-size-min-us = <1000000>; + qcom,algo-ss-win-size-max-us = <1000000>; + qcom,algo-ss-util-pct = <95>; + qcom,algo-ss-no-corr-below-freq = <0>; + + qcom,energy-active-coeff-a = <2492>; + qcom,energy-active-coeff-b = <0>; + qcom,energy-active-coeff-c = <0>; + qcom,energy-leakage-coeff-a = <11>; + qcom,energy-leakage-coeff-b = <157150>; + qcom,energy-leakage-coeff-c = <0>; + qcom,energy-leakage-coeff-d = <0>; + + qcom,power-current-temp = <25>; + qcom,power-num-freq = <4>; + + qcom,dcvs-freq@0 { + reg = <0>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@1 { + reg = <1>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@2 { + reg = <2>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@3 { + reg = <3>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <844545>; + qcom,leakage-energy-offset = <0>; + }; + }; + + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-iommu-domains.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-iommu-domains.dtsi new file mode 100644 index 000000000..25fca2a54 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-iommu-domains.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,iommu-domains { + compatible = "qcom,iommu-domains"; + + venus_domain_ns: qcom,iommu-domain1 { + label = "venus_ns"; + qcom,iommu-contexts = <&venus_ns>; + qcom,virtual-addr-pool = <0x40000000 0x3f000000 + 0x7f000000 0x1000000>; + }; + + venus_domain_cp: qcom,iommu-domain2 { + label = "venus_cp"; + qcom,iommu-contexts = <&venus_cp>; + qcom,virtual-addr-pool = <0x1000000 0x3f000000>; + qcom,secure-domain; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-iommu.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-iommu.dtsi new file mode 100644 index 000000000..ff3e0a59d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-iommu.dtsi @@ -0,0 +1,237 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm-iommu-v1.dtsi" + +&jpeg_iommu { + status = "ok"; + vdd-supply = <&gdsc_jpeg>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014>; + + qcom,iommu-bfb-data = <0x0000ffff + 0x00000000 + 0x4 + 0x4 + 0x0 + 0x0 + 0x10 + 0x50 + 0x0 + 0x10 + 0x20 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&mdp_iommu { + status = "ok"; + vdd-supply = <&gdsc_mdss>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x00000000 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000013 + 0x00000017 + 0x0 + 0x13 + 0x23 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&venus_iommu { + status = "ok"; + vdd-supply = <&gdsc_venus>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020 + 0x2024 + 0x2028 + 0x202c + 0x2030 + 0x2034 + 0x2038>; + + qcom,iommu-bfb-data = <0xffffffff + 0xffffffff + 0x00000004 + 0x00000008 + 0x00000000 + 0x00000000 + 0x00000094 + 0x000000b4 + 0x0 + 0x94 + 0x114 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&venus_ns { + qcom,iommu-ctx-sids = <0 1 2 3 4 5 7>; +}; + +&venus_cp { + qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84>; +}; + +&kgsl_iommu { + status = "ok"; + vdd-supply = <&gdsc_oxili_cx>; + qcom,alt-vdd-supply = <&gdsc_oxili_gx>; + qcom,iommu-enable-halt; + qcom,needs-alt-core-clk; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008>; + + qcom,iommu-bfb-data = <0x00000003 + 0x0 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000001 + 0x00000011 + 0x0 + 0x1 + 0x41 + 0x0>; +}; + +&vfe_iommu { + status = "ok"; + vdd-supply = <&gdsc_vfe>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x00000000 + 0x4 + 0x8 + 0x0 + 0x0 + 0x1b + 0x5b + 0x0 + 0x1b + 0x2b + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-ion.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-ion.dtsi new file mode 100644 index 000000000..dee64e538 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-ion.dtsi @@ -0,0 +1,66 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@8 { /* CP_MM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <8>; + qcom,heap-align = <0x1000>; + linux,contiguous-region = <&secure_mem>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + qcom,ion-heap@27 { /* QSECOM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <27>; + linux,contiguous-region = <&qsecom_mem>; + }; + + qcom,ion-heap@28 { /* AUDIO HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <28>; + qcom,heap-align = <0x1000>; + qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */ + qcom,memory-reservation-size = <0x314000>; + }; + qcom,ion-heap@23 { /* OTHER PIL HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <23>; + qcom,heap-align = <0x1000>; + qcom,memory-fixed = <0x06400000 0x2000000>; + }; + qcom,ion-heap@26 { /* MODEM PIL HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <26>; + qcom,heap-align = <0x1000>; + qcom,memory-fixed = <0x08400000 0x4E00000>; + + }; + + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-mdss.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-mdss.dtsi new file mode 100644 index 000000000..f58089709 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-mdss.dtsi @@ -0,0 +1,80 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_mdp@fd900000 { + compatible = "qcom,mdss_mdp"; + reg = <0xfd900000 0x22100>, + <0xfd924000 0x1000>; + reg-names = "mdp_phys", "vbif_phys"; + interrupts = <0 72 0>; + vdd-supply = <&gdsc_mdss>; + + qcom,max-clk-rate = <200000000>; + qcom,mdss-pipe-vig-off = <0x00001200>; + qcom,mdss-pipe-rgb-off = <0x00001E00>; + qcom,mdss-pipe-dma-off = <0x00002A00>; + qcom,mdss-pipe-vig-fetch-id = <1>; + qcom,mdss-pipe-rgb-fetch-id = <7>; + qcom,mdss-pipe-dma-fetch-id = <4>; + qcom,mdss-smp-data = <7 4096>; + + qcom,mdss-ctl-off = <0x00000600 0x00000700>; + qcom,mdss-mixer-intf-off = <0x00003200>; + qcom,mdss-mixer-wb-off = <0x00003E00>; + qcom,mdss-dspp-off = <0x00004600>; + qcom,mdss-pingpong-off = <0x00021B00>; + qcom,mdss-wb-off = <0x00011100 0x00013100>; + qcom,mdss-intf-off = <0x00000000 0x00021300>; + qcom,mdss-rot-block-size = <64>; + + qcom,vbif-settings = <0x004 0x00000001>, + <0x0D8 0x00000707>, + <0x124 0x00000003>; + qcom,mdp-settings = <0x02E0 0x000000A9>, + <0x02E4 0x00000055>; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x800000>; + }; + + mdss_fb1: qcom,mdss_fb_wfd { + cell-index = <1>; + compatible = "qcom,mdss-fb"; + }; + }; + + mdss_dsi0: qcom,mdss_dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0xfd922800 0x600>; + vdd-supply = <&pm8226_l15>; + vddio-supply = <&pm8226_l8>; + vdda-supply = <&pm8226_l4>; + qcom,supply-names = "vdd", "vddio", "vdda"; + qcom,supply-min-voltage-level = <2800000 1800000 1200000>; + qcom,supply-max-voltage-level = <2800000 1800000 1200000>; + qcom,supply-peak-current = <150000 100000 100000>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; + + qcom,mdss_wb_panel { + compatible = "qcom,mdss_wb"; + qcom,mdss_pan_res = <1280 720>; + qcom,mdss_pan_bpp = <24>; + qcom,mdss-fb-map = <&mdss_fb1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-mtp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-mtp.dtsi new file mode 100644 index 000000000..bcd1c41d6 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-mtp.dtsi @@ -0,0 +1,445 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-nt35590-720p-video.dtsi" +/include/ "msm8226-camera-sensor-mtp.dtsi" + +&soc { + serial@f991f000 { + status = "ok"; + }; + + qcom,mdss_dsi_nt35590_720p_video { + status = "ok"; + }; + + i2c@f9927000 { /* BLSP1 QUP5 */ + synaptics@20 { + compatible = "synaptics,rmi4"; + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <17 0x2008>; + vdd-supply = <&pm8226_l19>; + vcc_i2c-supply = <&pm8226_lvs1>; + synaptics,reset-gpio = <&msmgpio 16 0x00>; + synaptics,irq-gpio = <&msmgpio 17 0x2008>; + synaptics,button-map = <139 102 158>; + synaptics,i2c-pull-up; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 108 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 107 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 106 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@3 { + compatible = "micrel,ks8851"; + reg = <3>; + interrupt-parent = <&msmgpio>; + interrupts = <0 115 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&msmgpio 114 0>; + vdd-io-supply = <&pm8226_lvs1>; + vdd-phy-supply = <&pm8226_lvs1>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "SPK_OUT", "MCLK", + "SPK_OUT", "EXT_VDD_SPKR", + "AMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS1 External", + "MIC BIAS1 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic"; + + qcom,cdc-mclk-gpios = <&pm8226_gpios 1 0>; + qcom,cdc-vdd-spkr-gpios = <&pm8226_gpios 2 0>; + }; +}; + +&usb_otg { + #address-cells = <0>; + interrupt-parent = <&usb_otg>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 134 0 + 1 &intc 0 140 0 + 2 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "core_irq", "async_irq", "pmic_id_irq"; + + qcom,hsusb-otg-mode = <3>; + vbus_otg-supply = <&usb_otg_sw>; +}; + +&sdcc1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdcc2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <600>; #address-cells = <0>; interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "disabled"; +}; + +&sdhc_2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "ok"; +}; + +&spmi_bus { + qcom,pm8226@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "manual"; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + }; + }; + + qcom,leds@a300 { + status = "okay"; + qcom,led_mpp_4 { + label = "mpp"; + linux,name = "green"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,source-sel = <8>; + qcom,mode-ctrl = <0x60>; + qcom,pwm-channel = <0>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + + qcom,leds@a500 { + status = "okay"; + qcom,led_mpp_6 { + label = "mpp"; + linux,name = "red"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,mode-ctrl = <0x60>; + qcom,source-sel = <10>; + qcom,pwm-channel = <5>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + }; + + qcom,pm8226@1 { + qcom,leds@d300 { + status = "okay"; + }; + + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <20>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <0>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + }; +}; + +&pm8226_gpios { + gpio@c000 { /* GPIO 1 */ + /* XO_PMIC_CDC_MCLK enable for tapan codec */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS logic */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO*/ + qcom,vin-sel = <3>; /* QPNP_PIN_VIN3 */ + qcom,out-strength = <3>;/* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <3>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; +}; + +&pm8226_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + /* PA_THERM0 config */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <0>; /* AMUX 5 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + /* PA_THERM1 config */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; +}; + +&pm8226_vadc { + chan@14 { + label = "pa_therm0"; + reg = <0x14>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@17 { + label = "pa_therm1"; + reg = <0x17>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8226_bms { + status = "ok"; +}; + +&pm8226_chg { + qcom,charging-disabled; +}; + +&usb_otg_sw { + status = "okay"; +}; + +&slim_msm { + tapan_codec { + qcom,cdc-micbias1-ext-cap; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-pm.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-pm.dtsi new file mode 100644 index 000000000..3240efb75 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-pm.dtsi @@ -0,0 +1,389 @@ +/* Copyright (c) 2013 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f9099000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,core-id = <1>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f90a9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,core-id = <2>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f90b9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,core-id = <3>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f9012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9012000 0x1000>; + qcom,core-id = <0xffff>; /* L2/APCS SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-pmic-data0 = <0x02030080>; + qcom,saw2-pmic-data1 = <0x00030000>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + qcom,saw2-spm-cmd-ret = [00 03 00 7b 0f]; + qcom,saw2-spm-cmd-pc = [00 32 b0 10 e0 d0 6b c0 42 f0 + 11 07 01 b0 4e c0 d0 12 e0 6b 50 02 32 + 50 f0 7b 0f]; /*APCS_PMIC_OFF_L2RAM_OFF*/ + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x61706d73>; /* "smpa" */ + qcom,id = <0x01>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <3>; /* SVS SOC */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x616F646C>; /* "ldoa" */ + qcom,id = <0x03>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <3>; /* SVS SOC */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + + qcom,lpm-resources@3 { + reg = <0x3>; + qcom,name = "l2"; + qcom,local-resource-type; + qcom,init-value = "l2_cache_retention"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <1>; + qcom,ss-power = <784>; + qcom,energy-overhead = <190000>; + qcom,time-overhead = <100>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3000>; + qcom,ss-power = <725>; + qcom,energy-overhead = <99500>; + qcom,time-overhead = <3130>; + }; + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_retention"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <8000>; + qcom,ss-power = <138>; + qcom,energy-overhead = <1208400>; + qcom,time-overhead = <9200>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <4>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <9000>; + qcom,ss-power = <110>; + qcom,energy-overhead = <1250300>; + qcom,time-overhead = <9500>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <16300>; + qcom,ss-power = <63>; + qcom,energy-overhead = <2128000>; + qcom,time-overhead = <24200>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <4>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,latency-us = <24000>; + qcom,ss-power = <10>; + qcom,energy-overhead = <3202600>; + qcom,time-overhead = <33000>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <1>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <26000>; + qcom,ss-power = <2>; + qcom,energy-overhead = <4252000>; + qcom,time-overhead = <38000>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <47 172>, /* usb2_hsic_async_wakeup_irq */ + <53 104>, /* mdss_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <2 216>, /* tsens_upper_lower_int */ + <0xff 56>, /* q6_wdog_expired_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 61>, /* mss_a2_bam_irq */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_low */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr + <0xff 181>, /* o_wcss_apss_wdog_bite_and_reset_rdy */ + <0xff 188>, /* lpass_irq_out_apcs(0) */ + <0xff 189>, /* lpass_irq_out_apcs(1) */ + <0xff 190>, /* lpass_irq_out_apcs(2) */ + <0xff 191>, /* lpass_irq_out_apcs(3) */ + <0xff 192>, /* lpass_irq_out_apcs(4) */ + <0xff 194>, /* lpass_irq_out_apcs[6] */ + <0xff 195>, /* lpass_irq_out_apcs[7] */ + <0xff 196>, /* lpass_irq_out_apcs[8] */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 258>, /* rpm_ipc(28) */ + <0xff 259>, /* rpm_ipc(29) */ + <0xff 275>, /* rpm_ipc(30) */ + <0xff 276>, /* rpm_ipc(31) */ + <0xff 269>, /* rpm_wdog_expired_irq */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <3 1>, + <4 4 >, + <5 5 >, + <6 9 >, + <7 13>, + <8 17>, + <9 21>, + <10 27>, + <11 29>, + <12 31>, + <13 33>, + <14 35>, + <15 37>, + <16 38>, + <17 39>, + <18 41>, + <19 46>, + <20 48>, + <21 49>, + <22 50>, + <23 51>, + <24 52>, + <25 54>, + <26 62>, + <27 63>, + <28 64>, + <29 65>, + <30 66>, + <31 67>, + <32 68>, + <33 69>, + <34 71>, + <35 72>, + <36 106>, + <37 107>, + <38 108>, + <39 109>, + <40 110>, + <54 111>, + <55 113>; + }; + + qcom,pm-8x60@fe805664 { + compatible = "qcom,pm-8x60"; + reg = <0xfe805664 0x40>; + qcom,pc-mode = "tz_l2_int"; + qcom,use-sync-timer; + qcom,pc-resets-timer; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-qrd.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-qrd.dtsi new file mode 100644 index 000000000..fc9d9f9b9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-qrd.dtsi @@ -0,0 +1,406 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-nt35590-720p-video.dtsi" +/include/ "msm8226-camera-sensor-qrd.dtsi" + +&soc { + serial@f991f000 { + status = "ok"; + }; + + qcom,mdss_dsi_nt35590_720p_video { + status = "ok"; + }; + + i2c@f9927000 { /* BLSP1 QUP5 */ + synaptics@20 { + compatible = "synaptics,rmi4"; + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <17 0x2008>; + vdd-supply = <&pm8226_l19>; + vcc_i2c-supply = <&pm8226_lvs1>; + synaptics,reset-gpio = <&msmgpio 16 0x00>; + synaptics,irq-gpio = <&msmgpio 17 0x2008>; + synaptics,button-map = <139 102 158>; + synaptics,i2c-pull-up; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 108 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 107 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 106 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@3 { + compatible = "micrel,ks8851"; + reg = <3>; + interrupt-parent = <&msmgpio>; + interrupts = <0 115 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&msmgpio 114 0>; + vdd-io-supply = <&pm8226_lvs1>; + vdd-phy-supply = <&pm8226_lvs1>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "SPK_OUT", "MCLK", + "SPK_OUT", "EXT_VDD_SPKR", + "AMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS1 External", + "MIC BIAS1 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic"; + + qcom,cdc-mclk-gpios = <&pm8226_gpios 1 0>; + qcom,cdc-vdd-spkr-gpios = <&pm8226_gpios 2 0>; + qcom,cdc-us-euro-gpios = <&msmgpio 69 0>; + }; +}; + +&sdcc1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8226_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + vdd-io-supply = <&pm8226_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdcc2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <600>; + + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "disabled"; +}; + +&sdhc_2 { + vdd-supply = <&pm8226_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 38 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 38 0x1>; + + status = "ok"; +}; + +&spmi_bus { + qcom,pm8226@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "manual"; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + }; + }; + + qcom,leds@a300 { + status = "okay"; + qcom,led_mpp_4 { + label = "mpp"; + linux,name = "green"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,source-sel = <8>; + qcom,mode-ctrl = <0x60>; + qcom,pwm-channel = <0>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + + qcom,leds@a500 { + status = "okay"; + qcom,led_mpp_6 { + label = "mpp"; + linux,name = "red"; + linux,default-trigger = "none"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,current-setting = <5>; + qcom,id = <6>; + qcom,mode = "pwm"; + qcom,pwm-us = <1000>; + qcom,mode-ctrl = <0x60>; + qcom,source-sel = <10>; + qcom,pwm-channel = <5>; + qcom,start-idx = <1>; + qcom,duty-pcts = [00 00 00 00 64 + 64 00 00 00 00]; + qcom,use-blink; + }; + }; + }; + + qcom,pm8226@1 { + qcom,leds@d300 { + status = "okay"; + }; + + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <20>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <0>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + + qcom,vibrator@c000 { + status = "okay"; + qcom,vib-timeout-ms = <15000>; + qcom,vib-vtg-level-mV = <3100>; + }; + + }; +}; + +&pm8226_bms { + status = "okay"; + qcom,batt-type = <4>; + qcom,max-voltage-uv = <4350000>; +}; + +&pm8226_chg { + status = "okay"; + qcom,chg-vddmax-mv = <4350>; + qcom,chg-vddsafe-mv = <4350>; +}; + +&pm8226_gpios { + gpio@c000 { /* GPIO 1 */ + /* XO_PMIC_CDC_MCLK enable for tapan codec */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS logic */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO*/ + qcom,vin-sel = <3>; /* QPNP_PIN_VIN3 */ + qcom,out-strength = <3>;/* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <3>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; +}; + +&pm8226_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&slim_msm { + tapan_codec { + qcom,cdc-micbias1-ext-cap; + }; + +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-regulator.dtsi new file mode 100644 index 000000000..3254d17c8 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-regulator.dtsi @@ -0,0 +1,460 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SPM controlled regulators: */ + +&spmi_bus { + qcom,pm8226@1 { + pm8226_s2: spm-regulator@1700 { + compatible = "qcom,spm-regulator"; + regulator-name = "8226_s2"; + reg = <0x1700 0x100>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1275000>; + }; + }; +}; + +/* CPR controlled regulator */ + +&soc { + apc_vreg_corner: regulator@f9018000 { + status = "okay"; + compatible = "qcom,cpr-regulator"; + reg = <0xf9018000 0x1000>, <0xf9011064 4>, <0xfc4b80b0 8>, + <0xfc4bc450 16>; + reg-names = "rbcpr", "rbcpr_clk", "pvs_efuse", "cpr_efuse"; + interrupts = <0 15 0>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + qcom,num-efuse-bits = <5>; + qcom,pvs-bin-process = <0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 2 + 2 2 2 2 3 3 3 3 3 3 3 3 0 0 0 0>; + qcom,pvs-corner-ceiling-slow = <1155000 1160000 1275000>; + qcom,pvs-corner-ceiling-nom = <975000 1075000 1200000>; + qcom,pvs-corner-ceiling-fast = <900000 1000000 1140000>; + vdd-apc-supply = <&pm8226_s2>; + + vdd-mx-supply = <&pm8226_l3_ao>; + qcom,vdd-mx-vmax = <1350000>; + qcom,vdd-mx-vmin-method = <1>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <1>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <15>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <5>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <5000>; + }; +}; + +/* RPM controlled regulators: */ + +&rpm_bus { + rpm-regulator-smpa1 { + status = "okay"; + pm8226_s1: regulator-s1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + pm8226_s1_corner: regulator-s1-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s1_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + qcom,consumer-supplies = "vdd_dig", ""; + }; + pm8226_s1_corner_ao: regulator-s1-corner-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_s1_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + qcom,consumer-supplies = "vdd_sr2_dig", ""; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8226_s3: regulator-s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8226_s4: regulator-s4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + qcom,init-voltage = <2100000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa5 { + status = "okay"; + pm8226_s5: regulator-s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <1150000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8226_l1: regulator-l1 { + regulator-name = "8226_l1"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8226_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8226_l3: regulator-l3 { + regulator-name = "8226_l3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + pm8226_l3_ao: regulator-3-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l3_ao"; + qcom,set = <1>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + pm8226_l3_so: regulator-l3-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l3_so"; + qcom,set = <2>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + qcom,init-voltage = <750000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8226_l4: regulator-l4 { + regulator-name = "8226_l4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8226_l5: regulator-l5 { + regulator-name = "8226_l5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8226_l6: regulator-l6 { + regulator-name = "8226_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8226_l7: regulator-l7 { + regulator-name = "8226_l7"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + qcom,init-voltage = <1850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8226_l8: regulator-l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8226_l8_ao: regulator-l8-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l8_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,consumer-supplies = "vdd_sr2_pll", ""; + }; + + pm8226_l8_so: regulator-l8-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8226_l8_so"; + qcom,set = <2>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-enable = <0>; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8226_l9: regulator-l9 { + regulator-name = "8226_l9"; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8226_l10: regulator-l10 { + regulator-name = "8226_l10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8226_l12: regulator-l12 { + regulator-name = "8226_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8226_l14: regulator-l14 { + regulator-name = "8226_l14"; + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + qcom,init-voltage = <2750000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8226_l15: regulator-l15 { + regulator-name = "8226_l15"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8226_l16: regulator-l16 { + regulator-name = "8226_l16"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8226_l17: regulator-l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8226_l18: regulator-l18 { + regulator-name = "8226_l18"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8226_l19: regulator-l19 { + regulator-name = "8226_l19"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + pm8226_l20: regulator-l20 { + regulator-name = "8226_l20"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + pm8226_l21: regulator-l21 { + regulator-name = "8226_l21"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8226_l22: regulator-l22 { + regulator-name = "8226_l22"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + pm8226_l23: regulator-l23 { + regulator-name = "8226_l23"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + pm8226_l24: regulator-l24 { + regulator-name = "8226_l24"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa26 { + status = "okay"; + pm8226_l26: regulator-l26 { + regulator-name = "8226_l26"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa27 { + status = "okay"; + pm8226_l27: regulator-l27 { + regulator-name = "8226_l27"; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa28 { + status = "okay"; + pm8226_l28: regulator-l28 { + regulator-name = "8226_l28"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-vsa1 { + status = "okay"; + pm8226_lvs1: regulator-lvs1 { + status = "okay"; + }; + }; +}; + +&pm8226_chg_boost { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "8226_smbbp_boost"; +}; + +&soc { + usb_otg_sw: regulator-ncp380 { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_sw"; + gpio = <&msmgpio 67 0>; + parent-supply = <&pm8226_chg_boost>; + startup-delay-us = <4000>; + enable-active-high; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-sim.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-sim.dts new file mode 100644 index 000000000..240564632 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-sim.dts @@ -0,0 +1,135 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226.dtsi" +/include/ "msm8226-camera.dtsi" + +/ { + model = "Qualcomm MSM 8226 Simulator"; + compatible = "qcom,msm8226-sim", "qcom,msm8226", "qcom,sim"; + qcom,msm-id = <145 16 0>, + <158 16 0>, + <159 16 0>, + <198 16 0>; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; +}; + +&sdcc1 { + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + vdd-supply = <&pm8226_l17>; + vdd-io-supply = <&pm8226_l6>; + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + status = "ok"; +}; + +&sdcc2 { + vdd-supply = <&pm8226_l18>; + vdd-io-supply = <&pm8226_l21>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + status = "ok"; +}; + +&pm8226_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; +}; + +&pm8226_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-smp2p.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-smp2p.dtsi new file mode 100644 index 000000000..3921a686a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-smp2p.dtsi @@ -0,0 +1,225 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-wcnss { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <4>; + qcom,irq-bitmask = <0x40000>; + interrupts = <0 143 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + /* SMP2P SSR Driver for inbound entry from lpass. */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* SMP2P SSR Driver for outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_4_in: qcom,smp2pgpio-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_in { + compatible = "qcom,smp2pgpio_test_smp2p_4_in"; + gpios = <&smp2pgpio_smp2p_4_in 0 0>; + }; + + smp2pgpio_smp2p_4_out: qcom,smp2pgpio-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_in: qcom,smp2pgpio-ssr-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_out: qcom,smp2pgpio-ssr-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_out { + compatible = "qcom,smp2pgpio_test_smp2p_4_out"; + gpios = <&smp2pgpio_smp2p_4_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-cdp.dts new file mode 100644 index 000000000..9c49840d9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v1.dtsi" +/include/ "msm8226-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8226 CDP"; + compatible = "qcom,msm8226-cdp", "qcom,msm8226", "qcom,cdp"; + qcom,msm-id = <145 1 0>, + <158 1 0>, + <159 1 0>, + <198 1 0>, + <205 1 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-mtp.dts new file mode 100644 index 000000000..b1d46b1c4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v1.dtsi" +/include/ "msm8226-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8226 MTP"; + compatible = "qcom,msm8226-mtp", "qcom,msm8226", "qcom,mtp"; + qcom,msm-id = <145 8 0>, + <158 8 0>, + <159 8 0>, + <198 8 0>, + <205 8 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-qrd.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-qrd.dts new file mode 100644 index 000000000..d2aabac0c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1-qrd.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v1.dtsi" +/include/ "msm8226-qrd.dtsi" + +/ { + model = "Qualcomm MSM 8226 QRD"; + compatible = "qcom,msm8226-qrd", "qcom,msm8226", "qcom,qrd"; + qcom,msm-id = <145 11 0>, + <158 11 0>, + <159 11 0>, + <198 11 0>, + <205 11 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1.dtsi new file mode 100644 index 000000000..d471bece9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v1.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8226.dtsi file. + */ + +/include/ "msm8226.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-cdp.dts new file mode 100644 index 000000000..2b18491d9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v2.dtsi" +/include/ "msm8226-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8226v2 CDP"; + compatible = "qcom,msm8226-cdp", "qcom,msm8226", "qcom,cdp"; + qcom,msm-id = <145 1 0x20000>, + <158 1 0x20000>, + <159 1 0x20000>, + <198 1 0x20000>, + <205 1 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-mtp.dts new file mode 100644 index 000000000..f15dd4cb9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v2.dtsi" +/include/ "msm8226-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8226v2 MTP"; + compatible = "qcom,msm8226-mtp", "qcom,msm8226", "qcom,mtp"; + qcom,msm-id = <145 8 0x20000>, + <158 8 0x20000>, + <159 8 0x20000>, + <198 8 0x20000>, + <205 8 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-qrd.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-qrd.dts new file mode 100644 index 000000000..1a89d7894 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2-qrd.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8226-v2.dtsi" +/include/ "msm8226-qrd.dtsi" + +/ { + model = "Qualcomm MSM 8226v2 QRD"; + compatible = "qcom,msm8226-qrd", "qcom,msm8226", "qcom,qrd"; + qcom,msm-id = <145 11 0x20000>, + <158 11 0x20000>, + <159 11 0x20000>, + <198 11 0x20000>, + <205 11 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2.dtsi new file mode 100644 index 000000000..d471bece9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226-v2.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8226.dtsi file. + */ + +/include/ "msm8226.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226.dtsi new file mode 100644 index 000000000..7c981043c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8226.dtsi @@ -0,0 +1,1248 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM 8226"; + compatible = "qcom,msm8226"; + interrupt-parent = <&intc>; + + aliases { + spi0 = &spi_0; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + memory { + secure_mem: secure_region { + linux,contiguous-region; + reg = <0 0x6D00000>; + label = "secure_mem"; + }; + + qsecom_mem: qsecom_region { + linux,contiguous-region; + reg = <0 0x780000>; + label = "qsecom_mem"; + }; + }; + + soc: soc { }; +}; + +/include/ "msm8226-ion.dtsi" +/include/ "msm8226-camera.dtsi" +/include/ "msm-gdsc.dtsi" +/include/ "msm8226-iommu.dtsi" +/include/ "msm8226-pm.dtsi" +/include/ "msm8226-smp2p.dtsi" +/include/ "msm8226-gpu.dtsi" +/include/ "msm8226-bus.dtsi" +/include/ "msm8226-mdss.dtsi" +/include/ "msm8226-coresight.dtsi" +/include/ "msm8226-iommu-domains.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <117>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + qcom,mpm2-sleep-counter@fc4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xfc4a3000 0x1000>; + clock-frequency = <32768>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + qcom,vidc@fdc00000 { + compatible = "qcom,msm-vidc"; + reg = <0xfdc00000 0xff000>; + interrupts = <0 44 0>; + qcom,load-freq-tbl = <352800 160000000>, + <244800 133330000>, + <108000 66700000>; + qcom,hfi = "venus"; + qcom,bus-ports = <1>; + qcom,reg-presets = <0xE0024 0x0>, + <0x80124 0x3>, + <0xE0020 0x5555556>, + <0x800B0 0x10101001>, + <0x800B4 0x00101010>, + <0x800C0 0x1010100f>, + <0x800C4 0x00101010>, + <0x800D0 0x00000010>, + <0x800D4 0x00000010>, + <0x800D8 0x00000707>; + qcom,enc-ddr-ab-ib = <0 0>, + <129000 142000>, + <384000 422000>, + <866000 953000>; + qcom,dec-ddr-ab-ib = <0 0>, + <103000 134000>, + <268000 348000>, + <505000 657000>; + qcom,iommu-groups = <&venus_domain_ns &venus_domain_cp>; + qcom,iommu-group-buffer-types = <0xfff 0x1ff>; + qcom,buffer-type-tz-usage-table = <0x1 0x1>, + <0x1fe 0x2>; + qcom,max-hw-load = <352800>; /* 720p @ 30 + 1080p @ 30 */ + }; + + qcom,wfd { + compatible = "qcom,msm-wfd"; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + serial@f995e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf995e000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + qcom,sps@f9984000 { + compatible = "qcom,msm_sps"; + reg = <0xf9984000 0x15000>, + <0xf9999000 0xb000>; + interrupts = <0 94 0>; + }; + + qcom,usbbam@f9a44000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xf9a44000 0x11000>; + reg-names = "hsusb"; + interrupts = <0 135 0>; + interrupt-names = "hsusb"; + qcom,usb-bam-num-pipes = <16>; + qcom,usb-bam-fifo-baseaddr = <0xfe803000>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + + qcom,pipe0 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <3>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37c000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x600>; + qcom,descriptor-fifo-offset = <0x600>; + qcom,descriptor-fifo-size = <0x200>; + }; + }; + + usb_otg: usb@f9a55000 { + compatible = "qcom,hsusb-otg"; + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0>, <0 140 0>; + interrupt-names = "core_irq", "async_irq"; + hsusb_vdd_dig-supply = <&pm8226_s1_corner>; + HSUSB_1p8-supply = <&pm8226_l10>; + HSUSB_3p3-supply = <&pm8226_l20>; + qcom,vdd-voltage-level = <1 5 7>; + + qcom,hsusb-otg-phy-init-seq = + <0x44 0x80 0x68 0x81 0x24 0x82 0x13 0x83 0xffffffff>; + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <2>; + qcom,hsusb-otg-disable-reset; + qcom,dp-manual-pullup; + + qcom,msm-bus,name = "usb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 60000 960000>; + }; + + android_usb@fe8050c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8050c8 0xc8>; + qcom,android-usb-cdrom; + qcom,android-usb-swfi-latency = <1>; + }; + + wcd9xxx_intc: wcd9xxx-irq { + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&msmgpio>; + interrupts = <68 0>; + interrupt-names = "cdc-int"; + }; + + slim_msm: slim@fe12f000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xfe12f000 0x35000>, + <0xfe104000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + + tapan_codec { + compatible = "qcom,tapan-slim-pgd"; + elemental-addr = [00 01 E0 00 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28>; + qcom,cdc-reset-gpio = <&msmgpio 72 0>; + + cdc-vdd-buck-supply = <&pm8226_s4>; + qcom,cdc-vdd-buck-voltage = <2100000 2100000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-vdd-h-supply = <&pm8226_l6>; + qcom,cdc-vdd-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-h-current = <25000>; + + cdc-vdd-px-supply = <&pm8226_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <25000>; + + cdc-vdd-a-1p2v-supply = <&pm8226_l4>; + qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-a-1p2v-current = <10000>; + + cdc-vdd-cx-supply = <&pm8226_l4>; + qcom,cdc-vdd-cx-voltage = <1200000 1200000>; + qcom,cdc-vdd-cx-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-vdd-h", + "cdc-vdd-px", + "cdc-vdd-a-1p2v", + "cdc-vdd-cx"; + + qcom,cdc-micbias-ldoh-v = <0x3>; + qcom,cdc-micbias-cfilt1-mv = <1800>; + qcom,cdc-micbias-cfilt2-mv = <2700>; + qcom,cdc-micbias-cfilt3-mv = <1800>; + + qcom,cdc-micbias1-cfilt-sel = <0x0>; + qcom,cdc-micbias2-cfilt-sel = <0x1>; + qcom,cdc-micbias3-cfilt-sel = <0x2>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tapan-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 E0 00 17 02]; + }; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + sound { + compatible = "qcom,msm8226-audio-tapan"; + qcom,model = "msm8226-tapan-snd-card"; + qcom,tapan-mclk-clk-freq = <9600000>; + qcom,prim-auxpcm-gpio-clk = <&msmgpio 63 0>; + qcom,prim-auxpcm-gpio-sync = <&msmgpio 64 0>; + qcom,prim-auxpcm-gpio-din = <&msmgpio 65 0>; + qcom,prim-auxpcm-gpio-dout = <&msmgpio 66 0>; + qcom,prim-auxpcm-gpio-set = "prim-gpio-prim"; + }; + + qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + }; + + qcom,msm-pcm-lpa { + compatible = "qcom,msm-pcm-lpa"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + }; + + qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + qcom,msm-dai-q6-hdmi { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <8>; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + qcom,msm-dai-q6-sb-0-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16384>; + }; + + qcom,msm-dai-q6-sb-0-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16385>; + }; + + qcom,msm-dai-q6-sb-1-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16386>; + }; + + qcom,msm-dai-q6-sb-1-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16387>; + }; + + qcom,msm-dai-q6-sb-3-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16390>; + }; + + qcom,msm-dai-q6-sb-3-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16391>; + }; + + qcom,msm-dai-q6-sb-4-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16392>; + }; + + qcom,msm-dai-q6-sb-4-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16393>; + }; + + qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + qcom,msm-auxpcm { + compatible = "qcom,msm-auxpcm-resource"; + qcom,msm-cpudai-auxpcm-clk = "pcm_clk"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-slot = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + + qcom,msm-prim-auxpcm-rx { + qcom,msm-auxpcm-dev-id = <4106>; + compatible = "qcom,msm-auxpcm-dev"; + }; + + qcom,msm-prim-auxpcm-tx { + qcom,msm-auxpcm-dev-id = <4107>; + compatible = "qcom,msm-auxpcm-dev"; + }; + }; + + qcom,wcnss-wlan@fb000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xfb000000 0x280000>, + <0xf9011008 0x04>; + reg-names = "wcnss_mmio", "wcnss_fiq"; + interrupts = <0 145 0 0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8226_l3>; + qcom,pronto-vddcx-supply = <&pm8226_s1>; + qcom,pronto-vddpx-supply = <&pm8226_l6>; + qcom,iris-vddxo-supply = <&pm8226_l10>; + qcom,iris-vddrfa-supply = <&pm8226_l24>; + qcom,iris-vddpa-supply = <&pm8226_l16>; + qcom,iris-vdddig-supply = <&pm8226_l24>; + + gpios = <&msmgpio 40 0>, <&msmgpio 41 0>, <&msmgpio 42 0>, <&msmgpio 43 0>, <&msmgpio 44 0>; + qcom,has-pronto-hw; + qcom,has-autodetect-xo; + }; + + qcom,msm-adsp-sensors { + compatible = "qcom,msm-adsp-sensors"; + qcom,src-id = <11>; + qcom,dst-id = <604>; + qcom,ab = <32505856>; + qcom,ib = <32505856>; + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + }; + + qcom,smem@fa00000 { + compatible = "qcom,smem"; + reg = <0xfa00000 0x100000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1000>; + qcom,pil-string = "modem"; + interrupts = <0 25 1>; + }; + + qcom,smsm-modem { + compatible = "qcom,smsm"; + qcom,smsm-edge = <0>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x2000>; + interrupts = <0 26 1>; + }; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-wcnss { + compatible = "qcom,smd"; + qcom,smd-edge = <6>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x20000>; + qcom,pil-string = "wcnss"; + interrupts = <0 142 1>; + }; + + qcom,smsm-wcnss { + compatible = "qcom,smsm"; + qcom,smsm-edge = <6>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x80000>; + interrupts = <0 144 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,bcl { + compatible = "qcom,bcl"; + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + + reg = <0xf9824000 0x800>, + <0xf9824800 0x100>, + <0xf9804000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 123 0>, <0 137 0>; + interrupt-names = "core_irq", "bam_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdhc_1: sdhci@f9824900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + + reg = <0xf98a4000 0x800>, + <0xf98a4800 0x100>, + <0xf9884000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 125 0>, <0 220 0>; + interrupt-names = "core_irq", "bam_irq"; + + qcom,bus-width = <4>; + status = "disabled"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + status = "disabled"; + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0>, <0 187 0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + i2c@f9926000 { /* BLSP-1 QUP-4 */ + cell-index = <0>; + compatible = "qcom,i2c-qup"; + reg = <0xf9926000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 98 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + }; + + i2c@f9927000 { /* BLSP1 QUP5 */ + cell-index = <5>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9927000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 99 0>; + qcom,i2c-bus-freq = <384000>; + qcom,i2c-src-freq = <19200000>; + }; + + qcom,acpuclk@f9011050 { + compatible = "qcom,acpuclk-a7"; + reg = <0xf9011050 0x8>; + reg-names = "rcg_base"; + a7_cpu-supply = <&apc_vreg_corner>; + }; + + qcom,ocmem@fdd00000 { + compatible = "qcom,msm-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfdd02000 0x2000>, + <0xfe039000 0x400>, + <0xfec00000 0x20000>; + reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical"; + interrupts = <0 76 0 0 77 0>; + interrupt-names = "ocmem_irq", "dm_irq"; + qcom,ocmem-num-regions = <0x1>; + qcom,ocmem-num-macros = <0x2>; + qcom,resource-type = <0x706d636f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfec00000 0x20000>; + + partition@0 { + reg = <0x0 0x20000>; + qcom,ocmem-part-name = "graphics"; + qcom,ocmem-part-min = <0x20000>; + }; + }; + + qcom,venus@fdce0000 { + compatible = "qcom,pil-venus"; + reg = <0xfdce0000 0x4000>, + <0xfdc80000 0x400>; + reg-names = "wrapper_base", "vbif_base"; + vdd-supply = <&gdsc_venus>; + + qcom,firmware-name = "venus"; + }; + + qcom,pronto@fb21b000 { + compatible = "qcom,pil-pronto"; + reg = <0xfb21b000 0x3000>, + <0xfc401700 0x4>, + <0xfd485300 0xc>; + reg-names = "pmu_base", "clk_base", "halt_base"; + interrupts = <0 149 1>; + vdd_pronto_pll-supply = <&pm8226_l8>; + + qcom,firmware-name = "wcnss"; + + /* GPIO inputs from wcnss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>; + + /* GPIO output to wcnss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>; + }; + + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + + qcom,lpass@fe200000 { + compatible = "qcom,pil-q6v5-lpass"; + reg = <0xfe200000 0x00100>, + <0xfd485100 0x00010>, + <0xfc4016c0 0x00004>; + reg-names = "qdsp6_base", "halt_base", "restart_reg"; + vdd_cx-supply = <&pm8226_s1_corner>; + interrupts = <0 162 1>; + + qcom,firmware-name = "adsp"; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + qcom,mss@fc880000 { + compatible = "qcom,pil-q6v5-mss"; + reg = <0xfc880000 0x100>, + <0xfd485000 0x400>, + <0xfc820000 0x020>, + <0xfc401680 0x004>, + <0xfd485194 0x4>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg", "cxrail_bhs_reg"; + + interrupts = <0 24 1>; + vdd_cx-supply = <&pm8226_s1_corner>; + vdd_mx-supply = <&pm8226_l3>; + vdd_pll-supply = <&pm8226_l8>; + qcom,vdd_pll = <1800000>; + + qcom,is-loadable; + qcom,firmware-name = "mba"; + qcom,pil-self-auth; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x6400000 0x9b00000>; /* Address and Size of Hole */ + }; + + tsens: tsens@fc4a8000 { + compatible = "qcom,msm-tsens"; + reg = <0xfc4a8000 0x2000>, + <0xfc4b8000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + qcom,sensors = <4>; + qcom,slope = <2901 2846 3038 2955>; + qcom,calib-mode = "fuse_map2"; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <0>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-control-mask = <0xf>; + }; + + spi_0: spi@f9923000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xf9923000 0x1000>, + <0xf9904000 0xF000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 0>, <0 238 0>; + spi-max-frequency = <19200000>; + + gpios = <&msmgpio 3 0>, /* CLK */ + <&msmgpio 1 0>, /* MISO */ + <&msmgpio 0 0>; /* MOSI */ + cs-gpios = <&msmgpio 22 0>; + + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + }; + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + qcom,msm-rng@f9bff000 { + compatible = "qcom,msm-rng"; + reg = <0xf9bff000 0x200>; + qcom,msm-rng-iface-clk; + }; + + qcom,tz-log@fe805720 { + compatible = "qcom,tz-log"; + reg = <0x0fe805720 0x1000>; + }; + + jtag_mm0: jtagmm@fc33c000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc33c000 0x1000>, + <0xfc330000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm1: jtagmm@fc33d000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc33d000 0x1000>, + <0xfc332000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm2: jtagmm@fc33e000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc33e000 0x1000>, + <0xfc334000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm3: jtagmm@fc33f000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc33f000 0x1000>, + <0xfc336000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + qcom,qseecom@d980000 { + compatible = "qcom,qseecom"; + reg = <0xd980000 0x256000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; + + qcom,qcrypto@fd404000 { + compatible = "qcom,qcrypto"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + }; + + qcom,qcedev@fd400000 { + compatible = "qcom,qcedev"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + }; + + cpu-pmu { + compatible = "arm,cortex-a7-pmu"; + qcom,irq-is-percpu; + interrupts = <1 7 0xf00>; + }; +}; + +&gdsc_venus { + qcom,clock-names = "core_clk"; + status = "ok"; +}; + +&gdsc_mdss { + qcom,clock-names = "core_clk", "lut_clk"; + status = "ok"; +}; + +&gdsc_jpeg { + qcom,clock-names = "core_clk"; + status = "ok"; +}; + +&gdsc_vfe { + qcom,clock-names = "core_clk", "csi_clk", "cpp_clk"; + status = "ok"; +}; + +&gdsc_oxili_cx { + qcom,clock-names = "core_clk"; + status = "ok"; +}; + +&gdsc_usb_hsic { + status = "ok"; +}; + +/include/ "msm-pm8226-rpm-regulator.dtsi" +/include/ "msm-pm8226.dtsi" +/include/ "msm8226-regulator.dtsi" + +&pm8226_vadc { + chan@0 { + label = "usb_in"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@2 { + label = "vchg_sns"; + reg = <2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <3>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@31 { + label = "batt_id"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b2 { + label = "xo_therm_pu2"; + reg = <0xb2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@39 { + label = "usb_id_nopull"; + reg = <0x39>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8226_adc_tm { + /* Channel Node */ + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x48>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x68>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x70>; + }; + + chan@14 { + label = "pa_therm0"; + reg = <0x14>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; + + chan@17 { + label = "pa_therm1"; + reg = <0x17>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x80>; + qcom,thermal-node; + }; +}; + +&pm8226_chg { + status = "ok"; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-bus.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-bus.dtsi new file mode 100644 index 000000000..d9bb6ab20 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-bus.dtsi @@ -0,0 +1,1014 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm-mmss-noc@fc478000 { + compatible = "msm-bus-fabric"; + reg = <0xfc478000 0x00004000>; + cell-id = <2048>; + label = "msm_mmss_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <52>; + coresight-name = "coresight-mnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <5>; + + mas-mdp-port0 { + cell-id = <22>; + label = "mas-mdp-port0"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <8>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + mas-vfe { + cell-id = <29>; + label = "mas-vfe"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <2>; + qcom,mas-hw-id = <11>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + mas-mdpe { + cell-id = <92>; + label = "mas-mdpe"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,ws = <10000>; + qcom,qport = <7>; + qcom,mas-hw-id = <11>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + fab-bimc { + cell-id = <0>; + label = "fab-bimc"; + qcom,gateway; + qcom,slavep = <16>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <16>; + }; + + slv-camera-cfg { + cell-id = <589>; + label = "slv-camera-cfg"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <3>; + }; + + slv-display-cfg { + cell-id = <590>; + label = "slv-display-cfg"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <4>; + }; + + slv-cpr-cfg { + cell-id = <592>; + label = "slv-cpr-cfg"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <6>; + }; + + slv-cpr-xpu-cfg { + cell-id = <593>; + label = "slv-cpr-xpu-cfg"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <7>; + }; + + slv-misc-cfg { + cell-id = <594>; + label = "slv-misc-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <8>; + }; + + slv-misc-xpu-cfg { + cell-id = <595>; + label = "slv-misc-xpu-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <9>; + }; + + slv-gfx3d-cfg { + cell-id = <598>; + label = "slv-gfx3d-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <11>; + }; + + slv-mmss-clk-cfg { + cell-id = <599>; + label = "slv-mmss-clk-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <12>; + }; + + slv-mmss-clk-xpu-cfg { + cell-id = <600>; + label = "slv-mmss-clk-xpu-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <13>; + }; + + slv-mnoc-mpu-cfg { + cell-id = <601>; + label = "slv-mnoc-mpu-cfg"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <14>; + }; + + slv-onoc-mpu-cfg { + cell-id = <602>; + label = "slv-onoc-mpu-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <15>; + }; + + slv-service-mnoc { + cell-id = <603>; + label = "slv-service-mnoc"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <17>; + }; + + slv-dsi-cfg { + cell-id = <649>; + label = "slv-dsi-cfg"; + qcom,slavep = <19>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <19>; + }; + }; + + msm-sys-noc@fc460000 { + compatible = "msm-bus-fabric"; + reg = <0xfc460000 0x00004000>; + cell-id = <1024>; + label = "msm_sys_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <50>; + coresight-name = "coresight-snoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <3>; + + mas-lpass-ahb { + cell-id = <52>; + label = "mas-lpass-ahb"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,mas-hw-id = <18>; + }; + + mas-qdss-bam { + cell-id = <53>; + label = "mas-qdss-bam"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,mas-hw-id = <19>; + }; + + mas-snoc-cfg { + cell-id = <54>; + label = "mas-snoc-cfg"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,mas-hw-id = <20>; + }; + + fab-bimc { + cell-id = <0>; + label= "fab-bimc"; + qcom,gateway; + qcom,slavep = <7>; + qcom,masterp = <3>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <21>; + qcom,slv-hw-id = <24>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,slavep = <8>; + qcom,masterp = <4>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <22>; + qcom,slv-hw-id = <25>; + }; + + fab-pnoc { + cell-id = <4096>; + label = "fab-pnoc"; + qcom,gateway; + qcom,slavep = <10>; + qcom,masterp = <10>; + qcom,buswidth = <8>; + qcom,qport = <8>; + qcom,mas-hw-id = <29>; + qcom,slv-hw-id = <28>; + qcom,mode = "Fixed"; + qcom,prio0 = <2>; + qcom,prio1 = <2>; + }; + + fab-ovnoc { + cell-id = <6144>; + label = "fab-ovnoc"; + qcom,gateway; + qcom,buswidth = <8>; + qcom,mas-hw-id = <53>; + qcom,slv-hw-id = <77>; + }; + + mas-crypto-core0 { + cell-id = <55>; + label = "mas-crypto-core0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,mas-hw-id = <23>; + qcom,hw-sel = "NoC"; + qcom,prio0 = <1>; + qcom,prio1 = <1>; + }; + + mas-mss { + cell-id = <38>; + label = "mas-mss"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,mas-hw-id = <26>; + }; + + mas-mss-nav { + cell-id = <57>; + label = "mas-mss-nav"; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,mas-hw-id = <27>; + }; + + mas-ocmem-dma { + cell-id = <58>; + label = "mas-ocmem-dma"; + qcom,masterp = <9>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <7>; + qcom,mas-hw-id = <28>; + }; + + mas-wcss { + cell-id = <59>; + label = "mas-wcss"; + qcom,masterp = <11>; + qcom,tier = <2>; + qcom,mas-hw-id = <30>; + }; + + mas-qdss-etr { + cell-id = <60>; + label = "mas-qdss-etr"; + qcom,masterp = <12>; + qcom,tier = <2>; + qcom,qport = <10>; + qcom,mode = "Fixed"; + qcom,mas-hw-id = <31>; + }; + + slv-ocmem { + cell-id = <604>; + label = "slv-gmem"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <18>; + }; + + slv-ampss { + cell-id = <520>; + label = "slv-ampss"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <20>; + }; + + slv-lpass { + cell-id = <522>; + label = "slv-lpass"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <21>; + }; + + slv-wcss { + cell-id = <584>; + label = "slv-wcss"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <23>; + }; + + slv-ocimem { + cell-id = <585>; + label = "slv-ocimem"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <26>; + }; + + slv-service-snoc { + cell-id = <587>; + label = "slv-service-snoc"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <29>; + }; + + slv-qdss-stm { + cell-id = <588>; + label = "slv-qdss-stm"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <30>; + }; + + }; + + msm-periph-noc@fc468000 { + compatible = "msm-bus-fabric"; + reg = <0xfc468000 0x00004000>; + cell-id = <4096>; + label = "msm_periph_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <54>; + coresight-name = "coresight-pnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <6>; + + mas-pnoc-cfg { + cell-id = <88>; + label = "mas-pnoc-cfg"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <43>; + }; + + mas-sdcc-1 { + cell-id = <78>; + label = "mas-sdcc-1"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <33>; + }; + + mas-sdcc-2 { + cell-id = <81>; + label = "mas-sdcc-2"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <35>; + }; + + mas-blsp-1 { + cell-id = <86>; + label = "mas-blsp-1"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <41>; + }; + + mas-usb-hs { + cell-id = <87>; + label = "mas-usb-hs"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <42>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <12>; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <45>; + qcom,mas-hw-id = <44>; + }; + + slv-sdcc-1 { + cell-id = <606>; + label = "slv-sdcc-1"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <31>; + }; + + slv-sdcc-2 { + cell-id = <608>; + label = "slv-sdcc-2"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <33>; + }; + + slv-blsp-1 { + cell-id = <613>; + label = "slv-blsp-1"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <39>; + }; + + slv-usb-hs { + cell-id = <614>; + label = "slv-usb-hs"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <40>; + }; + + slv-pdm { + cell-id = <615>; + label = "slv-pdm"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <41>; + }; + + slv-periph-apu-cfg { + cell-id = <616>; + label = "slv-periph-apu-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <42>; + }; + + slv-pnoc-mpu-cfg { + cell-id = <617>; + label = "slv-pnoc-mpu-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <43>; + }; + + slv-prng { + cell-id = <618>; + label = "slv-prng"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <44>; + }; + + slv-service-pnoc { + cell-id = <619>; + label = "slv-service-pnoc"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <46>; + }; + + }; + + msm-config-noc@fc480000 { + compatible = "msm-bus-fabric"; + reg = <0xfc480000 0x00004000>; + cell-id = <5120>; + label = "msm_config_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-rpm-inst { + cell-id = <72>; + label = "mas-rpm-inst"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <45>; + }; + + mas-rpm-data { + cell-id = <73>; + label = "mas-rpm-data"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <46>; + }; + + mas-rpm-sys { + cell-id = <74>; + label = "mas-rpm-sys"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <47>; + }; + + mas-dehr { + cell-id = <75>; + label = "mas-dehr"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <48>; + }; + + mas-qdss-dsp { + cell-id = <76>; + label = "mas-qdss-dap"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <49>; + }; + + mas-spdm { + cell-id = <36>; + label = "mas-spdm"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <50>; + }; + + mas-tic { + cell-id = <77>; + label = "mas-tic"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <51>; + }; + + slv-clk-ctl { + cell-id = <620>; + label = "slv-clk-ctl"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <47>; + }; + + slv-cnoc-mss { + cell-id = <621>; + label = "slv-cnoc-mss"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <48>; + }; + + slv-security { + cell-id = <622>; + label = "slv-security"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <49>; + }; + + slv-tcsr { + cell-id = <623>; + label = "slv-tcsr"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <50>; + }; + + slv-tlmm { + cell-id = <624>; + label = "slv-tlmm"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <51>; + }; + + slv-crypto-0-cfg { + cell-id = <625>; + label = "slv-crypto-0-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <52>; + }; + + slv-imem-cfg { + cell-id = <627>; + label = "slv-imem-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <54>; + }; + + slv-message-ram { + cell-id = <628>; + label = "slv-message-ram"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <55>; + }; + + slv-bimc-cfg { + cell-id = <629>; + label = "slv-bimc-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <56>; + }; + + slv-boot-rom { + cell-id = <630>; + label = "slv-boot-rom"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <57>; + }; + + slv-pmic-arb { + cell-id = <632>; + label = "slv-pmic-arb"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <59>; + }; + + slv-spdm-wrapper { + cell-id = <633>; + label = "slv-spdm-wrapper"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <60>; + }; + + slv-dehr-cfg { + cell-id = <634>; + label = "slv-dehr-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <61>; + }; + + slv-mpm { + cell-id = <536>; + label = "slv-mpm"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <62>; + }; + + slv-qdss-cfg { + cell-id = <635>; + label = "slv-qdss-cfg"; + qcom,slavep = <16>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <63>; + }; + + slv-rbcpr-cfg { + cell-id = <636>; + label = "slv-rbcpr-cfg"; + qcom,slavep = <17>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <64>; + }; + + slv-rbcpr-qdss-apu-cfg { + cell-id = <637>; + label = "slv-rbcpr-qdss-apu-cfg"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <65>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <26>; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <52>; + qcom,slv-hw-id = <75>; + }; + + slv-cnoc-mnoc-mmss-cfg { + cell-id = <631>; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <58>; + }; + + slv-cnoc-mnoc-cfg { + cell-id = <640>; + label = "slv-cnoc-mnoc-cfg"; + qcom,slavep = <19>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <66>; + }; + + slv-pnoc-cfg { + cell-id = <641>; + label = "slv-pnoc-cfg"; + qcom,slavep = <21>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <69>; + }; + + slv-snoc-mpu-cfg { + cell-id = <638>; + label = "slv-snoc-mpu-cfg"; + qcom,slavep = <20>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <67>; + }; + + slv-snoc-cfg { + cell-id = <642>; + label = "slv-snoc-cfg"; + qcom,slavep = <22>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <70>; + }; + + slv-phy-apu-cfg { + cell-id = <644>; + label = "slv-phy-apu-cfg"; + qcom,slavep = <23>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <72>; + }; + + slv-ebi1-phy-cfg { + cell-id = <645>; + label = "slv-ebi1-phy-cfg"; + qcom,slavep = <24>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <73>; + }; + + slv-rpm { + cell-id = <534>; + label = "slv-rpm"; + qcom,slavep = <25>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <74>; + }; + + slv-service-cnoc { + cell-id = <646>; + label = "slv-service-cnoc"; + qcom,slavep = <27>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <76>; + }; + + }; + + msm-bimc@0xfc380000 { + compatible = "msm-bus-fabric"; + reg = <0xfc380000 0x0006A000>; + cell-id = <0>; + label = "msm_bimc"; + qcom,fabclk-dual = "mem_clk"; + qcom,fabclk-active = "mem_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "BIMC"; + qcom,rpm-en; + + coresight-id = <55>; + coresight-name = "coresight-bimc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <3>; + + mas-ampss-m0 { + cell-id = <1>; + label = "mas-ampss-m0"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Fixed"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <0>; + qcom,prio-rd = <1>; + qcom,prio-wr = <1>; + qcom,prio-lvl = <1>; + }; + + mas-mss-proc { + cell-id = <65>; + label = "mas-mss-proc"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <1>; + }; + + fab-mmss-noc { + cell-id = <2048>; + label = "fab_mmss_noc"; + qcom,masterp = <1>; + qcom,qport = <1>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Bypass"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <2>; + qcom,masterp = <2>; + qcom,qport = <2>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <3>; + qcom,slv-hw-id = <2>; + }; + + mas-lpass-proc { + cell-id = <11>; + label = "mas-lpass-proc"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,qport = <4>; + qcom,mas-hw-id = <25>; + qcom,mode = "Fixed"; + qcom,prio0 = <1>; + qcom,prio1 = <1>; + }; + + mas-gfx3d { + cell-id = <26>; + label = "mas-gfx3d"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,ws = <10000>; + qcom,qport = <5>; + qcom,mas-hw-id = <6>; + }; + + + slv-ebi-ch0 { + cell-id = <512>; + label = "slv-ebi-ch0"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <0>; + }; + }; + +}; + + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-camera-sensor-cdp-mtp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-camera-sensor-cdp-mtp.dtsi new file mode 100644 index 000000000..d05726006 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-camera-sensor-cdp-mtp.dtsi @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&i2c { + + led_flash0: qcom,led-flash@60 { + cell-index = <0>; + reg = <0x60>; + qcom,slave-id = <0x60 0x00 0x0011>; + compatible = "qcom,led-flash"; + qcom,flash-name = "adp1600"; + qcom,flash-type = <1>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 18 0>, + <&msmgpio 19 0>; + qcom,gpio-flash-en = <0>; + qcom,gpio-flash-now = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <0 0>; + qcom,gpio-req-tbl-label = "FLASH_EN", + "FLASH_NOW"; + }; + + actuator0: qcom,actuator@6e { + cell-index = <3>; + reg = <0x6c>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6f { + compatible = "qcom,ov8825"; + reg = <0x6f>; + qcom,slave-id = <0x6c 0x300a 0x8825>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov8825"; + cam_vdig-supply = <&pm8110_l2>; + cam_vana-supply = <&pm8110_l19>; + cam_vio-supply = <&pm8110_l14>; + cam_vaf-supply = <&pm8110_l16>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 0 0 0>; + qcom,cam-vreg-min-voltage = <1200000 1800000 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1200000 1800000 2850000 3000000>; + qcom,cam-vreg-op-mode = <200000 8000 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 13 0>, + <&msmgpio 21 0>, + <&msmgpio 20 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,csi-lane-assign = <0xe4>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; + + qcom,camera@6d { + compatible = "qcom,ov9724"; + reg = <0x6d>; + qcom,slave-id = <0x20 0x0 0x9724>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov9724"; + cam_vdig-supply = <&pm8110_l4>; + cam_vana-supply = <&pm8110_l19>; + cam_vio-supply = <&pm8110_l14>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-type = <0 1 0>; + qcom,cam-vreg-min-voltage = <1200000 0 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 14 0>, + <&msmgpio 15 0>, + <&msmgpio 8 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0xe4>; + qcom,csi-lane-mask = <0x1>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-camera.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-camera.dtsi new file mode 100644 index 000000000..b1c94dd24 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-camera.dtsi @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc{ + qcom,msm-cam@fd8c0000 { + compatible = "qcom,msm-cam"; + reg = <0xfd8C0000 0x10000>; + reg-names = "msm-cam"; + }; + + qcom,csiphy@fda00c00 { + cell-index = <0>; + compatible = "qcom,csiphy"; + reg = <0xfda00c00 0x1f4>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + }; + + qcom,csiphy@fda01000 { + cell-index = <1>; + compatible = "qcom,csiphy"; + reg = <0xfda01000 0x1f4>; + reg-names = "csiphy"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + }; + + qcom,csid@fda00000 { + cell-index = <0>; + compatible = "qcom,csid"; + reg = <0xfda00000 0x100>; + reg-names = "csid"; + interrupts = <0 50 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8110_l4>; + }; + + qcom,csid@fda00400 { + cell-index = <1>; + compatible = "qcom,csid"; + reg = <0xfda00400 0x100>; + reg-names = "csid"; + interrupts = <0 51 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8110_l4>; + }; + + qcom,ispif@fda00800 { + cell-index = <0>; + compatible = "qcom,ispif"; + reg = <0xfda00800 0x200>; + reg-names = "ispif"; + interrupts = <0 52 0>; + interrupt-names = "ispif"; + }; + + qcom,vfe@fde00000 { + cell-index = <0>; + compatible = "qcom,vfe32"; + reg = <0xfde00000 0x800>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 49 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + }; + +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-cdp.dts new file mode 100644 index 000000000..bbdc2b8df --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-cdp.dts @@ -0,0 +1,396 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" +/include/ "dsi-v2-panel-truly-wvga-video.dtsi" +/include/ "msm8610-camera-sensor-cdp-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8610 CDP"; + compatible = "qcom,msm8610-cdp", "qcom,msm8610", "qcom,cdp"; + qcom,msm-id = <147 1 0>, <165 1 0>, <161 1 0>, <162 1 0>, + <163 1 0>, <164 1 0>, <166 1 0>; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; + + i2c@f9923000{ + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <1 0x2>; + vdd_ana-supply = <&pm8110_l19>; + vcc_i2c-supply = <&pm8110_l14>; + atmel,reset-gpio = <&msmgpio 0 0x00>; + atmel,irq-gpio = <&msmgpio 1 0x00>; + atmel,panel-coords = <0 0 508 880>; + atmel,display-coords = <0 0 480 800>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x81>; + atmel,variant-id = <0x15>; + atmel,version = <0x11>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 1D 01 00 0C 04 0D 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 + /* Object 8, Instance = 0 */ + 19 00 14 14 FF 00 FF 00 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 13 0B 00 20 32 01 03 + 00 32 05 30 0A 05 0A 00 70 03 + FC 01 00 36 2F 2C 00 00 40 00 + 00 0A 00 00 02 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 03 00 18 79 A8 61 + /* Object 58, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 42, Instance = 0 */ + 00 00 00 00 00 00 00 00 + /* Object 46, Instance = 0 */ + 04 03 08 10 00 00 00 00 00 + /* Object 47, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + /* Object 48, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <480>; + qcom,disp-maxy = <800>; + qcom,panel-maxx = <508>; + qcom,panel-maxy = <880>; + qcom,key-codes = <158 102 139>; + qcom,y-offset = <35>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 73 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 74 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 72 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "INT_LDO_H", "MCLK", + "MIC BIAS External", "Handset Mic", + "MIC BIAS Internal2", "Headset Mic", + "AMIC1", "MIC BIAS External", + "AMIC2", "MIC BIAS Internal2"; + }; +}; + +&i2c_cdc { + msm8x10_wcd_codec@0d{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x0d>; + cdc-vdda-cp-supply = <&pm8110_s4>; + qcom,cdc-vdda-cp-voltage = <2150000 2150000>; + qcom,cdc-vdda-cp-current = <650000>; + + cdc-vdda-h-supply = <&pm8110_l6>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <250000>; + + cdc-vdd-px-supply = <&pm8110_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-1p2v-supply = <&pm8110_l4>; + qcom,cdc-vdd-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-1p2v-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8110_l20>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias-cfilt-sel = <0x0>; + qcom,cdc-micbias-cfilt-mv = <1800000>; + qcom,cdc-mclk-clk-rate = <12288000>; + }; + + msm8x10_wcd_codec@77{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x77>; + }; + + msm8x10_wcd_codec@66{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x66>; + }; + + msm8x10_wcd_codec@55{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x55>; + }; +}; + +&spmi_bus { + qcom,pm8110@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux-default-trigger = "hr-trigger"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + qcom,mode = "manual"; + }; + }; + + qcom,leds@a200 { + status = "okay"; + qcom,led_mpp_3 { + label = "mpp"; + linux,name = "wled-backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,default-state = "on"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x10>; + qcom,mode = "manual"; + }; + }; + }; +}; + +&spmi_bus { + qcom,pm8110@1 { + qcom,vibrator@c000 { + status = "okay"; + qcom,vib-timeout-ms = <15000>; + qcom,vib-vtg-level-mV = <3100>; + }; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm8110_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 400000>; + + vdd-io-supply = <&pm8110_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 60000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8110_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 400000>; + + vdd-io-supply = <&pm8110_l21>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 50000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 42 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 42 0x1>; + + status = "ok"; +}; + +&pm8110_chg { + status = "ok"; + qcom,charging-disabled; + qcom,use-default-batt-values; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8110_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; +}; + +&pm8110_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + status = "disabled"; + }; + + mpp@a200 { /* MPP 3 */ + status = "disabled"; + }; + + mpp@a300 { /* MPP 4 */ + /* PA_THERM config */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; +}; + +/* CoreSight */ +&tpiu { + qcom,seta-gpios = <&msmgpio 4 0>, + <&msmgpio 5 0>, + <&msmgpio 6 0>, + <&msmgpio 7 0>, + <&msmgpio 22 0>, + <&msmgpio 23 0>, + <&msmgpio 24 0>, + <&msmgpio 25 0>, + <&msmgpio 26 0>, + <&msmgpio 27 0>, + <&msmgpio 28 0>, + <&msmgpio 29 0>, + <&msmgpio 30 0>, + <&msmgpio 31 0>, + <&msmgpio 94 0>, + <&msmgpio 95 0>, + <&msmgpio 96 0>, + <&msmgpio 97 0>; + qcom,seta-gpios-func = <9 9 8 11 2 2 2 2 2 2 3 2 3 3 4 4 4 4>; + qcom,seta-gpios-drv = <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>; + qcom,seta-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + qcom,seta-gpios-dir = <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>; + + qcom,setb-gpios = <&msmgpio 8 0>, + <&msmgpio 10 0>, + <&msmgpio 11 0>, + <&msmgpio 13 0>, + <&msmgpio 14 0>, + <&msmgpio 15 0>, + <&msmgpio 16 0>, + <&msmgpio 17 0>, + <&msmgpio 18 0>, + <&msmgpio 19 0>, + <&msmgpio 20 0>, + <&msmgpio 21 0>, + <&msmgpio 42 0>, + <&msmgpio 80 0>, + <&msmgpio 81 0>, + <&msmgpio 82 0>, + <&msmgpio 83 0>, + <&msmgpio 84 0>; + qcom,setb-gpios-func = <10 8 8 6 9 9 9 9 9 9 9 9 5 7 7 8 8 8>; + qcom,setb-gpios-drv = <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>; + qcom,setb-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + qcom,setb-gpios-dir = <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-coresight.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-coresight.dtsi new file mode 100644 index 000000000..516522eb0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-coresight.dtsi @@ -0,0 +1,357 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@fc326000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc326000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + }; + + tpiu: tpiu@fc320000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc320000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + vdd-supply = <&pm8110_l18>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 400000>; + }; + + replicator: replicator@fc324000 { + compatible = "qcom,coresight-replicator"; + reg = <0xfc324000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + }; + + tmc_etf: tmc@fc325000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc325000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + }; + + funnel_merg: funnel@fc323000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc323000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc321000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc321000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + funnel_in1: funnel@fc322000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc322000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <6>; + coresight-name = "coresight-funnel-in1"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <1>; + }; + + funnel_a7ss: funnel@fc355000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc355000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <7>; + coresight-name = "coresight-funnel-a7ss"; + coresight-nr-inports = <4>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <6>; + }; + + stm: stm@fc302000 { + compatible = "arm,coresight-stm"; + reg = <0xfc302000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <8>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc34c000 { + compatible = "arm,coresight-etm"; + reg = <0xfc34c000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <9>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <0>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm1: etm@fc34d000 { + compatible = "arm,coresight-etm"; + reg = <0xfc34d000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <10>; + coresight-name = "coresight-etm1"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <1>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm2: etm@fc34e000 { + compatible = "arm,coresight-etm"; + reg = <0xfc34e000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <11>; + coresight-name = "coresight-etm2"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <2>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm3: etm@fc34f000 { + compatible = "arm,coresight-etm"; + reg = <0xfc34f000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <12>; + coresight-name = "coresight-etm3"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_a7ss>; + coresight-child-ports = <3>; + + qcom,pc-save; + qcom,round-robin; + }; + + csr: csr@fc301000 { + compatible = "qcom,coresight-csr"; + reg = <0xfc301000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <13>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <1>; + }; + + cti0: cti@fc310000 { + compatible = "arm,coresight-cti"; + reg = <0xfc310000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <14>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + }; + + cti1: cti@fc311000 { + compatible = "arm,coresight-cti"; + reg = <0xfc311000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + cti2: cti@fc312000 { + compatible = "arm,coresight-cti"; + reg = <0xfc312000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + }; + + cti3: cti@fc313000 { + compatible = "arm,coresight-cti"; + reg = <0xfc313000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + }; + + cti4: cti@fc314000 { + compatible = "arm,coresight-cti"; + reg = <0xfc314000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <18>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + }; + + cti5: cti@fc315000 { + compatible = "arm,coresight-cti"; + reg = <0xfc315000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <19>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + }; + + cti6: cti@fc316000 { + compatible = "arm,coresight-cti"; + reg = <0xfc316000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <20>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + }; + + cti7: cti@fc317000 { + compatible = "arm,coresight-cti"; + reg = <0xfc317000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <21>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + }; + + cti8: cti@fc318000 { + compatible = "arm,coresight-cti"; + reg = <0xfc318000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <22>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + }; + + cti_cpu0: cti@fc351000 { + compatible = "arm,coresight-cti"; + reg = <0xfc351000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <23>; + coresight-name = "coresight-cti-cpu0"; + coresight-nr-inports = <0>; + }; + + cti_cpu1: cti@fc352000 { + compatible = "arm,coresight-cti"; + reg = <0xfc352000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <24>; + coresight-name = "coresight-cti-cpu1"; + coresight-nr-inports = <0>; + }; + + cti_cpu2: cti@fc353000 { + compatible = "arm,coresight-cti"; + reg = <0xfc353000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <25>; + coresight-name = "coresight-cti-cpu2"; + coresight-nr-inports = <0>; + }; + + cti_cpu3: cti@fc354000 { + compatible = "arm,coresight-cti"; + reg = <0xfc354000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <26>; + coresight-name = "coresight-cti-cpu3"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@fd820018 { + compatible = "qcom,coresight-hwevent"; + reg = <0xfd820018 0x80>, + <0xf9011080 0x80>, + <0xfd4ab160 0x80>; + reg-names = "mmss-mux", "apcs-mux", "ppss-mux"; + + coresight-id = <27>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + + qcom,hwevent-clks = "core_mmss_clk"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-gpu.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-gpu.dtsi new file mode 100644 index 000000000..7e3ee0dcb --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-gpu.dtsi @@ -0,0 +1,167 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + msm_gpu: qcom,kgsl-3d0@fdc00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0xfdc00000 0x10000 + 0xfdc10000 0x10000>; + reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_shader_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03000520>; + + qcom,initial-pwrlevel = <1>; + + qcom,idle-timeout = <8>; /* */ + qcom,strtstp-sleepwake; + qcom,clk-map = <0x000005E>; /* KGSL_CLK_CORE | + KGSL_CLK_IFACE | KGSL_CLK_MEM | KGSL_CLK_MEM_IFACE | + KGSL_CLK_ALT_MEM_IFACE */ + + /* Bus Scale Settings */ + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 800000>, + <26 512 0 1600000>, + <26 512 0 2128000>; + + /* GDSC oxili regulators */ + vdd-supply = <&gdsc_oxili_cx>; + + /* IOMMU Data */ + iommu = <&gfx_iommu>; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <3>; + qcom,io-fraction = <0>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <300000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <150000000>; + qcom,bus-freq = <1>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,io-fraction = <0>; + }; + }; + + /* DVCS Info */ + qcom,dcvs-core-info { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,dcvs-core-info"; + + qcom,num-cores = <1>; + qcom,sensors = <0>; + + qcom,core-core-type = <1>; + + qcom,algo-disable-pc-threshold = <0>; + qcom,algo-em-win-size-min-us = <100000>; + qcom,algo-em-win-size-max-us = <300000>; + qcom,algo-em-max-util-pct = <97>; + qcom,algo-group-id = <95>; + qcom,algo-max-freq-chg-time-us = <100000>; + qcom,algo-slack-mode-dynamic = <100000>; + qcom,algo-slack-weight-thresh-pct = <0>; + qcom,algo-slack-time-min-us = <39000>; + qcom,algo-slack-time-max-us = <39000>; + qcom,algo-ss-win-size-min-us = <1000000>; + qcom,algo-ss-win-size-max-us = <1000000>; + qcom,algo-ss-util-pct = <95>; + qcom,algo-ss-no-corr-below-freq = <0>; + + qcom,energy-active-coeff-a = <2492>; + qcom,energy-active-coeff-b = <0>; + qcom,energy-active-coeff-c = <0>; + qcom,energy-leakage-coeff-a = <11>; + qcom,energy-leakage-coeff-b = <157150>; + qcom,energy-leakage-coeff-c = <0>; + qcom,energy-leakage-coeff-d = <0>; + + qcom,power-current-temp = <25>; + qcom,power-num-freq = <4>; + + qcom,dcvs-freq@0 { + reg = <0>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@1 { + reg = <1>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@2 { + reg = <2>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@3 { + reg = <3>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <844545>; + qcom,leakage-energy-offset = <0>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-iommu-domains.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-iommu-domains.dtsi new file mode 100644 index 000000000..6f438972d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-iommu-domains.dtsi @@ -0,0 +1,36 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,iommu-domains { + compatible = "qcom,iommu-domains"; + + qcom,iommu-domain1 { + label = "lpass_secure"; + qcom,iommu-contexts = <&lpass_q6_fw>; + qcom,virtual-addr-pool = <0x00000000 0x0FFFFFFF + 0xF0000000 0x0FFFFFFF>; + }; + + qcom,iommu-domain2 { + label = "lpass_audio"; + qcom,iommu-contexts = <&lpass_audio_shared>; + qcom,virtual-addr-pool = <0x10000000 0x0FFFFFFF>; + }; + + q6_domain_ns:qcom,iommu-domain3 { + label = "lpass_video"; + qcom,iommu-contexts = <&lpass_video_shared>; + qcom,virtual-addr-pool = <0x20000000 0x0FFFFFFF>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-ion.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-ion.dtsi new file mode 100644 index 000000000..456b60ced --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-ion.dtsi @@ -0,0 +1,38 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + qcom,ion-heap@27 { /* QSECOM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <27>; + linux,contiguous-region = <&qsecom_mem>; + }; + }; +}; + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-mdss.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-mdss.dtsi new file mode 100644 index 000000000..af0e3e4e3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-mdss.dtsi @@ -0,0 +1,37 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_mdp@fd900000 { + compatible = "qcom,mdss_mdp3"; + reg = <0xfd900000 0x100000>; + reg-names = "mdp_phys"; + interrupts = <0 72 0>; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x300000>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi@fdd00000 { + compatible = "qcom,msm-dsi-v2"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0xfdd00000 0x100000>; + interrupts = <0 30 0>; + vdda-supply = <&pm8110_l4>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-mtp.dts new file mode 100644 index 000000000..9406a0911 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-mtp.dts @@ -0,0 +1,354 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" +/include/ "dsi-v2-panel-truly-wvga-video.dtsi" +/include/ "msm8610-camera-sensor-cdp-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8610 MTP"; + compatible = "qcom,msm8610-mtp", "qcom,msm8610", "qcom,mtp"; + qcom,msm-id = <147 8 0>, <165 8 0>, <161 8 0>, <162 8 0>, + <163 8 0>, <164 8 0>, <166 8 0>; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; + + i2c@f9923000{ + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <1 0x2>; + vdd_ana-supply = <&pm8110_l19>; + vcc_i2c-supply = <&pm8110_l14>; + atmel,reset-gpio = <&msmgpio 0 0x00>; + atmel,irq-gpio = <&msmgpio 1 0x00>; + atmel,panel-coords = <0 0 508 880>; + atmel,display-coords = <0 0 480 800>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x81>; + atmel,variant-id = <0x15>; + atmel,version = <0x11>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 1D 01 00 0C 04 0D 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 + /* Object 8, Instance = 0 */ + 19 00 14 14 FF 00 FF 00 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 13 0B 00 20 32 01 03 + 00 32 05 30 0A 05 0A 00 70 03 + FC 01 00 36 2F 2C 00 00 40 00 + 00 0A 00 00 02 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 03 00 18 79 A8 61 + /* Object 58, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 42, Instance = 0 */ + 00 00 00 00 00 00 00 00 + /* Object 46, Instance = 0 */ + 04 03 08 10 00 00 00 00 00 + /* Object 47, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + /* Object 48, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <480>; + qcom,disp-maxy = <800>; + qcom,panel-maxx = <508>; + qcom,panel-maxy = <880>; + qcom,key-codes = <158 102 139>; + qcom,y-offset = <35>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 73 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 74 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 72 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "INT_LDO_H", "MCLK", + "MIC BIAS External", "Handset Mic", + "MIC BIAS Internal2", "Headset Mic", + "AMIC1", "MIC BIAS External", + "AMIC2", "MIC BIAS Internal2"; + }; +}; + +&i2c_cdc { + msm8x10_wcd_codec@0d{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x0d>; + cdc-vdda-cp-supply = <&pm8110_s4>; + qcom,cdc-vdda-cp-voltage = <2150000 2150000>; + qcom,cdc-vdda-cp-current = <650000>; + + cdc-vdda-h-supply = <&pm8110_l6>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <250000>; + + cdc-vdd-px-supply = <&pm8110_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-1p2v-supply = <&pm8110_l4>; + qcom,cdc-vdd-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-1p2v-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8110_l20>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias-cfilt-sel = <0x0>; + qcom,cdc-micbias-cfilt-mv = <1800000>; + qcom,cdc-mclk-clk-rate = <12288000>; + }; + + msm8x10_wcd_codec@77{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x77>; + }; + + msm8x10_wcd_codec@66{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x66>; + }; + + msm8x10_wcd_codec@55{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x55>; + }; +}; + +&spmi_bus { + qcom,pm8110@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "button-backlight"; + linux-default-trigger = "hr-trigger"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x60>; + qcom,mode = "manual"; + }; + }; + + qcom,leds@a200 { + status = "okay"; + qcom,led_mpp_3 { + label = "mpp"; + linux,name = "wled-backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,default-state = "on"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x10>; + qcom,mode = "manual"; + }; + }; + }; +}; + +&spmi_bus { + qcom,pm8110@1 { + qcom,vibrator@c000 { + status = "okay"; + qcom,vib-timeout-ms = <15000>; + qcom,vib-vtg-level-mV = <3100>; + }; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm8110_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 400000>; + + vdd-io-supply = <&pm8110_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 60000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8110_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 400000>; + + vdd-io-supply = <&pm8110_l21>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 50000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 42 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 42 0x1>; + + status = "ok"; +}; + +&pm8110_chg { + status = "ok"; + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8110_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; +}; + +&pm8110_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + status = "disabled"; + }; + + mpp@a200 { /* MPP 3 */ + status = "disabled"; + }; + + mpp@a300 { /* MPP 4 */ + /* PA_THERM config */ + qcom,mode = <4>; /* AIN input */ + qcom,invert = <1>; /* Enable MPP */ + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + }; +}; + +&pm8110_bms { + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-pm.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-pm.dtsi new file mode 100644 index 000000000..938b2aa2a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-pm.dtsi @@ -0,0 +1,391 @@ +/* Copyright (c) 2013 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f9099000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,core-id = <1>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f90a9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,core-id = <2>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f90b9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,core-id = <3>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-spm-cmd-wfi = [60 03 60 0b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 10 80 30 90 5b 60 03 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 10 80 30 90 5b 60 07 60 3b 76 76 + 0b 94 5b 80 10 06 26 30 0f]; + }; + + qcom,spm@f9012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9012000 0x1000>; + qcom,core-id = <0xffff>; /* L2/APCS SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3c102800>; + qcom,saw2-spm-ctl = <0x0>; + qcom,saw2-pmic-data0 = <0x02030080>; + qcom,saw2-pmic-data1 = <0x00030000>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + qcom,saw2-spm-cmd-ret = [00 03 00 7b 0f]; + qcom,saw2-spm-cmd-pc = [00 32 b0 10 e0 d0 6b c0 42 f0 + 11 07 01 b0 4e c0 d0 12 e0 6b 50 02 32 + 50 f0 7b 0f]; /*APCS_PMIC_OFF_L2RAM_OFF*/ + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x61706d73>; /* "smpa" */ + qcom,id = <0x01>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <3>; /* SVS SOC */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x616F646C>; /* "ldoa" */ + qcom,id = <0x03>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <3>; /* SVS SOC */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + + qcom,lpm-resources@3 { + reg = <0x3>; + qcom,name = "l2"; + qcom,local-resource-type; + qcom,init-value = "l2_cache_retention"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <1>; + qcom,ss-power = <784>; + qcom,energy-overhead = <190000>; + qcom,time-overhead = <100>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3000>; + qcom,ss-power = <725>; + qcom,energy-overhead = <99500>; + qcom,time-overhead = <3130>; + }; + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_retention"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <8000>; + qcom,ss-power = <138>; + qcom,energy-overhead = <1208400>; + qcom,time-overhead = <9200>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <4>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <9000>; + qcom,ss-power = <110>; + qcom,energy-overhead = <1250300>; + qcom,time-overhead = <9500>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <4>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <16300>; + qcom,ss-power = <63>; + qcom,energy-overhead = <2128000>; + qcom,time-overhead = <24200>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <4>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,latency-us = <24000>; + qcom,ss-power = <10>; + qcom,energy-overhead = <3202600>; + qcom,time-overhead = <33000>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <1>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <26000>; + qcom,ss-power = <2>; + qcom,energy-overhead = <4252000>; + qcom,time-overhead = <38000>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <47 172>, /* usb2_hsic_async_wakeup_irq */ + <53 104>, /* mdss_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <2 216>, /* tsens_upper_lower_int */ + <0xff 56>, /* q6_wdog_expired_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 61>, /* mss_a2_bam_irq */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_low */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr + <0xff 181>, /* o_wcss_apss_wdog_bite_and_reset_rdy */ + <0xff 161>, /* lpass_irq_out_spare[4] / + <0xff 162>, /* lpass_irq_out_spare[5]*/ + <0xff 234>, /* lpass_irq_out_spare[6]*/ + <0xff 235>, /* lpass_irq_out_spare[7]*/ + <0xff 188>, /* lpass_irq_out_apcs(0) */ + <0xff 189>, /* lpass_irq_out_apcs(1) */ + <0xff 190>, /* lpass_irq_out_apcs(2) */ + <0xff 191>, /* lpass_irq_out_apcs(3) */ + <0xff 192>, /* lpass_irq_out_apcs(4) */ + <0xff 194>, /* lpass_irq_out_apcs(6) */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 258>, /* rpm_ipc(28) */ + <0xff 259>, /* rpm_ipc(29) */ + <0xff 275>, /* rpm_ipc(30) */ + <0xff 276>, /* rpm_ipc(31) */ + <0xff 269>, /* rpm_wdog_expired_irq */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <3 1>, + <4 4 >, + <5 5 >, + <6 9 >, + <7 13>, + <8 17>, + <9 21>, + <10 27>, + <11 29>, + <12 31>, + <13 33>, + <14 35>, + <15 37>, + <16 38>, + <17 39>, + <18 41>, + <19 46>, + <20 48>, + <21 49>, + <22 50>, + <23 51>, + <24 52>, + <25 54>, + <26 62>, + <27 63>, + <28 64>, + <29 65>, + <30 66>, + <31 67>, + <32 68>, + <33 69>, + <34 71>, + <35 72>, + <36 106>, + <37 107>, + <38 108>, + <39 109>, + <40 110>, + <54 111>, + <55 113>; + }; + + qcom,pm-8x60@fe805664 { + compatible = "qcom,pm-8x60"; + reg = <0xfe805664 0x40>; + qcom,pc-mode = "tz_l2_int"; + qcom,use-sync-timer; + qcom,pc-resets-timer; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-qrd.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-qrd.dts new file mode 100644 index 000000000..5f9365a2a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-qrd.dts @@ -0,0 +1,267 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" +/include/ "dsi-v2-panel-hx8379a-wvga-video.dtsi" + +/ { + model = "Qualcomm MSM 8610 QRD"; + compatible = "qcom,msm8610-qrd", "qcom,msm8610", "qcom,qrd"; + qcom,msm-id = <147 11 0>, <165 11 0>, <161 11 0>, <162 11 0>, + <163 11 0>, <164 11 0>, <166 11 0>; +}; + +&soc { + i2c@f9923000{ + focaltech@38{ + compatible = "focaltech,5x06"; + reg = <0x38>; + interrupt-parent = <&msmgpio>; + interrupts = <1 0x2>; + vdd-supply = <&pm8110_l19>; + vcc_i2c-supply = <&pm8110_l14>; + focaltech,family-id = <0x06>; + focaltech,reset-gpio = <&msmgpio 0 0x00>; + focaltech,irq-gpio = <&msmgpio 1 0x00>; + focaltech,display-coords = <0 0 480 800>; + focaltech,panel-coords = <0 0 480 800>; + focaltech,button-map= <139 102 158>; + focaltech,no-force-update; + focaltech,i2c-pull-up; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "ft5x06_ts"; + qcom,disp-maxx = <480>; + qcom,disp-maxy = <800>; + qcom,panel-maxx = <481>; + qcom,panel-maxy = <940>; + qcom,key-codes = <139 0 102 158 0 0 0>; + qcom,y-offset = <0>; + }; + serial@f991e000 { + status = "ok"; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&msmgpio 73 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&msmgpio 74 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&msmgpio 72 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + i2c@f9927000 { + msm8x10_wcd_codec@0d{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x0d>; + cdc-vdda-cp-supply = <&pm8110_s4>; + qcom,cdc-vdda-cp-voltage = <2150000 2150000>; + qcom,cdc-vdda-cp-current = <650000>; + + cdc-vdda-h-supply = <&pm8110_l6>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <250000>; + + cdc-vdd-px-supply = <&pm8110_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-1p2v-supply = <&pm8110_l4>; + qcom,cdc-vdd-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-1p2v-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8110_l20>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias-cfilt-sel = <0x0>; + qcom,cdc-micbias-cfilt-mv = <1800000>; + qcom,cdc-mclk-clk-rate = <12288000>; + }; + + msm8x10_wcd_codec@77{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x77>; + }; + + msm8x10_wcd_codec@66{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x66>; + }; + + msm8x10_wcd_codec@55{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x55>; + }; + }; + + sound { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "INT_LDO_H", "MCLK", + "MIC BIAS Internal1", "Handset Mic", + "MIC BIAS Internal2", "Headset Mic", + "AMIC1", "MIC BIAS Internal1", + "AMIC2", "MIC BIAS Internal2"; + }; +}; + +&spmi_bus { + qcom,pm8110@0 { + qcom,leds@a100 { + status = "okay"; + qcom,led_mpp_2 { + label = "mpp"; + linux,name = "wled-homerow"; + linux-default-trigger = "hr-trigger"; + qcom,default-state = "off"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x61>; + }; + }; + + qcom,leds@a200 { + status = "okay"; + qcom,led_mpp_3 { + label = "mpp"; + linux,name = "wled-backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,default-state = "on"; + qcom,max-current = <40>; + qcom,id = <6>; + qcom,source-sel = <1>; + qcom,mode-ctrl = <0x10>; + }; + }; + }; +}; + +&spmi_bus { + qcom,pm8110@1 { + qcom,vibrator@c000 { + status = "okay"; + qcom,vib-timeout-ms = <15000>; + qcom,vib-vtg-level-mV = <3100>; + }; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm8110_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 400000>; + + vdd-io-supply = <&pm8110_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 60000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8110_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 400000>; + + vdd-io-supply = <&pm8110_l21>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 50000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 42 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 42 0x1>; + + status = "ok"; +}; + +&pm8110_chg { + status = "ok"; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-regulator.dtsi new file mode 100644 index 000000000..09520c537 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-regulator.dtsi @@ -0,0 +1,358 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SPM controlled regulators */ + +&spmi_bus { + qcom,pm8110@1 { + pm8110_s2: spm-regulator@1700 { + compatible = "qcom,spm-regulator"; + regulator-name = "8110_s2"; + reg = <0x1700 0x100>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + }; + }; +}; + +/* CPR controlled regulator */ + +&soc { + apc_vreg_corner: regulator@f9018000 { + status = "okay"; + compatible = "qcom,cpr-regulator"; + reg = <0xf9018000 0x1000>, <0xf9011064 4>, <0xfc4b80b0 8>, + <0xfc4bc450 16>; + reg-names = "rbcpr", "rbcpr_clk", "pvs_efuse", "cpr_efuse"; + interrupts = <0 15 0>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + qcom,num-efuse-bits = <5>; + qcom,pvs-bin-process = <0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 2 + 2 2 2 2 3 3 3 3 3 3 3 3 0 0 0 0>; + qcom,pvs-corner-ceiling-slow = <1150000 1150000 1275000>; + qcom,pvs-corner-ceiling-nom = <975000 1075000 1200000>; + qcom,pvs-corner-ceiling-fast = <900000 1000000 1140000>; + vdd-apc-supply = <&pm8110_s2>; + + vdd-mx-supply = <&pm8110_l3_ao>; + qcom,vdd-mx-vmax = <1350000>; + qcom,vdd-mx-vmin-method = <1>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <1>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <15>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <5>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <5000>; + }; +}; + +/* RPM controlled regulators: */ + +&rpm_bus { + + rpm-regulator-smpa1 { + status = "okay"; + pm8110_s1: regulator-s1 { + status = "okay"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1275000>; + }; + + pm8110_s1_corner: regulator-s1-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s1_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + qcom,consumer-supplies = "vdd_dig", ""; + }; + + pm8110_s1_corner_ao: regulator-s1-corner-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_s1_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + qcom,consumer-supplies = "vdd_sr2_dig", ""; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8110_s3: regulator-s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8110_s4: regulator-s4 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + qcom,init-voltage = <2150000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8110_l1: regulator-l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8110_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8110_l3: regulator-l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + + pm8110_l3_ao: regulator-l3-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l3_ao"; + qcom,set = <1>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + status = "okay"; + }; + + pm8110_l3_so: regulator-l3-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l3_so"; + qcom,set = <2>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1275000>; + qcom,init-voltage = <750000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8110_l4: regulator-l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8110_l5: regulator-l5 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8110_l6: regulator-l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8110_l7: regulator-l7 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8110_l8: regulator-l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8110_l9: regulator-l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8110_l10: regulator-l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8110_l10_ao: regulator-l10-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l10_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,consumer-supplies = "vdd_sr2_pll", ""; + }; + + pm8110_l10_so: regulator-l10-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8110_l10_so"; + qcom,set = <2>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-enable = <0>; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8110_l12: regulator-l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8110_l14: regulator-l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8110_l15: regulator-l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8110_l16: regulator-l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8110_l17: regulator-l17 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8110_l18: regulator-l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8110_l19: regulator-l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + pm8110_l20: regulator-l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + pm8110_l21: regulator-l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8110_l22: regulator-l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; + status = "okay"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-rumi.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-rumi.dts new file mode 100644 index 000000000..7f0648541 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-rumi.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" + +/ { + model = "Qualcomm MSM 8610 Rumi"; + compatible = "qcom,msm8610-rumi", "qcom,msm8610", "qcom,rumi"; + qcom,msm-id = <147 15 0>; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; +}; + +&gfx_iommu { + status = "disabled"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-sim.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-sim.dts new file mode 100644 index 000000000..7c57fe667 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-sim.dts @@ -0,0 +1,72 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8610.dtsi" + +/ { + model = "Qualcomm MSM 8610 Simulator"; + compatible = "qcom,msm8610-sim", "qcom,msm8610", "qcom,sim"; + qcom,msm-id = <147 16 0>; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; +}; + +&i2c_cdc { + msm8x10_wcd_codec@0d{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x0d>; + cdc-vdda-cp-supply = <&pm8110_s4>; + qcom,cdc-vdda-cp-voltage = <2150000 2150000>; + qcom,cdc-vdda-cp-current = <650000>; + + cdc-vdda-h-supply = <&pm8110_l6>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <250000>; + + cdc-vdd-px-supply = <&pm8110_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-1p2v-supply = <&pm8110_l4>; + qcom,cdc-vdd-1p2v-voltage = <1200000 1200000>; + qcom,cdc-vdd-1p2v-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8110_l20>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias-cfilt-sel = <0x0>; + qcom,cdc-micbias-cfilt-mv = <1800000>; + qcom,cdc-mclk-clk-rate = <12288000>; + }; + + msm8x10_wcd_codec@77{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x77>; + }; + + msm8x10_wcd_codec@66{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x66>; + }; + + msm8x10_wcd_codec@55{ + compatible = "qcom,msm8x10-wcd-i2c"; + reg = <0x55>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-smp2p.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-smp2p.dtsi new file mode 100644 index 000000000..3921a686a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610-smp2p.dtsi @@ -0,0 +1,225 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-wcnss { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <4>; + qcom,irq-bitmask = <0x40000>; + interrupts = <0 143 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + /* SMP2P SSR Driver for inbound entry from lpass. */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* SMP2P SSR Driver for outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_4_in: qcom,smp2pgpio-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_in { + compatible = "qcom,smp2pgpio_test_smp2p_4_in"; + gpios = <&smp2pgpio_smp2p_4_in 0 0>; + }; + + smp2pgpio_smp2p_4_out: qcom,smp2pgpio-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_in: qcom,smp2pgpio-ssr-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_out: qcom,smp2pgpio-ssr-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_out { + compatible = "qcom,smp2pgpio_test_smp2p_4_out"; + gpios = <&smp2pgpio_smp2p_4_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610.dtsi new file mode 100644 index 000000000..a62df58d9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8610.dtsi @@ -0,0 +1,1075 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM 8610"; + compatible = "qcom,msm8610"; + interrupt-parent = <&intc>; + + memory { + qsecom_mem: qsecom_region { + linux,contiguous-region; + reg = <0 0x100000>; + label = "qsecom_mem"; + }; + }; + + aliases { + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + spi4 = &spi_4; + }; + + soc: soc { }; +}; + +/include/ "msm8610-camera.dtsi" +/include/ "msm-iommu-v0.dtsi" +/include/ "msm8610-ion.dtsi" +/include/ "msm8610-gpu.dtsi" +/include/ "msm-gdsc.dtsi" +/include/ "msm8610-coresight.dtsi" +/include/ "msm8610-pm.dtsi" +/include/ "msm8610-smp2p.dtsi" +/include/ "msm8610-bus.dtsi" +/include/ "msm8610-mdss.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <102>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + qcom,mpm2-sleep-counter@fc4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xfc4a3000 0x1000>; + clock-frequency = <32768>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,smmu-enabled; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + serial@f991e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991e000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + }; + + qcom,vidc@fdc00000 { + compatible = "qcom,msm-vidc"; + qcom,vidc-ns-map = <0x40000000 0x40000000>; + qcom,iommu-groups = <&q6_domain_ns>; + qcom,iommu-group-buffer-types = <0xfff>; + qcom,buffer-type-tz-usage-map = <0x1 0x1>, + <0x1fe 0x2>; + qcom,hfi = "q6"; + qcom,max-hw-load = <108000>; /* 720p @ 30 * 1 */ + }; + + qcom,usbbam@f9a44000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xf9a44000 0x11000>; + reg-names = "hsusb"; + interrupts = <0 135 0>; + interrupt-names = "hsusb"; + qcom,usb-bam-num-pipes = <16>; + qcom,usb-bam-fifo-baseaddr = <0xfe803000>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + + qcom,pipe0 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <3>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37c000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x600>; + qcom,descriptor-fifo-offset = <0x600>; + qcom,descriptor-fifo-size = <0x200>; + }; + }; + + usb@f9a55000 { + compatible = "qcom,hsusb-otg"; + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0>, <0 140 0>; + interrupt-names = "core_irq", "async_irq"; + HSUSB_VDDCX-supply = <&pm8110_s1>; + HSUSB_1p8-supply = <&pm8110_l10>; + HSUSB_3p3-supply = <&pm8110_l20>; + + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <2>; + qcom,hsusb-otg-disable-reset; + qcom,dp-manual-pullup; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 60000 960000>; + }; + + android_usb@fe8050c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8050c8 0xc8>; + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>, + <0xf9824800 0x100>, + <0xf9804000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 123 0>, <0 137 0>; + interrupt-names = "core_irq", "bam_irq"; + + vdd-supply = <&pm8110_l17>; + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <9000 400000>; + + vdd-io-supply = <&pm8110_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <9000 60000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2900 2900>; + qcom,bus-width = <8>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + status = "disabled"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>, + <0xf98a4800 0x100>, + <0xf9884000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 125 0>, <0 220 0>; + interrupt-names = "core_irq", "bam_irq"; + + vdd-supply = <&pm8110_l18>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 400000>; + + vdd-io-supply = <&pm8110_l21>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <9000 50000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <4>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + status = "disabled"; + }; + + sdhc_1: sdhci@f9824900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + status = "disabled"; + }; + + qcom,sps { + compatible = "qcom,msm_sps"; + qcom,device-type = <3>; + }; + + qcom,smem@d900000 { + compatible = "qcom,smem"; + reg = <0xd900000 0x100000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1000>; + qcom,pil-string = "modem"; + interrupts = <0 25 1>; + }; + + qcom,smsm-modem { + compatible = "qcom,smsm"; + qcom,smsm-edge = <0>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x2000>; + interrupts = <0 26 1>; + }; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-wcnss { + compatible = "qcom,smd"; + qcom,smd-edge = <6>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x20000>; + qcom,pil-string = "wcnss"; + interrupts = <0 142 1>; + }; + + qcom,smsm-wcnss { + compatible = "qcom,smsm"; + qcom,smsm-edge = <6>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x80000>; + interrupts = <0 144 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + rpm-standalone; + }; + + qcom,bcl { + compatible = "qcom,bcl"; + }; + + qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x07B00000 0x6400000>; /* Address and Size of Hole */ + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + }; + + qcom,acpuclk@f9011050 { + compatible = "qcom,acpuclk-a7"; + reg = <0xf9011050 0x8>; + reg-names = "rcg_base"; + a7_cpu-supply = <&apc_vreg_corner>; + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0>, <0 187 0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + i2c@f9923000 { /* BLSP-1 QUP-1 */ + cell-index = <1>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9923000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 95 0>; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + qcom,sda-gpio = <&msmgpio 2 0>; + qcom,scl-gpio = <&msmgpio 3 0>; + }; + + i2c_cdc: i2c@f9927000 { /* BLSP1 QUP5 */ + cell-index = <5>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9927000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 99 0>; + qcom,i2c-bus-freq = <100000>; + }; + + i2c: i2c@f9928000 { /* BLSP1 QUP6 */ + cell-index = <6>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9928000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 100 0>; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + qcom,sda-gpio = <&msmgpio 16 0>; + qcom,scl-gpio = <&msmgpio 17 0>; + }; + + i2c@f9925000 { /* BLSP-1 QUP-3 */ + cell-index = <0>; + compatible = "qcom,i2c-qup"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xf9925000 0x1000>; + interrupt-names = "qup_err_intr"; + interrupts = <0 97 0>; + qcom,i2c-bus-freq = <100000>; + }; + + spi_4: spi@f9926000 { /* BLSP1 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xf9926000 0x1000>, + <0xf9904000 0x15000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 0>, <0 238 0>; + spi-max-frequency = <50000000>; + + gpios = <&msmgpio 89 0>, /* CLK */ + <&msmgpio 87 0>, /* MISO */ + <&msmgpio 86 0>; /* MOSI */ + cs-gpios = <&msmgpio 88 0>; + + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <18>; + qcom,bam-producer-pipe-index = <19>; + }; + + qcom,pronto@fb21b000 { + compatible = "qcom,pil-pronto"; + reg = <0xfb21b000 0x3000>, + <0xfc401700 0x4>, + <0xfd485300 0xc>; + reg-names = "pmu_base", "clk_base", "halt_base"; + interrupts = <0 149 1>; + vdd_pronto_pll-supply = <&pm8110_l10>; + + qcom,firmware-name = "wcnss"; + + /* GPIO inputs from wcnss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>; + + /* GPIO output to wcnss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>; + }; + + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + + sound { + compatible = "qcom,msm8x10-audio-codec"; + qcom,model = "msm8x10-snd-card"; + }; + + qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + }; + + qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + qcom,msm-pcm-lpa { + compatible = "qcom,msm-pcm-lpa"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + }; + + qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <3>; + }; + + qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <3>; + qcom,msm-mi2s-tx-lines = <0>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + qcom,wcnss-wlan@fb000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xfb000000 0x280000>, + <0xf9011008 0x04>; + reg-names = "wcnss_mmio", "wcnss_fiq"; + interrupts = <0 145 0>, <0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8110_l3>; + qcom,pronto-vddcx-supply = <&pm8110_s1>; + qcom,pronto-vddpx-supply = <&pm8110_l6>; + qcom,iris-vddxo-supply = <&pm8110_l10>; + qcom,iris-vddrfa-supply = <&pm8110_l5>; + qcom,iris-vddpa-supply = <&pm8110_l16>; + qcom,iris-vdddig-supply = <&pm8110_l5>; + + gpios = <&msmgpio 23 0>, <&msmgpio 24 0>, <&msmgpio 25 0>, <&msmgpio 26 0>, <&msmgpio 27 0>; + qcom,has-pronto-hw; + qcom,wlan-rx-buff-count = <256>; + }; + + qcom,mss@fc880000 { + compatible = "qcom,pil-q6v5-mss"; + reg = <0xfc880000 0x100>, + <0xfd485000 0x400>, + <0xfc820000 0x020>, + <0xfc401680 0x004>, + <0xfd485194 0x4>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg", "cxrail_bhs_reg"; + + interrupts = <0 24 1>; + vdd_cx-supply = <&pm8110_s1_corner>; + vdd_mx-supply = <&pm8110_l3>; + vdd_pll-supply = <&pm8110_l10>; + qcom,vdd_pll = <1800000>; + qcom,is-loadable; + qcom,firmware-name = "mba"; + qcom,pil-self-auth; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + qcom,lpass@fe200000 { + compatible = "qcom,pil-q6v5-lpass"; + reg = <0xfe200000 0x00100>, + <0xfd485100 0x00010>, + <0xfc4016c0 0x00004>; + reg-names = "qdsp6_base", "halt_base", "restart_reg"; + interrupts = <0 162 1>; + vdd_cx-supply = <&pm8110_s1_corner>; + qcom,firmware-name = "adsp"; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + tsens: tsens@fc4a8000 { + compatible = "qcom,msm-tsens"; + reg = <0xfc4a8000 0x2000>, + <0xfc4b8000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + qcom,sensors = <2>; + qcom,slope = <2901 2846>; + qcom,calib-mode = "fuse_map3"; + qcom,sensor-id = <0 5>; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <5>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-control-mask = <0xf>; + }; + + qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + }; + + qcom,qseecom@7B00000 { + compatible = "qcom,qseecom"; + reg = <0x7B00000 0x500000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; + + qcom,msm-rng@f9bff000 { + compatible = "qcom,msm-rng"; + reg = <0xf9bff000 0x200>; + qcom,msm-rng-iface-clk; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + jtag_mm0: jtagmm@fc34c000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc34c000 0x1000>, + <0xfc340000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm1: jtagmm@fc34d000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc34d000 0x1000>, + <0xfc342000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm2: jtagmm@fc34e000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc34e000 0x1000>, + <0xfc344000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + jtag_mm3: jtagmm@fc34f000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc34f000 0x1000>, + <0xfc346000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + qcom,tz-log@fe805720 { + compatible = "qcom,tz-log"; + reg = <0x0fe805720 0x1000>; + }; + + qcom,qcrypto@fd404000 { + compatible = "qcom,qcrypto"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <1>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 3936000>; + }; + + qcom,qcedev@fd400000 { + compatible = "qcom,qcedev"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <1>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 3936000>; + }; + +}; + +&gdsc_vfe { + status = "ok"; +}; + +&gdsc_oxili_cx { + status = "ok"; +}; + +&lpass_iommu { + status = "ok"; +}; + +&copss_iommu { + status = "ok"; +}; + +&mdpe_iommu { + status = "ok"; +}; + +&mdps_iommu { + status = "ok"; +}; + +&gfx_iommu { + status = "ok"; +}; + +&vfe_iommu { + status = "ok"; +}; + +/include/ "msm8610-iommu-domains.dtsi" + +/include/ "msm-pm8110-rpm-regulator.dtsi" +/include/ "msm-pm8110.dtsi" +/include/ "msm8610-regulator.dtsi" + +&pm8110_vadc { + chan@0 { + label = "usb_in"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <4>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@2 { + label = "vchg_sns"; + reg = <2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <2>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@31 { + label = "batt_id"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@b2 { + label = "xo_therm_pu2"; + reg = <0xb2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@13 { + label = "pa_therm0"; + reg = <0x13>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8110_adc_tm { + /* Channel Node */ + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <1>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x48>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x68>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <3>; + qcom,btm-channel-number = <0x70>; + }; + + chan@13 { + label = "pa_therm0"; + reg = <0x13>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8660-surf.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8660-surf.dts new file mode 100644 index 000000000..4518fc4a3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8660-surf.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM8660 SURF"; + compatible = "qcom,msm8660-surf", "qcom,msm8660", "qcom,surf"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@02080000 { + compatible = "qcom,msm-8660-qgic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02080000 0x1000 >, + < 0x02081000 0x1000 >; + }; + + serial@19c400000 { + compatible = "qcom,msm-hsuart", "qcom,msm-uart"; + reg = <0x19c40000 0x1000>, + <0x19c00000 0x1000>; + interrupts = <0 195 0x0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-cdp.dts new file mode 100644 index 000000000..7a91d40ee --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-cdp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/include/ "msm8926.dtsi" +/include/ "msm8226-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8926 CDP"; + compatible = "qcom,msm8926-cdp", "qcom,msm8926", "qcom,cdp"; + qcom,msm-id = <200 1 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-mtp.dts new file mode 100644 index 000000000..fea925d62 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/include/ "msm8926.dtsi" +/include/ "msm8226-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8926 MTP"; + compatible = "qcom,msm8926-mtp", "qcom,msm8926", "qcom,mtp"; + qcom,msm-id = <200 8 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-qrd.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-qrd.dts new file mode 100644 index 000000000..e056b7e87 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926-qrd.dts @@ -0,0 +1,21 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "msm8926.dtsi" +/include/ "msm8226-qrd.dtsi" + +/ { + model = "Qualcomm MSM 8926 QRD"; + compatible = "qcom,msm8926-qrd", "qcom,msm8926", "qcom,qrd"; + qcom,msm-id = <200 11 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926.dtsi new file mode 100644 index 000000000..6f3f59251 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8926.dtsi @@ -0,0 +1,30 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Only 8926-specific property overrides should be placed inside this + * file. Device definitions should be placed inside the msm8226.dtsi + * file. + */ + +/include/ "msm8226.dtsi" + +/ { + model = "Qualcomm MSM 8926"; + compatible = "qcom,msm8926"; +}; + +&soc { + qcom,mss@fc880000 { + vdd_mss-supply = <&pm8226_s5>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-bus.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-bus.dtsi new file mode 100644 index 000000000..609a1b302 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-bus.dtsi @@ -0,0 +1,1411 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm-mmss-noc@fc478000 { + compatible = "msm-bus-fabric"; + reg = <0xfc478000 0x00004000>; + cell-id = <2048>; + label = "msm_mmss_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <52>; + coresight-name = "coresight-mnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <5>; + + mas-gfx3d { + cell-id = <26>; + label = "mas-gfx3d"; + qcom,masterp = <2 3>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <2 3>; + qcom,mas-hw-id = <6>; + }; + + mas-jpeg { + cell-id = <62>; + label = "mas-jpeg"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <7>; + }; + + mas-mdp-port0 { + cell-id = <22>; + label = "mas-mdp-port0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,qport = <1>; + qcom,ws = <10000>; + qcom,mas-hw-id = <8>; + }; + + mas-video-p0 { + cell-id = <63>; + label = "mas-video-p0"; + qcom,masterp = <6 7>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <4 5>; + qcom,mas-hw-id = <9>; + }; + + mas-vfe { + cell-id = <29>; + label = "mas-vfe"; + qcom,masterp = <16>; + qcom,tier = <2>; + qcom,hw-sel = "NoC"; + qcom,perm-mode = "Bypass"; + qcom,mode = "Bypass"; + qcom,ws = <10000>; + qcom,qport = <6>; + qcom,mas-hw-id = <11>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,masterp = <0 1>; + qcom,buswidth = <16>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <4>; + }; + + fab-bimc { + cell-id = <0>; + label = "fab-bimc"; + qcom,gateway; + qcom,slavep = <16 17>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <16>; + }; + + slv-camera-cfg { + cell-id = <589>; + label = "slv-camera-cfg"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <3>; + }; + + slv-display-cfg { + cell-id = <590>; + label = "slv-display-cfg"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <4>; + }; + + slv-ocmem-cfg { + cell-id = <591>; + label = "slv-ocmem-cfg"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <5>; + }; + + slv-cpr-cfg { + cell-id = <592>; + label = "slv-cpr-cfg"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <6>; + }; + + slv-cpr-xpu-cfg { + cell-id = <593>; + label = "slv-cpr-xpu-cfg"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <7>; + }; + + slv-misc-cfg { + cell-id = <594>; + label = "slv-misc-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <8>; + }; + + slv-misc-xpu-cfg { + cell-id = <595>; + label = "slv-misc-xpu-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <9>; + }; + + slv-venus-cfg { + cell-id = <596>; + label = "slv-venus-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <10>; + }; + + slv-gfx3d-cfg { + cell-id = <598>; + label = "slv-gfx3d-cfg"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <11>; + }; + + slv-mmss-clk-cfg { + cell-id = <599>; + label = "slv-mmss-clk-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <12>; + }; + + slv-mmss-clk-xpu-cfg { + cell-id = <600>; + label = "slv-mmss-clk-xpu-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <13>; + }; + + slv-mnoc-mpu-cfg { + cell-id = <601>; + label = "slv-mnoc-mpu-cfg"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <14>; + }; + + slv-onoc-mpu-cfg { + cell-id = <602>; + label = "slv-onoc-mpu-cfg"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <15>; + }; + + slv-service-mnoc { + cell-id = <603>; + label = "slv-service-mnoc"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,hw-sel = "NoC"; + qcom,slv-hw-id = <17>; + }; + + }; + + msm-sys-noc@fc460000 { + compatible = "msm-bus-fabric"; + reg = <0xfc460000 0x00004000>; + cell-id = <1024>; + label = "msm_sys_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <50>; + coresight-name = "coresight-snoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <3>; + + msm-lpass-ahb { + cell-id = <52>; + label = "mas-lpass-ahb"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,qport = <0>; + qcom,mas-hw-id = <18>; + qcom,mode = "Fixed"; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + mas-qdss-bam { + cell-id = <53>; + label = "mas-qdss-bam"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <1>; + qcom,mas-hw-id = <19>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,hw-sel = "NoC"; + }; + + mas-snoc-cfg { + cell-id = <54>; + label = "mas-snoc-cfg"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,mas-hw-id = <20>; + }; + + fab-bimc { + cell-id = <0>; + label= "fab-bimc"; + qcom,gateway; + qcom,slavep = <7 8>; + qcom,masterp = <3>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <21>; + qcom,slv-hw-id = <24>; + }; + + fab-cnoc { + cell-id = <5120>; + label = "fab-cnoc"; + qcom,gateway; + qcom,slavep = <9>; + qcom,masterp = <4>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <22>; + qcom,slv-hw-id = <25>; + }; + + fab-pnoc { + cell-id = <4096>; + label = "fab-pnoc"; + qcom,gateway; + qcom,slavep = <12>; + qcom,masterp = <11>; + qcom,buswidth = <8>; + qcom,qport = <8>; + qcom,mas-hw-id = <29>; + qcom,slv-hw-id = <28>; + qcom,mode = "Fixed"; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + fab-ovnoc { + cell-id = <6144>; + label = "fab-ovnoc"; + qcom,gateway; + qcom,buswidth = <8>; + qcom,mas-hw-id = <53>; + qcom,slv-hw-id = <77>; + }; + + mas-crypto-core0 { + cell-id = <55>; + label = "mas-crypto-core0"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <2>; + qcom,mas-hw-id = <23>; + qcom,hw-sel = "NoC"; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + }; + + mas-crypto-core1 { + cell-id = <56>; + label = "mas-crypto-core1"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <3>; + qcom,mas-hw-id = <24>; + qcom,hw-sel = "NoC"; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + }; + + mas-lpass-proc { + cell-id = <11>; + label = "mas-lpass-proc"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,qport = <4>; + qcom,mas-hw-id = <25>; + qcom,mode = "Fixed"; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + }; + + mas-mss { + cell-id = <38>; + label = "mas-mss"; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,mas-hw-id = <26>; + }; + + mas-mss-nav { + cell-id = <57>; + label = "mas-mss-nav"; + qcom,masterp = <9>; + qcom,tier = <2>; + qcom,mas-hw-id = <27>; + }; + + mas-ocmem-dma { + cell-id = <58>; + label = "mas-ocmem-dma"; + qcom,masterp = <10>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <7>; + qcom,mas-hw-id = <28>; + }; + + mas-wcss { + cell-id = <59>; + label = "mas-wcss"; + qcom,masterp = <12>; + qcom,tier = <2>; + qcom,mas-hw-id = <30>; + }; + + mas-qdss-etr { + cell-id = <60>; + label = "mas-qdss-etr"; + qcom,masterp = <13>; + qcom,tier = <2>; + qcom,qport = <10>; + qcom,mode = "Fixed"; + qcom,mas-hw-id = <31>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,hw-sel = "NoC"; + }; + + mas-usb3 { + cell-id = <61>; + label = "mas-usb3"; + qcom,masterp = <14>; + qcom,tier = <2>; + qcom,mode = "Fixed"; + qcom,qport = <11>; + qcom,mas-hw-id = <32>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,hw-sel = "NoC"; + qcom,iface-clk-node = "msm_usb3"; + }; + + slv-ampss { + cell-id = <520>; + label = "slv-ampss"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <20>; + }; + + slv-lpass { + cell-id = <522>; + label = "slv-lpass"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <21>; + }; + + slv-usb3 { + cell-id = <583>; + label = "slv-usb3"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <22>; + }; + + slv-wcss { + cell-id = <584>; + label = "slv-wcss"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <23>; + }; + + slv-ocimem { + cell-id = <585>; + label = "slv-ocimem"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <26>; + }; + + slv-snoc-ocmem { + cell-id = <586>; + label = "slv-snoc-ocmem"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <27>; + }; + + slv-service-snoc { + cell-id = <587>; + label = "slv-service-snoc"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <29>; + }; + + slv-qdss-stm { + cell-id = <588>; + label = "slv-qdss-stm"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <30>; + }; + + }; + + msm-periph-noc@fc468000 { + compatible = "msm-bus-fabric"; + reg = <0xfc468000 0x00004000>; + cell-id = <4096>; + label = "msm_periph_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <54>; + coresight-name = "coresight-pnoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <6>; + + mas-pnoc-cfg { + cell-id = <88>; + label = "mas-pnoc-cfg"; + qcom,masterp = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <43>; + }; + + mas-sdcc-1 { + cell-id = <78>; + label = "mas-sdcc-1"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <33>; + }; + + mas-sdcc-3 { + cell-id = <79>; + label = "mas-sdcc-3"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <34>; + }; + + mas-sdcc-4 { + cell-id = <80>; + label = "mas-sdcc-4"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <36>; + }; + + mas-sdcc-2 { + cell-id = <81>; + label = "mas-sdcc-2"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <35>; + }; + + mas-tsif { + cell-id = <82>; + label = "mas-tsif"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <37>; + }; + + mas-bam-dma { + cell-id = <83>; + label = "mas-bam-dma"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <38>; + }; + + mas-blsp-2 { + cell-id = <84>; + label = "mas-blsp-2"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <39>; + }; + + mas-usb-hsic { + cell-id = <85>; + label = "mas-usb-hsic"; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <40>; + }; + + mas-blsp-1 { + cell-id = <86>; + label = "mas-blsp-1"; + qcom,masterp = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <41>; + }; + + mas-usb-hs { + cell-id = <87>; + label = "mas-usb-hs"; + qcom,masterp = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <42>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <14>; + qcom,masterp = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <45>; + qcom,mas-hw-id = <44>; + }; + + slv-sdcc-1 { + cell-id = <606>; + label = "slv-sdcc-1"; + qcom,slavep = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <31>; + }; + + slv-sdcc-3 { + cell-id = <607>; + label = "slv-sdcc-3"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <32>; + }; + + slv-sdcc-2 { + cell-id = <608>; + label = "slv-sdcc-2"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <33>; + }; + + slv-sdcc-4 { + cell-id = <609>; + label = "slv-sdcc-4"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <34>; + }; + + slv-tsif { + cell-id = <575>; + label = "slv-tsif"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <35>; + }; + + slv-bam-dma { + cell-id = <610>; + label = "slv-bam-dma"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <36>; + }; + + slv-blsp-2 { + cell-id = <611>; + label = "slv-blsp-2"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <37>; + }; + + slv-usb-hsic { + cell-id = <612>; + label = "slv-usb-hsic"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <38>; + }; + + slv-blsp-1 { + cell-id = <613>; + label = "slv-blsp-1"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <39>; + }; + + slv-usb-hs { + cell-id = <614>; + label = "slv-usb-hs"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <40>; + }; + + slv-pdm { + cell-id = <615>; + label = "slv-pdm"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <41>; + }; + + slv-periph-apu-cfg { + cell-id = <616>; + label = "slv-periph-apu-cfg"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <42>; + }; + + slv-pnoc-mpu-cfg { + cell-id = <617>; + label = "slv-pnoc-mpu-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <43>; + }; + + slv-prng { + cell-id = <618>; + label = "slv-prng"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <44>; + }; + + slv-service-pnoc { + cell-id = <619>; + label = "slv-service-pnoc"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <46>; + }; + + }; + + msm-config-noc@fc480000 { + compatible = "msm-bus-fabric"; + reg = <0xfc480000 0x00004000>; + cell-id = <5120>; + label = "msm_config_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + mas-rpm-inst { + cell-id = <72>; + label = "mas-rpm-inst"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <45>; + }; + + mas-rpm-data { + cell-id = <73>; + label = "mas-rpm-data"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <46>; + }; + + mas-rpm-sys { + cell-id = <74>; + label = "mas-rpm-sys"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <47>; + }; + + mas-dehr { + cell-id = <75>; + label = "mas-dehr"; + qcom,masterp = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <48>; + }; + + mas-qdss-dsp { + cell-id = <76>; + label = "mas-qdss-dap"; + qcom,masterp = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <49>; + }; + + mas-spdm { + cell-id = <36>; + label = "mas-spdm"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <50>; + }; + + mas-tic { + cell-id = <77>; + label = "mas-tic"; + qcom,masterp = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <51>; + }; + + slv-clk-ctl { + cell-id = <620>; + label = "slv-clk-ctl"; + qcom,slavep = <1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <47>; + }; + + slv-cnoc-mss { + cell-id = <621>; + label = "slv-cnoc-mss"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <48>; + }; + + slv-security { + cell-id = <622>; + label = "slv-security"; + qcom,slavep = <3>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <49>; + }; + + slv-tcsr { + cell-id = <623>; + label = "slv-tcsr"; + qcom,slavep = <4>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <50>; + }; + + slv-tlmm { + cell-id = <624>; + label = "slv-tlmm"; + qcom,slavep = <5>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <51>; + }; + + slv-crypto-0-cfg { + cell-id = <625>; + label = "slv-crypto-0-cfg"; + qcom,slavep = <6>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <52>; + }; + + slv-crypto-1-cfg { + cell-id = <626>; + label = "slv-crypto-1-cfg"; + qcom,slavep = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <53>; + }; + + slv-imem-cfg { + cell-id = <627>; + label = "slv-imem-cfg"; + qcom,slavep = <8>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <54>; + }; + + slv-message-ram { + cell-id = <628>; + label = "slv-message-ram"; + qcom,slavep = <9>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <55>; + }; + + slv-bimc-cfg { + cell-id = <629>; + label = "slv-bimc-cfg"; + qcom,slavep = <10>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <56>; + }; + + slv-boot-rom { + cell-id = <630>; + label = "slv-boot-rom"; + qcom,slavep = <11>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <57>; + }; + + slv-pmic-arb { + cell-id = <632>; + label = "slv-pmic-arb"; + qcom,slavep = <13>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <59>; + }; + + slv-spdm-wrapper { + cell-id = <633>; + label = "slv-spdm-wrapper"; + qcom,slavep = <14>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <60>; + }; + + slv-dehr-cfg { + cell-id = <634>; + label = "slv-dehr-cfg"; + qcom,slavep = <15>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <61>; + }; + + slv-mpm { + cell-id = <536>; + label = "slv-mpm"; + qcom,slavep = <16>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <62>; + }; + + slv-qdss-cfg { + cell-id = <635>; + label = "slv-qdss-cfg"; + qcom,slavep = <17>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <63>; + }; + + slv-rbcpr-cfg { + cell-id = <636>; + label = "slv-rbcpr-cfg"; + qcom,slavep = <18>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <64>; + }; + + slv-rbcpr-qdss-apu-cfg { + cell-id = <637>; + label = "slv-rbcpr-qdss-apu-cfg"; + qcom,slavep = <19>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <65>; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <29>; + qcom,masterp = <7>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <52>; + qcom,slv-hw-id = <75>; + }; + + slv-cnoc-onoc-cfg { + cell-id = <639>; + label = "slv-cnoc-onoc-cfg"; + qcom,slavep = <22>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <68>; + }; + + slv-cnoc-mnoc-mmss-cfg { + cell-id = <631>; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,slavep = <12>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <58>; + }; + + slv-cnoc-mnoc-cfg { + cell-id = <640>; + label = "slv-cnoc-mnoc-cfg"; + qcom,slavep = <20>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <66>; + }; + + slv-pnoc-cfg { + cell-id = <641>; + label = "slv-pnoc-cfg"; + qcom,slavep = <23>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <69>; + }; + + slv-snoc-mpu-cfg { + cell-id = <638>; + label = "slv-snoc-mpu-cfg"; + qcom,slavep = <21>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <67>; + }; + + slv-snoc-cfg { + cell-id = <642>; + label = "slv-snoc-cfg"; + qcom,slavep = <24>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <70>; + }; + + slv-ebi1-dll-cfg { + cell-id = <643>; + label = "slv-ebi1-dll-cfg"; + qcom,slavep = <25>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <71>; + }; + + slv-phy-apu-cfg { + cell-id = <644>; + label = "slv-phy-apu-cfg"; + qcom,slavep = <26>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <72>; + }; + + slv-ebi1-phy-cfg { + cell-id = <645>; + label = "slv-ebi1-phy-cfg"; + qcom,slavep = <27>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <73>; + }; + + slv-rpm { + cell-id = <534>; + label = "slv-rpm"; + qcom,slavep = <28>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <74>; + }; + + slv-service-cnoc { + cell-id = <646>; + label = "slv-service-cnoc"; + qcom,slavep = <30>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <76>; + }; + + }; + + msm-bimc@0xfc380000 { + compatible = "msm-bus-fabric"; + reg = <0xfc380000 0x0006A000>; + cell-id = <0>; + label = "msm_bimc"; + qcom,fabclk-dual = "mem_clk"; + qcom,fabclk-active = "mem_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <19200>; + qcom,hw-sel = "BIMC"; + qcom,rpm-en; + + coresight-id = <55>; + coresight-name = "coresight-bimc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <3>; + + mas-ampss-m0 { + cell-id = <1>; + label = "mas-ampss-m0"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Limiter"; + qcom,qport = <0>; + qcom,ws = <10000>; + qcom,mas-hw-id = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,mode-thresh = "Fixed"; + qcom,thresh = <2000000>; + qcom,dual-conf; + qcom,bimc,bw = <300000>; + qcom,bimc,gp = <5>; + qcom,bimc,thmp = <50>; + }; + + mas-ampss-m1 { + cell-id = <2>; + label = "mas-ampss-m1"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Limiter"; + qcom,qport = <1>; + qcom,ws = <10000>; + qcom,mas-hw-id = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,mode-thresh = "Fixed"; + qcom,thresh = <2000000>; + qcom,dual-conf; + qcom,bimc,bw = <300000>; + qcom,bimc,gp = <5>; + qcom,bimc,thmp = <50>; + }; + + mas-mss-proc { + cell-id = <65>; + label = "mas-mss-proc"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,hw-sel = "RPM"; + qcom,mas-hw-id = <1>; + }; + + fab-mmss-noc { + cell-id = <2048>; + label = "fab_mmss_noc"; + qcom,gateway; + qcom,masterp = <3 4>; + qcom,qport = <3 4>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <2>; + qcom,hw-sel = "BIMC"; + qcom,mode = "Bypass"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,slavep = <3>; + qcom,masterp = <5 6>; + qcom,qport = <5 6>; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <3>; + qcom,slv-hw-id = <2>; + qcom,mode = "Bypass"; + qcom,hw-sel = "RPM"; + }; + + slv-ebi-ch0 { + cell-id = <512>; + label = "slv-ebi-ch0"; + qcom,slavep = <0 1>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <0>; + qcom,mode = "Bypass"; + }; + + slv-ampss-l2 { + cell-id = <514>; + label = "slv-ampss-l2"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,slv-hw-id = <1>; + }; + }; + + msm-ocmem-vnoc@6144 { + compatible = "msm-bus-fabric"; + reg = <0x6144 0x2>; + cell-id = <6144>; + label = "msm-ocmem-vnoc"; + qcom,ntieredslaves = <0>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + qcom,virt; + + mas-v-ocmem-gfx3d { + cell-id = <89>; + label = "mas-v-ocmem-gfx3d"; + qcom,tier = <2>; + qcom,buswidth = <8>; + qcom,mas-hw-id = <55>; + }; + + slv-ocmem { + cell-id = <604>; + label = "slv-ocmem"; + qcom,slavep = <0 1>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,slv-hw-id = <18>; + qcom,slaveclk-dual = "ocmem_clk"; + qcom,slaveclk-active = "ocmem_a_clk"; + }; + + fab-snoc { + cell-id = <1024>; + label = "fab-snoc"; + qcom,gateway; + qcom,buswidth = <8>; + qcom,ws = <10000>; + qcom,mas-hw-id = <57>; + qcom,slv-hw-id = <80>; + }; + + fab-onoc { + cell-id = <3072>; + label = "fab-onoc"; + qcom,gateway; + qcom,buswidth = <16>; + qcom,ws = <10000>; + qcom,mas-hw-id = <56>; + qcom,slv-hw-id = <79>; + }; + + }; + + msm-ocmem-noc@fc470000 { + compatible = "msm-bus-fabric"; + reg = <0xfc470000 0x00004000>; + cell-id = <3072>; + label = "msm_ocmem_noc"; + qcom,fabclk-dual = "bus_clk"; + qcom,fabclk-active = "bus_a_clk"; + qcom,ntieredslaves = <0>; + qcom,qos-freq = <4800>; + qcom,hw-sel = "NoC"; + qcom,rpm-en; + + coresight-id = <51>; + coresight-name = "coresight-onoc"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <4>; + + fab-ocmem-vnoc { + cell-id = <6144>; + label = "fab-ocmem-vnoc"; + qcom,gateway; + qcom,buswidth = <16>; + qcom,mas-hw-id = <54>; + qcom,slv-hw-id = <78>; + }; + + mas-jpeg-ocmem { + cell-id = <66>; + label = "mas-jpeg-ocmem"; + qcom,masterp = <1>; + qcom,tier = <2>; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,qport = <0>; + qcom,mas-hw-id = <13>; + qcom,hw-sel = "NoC"; + }; + + mas-mdp-ocmem { + cell-id = <67>; + label = "mas-mdp-ocmem"; + qcom,masterp = <2>; + qcom,tier = <2>; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,mas-hw-id = <14>; + qcom,hw-sel = "NoC"; + }; + + mas-video-ocmem { + cell-id = <68>; + label = "mas-video-ocmem"; + qcom,masterp = <3 4>; + qcom,tier = <2>; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,qport = <2 3>; + qcom,mas-hw-id = <15>; + qcom,hw-sel = "NoC"; + }; + + mas-vfe-ocmem { + cell-id = <70>; + label = "mas-vfe-ocmem"; + qcom,masterp = <5>; + qcom,tier = <2>; + qcom,perm-mode = "Fixed"; + qcom,mode = "Fixed"; + qcom,qport = <4>; + qcom,mas-hw-id = <17>; + qcom,hw-sel = "NoC"; + qcom,prio-rd = <1>; + qcom,prio-wr = <1>; + }; + + mas-cnoc-onoc-cfg { + cell-id = <71>; + label = "mas-cnoc-onoc-cfg"; + qcom,masterp = <0>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,mas-hw-id = <12>; + qcom,hw-sel = "NoC"; + }; + + slv-service-onoc { + cell-id = <605>; + label = "slv-service-onoc"; + qcom,slavep = <2>; + qcom,tier = <2>; + qcom,buswidth = <16>; + qcom,slv-hw-id = <19>; + }; + }; +}; + + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-cdp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-cdp.dtsi new file mode 100644 index 000000000..4a9820dab --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-cdp.dtsi @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18 0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e 0x0>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "s5k3l1yx"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "imx135"; + qcom,actuator-src = <&actuator1>; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,sensor-type = <0>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c 0x0>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov2720"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90 0x0>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "mt9m114"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 92 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-dragonboard.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-dragonboard.dtsi new file mode 100644 index 000000000..e84a47d62 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-dragonboard.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18 0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e 0x0>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,actuator-src = <&actuator0>; + qcom,sensor-name = "s5k3l1yx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "imx135"; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c 0x0>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <180>; + qcom,sensor-name = "ov2720"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90 0x0>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "mt9m114"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 94 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-fluid.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-fluid.dtsi new file mode 100644 index 000000000..f61b83a45 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-fluid.dtsi @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <270>; + qcom,sensor-name = "s5k3l1yx"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,sensor-name = "imx135"; + qcom,actuator-src = <&actuator1>; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,sensor-type = <0>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov2720"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <1>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "mt9m114"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 92 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-liquid.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-liquid.dtsi new file mode 100644 index 000000000..cf968d208 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-liquid.dtsi @@ -0,0 +1,190 @@ + +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,actuator-src = <&actuator0>; + qcom,sensor-name = "s5k3l1yx"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs2>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "imx135"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs2>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,sensor-type = <0>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <180>; + qcom,sensor-name = "ov2720"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs2>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + qcom,sensor-name = "mt9m114"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs2>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 92 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-mtp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-mtp.dtsi new file mode 100644 index 000000000..6ad62137c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera-sensor-mtp.dtsi @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cci { + + actuator0: qcom,actuator@18 { + cell-index = <0>; + reg = <0x18>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@36 { + cell-index = <1>; + reg = <0x36>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + qcom,camera@6e { + compatible = "qcom,s5k3l1yx"; + reg = <0x6e>; + qcom,slave-id = <0x6e 0x0 0x3121>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,actuator-src = <&actuator0>; + qcom,led-flash-src = <&led_flash0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "s5k3l1yx"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + status = "ok"; + }; + + qcom,camera@20 { + compatible = "qcom,imx135"; + reg = <0x20>; + qcom,slave-id = <0x20 0x0016 0x0135>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,sensor-name = "imx135"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + cam_vaf-supply = <&pm8941_l23>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-type = <0 1 0 0>; + qcom,cam-vreg-min-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-max-voltage = <1225000 0 2850000 3000000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 15 0>, + <&msmgpio 90 0>, + <&msmgpio 89 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 30000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x1F>; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,sensor-type = <0>; + qcom,cci-master = <0>; + status = "ok"; + }; + + + qcom,camera@6c { + compatible = "qcom,ov2720"; + reg = <0x6c>; + qcom,slave-id = <0x6c 0x300A 0x2720>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,sensor-name = "ov2720"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 17 0>, + <&msmgpio 18 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x7>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <1>; + status = "ok"; + }; + + qcom,camera@90 { + compatible = "qcom,mt9m114"; + reg = <0x90>; + qcom,slave-id = <0x90 0x0 0x2481>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <0>; + qcom,sensor-name = "mt9m114"; + qcom,vdd-cx-supply = <&pm8841_s2>; + qcom,vdd-cx-name = "qcom,vdd-cx"; + cam_vdig-supply = <&pm8941_l3>; + cam_vana-supply = <&pm8941_l17>; + cam_vio-supply = <&pm8941_lvs3>; + qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio"; + qcom,cam-vreg-type = <0 0 1>; + qcom,cam-vreg-min-voltage = <1225000 2850000 0>; + qcom,cam-vreg-max-voltage = <1225000 2850000 0>; + qcom,cam-vreg-op-mode = <105000 80000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 16 0>, + <&msmgpio 92 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1"; + qcom,gpio-set-tbl-num = <1 1>; + qcom,gpio-set-tbl-flags = <0 2>; + qcom,gpio-set-tbl-delay = <1000 4000>; + qcom,csi-lane-assign = <0x4320>; + qcom,csi-lane-mask = <0x3>; + qcom,sensor-position = <1>; + qcom,sensor-mode = <1>; + qcom,cci-master = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera.dtsi new file mode 100644 index 000000000..786e9e381 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-camera.dtsi @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,msm-cam@fd8C0000 { + compatible = "qcom,msm-cam"; + reg = <0xfd8C0000 0x10000>; + reg-names = "msm-cam"; + }; + + qcom,csiphy@fda0ac00 { + cell-index = <0>; + compatible = "qcom,csiphy"; + reg = <0xfda0ac00 0x200>, + <0xfda00030 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + }; + + qcom,csiphy@fda0b000 { + cell-index = <1>; + compatible = "qcom,csiphy"; + reg = <0xfda0b000 0x200>, + <0xfda00038 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + }; + + qcom,csiphy@fda0b400 { + cell-index = <2>; + compatible = "qcom,csiphy"; + reg = <0xfda0b400 0x200>, + <0xfda00040 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 80 0>; + interrupt-names = "csiphy"; + }; + + qcom,csid@fda08000 { + cell-index = <0>; + compatible = "qcom,csid"; + reg = <0xfda08000 0x100>; + reg-names = "csid"; + interrupts = <0 51 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + }; + + qcom,csid@fda08400 { + cell-index = <1>; + compatible = "qcom,csid"; + reg = <0xfda08400 0x100>; + reg-names = "csid"; + interrupts = <0 52 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + }; + + qcom,csid@fda08800 { + cell-index = <2>; + compatible = "qcom,csid"; + reg = <0xfda08800 0x100>; + reg-names = "csid"; + interrupts = <0 53 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + }; + + qcom,csid@fda08C00 { + cell-index = <3>; + compatible = "qcom,csid"; + reg = <0xfda08C00 0x100>; + reg-names = "csid"; + interrupts = <0 54 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + }; + + qcom,ispif@fda0A000 { + cell-index = <0>; + compatible = "qcom,ispif"; + reg = <0xfda0A000 0x500>, + <0xfda00020 0x10>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 55 0>; + interrupt-names = "ispif"; + }; + + qcom,vfe@fda10000 { + cell-index = <0>; + compatible = "qcom,vfe40"; + reg = <0xfda10000 0x1000>, + <0xfda40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 57 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + }; + + qcom,vfe@fda14000 { + cell-index = <1>; + compatible = "qcom,vfe40"; + reg = <0xfda14000 0x1000>, + <0xfda40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 58 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + }; + + qcom,jpeg@fda1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0xfda1c000 0x400>; + reg-names = "jpeg"; + interrupts = <0 59 0>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + }; + + qcom,jpeg@fda20000 { + cell-index = <1>; + compatible = "qcom,jpeg"; + reg = <0xfda20000 0x400>; + reg-names = "jpeg"; + interrupts = <0 60 0>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + }; + + qcom,jpeg@fda24000 { + cell-index = <2>; + compatible = "qcom,jpeg"; + reg = <0xfda24000 0x400>; + reg-names = "jpeg"; + interrupts = <0 61 0>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + }; + + qcom,irqrouter@fda00000 { + cell-index = <0>; + compatible = "qcom,irqrouter"; + reg = <0xfda00000 0x100>; + reg-names = "irqrouter"; + }; + + qcom,cpp@fda04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xfda04000 0x100>, + <0xfda40000 0x200>, + <0xfda18000 0x008>; + reg-names = "cpp", "cpp_vbif", "cpp_hw"; + interrupts = <0 49 0>; + interrupt-names = "cpp"; + vdd-supply = <&gdsc_vfe>; + }; + + led_flash0: qcom,camera-led-flash { + cell-index = <0>; + compatible = "qcom,camera-led-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pm8941_flash0 &pm8941_flash1>; + }; + + cci: qcom,cci@fda0C000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xfda0C000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 50 0>; + interrupt-names = "cci"; + gpios = <&msmgpio 19 0>, + <&msmgpio 20 0>, + <&msmgpio 21 0>, + <&msmgpio 22 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + qcom,hw-thigh = <78>; + qcom,hw-tlow = <114>; + qcom,hw-tsu-sto = <28>; + qcom,hw-tsu-sta = <28>; + qcom,hw-thd-dat = <10>; + qcom,hw-thd-sta = <77>; + qcom,hw-tbuf = <118>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-cdp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-cdp.dtsi new file mode 100644 index 000000000..2a60df4f4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-cdp.dtsi @@ -0,0 +1,729 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-toshiba-720p-video.dtsi" +/include/ "dsi-panel-orise-720p-video.dtsi" +/include/ "msm8974-leds.dtsi" +/include/ "msm8974-camera-sensor-cdp.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_dsi_toshiba_720p_video { + status = "ok"; + qcom,cont-splash-enabled; + }; + + qcom,mdss_dsi_orise_720p_video { + status = "disable"; + }; + + qcom,hdmi_tx@fd922100 { + status = "ok"; + }; + + i2c@f9924000 { + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l18>; + vcc_i2c-supply = <&pm8941_lvs1>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 760 1424>; + atmel,display-coords = <0 0 720 1280>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x82>; + atmel,variant-id = <0x19>; + atmel,version = <0x10>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 15 01 00 03 0A 0C 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 03 + /* Object 8, Instance = 0 */ + 0F 00 0A 0A 00 00 0A 0A 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 18 0E 00 70 46 02 01 + 00 0A 03 31 04 05 0A 0A 90 05 + F8 02 05 F1 F1 0F 00 00 08 2D + 12 06 00 00 00 01 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 23, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 00 00 00 00 + /* Object 42, Instance = 0 */ + 33 1E 19 10 80 00 00 00 FF 00 + /* Object 46, Instance = 0 */ + 00 00 10 10 00 00 03 00 00 01 + /* Object 47, Instance = 0 */ + 08 0A 28 0A 02 0A 00 8C 00 20 + 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 00 00 00 18 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 01 2A 00 16 00 00 00 00 0B 01 + 02 03 04 08 00 00 08 10 18 05 + 00 0A 05 05 50 14 19 34 1A 7F + 00 00 00 00 00 00 00 00 00 30 + 05 02 00 01 00 05 00 00 00 00 + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <720>; + qcom,disp-maxy = <1280>; + qcom,panel-maxx = <760>; + qcom,panel-maxy = <1424>; + qcom,key-codes = <158 139 102 217>; + }; + + i2c@f9967000 { + isa1200@48 { + status = "okay"; + reg = <0x48>; + vcc_i2c-supply = <&pm8941_s3>; + compatible = "imagis,isa1200"; + label = "vibrator"; + imagis,chip-en; + imagis,smart-en; + imagis,need-pwm-clk; + imagis,ext-clk-en; + imagis,hap-en-gpio = <&msmgpio 86 0x00>; + imagis,max-timeout = <15000>; + imagis,pwm-div = <256>; + imagis,mode-ctrl = <2>; + imagis,regulator { + regulator-name = "vcc_i2c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-max-microamp = <9360>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@2 { + compatible = "micrel,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <94 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&pm8941_mpps 6 0>; + vdd-io-supply = <&spi_eth_vreg>; + vdd-phy-supply = <&spi_eth_vreg>; + }; + }; + + sound { + qcom,model = "msm8974-taiko-cdp-snd-card"; + qcom,hdmi-audio-rx; + qcom,us-euro-gpios = <&pm8941_gpios 20 0>; + qcom,cdc-micbias2-headset-only; + }; + + usb2_otg_sw: regulator-tpd4s214 { + compatible = "regulator-fixed"; + regulator-name = "usb2_otg_sw"; + gpio = <&pm8941_gpios 18 0>; + parent-supply = <&pm8941_boost>; + startup-delay-us = <17000>; + enable-active-high; + }; + + hsic_host: hsic@f9a00000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a00000 0x400>; + #address-cells = <0>; + interrupt-parent = <&hsic_host>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 136 0 + 1 &intc 0 148 0 + 2 &msmgpio 144 0x8>; + interrupt-names = "core_irq", "async_irq", "wakeup"; + HSIC_VDDCX-supply = <&pm8841_s2>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + hsic,strobe-gpio = <&msmgpio 144 0x00>; + hsic,data-gpio = <&msmgpio 145 0x00>; + hsic,resume-gpio = <&msmgpio 80 0x00>; + hsic,ignore-cal-pad-config; + hsic,strobe-pad-offset = <0x2050>; + hsic,data-pad-offset = <0x2054>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>; + }; + + wlan0: qca,wlan { + compatible = "qca,ar6004-hsic"; + qcom,msm-bus,name = "wlan"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>, + <85 512 40000 320000>, + <85 512 40000 480000>, + <85 512 40000 800000>; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <25>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <2>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + + qcom,leds@d900 { + status = "disabled"; + }; + + qcom,leds@da00 { + status = "disabled"; + }; + + qcom,leds@db00 { + status = "disabled"; + }; + + qcom,leds@dc00 { + status = "disabled"; + }; + + qcom,leds@dd00 { + status = "disabled"; + }; + + qcom,leds@de00 { + status = "disabled"; + }; + + qcom,leds@df00 { + status = "disabled"; + }; + + qcom,leds@e000 { + status = "disabled"; + }; + + qcom,leds@e100 { + status = "disabled"; + }; + }; +}; + +&sdcc1 { + status = "disabled"; +}; + +&sdcc2 { + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + wp-gpios = <&pm8941_gpios 29 0x1>; + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; + +/* Drive strength recommendations for clock line from hardware team is 10 mA. + * But since the driver has been been using the below values from the start + * without any problems, continue to use those. + */ +&sdcc1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdcc2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&uart7 { + status = "ok"; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; +}; + +&usb3 { + qcom,otg-capability; +}; + +&pm8941_chg { + status = "ok"; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c300 { /* GPIO 4 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <1>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <2>; + qcom,vin-sel = <2>; + qcom,out-strength = <2>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + /* usb2_otg_sw regulator enable */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS logic */ + qcom,invert = <0>; /* Output low initially */ + qcom,vin-sel = <2>; /* PM8941 S3 = 1.8 V */ + qcom,src-sel = <0>; /* Constant */ + qcom,out-strength = <2>; /* Medium drive strength */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,invert = <0>; /* Output low initially */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; + + gpio@d600 { /* GPIO 23 */ + }; + + gpio@d700 { /* GPIO 24 */ + }; + + gpio@d800 { /* GPIO 25 */ + }; + + gpio@d900 { /* GPIO 26 */ + }; + + gpio@da00 { /* GPIO 27 */ + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,pull = <0>; /* set to default pull */ + qcom,master-en = <1>; + qcom,vin-sel = <2>; /* select 1.8 V source */ + }; + + gpio@dd00 { /* GPIO 30 */ + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + }; + + gpio@e000 { /* GPIO 33 */ + }; + + gpio@e100 { /* GPIO 34 */ + }; + + gpio@e200 { /* GPIO 35 */ + }; + + gpio@e300 { /* GPIO 36 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <3>; /* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */ + qcom,master-en = <1>; + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + status = "disabled"; + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + /* SPI_ETH config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a500 { /* MPP 6 */ + /* SPI_ETH_RST config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; +}; + +/* CoreSight */ +&tpiu { + qcom,seta-gpios = <&msmgpio 31 0>, + <&msmgpio 32 0>, + <&msmgpio 33 0>, + <&msmgpio 34 0>, + <&msmgpio 35 0>, + <&msmgpio 36 0>, + <&msmgpio 37 0>, + <&msmgpio 38 0>, + <&msmgpio 39 0>, + <&msmgpio 40 0>, + <&msmgpio 41 0>, + <&msmgpio 42 0>, + <&msmgpio 43 0>, + <&msmgpio 44 0>, + <&msmgpio 45 0>, + <&msmgpio 46 0>, + <&msmgpio 47 0>, + <&msmgpio 48 0>; + qcom,seta-gpios-func = <4 4 4 3 4 4 4 3 4 3 5 5 5 5 4 4 5 5>; + qcom,seta-gpios-drv = <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>; + qcom,seta-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + qcom,seta-gpios-dir = <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>; + + qcom,setb-gpios = <&msmgpio 15 0>, + <&msmgpio 16 0>, + <&msmgpio 17 0>, + <&msmgpio 18 0>, + <&msmgpio 19 0>, + <&msmgpio 20 0>, + <&msmgpio 21 0>, + <&msmgpio 22 0>, + <&msmgpio 23 0>, + <&msmgpio 24 0>, + <&msmgpio 25 0>, + <&msmgpio 26 0>, + <&msmgpio 27 0>, + <&msmgpio 28 0>, + <&msmgpio 89 0>, + <&msmgpio 90 0>, + <&msmgpio 91 0>, + <&msmgpio 92 0>; + qcom,setb-gpios-func = <2 2 2 2 5 5 5 5 6 6 6 7 7 5 2 3 3 3>; + qcom,setb-gpios-drv = <7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7>; + qcom,setb-gpios-pull = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + qcom,setb-gpios-dir = <2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2>; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias1-ext-cap; + qcom,cdc-micbias3-ext-cap; + qcom,cdc-micbias4-ext-cap; + + /* If boot isn't available, vph_pwr_vreg can be used instead */ + cdc-vdd-spkdrv-supply = <&pm8941_boost>; + qcom,cdc-vdd-spkdrv-voltage = <5000000 5000000>; + qcom,cdc-vdd-spkdrv-current = <1250000>; + + qcom,cdc-on-demand-supplies = "cdc-vdd-spkdrv"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-clock.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-clock.dtsi new file mode 100644 index 000000000..bed5d70be --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-clock.dtsi @@ -0,0 +1,27 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + + qcom,pm8941@0 { + + pm8941_clkdiv1: clkdiv@5b00 { + qcom,cxo-div = <2>; + }; + + pm8941_clkdiv2: clkdiv@5c00 { + }; + + pm8941_clkdiv3: clkdiv@5d00 { + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-coresight.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-coresight.dtsi new file mode 100644 index 000000000..1610f1f43 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-coresight.dtsi @@ -0,0 +1,381 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@fc322000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc322000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + }; + + tpiu: tpiu@fc318000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc318000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + vdd-supply = <&pm8941_l21>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + }; + + replicator: replicator@fc31c000 { + compatible = "qcom,coresight-replicator"; + reg = <0xfc31c000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + }; + + tmc_etf: tmc@fc307000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc307000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + }; + + funnel_merg: funnel@fc31b000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31b000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc319000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc319000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + funnel_in1: funnel@fc31a000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31a000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <6>; + coresight-name = "coresight-funnel-in1"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <1>; + }; + + funnel_kpss: funnel@fc345000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc345000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <7>; + coresight-name = "coresight-funnel-kpss"; + coresight-nr-inports = <4>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <5>; + }; + + funnel_mmss: funnel@fc364000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc364000 0x1000>; + reg-names = "funnel-base"; + + + coresight-id = <8>; + coresight-name = "coresight-funnel-mmss"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <1>; + }; + + stm: stm@fc321000 { + compatible = "arm,coresight-stm"; + reg = <0xfc321000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <9>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc33c000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33c000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <10>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <0>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm1: etm@fc33d000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33d000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <11>; + coresight-name = "coresight-etm1"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <1>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm2: etm@fc33e000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33e000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <12>; + coresight-name = "coresight-etm2"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <2>; + + qcom,pc-save; + qcom,round-robin; + }; + + etm3: etm@fc33f000 { + compatible = "arm,coresight-etm"; + reg = <0xfc33f000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <13>; + coresight-name = "coresight-etm3"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_kpss>; + coresight-child-ports = <3>; + + qcom,pc-save; + qcom,round-robin; + }; + + csr: csr@fc302000 { + compatible = "qcom,coresight-csr"; + reg = <0xfc302000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <14>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <3>; + }; + + cti0: cti@fc308000 { + compatible = "arm,coresight-cti"; + reg = <0xfc308000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + }; + + cti1: cti@fc309000 { + compatible = "arm,coresight-cti"; + reg = <0xfc309000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + cti2: cti@fc30a000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30a000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + }; + + cti3: cti@fc30b000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30b000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <18>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + }; + + cti4: cti@fc30c000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30c000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <19>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + }; + + cti5: cti@fc30d000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30d000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <20>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + }; + + cti6: cti@fc30e000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30e000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <21>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + }; + + cti7: cti@fc30f000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30f000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <22>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + }; + + cti8: cti@fc310000 { + compatible = "arm,coresight-cti"; + reg = <0xfc310000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <23>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + }; + + cti_l2: cti@fc340000 { + compatible = "arm,coresight-cti"; + reg = <0xfc340000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <24>; + coresight-name = "coresight-cti-l2"; + coresight-nr-inports = <0>; + }; + + cti_cpu0: cti@fc341000 { + compatible = "arm,coresight-cti"; + reg = <0xfc341000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <25>; + coresight-name = "coresight-cti-cpu0"; + coresight-nr-inports = <0>; + }; + + cti_cpu1: cti@fc342000 { + compatible = "arm,coresight-cti"; + reg = <0xfc342000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <26>; + coresight-name = "coresight-cti-cpu1"; + coresight-nr-inports = <0>; + }; + + cti_cpu2: cti@fc343000 { + compatible = "arm,coresight-cti"; + reg = <0xfc343000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <27>; + coresight-name = "coresight-cti-cpu2"; + coresight-nr-inports = <0>; + }; + + cti_cpu3: cti@fc344000 { + compatible = "arm,coresight-cti"; + reg = <0xfc344000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <28>; + coresight-name = "coresight-cti-cpu3"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@fdf30018 { + compatible = "qcom,coresight-hwevent"; + reg = <0xfdf30018 0x80>, + <0xf9011080 0x80>, + <0xfd4ab160 0x80>; + reg-names = "mmss-mux", "apcs-mux", "ppss-mux"; + + coresight-id = <29>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + + qcom,hwevent-clks = "core_mmss_clk"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-fluid.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-fluid.dtsi new file mode 100644 index 000000000..a822af5fa --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-fluid.dtsi @@ -0,0 +1,667 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-toshiba-720p-video.dtsi" +/include/ "msm8974-camera-sensor-fluid.dtsi" +/include/ "msm8974-leds.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_dsi_toshiba_720p_video { + status = "ok"; + qcom,cont-splash-enabled; + }; + + qcom,hdmi_tx@fd922100 { + status = "ok"; + }; + + i2c@f9924000 { + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l18>; + vcc_i2c-supply = <&pm8941_lvs1>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 760 1424>; + atmel,display-coords = <0 0 720 1280>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x82>; + atmel,variant-id = <0x19>; + atmel,version = <0x10>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 15 01 00 03 0A 0C 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 03 + /* Object 8, Instance = 0 */ + 0F 00 0A 0A 00 00 0A 0A 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 18 0E 00 70 46 02 01 + 00 0A 03 31 04 05 0A 0A 90 05 + F8 02 05 F1 F1 0F 00 00 08 2D + 12 06 00 00 00 01 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 23, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 00 00 00 00 + /* Object 42, Instance = 0 */ + 33 1E 19 10 80 00 00 00 FF 00 + /* Object 46, Instance = 0 */ + 00 00 10 10 00 00 03 00 00 01 + /* Object 47, Instance = 0 */ + 08 0A 28 0A 02 0A 00 8C 00 20 + 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 00 00 00 18 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 01 2A 00 16 00 00 00 00 0B 01 + 02 03 04 08 00 00 08 10 18 05 + 00 0A 05 05 50 14 19 34 1A 7F + 00 00 00 00 00 00 00 00 00 30 + 05 02 00 01 00 05 00 00 00 00 + 00 00 00 00 + ]; + }; + }; + }; + + i2c@f9967000 { + sii8334@72 { + compatible = "qcom,mhl-sii8334"; + reg = <0x72>; + interrupt-parent = <&msmgpio>; + interrupts = <82 0x8>; + mhl-intr-gpio = <&msmgpio 82 0>; + mhl-pwr-gpio = <&msmgpio 12 0>; + mhl-rst-gpio = <&pm8941_mpps 8 0>; + avcc_18-supply = <&pm8941_l24>; + avcc_12-supply = <&pm8941_l2>; + smps3a-supply = <&pm8941_s3>; + vdda-supply = <&pm8941_l12>; + qcom,hdmi-tx-map = <&mdss_hdmi_tx>; + }; + + isa1200@48 { + status = "okay"; + reg = <0x48>; + vcc_i2c-supply = <&pm8941_s3>; + compatible = "imagis,isa1200"; + label = "vibrator"; + imagis,chip-en; + imagis,need-pwm-clk; + imagis,ext-clk-en; + imagis,hap-en-gpio = <&msmgpio 86 0x00>; + imagis,max-timeout = <15000>; + imagis,pwm-div = <256>; + imagis,mode-ctrl = <2>; + imagis,regulator { + regulator-name = "vcc_i2c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-max-microamp = <9360>; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <720>; + qcom,disp-maxy = <1280>; + qcom,panel-maxx = <760>; + qcom,panel-maxy = <1424>; + qcom,key-codes = <158 139 102 217>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@2 { + compatible = "micrel,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <94 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&pm8941_mpps 6 0>; + vdd-io-supply = <&spi_eth_vreg>; + vdd-phy-supply = <&spi_eth_vreg>; + }; + }; + + sound { + qcom,model = "msm8974-taiko-fluid-snd-card"; + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "AMIC1", "MIC BIAS1 Internal1", + "MIC BIAS1 Internal1", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC2", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic2", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4", + "DMIC5", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic5", + "DMIC6", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic6", + "Lineout_1 amp", "LINEOUT1", + "Lineout_3 amp", "LINEOUT3"; + + qcom,hdmi-audio-rx; + qcom,ext-ult-lo-amp-gpio = <&pm8941_gpios 6 0>; + qcom,cdc-micbias2-headset-only; + }; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias1-ext-cap; + qcom,cdc-micbias2-ext-cap; + qcom,cdc-micbias3-ext-cap; + qcom,cdc-micbias4-ext-cap; + + /* If boot isn't available, vph_pwr_vreg can be used instead */ + cdc-vdd-spkdrv-supply = <&pm8941_boost>; + qcom,cdc-vdd-spkdrv-voltage = <5000000 5000000>; + qcom,cdc-vdd-spkdrv-current = <1250000>; + + qcom,cdc-on-demand-supplies = "cdc-vdd-spkdrv"; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <25>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <2>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + + qcom,leds@d900 { + status = "disabled"; + }; + + qcom,leds@da00 { + status = "disabled"; + }; + + qcom,leds@db00 { + status = "disabled"; + }; + + qcom,leds@dc00 { + status = "disabled"; + }; + + qcom,leds@dd00 { + status = "disabled"; + }; + + qcom,leds@de00 { + status = "disabled"; + }; + + qcom,leds@df00 { + status = "disabled"; + }; + + qcom,leds@e000 { + status = "disabled"; + }; + + qcom,leds@e100 { + status = "disabled"; + }; + }; +}; + +&sdcc1 { + status = "disabled"; +}; + +&sdcc2 { + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; + +/* Drive strength recommendations for clock line from hardware team is 10 mA. + * But since the driver has been been using the below values from the start + * without any problems, continue to use those. + */ +&sdcc1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdcc2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&usb3 { + qcom,otg-capability; +}; + +&pm8941_bms { + status = "ok"; +}; + +&pm8941_chg { + status = "ok"; + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c300 { /* GPIO 4 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c500 { /* GPIO 6 */ + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@cc00 { /* GPIO 13 */ + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <1>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; + + gpio@d600 { /* GPIO 23 */ + }; + + gpio@d700 { /* GPIO 24 */ + }; + + gpio@d800 { /* GPIO 25 */ + }; + + gpio@d900 { /* GPIO 26 */ + }; + + gpio@da00 { /* GPIO 27 */ + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,pull = <0>; /* set to default pull */ + qcom,master-en = <1>; + qcom,vin-sel = <2>; /* select 1.8 V source */ + }; + + gpio@dd00 { /* GPIO 30 */ + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + }; + + gpio@e000 { /* GPIO 33 */ + }; + + gpio@e100 { /* GPIO 34 */ + }; + + gpio@e200 { /* GPIO 35 */ + }; + + gpio@e300 { /* GPIO 36 */ + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + status = "disabled"; + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + /* SPI_ETH_RST config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,pull = <0>; + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; +}; + +&spi_epm { + epm-adc@0 { + compatible = "cy,epm-adc-cy8c5568lti-114"; + reg = <0>; + interrupt-parent = <&msmgpio>; + spi-max-frequency = <960000>; + qcom,channels = <31>; + qcom,gain = <100 100 100 50 100 100 1 100 1 50 + 1 100 1 100 50 50 50 50 50 50 + 100 50 100 50 50 50 50 50 50 50 + 50>; + qcom,rsense = <2 2 2 200 20 2 1 2 1 30 + 1 10 1 30 50 30 500 30 100 30 + 100 500 20 200 1000 20 1000 1000 70 200 + 50>; + qcom,channel-type = <0x1540>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-gpu.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-gpu.dtsi new file mode 100644 index 000000000..06b9c187b --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-gpu.dtsi @@ -0,0 +1,185 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + msm_gpu: qcom,kgsl-3d0@fdb00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0xfdb00000 0x10000 + 0xfdb20000 0x10000>; + reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03030000>; + + qcom,initial-pwrlevel = <2>; + qcom,step-pwrlevel = <2>; + + qcom,idle-timeout = <8>; // + qcom,strtstp-sleepwake; + qcom,clk-map = <0x0000006>; //KGSL_CLK_CORE | KGSL_CLK_IFACE + + /* Bus Scale Settings */ + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, <89 604 0 0>, + <26 512 0 2200000>, <89 604 0 3000000>, + <26 512 0 4000000>, <89 604 0 3000000>, + <26 512 0 4000000>, <89 604 0 4500000>, + <26 512 0 6400000>, <89 604 0 4500000>, + <26 512 0 6400000>, <89 604 0 7600000>; + + /* GDSC oxili regulators */ + vddcx-supply = <&gdsc_oxili_cx>; + vdd-supply = <&gdsc_oxili_gx>; + + /* Power levels */ + + /* IOMMU Data */ + iommu = <&kgsl_iommu>; + + /* Trace bus */ + coresight-id = <67>; + coresight-name = "coresight-gfx"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_mmss>; + coresight-child-ports = <7>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <450000000>; + qcom,bus-freq = <5>; + qcom,io-fraction = <33>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,io-fraction = <66>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <3>; + qcom,io-fraction = <66>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <2>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <200000000>; + qcom,bus-freq = <1>; + qcom,io-fraction = <100>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,io-fraction = <0>; + }; + }; + + qcom,dcvs-core-info { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,dcvs-core-info"; + + qcom,num-cores = <1>; + qcom,sensors = <0>; + + qcom,core-core-type = <1>; + + qcom,algo-disable-pc-threshold = <0>; + qcom,algo-em-win-size-min-us = <100000>; + qcom,algo-em-win-size-max-us = <300000>; + qcom,algo-em-max-util-pct = <97>; + qcom,algo-group-id = <95>; + qcom,algo-max-freq-chg-time-us = <100000>; + qcom,algo-slack-mode-dynamic = <100000>; + qcom,algo-slack-weight-thresh-pct = <0>; + qcom,algo-slack-time-min-us = <39000>; + qcom,algo-slack-time-max-us = <39000>; + qcom,algo-ss-win-size-min-us = <1000000>; + qcom,algo-ss-win-size-max-us = <1000000>; + qcom,algo-ss-util-pct = <95>; + qcom,algo-ss-no-corr-below-freq = <0>; + + qcom,energy-active-coeff-a = <2492>; + qcom,energy-active-coeff-b = <0>; + qcom,energy-active-coeff-c = <0>; + qcom,energy-leakage-coeff-a = <11>; + qcom,energy-leakage-coeff-b = <157150>; + qcom,energy-leakage-coeff-c = <0>; + qcom,energy-leakage-coeff-d = <0>; + + qcom,power-current-temp = <25>; + qcom,power-num-freq = <4>; + + qcom,dcvs-freq@0 { + reg = <0>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@1 { + reg = <1>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@2 { + reg = <2>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <100>; + qcom,leakage-energy-offset = <0>; + }; + + qcom,dcvs-freq@3 { + reg = <3>; + qcom,freq = <0>; + qcom,voltage = <0>; + qcom,is_trans_level = <0>; + qcom,active-energy-offset = <844545>; + qcom,leakage-energy-offset = <0>; + }; + }; + + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-ion.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-ion.dtsi new file mode 100644 index 000000000..63f6d59c2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-ion.dtsi @@ -0,0 +1,59 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@8 { /* CP_MM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <8>; + qcom,heap-align = <0x1000>; + linux,contiguous-region = <&secure_mem>; + }; + + qcom,ion-heap@22 { /* adsp heap */ + compatible = "qcom,msm-ion-reserve"; + reg = <22>; + qcom,heap-align = <0x1000>; + linux,contiguous-region = <&adsp_mem>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + qcom,ion-heap@27 { /* QSECOM HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <27>; + linux,contiguous-region = <&qsecom_mem>; + }; + + qcom,ion-heap@28 { /* AUDIO HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <28>; + qcom,heap-align = <0x1000>; + qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */ + qcom,memory-reservation-size = <0x614000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-leds.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-leds.dtsi new file mode 100644 index 000000000..5e91f4597 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-leds.dtsi @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d000 { + status = "okay"; + qcom,rgb_0 { + label = "rgb"; + linux,name = "led:rgb_red"; + qcom,mode = "pwm"; + qcom,pwm-channel = <6>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + qcom,id = <3>; + linux,default-trigger = + "battery-charging"; + }; + + qcom,rgb_1 { + label = "rgb"; + linux,name = "led:rgb_green"; + qcom,mode = "pwm"; + qcom,pwm-channel = <5>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + qcom,id = <4>; + linux,default-trigger = "battery-full"; + }; + + qcom,rgb_2 { + label = "rgb"; + linux,name = "led:rgb_blue"; + qcom,mode = "pwm"; + qcom,pwm-channel = <4>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,id = <5>; + status = "disabled"; + }; + }; + + qcom,leds@d100 { + status = "disabled"; + }; + + qcom,leds@d200 { + status = "disabled"; + }; + + qcom,leds@d300 { + status = "okay"; + pm8941_flash0: qcom,flash_0 { + qcom,max-current = <1000>; + qcom,default-state = "off"; + qcom,headroom = <3>; + qcom,duration = <1280>; + qcom,clamp-curr = <200>; + qcom,startup-dly = <3>; + qcom,safety-timer; + label = "flash"; + linux,default-trigger = + "flash0_trigger"; + qcom,id = <1>; + linux,name = "led:flash_0"; + qcom,current = <625>; + }; + + pm8941_flash1: qcom,flash_1 { + qcom,max-current = <1000>; + qcom,default-state = "off"; + qcom,headroom = <3>; + qcom,duration = <1280>; + qcom,clamp-curr = <200>; + qcom,startup-dly = <3>; + qcom,safety-timer; + linux,default-trigger = + "flash1_trigger"; + label = "flash"; + qcom,id = <2>; + linux,name = "led:flash_1"; + qcom,current = <625>; + }; + + pm8941_torch: qcom,flash_torch { + qcom,max-current = <200>; + qcom,default-state = "off"; + qcom,headroom = <0>; + qcom,startup-dly = <1>; + linux,default-trigger = + "torch_trigger"; + label = "flash"; + qcom,id = <2>; + linux,name = "led:flash_torch"; + qcom,current = <200>; + qcom,torch-enable; + }; + }; + + qcom,leds@d400 { + status = "disabled"; + }; + + qcom,leds@d500 { + status = "disabled"; + }; + + qcom,leds@d600 { + status = "disabled"; + }; + + qcom,leds@d700 { + status = "disabled"; + }; + }; +}; + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-liquid.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-liquid.dtsi new file mode 100644 index 000000000..2dc52b6be --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-liquid.dtsi @@ -0,0 +1,893 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm8974-leds.dtsi" +/include/ "msm8974-camera-sensor-liquid.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_edp@fd923400 { + status = "ok"; + }; + + i2c@f9967000 { + battery@b { + compatible = "ti,bq28400-battery"; + reg = <0xb>; + ti,temp-cold = <2>; /* degree celsius */ + ti,temp-hot = <43>; /* degree celsius */ + }; + + charger@2b { + compatible = "summit,smb350-charger"; + reg = <0x2b>; /* 0x56/0x57 */ + summit,stat-gpio = <&pm8941_gpios 30 0x00>; + summit,chg-en-n-gpio = <&pm8941_gpios 10 0x00>; + summit,chg-susp-n-gpio = <&pm8941_gpios 13 0x00>; + summit,chg-current-ma = <1600>; + summit,term-current-ma = <300>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + home { + label = "home"; + gpios = <&pm8941_gpios 1 0x1>; + linux,input-type = <1>; + linux,code = <102>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 0x1>; + linux,input-type = <1>; + linux,code = <114>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + qcom,hdmi_tx@fd922100 { + status = "ok"; + + qcom,hdmi-tx-mux-sel = <&pm8841_mpps 3 0>; + qcom,hdmi-tx-mux-en = <&pm8841_mpps 4 0>; + }; + + drv2667_vreg: drv2667_vdd_vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_drv2667"; + }; + + i2c@f9967000 { + ti-drv2667@59 { + compatible = "ti,drv2667"; + reg = <0x59>; + vdd-supply = <&drv2667_vreg>; + vdd-i2c-supply = <&pm8941_s3>; + ti,label = "vibrator"; + ti,gain = <2>; + ti,idle-timeout-ms = <20>; + ti,max-runtime-ms = <15000>; + ti,mode = <2>; + ti,wav-seq = [ + /* wave form id */ + 01 + /* header size, start and stop bytes */ + 05 80 06 00 09 + /* repeat, amp, freq, duration, envelope */ + 01 ff 19 02 00]; + }; + }; + + i2c@f9924000 { + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l22>; + vcc_i2c-supply = <&pm8941_s3>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 1080 1920>; + atmel,display-coords = <0 0 1080 1920>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0xa2>; + atmel,variant-id = <0x00>; + atmel,version = <0x11>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 16 00 00 14 09 0C 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 7, Instance = 0 */ + FF FF 0A 03 + /* Object 8, Instance = 0 */ + 5F 00 14 14 00 00 00 01 00 00 + /* Object 9, Instance = 0 */ + 8F 00 00 20 34 00 87 3C 08 03 + 00 05 03 80 0A 14 14 0A 80 07 + 38 04 00 00 00 00 00 00 00 00 + 0F 0F 2E 33 02 00 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 04 00 + /* Object 24, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 54 6F F0 55 00 00 00 00 + 00 00 00 00 00 + /* Object 27, Instance = 0 */ + 00 00 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 14 14 14 14 + /* Object 42, Instance = 0 */ + 20 14 00 00 00 14 11 00 03 00 + /* Object 43, Instance = 0 */ + 09 00 01 01 91 00 80 00 00 00 + 00 00 + /* Object 46, Instance = 0 */ + 00 00 10 10 00 00 01 00 00 0F + 0A + /* Object 47, Instance = 0 */ + 00 14 23 02 05 1E 01 78 03 10 + 00 00 0C 00 00 00 00 00 00 00 + 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 02 00 01 30 13 14 14 14 15 15 + 15 15 15 15 15 16 16 16 16 16 + 16 16 16 16 16 15 14 14 14 14 + 15 14 14 14 14 13 00 00 01 02 + 05 05 00 00 00 00 00 00 00 00 + 00 + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 00 01 03 01 00 00 00 00 00 0A + 0F 14 19 23 05 00 0A 05 05 69 + 23 23 34 11 64 06 06 04 40 00 + 00 00 00 00 69 4B 02 00 00 80 + 0A 14 14 18 18 10 10 80 00 80 + 00 00 0F 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 63, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 + ]; + }; + atmel,cfg_2 { + atmel,family-id = <0xa2>; + atmel,variant-id = <0x00>; + atmel,version = <0x11>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 19 03 00 1E 05 0D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 C3 + /* Object 8, Instance = 0 */ + 41 00 14 14 00 00 00 01 00 00 + /* Object 9, Instance = 0 */ + 8F 00 00 20 34 00 87 4B 02 03 + 00 05 03 41 0A 14 14 0A 80 07 + 38 04 00 00 03 03 08 28 02 3C + 0F 0F 2E 33 01 00 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 04 00 + /* Object 24, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 54 6F F0 55 00 00 00 00 + 00 00 00 00 00 + /* Object 27, Instance = 0 */ + 00 00 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 14 14 14 14 + /* Object 42, Instance = 0 */ + 23 32 14 14 80 00 0A 00 05 05 + /* Object 43, Instance = 0 */ + 08 00 01 01 91 00 80 00 00 00 + 00 00 + /* Object 46, Instance = 0 */ + 00 00 18 18 00 00 01 00 00 0F + 0A + /* Object 47, Instance = 0 */ + 00 14 28 02 05 28 01 78 03 10 + 00 00 0C 00 00 00 00 00 00 00 + 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 01 00 00 30 13 14 14 14 15 15 + 15 15 15 15 15 16 16 16 16 16 + 16 16 16 16 16 15 14 14 14 14 + 15 14 14 14 14 13 03 20 03 01 + 0A 04 00 00 00 00 00 00 00 00 + 1A + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 00 03 00 07 02 00 00 00 00 00 + 0F 17 23 2D 05 00 05 03 03 69 + 14 14 34 11 64 06 06 04 40 00 + 00 00 00 00 69 3C 02 04 01 00 + 0A 14 14 03 03 03 03 00 00 00 + 00 64 1E 01 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 + /* Object 63, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 + /* Object 65, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 + /* Object 66, Instance = 0 */ + 00 00 00 00 00 + ]; + }; + }; + }; + + ext_5v: regulator-smb210 { + compatible = "regulator-fixed"; + regulator-name = "ext_5v"; + gpio = <&pm8941_mpps 2 0>; + startup-delay-us = <12000>; + enable-active-high; + }; + + ath_chip_pwd_l: ath_chip_reset { + compatible = "regulator-fixed"; + regulator-name = "ath_chip_pwd_l"; + gpio = <&pm8941_gpios 33 0>; + enable-active-high; + }; + + bt_ar3002 { + compatible = "qca,ar3002"; + qca,bt-reset-gpio = <&pm8941_gpios 34 0>; + qca,bt-chip-pwd-supply = <&ath_chip_pwd_l>; + qca,bt-vdd-io-supply = <&pm8941_s3>; + qca,bt-vdd-pa-supply = <&pm8941_l19>; + }; + + bt_ar3002_sleep { + compatible = "qca,ar3002_bluesleep"; + host-wake-gpio = <&msmgpio 79 0>; + ext-wake-gpio = <&msmgpio 51 0>; + interrupt-parent = <&msmgpio>; + interrupts = <79 2>; + interrupt-names = "host_wake"; + }; + + sound { + qcom,model = "msm8974-taiko-liquid-snd-card"; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "Lineout_1 amp", "LINEOUT1", + "Lineout_3 amp", "LINEOUT3", + "Lineout_2 amp", "LINEOUT2", + "Lineout_4 amp", "LINEOUT4", + "SPK_ultrasound amp", "SPK_OUT", + "AMIC1", "MIC BIAS4 External", + "MIC BIAS4 External", "Analog Mic4", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic6", + "AMIC6", "MIC BIAS1 External", + "MIC BIAS1 External", "Analog Mic7", + "DMIC1", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic1", + "DMIC2", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic2", + "DMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4", + "DMIC5", "MIC BIAS2 External", + "MIC BIAS2 External", "Digital Mic5", + "DMIC6", "MIC BIAS2 External", + "MIC BIAS2 External", "Digital Mic6"; + + qcom,ext-spk-amp-supply = <&ext_5v>; + qcom,ext-spk-amp-gpio = <&pm8841_mpps 1 0>; + qcom,dock-plug-det-irq = <&pm8841_mpps 2 0>; + qcom,ext-ult-spk-amp-gpio = <&pm8941_gpios 6 0>; + qcom,hdmi-audio-rx; + + qcom,prim-auxpcm-gpio-clk = <&msmgpio 74 0>; + qcom,prim-auxpcm-gpio-sync = <&msmgpio 75 0>; + qcom,prim-auxpcm-gpio-din = <&msmgpio 76 0>; + qcom,prim-auxpcm-gpio-dout = <&msmgpio 77 0>; + qcom,prim-auxpcm-gpio-set = "prim-gpio-tert"; + }; + + hsic_hub { + compatible = "qcom,hsic-smsc-hub"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + smsc,reset-gpio = <&pm8941_gpios 8 0x00>; + smsc,refclk-gpio = <&pm8941_gpios 16 0x00>; + smsc,int-gpio = <&msmgpio 50 0x00>; + hub_int-supply = <&pm8941_l10>; + hub_vbus-supply = <&ext_5v>; + + hsic_host: hsic@f9a00000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a00000 0x400>; + #address-cells = <0>; + interrupt-parent = <&hsic_host>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 136 0 + 1 &intc 0 148 0 + 2 &msmgpio 144 0x8>; + interrupt-names = "core_irq", "async_irq", "wakeup"; + HSIC_VDDCX-supply = <&pm8841_s2>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + hsic,strobe-gpio = <&msmgpio 144 0x00>; + hsic,data-gpio = <&msmgpio 145 0x00>; + hsic,ignore-cal-pad-config; + hsic,strobe-pad-offset = <0x2050>; + hsic,data-pad-offset = <0x2054>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>; + }; + }; + + wlan0: qca,wlan { + compatible = "qca,ar6004-hsic"; + qcom,msm-bus,name = "wlan"; + qca,wifi-chip-pwd-supply = <&ath_chip_pwd_l>; + qca,wifi-vddpa-supply = <&pm8941_l19>; + qca,wifi-vddio-supply = <&pm8941_l10>; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 160000>, + <85 512 40000 320000>, + <85 512 40000 480000>, + <85 512 40000 800000>; + }; + + wlan_sdio:qca,wlan_sdio { + compatible = "qca,ar6004-sdio"; + qcom,msm-bus,name = "wlan_sdio"; + qca,wifi-chip-pwd-supply = <&ath_chip_pwd_l>; + }; +}; + +&mdss_fb0 { + qcom,memory-reservation-size = <0x1000000>; /* size 16MB */ +}; + +&uart7 { + status = "ok"; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; +}; + +&usb3 { + qcom,otg-capability; +}; + +&pm8941_mvs2 { + parent-supply = <&ext_5v>; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <2>; + qcom,src-sel = <0>; + }; + + gpio@c500 { /* GPIO 6 */ + /* ULTRASOUND_EN_1 PA AB enable */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,pull = <4>; /* PULL_DOWN */ + qcom,vin-sel = <0>; /* VPH */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@c600 { /* GPIO 7 */ + }; + + gpio@c700 { /* GPIO 8 */ + /* HSIC_HUB-RESET */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,pull = <5>; /* PULL_NO */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,master-en = <1>; + }; + + gpio@c800 { /* GPIO 9 */ + }; + + gpio@c900 { /* GPIO 10 */ + /* SMB350-CHG-EN-N */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,pull = <5>; /* PULL_NO */ + qcom,vin-sel = <0>; /* VPH */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@ca00 { /* GPIO 11 */ + }; + + gpio@cb00 { /* GPIO 12 */ + }; + + gpio@cc00 { /* GPIO 13 */ + /* SMB350-CHG-SUSP-N */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,pull = <5>; /* PULL_NO */ + qcom,vin-sel = <0>; /* VPH */ + qcom,out-strength = <2>; /* STRENGTH_MED */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@cd00 { /* GPIO 14 */ + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <1>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + /* HSIC_HUB-INT_N */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <3>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + }; + + gpio@d600 { /* GPIO 23 */ + }; + + gpio@d700 { /* GPIO 24 */ + }; + + gpio@d800 { /* GPIO 25 */ + }; + + gpio@d900 { /* GPIO 26 */ + }; + + gpio@da00 { /* GPIO 27 */ + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,pull = <0>; /* set to default pull */ + qcom,master-en = <1>; + qcom,vin-sel = <2>; /* select 1.8 V source */ + }; + + gpio@dd00 { /* GPIO 30 */ + /* SMB350-STAT */ + qcom,mode = <0>; /* DIG_IN */ + qcom,pull = <5>; /* PULL_NO */ + qcom,vin-sel = <2>; /* S3 1.8V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + }; + + gpio@e000 { /* GPIO 33 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <1>; + qcom,master-en = <1>; + }; + + gpio@e100 { /* GPIO 34 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,invert = <0>; + qcom,master-en = <1>; + }; + + gpio@e200 { /* GPIO 35 */ + }; + + gpio@e300 { /* GPIO 36 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <3>; /* QPNP_PIN_OUT_STRENGTH_HIGH */ + qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */ + qcom,master-en = <1>; + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + status = "disabled"; + }; + + mpp@a100 { /* MPP 2 */ + /* ext_5v regulator enable */ + qcom,mode = <1>; /* Digital output */ + qcom,invert = <0>; /* Output low initially */ + qcom,vin-sel = <2>; /* PM8941 S3 = 1.8 V */ + qcom,src-sel = <0>; /* Constant */ + qcom,master-en = <1>; /* Enable MPP */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + /* SPI_ETH config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a500 { /* MPP 6 */ + /* SPI_ETH_RST config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a600 { /* MPP 7 */ + }; + + mpp@a700 { /* MPP 8 */ + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + /* CLASS_D_EN speakers PA */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* PNP_PIN_OUT_BUF_CMOS */ + qcom,vin-sel = <2>; /* S3A 1.8v */ + qcom,src-select = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a100 { /* MPP 2 */ + /* DOCK_PLUG_DET speakers+docking detect irq*/ + qcom,mode = <0>; /* DIG_IN */ + qcom,vin-sel = <2>; /* S3A 1.8v */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a200 { /* HDMI_MUX_SEL MPP 3*/ + status = "ok"; + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8841_S3A 1.8V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a300 { /* HDMI_MUX_EN MPP 4*/ + status = "ok"; + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <0>; /* PM8841_VPH 3.4V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; +}; + +&vph_pwr_vreg { + status = "ok"; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias1-ext-cap; + qcom,cdc-micbias2-ext-cap; + qcom,cdc-micbias3-ext-cap; + qcom,cdc-micbias4-ext-cap; + + /* + * Liquid has external spkrdrv supply. Give a dummy supply to + * make codec driver's happy. + */ + cdc-vdd-spkdrv-supply = <&vph_pwr_vreg>; + qcom,cdc-vdd-spkdrv-voltage = <0 0>; + qcom,cdc-vdd-spkdrv-current = <0>; + + qcom,cdc-on-demand-supplies = "cdc-vdd-spkdrv"; + }; +}; + +&spi_epm { + epm-adc@0 { + compatible = "cy,epm-adc-cy8c5568lti-114"; + reg = <0>; + interrupt-parent = <&msmgpio>; + spi-max-frequency = <960000>; + qcom,channels = <31>; + qcom,gain = <50 50 50 50 50 100 50 50 50 50 + 50 50 50 50 100 50 50 50 50 100 + 50 50 50 100 50 50 50 1 1 1 + 1>; + qcom,rsense = <40 10 10 25 10 1000 75 25 10 25 + 33 500 200 10 500 100 33 200 25 100 + 75 500 50 200 5 5 3 1 1 1 + 1>; + qcom,channel-type = <0xf0000000>; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d000 { + qcom,rgb_2 { + status = "ok"; + qcom,default-state = "on"; + qcom,turn-off-delay-ms = <1000>; + }; + }; + }; +}; + +&pm8941_chg { + status = "ok"; + otg-parent-supply = <&ext_5v>; + + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&sdcc1 { + status = "disabled"; +}; + +&sdcc2 { + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; + +/* Drive strength recommendations for clock line from hardware team is 10 mA. + * But since the driver has been been using the below values from the start + * without any problems, continue to use those. + */ +&sdcc1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdcc2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-mdss.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-mdss.dtsi new file mode 100644 index 000000000..6b8d600ed --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-mdss.dtsi @@ -0,0 +1,148 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_mdp: qcom,mdss_mdp@fd900000 { + compatible = "qcom,mdss_mdp"; + reg = <0xfd900000 0x22100>, + <0xfd924000 0x1000>; + reg-names = "mdp_phys", "vbif_phys"; + interrupts = <0 72 0>; + vdd-supply = <&gdsc_mdss>; + + qcom,max-clk-rate = <320000000>; + qcom,mdss-pipe-vig-off = <0x00001200 0x00001600 + 0x00001A00>; + qcom,mdss-pipe-rgb-off = <0x00001E00 0x00002200 + 0x00002600>; + qcom,mdss-pipe-dma-off = <0x00002A00 0x00002E00>; + qcom,mdss-pipe-vig-fetch-id = <1 4 7>; + qcom,mdss-pipe-rgb-fetch-id = <16 17 18>; + qcom,mdss-pipe-dma-fetch-id = <10 13>; + qcom,mdss-smp-data = <22 4096>; + + qcom,mdss-ctl-off = <0x00000600 0x00000700 0x00000800 + 0x00000900 0x0000A00>; + qcom,mdss-mixer-intf-off = <0x00003200 0x00003600 + 0x00003A00>; + qcom,mdss-mixer-wb-off = <0x00003E00 0x00004200>; + qcom,mdss-dspp-off = <0x00004600 0x00004A00 0x00004E00>; + qcom,mdss-wb-off = <0x00011100 0x00013100 0x00015100 + 0x00017100 0x00019100>; + qcom,mdss-intf-off = <0x00021100 0x00021300 + 0x00021500 0x00021700>; + + qcom,vbif-settings = <0x0004 0x00000001>, + <0x00D8 0x00000707>, + <0x00F0 0x00000030>, + <0x0124 0x00000001>, + <0x0178 0x00000FFF>, + <0x017C 0x0FFF0FFF>, + <0x0160 0x22222222>, + <0x0164 0x00002222>; + qcom,mdp-settings = <0x02E0 0x000000E9>, + <0x02E4 0x00000055>, + <0x03AC 0xC0000CCC>, + <0x03B4 0xC0000CCC>, + <0x03BC 0x00CCCCCC>, + <0x04A8 0x0CCCC0C0>, + <0x04B0 0xCCCCC0C0>, + <0x04B8 0xCCCCC000>; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x800000>; + }; + + mdss_fb1: qcom,mdss_fb_external { + cell-index = <1>; + compatible = "qcom,mdss-fb"; + }; + + mdss_fb2: qcom,mdss_fb_wfd { + cell-index = <2>; + compatible = "qcom,mdss-fb"; + }; + }; + + mdss_dsi0: qcom,mdss_dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0xfd922800 0x600>; + vdd-supply = <&pm8941_l22>; + vddio-supply = <&pm8941_l12>; + vdda-supply = <&pm8941_l2>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; + + mdss_dsi1: qcom,mdss_dsi@fd922e00 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->1"; + cell-index = <1>; + reg = <0xfd922e00 0x600>; + vdd-supply = <&pm8941_l22>; + vddio-supply = <&pm8941_l12>; + vdda-supply = <&pm8941_l2>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; + + mdss_hdmi_tx: qcom,hdmi_tx@fd922100 { + cell-index = <0>; + compatible = "qcom,hdmi-tx"; + reg = <0xfd922100 0x35C>, + <0xfd922500 0x7C>, + <0xfc4b8000 0x60F0>; + reg-names = "core_physical", "phy_physical", "qfprom_physical"; + + hpd-gdsc-supply = <&gdsc_mdss>; + hpd-5v-supply = <&pm8941_mvs2>; + core-vdda-supply = <&pm8941_l12>; + core-vcc-supply = <&pm8941_s3>; + qcom,hdmi-tx-supply-names = "hpd-gdsc", "hpd-5v", "core-vdda", "core-vcc"; + qcom,hdmi-tx-min-voltage-level = <0 0 1800000 1800000>; + qcom,hdmi-tx-max-voltage-level = <0 0 1800000 1800000>; + qcom,hdmi-tx-peak-current = <0 0 1800000 0>; + + qcom,hdmi-tx-cec = <&msmgpio 31 0>; + qcom,hdmi-tx-ddc-clk = <&msmgpio 32 0>; + qcom,hdmi-tx-ddc-data = <&msmgpio 33 0>; + qcom,hdmi-tx-hpd = <&msmgpio 34 0>; + qcom,mdss-fb-map = <&mdss_fb1>; + qcom,msm-hdmi-audio-rx { + compatible = "qcom,msm-hdmi-audio-codec-rx"; + }; + }; + + qcom,mdss_wb_panel { + compatible = "qcom,mdss_wb"; + qcom,mdss_pan_res = <1920 1080>; + qcom,mdss_pan_bpp = <24>; + qcom,mdss-fb-map = <&mdss_fb2>; + }; + + mdss_edp: qcom,mdss_edp@fd923400 { + compatible = "qcom,mdss-edp"; + reg = <0xfd923400 0x700>, + <0xfd8c2000 0x1000>; + reg-names = "edp_base", "mmss_cc_base"; + vdda-supply = <&pm8941_l12>; + gpio-panel-en = <&msmgpio 58 0>; + gpio-panel-pwm = <&pm8941_gpios 36 0>; + qcom,panel-lpg-channel = <7>; /* LPG Channel 8 */ + qcom,panel-pwm-period = <53>; + status = "disable"; + qcom,mdss-fb-map = <&mdss_fb0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-mtp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-mtp.dtsi new file mode 100644 index 000000000..e798fc0f9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-mtp.dtsi @@ -0,0 +1,705 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-toshiba-720p-video.dtsi" +/include/ "msm8974-camera-sensor-mtp.dtsi" +/include/ "msm8974-leds.dtsi" + +&soc { + serial@f991e000 { + status = "ok"; + }; + + qcom,mdss_dsi_toshiba_720p_video { + status = "ok"; + qcom,cont-splash-enabled; + }; + + qcom,hdmi_tx@fd922100 { + status = "disabled"; + }; + + i2c@f9924000 { + atmel_mxt_ts@4a { + compatible = "atmel,mxt-ts"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <61 0x2>; + vdd_ana-supply = <&pm8941_l18>; + vcc_i2c-supply = <&pm8941_lvs1>; + atmel,reset-gpio = <&msmgpio 60 0x00>; + atmel,irq-gpio = <&msmgpio 61 0x00>; + atmel,panel-coords = <0 0 760 1424>; + atmel,display-coords = <0 0 720 1280>; + atmel,i2c-pull-up; + atmel,no-force-update; + atmel,cfg_1 { + atmel,family-id = <0x82>; + atmel,variant-id = <0x19>; + atmel,version = <0x10>; + atmel,build = <0xaa>; + atmel,config = [ + /* Object 6, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 38, Instance = 0 */ + 15 01 00 03 0A 0C 00 00 + /* Object 7, Instance = 0 */ + 20 08 32 03 + /* Object 8, Instance = 0 */ + 0F 00 0A 0A 00 00 0A 0A 00 00 + /* Object 9, Instance = 0 */ + 83 00 00 18 0E 00 70 46 02 01 + 00 0A 03 31 04 05 0A 0A 90 05 + F8 02 05 F1 F1 0F 00 00 08 2D + 12 06 00 00 00 01 + /* Object 15, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 + /* Object 18, Instance = 0 */ + 00 00 + /* Object 19, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 23, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 25, Instance = 0 */ + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + /* Object 40, Instance = 0 */ + 00 00 00 00 00 + /* Object 42, Instance = 0 */ + 33 1E 19 10 80 00 00 00 FF 00 + /* Object 46, Instance = 0 */ + 00 00 10 10 00 00 03 00 00 01 + /* Object 47, Instance = 0 */ + 08 0A 28 0A 02 0A 00 8C 00 20 + 00 00 00 + /* Object 55, Instance = 0 */ + 00 00 00 00 00 00 + /* Object 56, Instance = 0 */ + 00 00 00 18 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 05 05 + 05 05 05 05 05 05 05 05 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 + /* Object 57, Instance = 0 */ + 00 00 00 + /* Object 61, Instance = 0 */ + 00 00 00 00 00 + /* Object 62, Instance = 0 */ + 01 2A 00 16 00 00 00 00 0B 01 + 02 03 04 08 00 00 08 10 18 05 + 00 0A 05 05 50 14 19 34 1A 7F + 00 00 00 00 00 00 00 00 00 30 + 05 02 00 01 00 05 00 00 00 00 + 00 00 00 00 + ]; + }; + }; + }; + + gen-vkeys { + compatible = "qcom,gen-vkeys"; + label = "atmel_mxt_ts"; + qcom,disp-maxx = <720>; + qcom,disp-maxy = <1280>; + qcom,panel-maxx = <760>; + qcom,panel-maxy = <1424>; + qcom,key-codes = <158 139 102 217>; + }; + + i2c@f9967000 { + isa1200@48 { + status = "okay"; + reg = <0x48>; + vcc_i2c-supply = <&pm8941_s3>; + compatible = "imagis,isa1200"; + label = "vibrator"; + imagis,chip-en; + imagis,need-pwm-clk; + imagis,ext-clk-en; + imagis,hap-en-gpio = <&msmgpio 86 0x00>; + imagis,max-timeout = <15000>; + imagis,pwm-div = <256>; + imagis,mode-ctrl = <2>; + imagis,regulator { + regulator-name = "vcc_i2c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-max-microamp = <9360>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera_focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + spi@f9923000 { + ethernet-switch@2 { + compatible = "micrel,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <94 0>; + spi-max-frequency = <4800000>; + rst-gpio = <&pm8941_mpps 6 0>; + vdd-io-supply = <&spi_eth_vreg>; + vdd-phy-supply = <&spi_eth_vreg>; + }; + }; + + sound { + qcom,model = "msm8974-taiko-mtp-snd-card"; + qcom,cdc-micbias2-headset-only; + }; +}; + +&spmi_bus { + qcom,pm8941@1 { + qcom,leds@d800 { + status = "okay"; + qcom,wled_0 { + label = "wled"; + linux,name = "wled:backlight"; + linux,default-trigger = "bkl-trigger"; + qcom,cs-out-en; + qcom,op-fdbck = <1>; + qcom,default-state = "on"; + qcom,max-current = <25>; + qcom,ctrl-delay-us = <0>; + qcom,boost-curr-lim = <3>; + qcom,cp-sel = <0>; + qcom,switch-freq = <2>; + qcom,ovp-val = <2>; + qcom,num-strings = <1>; + qcom,id = <0>; + }; + }; + + qcom,leds@d900 { + status = "disabled"; + }; + + qcom,leds@da00 { + status = "disabled"; + }; + + qcom,leds@db00 { + status = "disabled"; + }; + + qcom,leds@dc00 { + status = "disabled"; + }; + + qcom,leds@dd00 { + status = "disabled"; + }; + + qcom,leds@de00 { + status = "disabled"; + }; + + qcom,leds@df00 { + status = "disabled"; + }; + + qcom,leds@e000 { + status = "disabled"; + }; + + qcom,leds@e100 { + status = "disabled"; + }; + }; +}; + +&sdcc1 { + status = "disabled"; +}; + +&sdcc2 { + #address-cells = <0>; + interrupt-parent = <&sdcc2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + status = "disabled"; +}; + +&sdhc_1 { + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,nonremovable; + status = "ok"; +}; + +&sdhc_2 { + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &msmgpio 62 0x3>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&msmgpio 62 0x1>; + + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + status = "ok"; +}; + +/* Drive strength recommendations for clock line from hardware team is 10 mA. + * But since the driver has been been using the below values from the start + * without any problems, continue to use those. + */ +&sdcc1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdcc2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_1 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&sdhc_2 { + qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ +}; + +&usb_otg { + qcom,hsusb-otg-otg-control = <2>; +}; + +&uart7 { + status = "ok"; +}; + +&usb3 { + qcom,otg-capability; +}; + +&pm8941_bms { + status = "ok"; +}; + +&pm8941_chg { + status = "ok"; + qcom,charging-disabled; + + qcom,chgr@1000 { + status = "ok"; + }; + + qcom,buck@1100 { + status = "ok"; + }; + + qcom,bat-if@1200 { + status = "ok"; + }; + + qcom,usb-chgpth@1300 { + status = "ok"; + }; + + qcom,dc-chgpth@1400 { + status = "ok"; + }; + + qcom,boost@1500 { + status = "ok"; + }; + + qcom,chg-misc@1600 { + status = "ok"; + }; +}; + +&pm8941_gpios { + gpio@c000 { /* GPIO 1 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c100 { /* GPIO 2 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c200 { /* GPIO 3 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,vin-sel = <2>; + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@c300 { /* GPIO 4 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@c400 { /* GPIO 5 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@c500 { /* GPIO 6 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c600 { /* GPIO 7 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c700 { /* GPIO 8 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <0>; /* QPNP_PIN_PULL_UP_30 */ + qcom,master-en = <1>; + }; + + gpio@c800 { /* GPIO 9 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@c900 { /* GPIO 10 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@ca00 { /* GPIO 11 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@cb00 { /* GPIO 12 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@cd00 { /* GPIO 14 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@ce00 { /* GPIO 15 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <1>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + }; + + gpio@cf00 { /* GPIO 16 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <2>; + qcom,out-strength = <3>; + qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */ + qcom,master-en = <1>; + }; + + gpio@d000 { /* GPIO 17 */ + }; + + gpio@d100 { /* GPIO 18 */ + }; + + gpio@d200 { /* GPIO 19 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */ + qcom,pull = <5>; /* QPNP_PIN_PULL_NO */ + qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */ + qcom,master-en = <1>; + }; + + gpio@d300 { /* GPIO 20 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@d400 { /* GPIO 21 */ + }; + + gpio@d500 { /* GPIO 22 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@d600 { /* GPIO 23 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@d700 { /* GPIO 24 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@d800 { /* GPIO 25 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@d900 { /* GPIO 26 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@da00 { /* GPIO 27 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@db00 { /* GPIO 28 */ + }; + + gpio@dc00 { /* GPIO 29 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */ + qcom,master-en = <1>; + }; + + gpio@dd00 { /* GPIO 30 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@de00 { /* GPIO 31 */ + }; + + gpio@df00 { /* GPIO 32 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@e000 { /* GPIO 33 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@e100 { /* GPIO 34 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@e200 { /* GPIO 35 */ + qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */ + qcom,pull = <4>; /* QPNP_PIN_PULL_DN */ + qcom,master-en = <1>; + }; + + gpio@e300 { /* GPIO 36 */ + }; +}; + +&pm8941_mpps { + + mpp@a000 { /* MPP 1 */ + status = "disabled"; + }; + + mpp@a100 { /* MPP 2 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,master-en = <1>; + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + /* SPI_ETH_RST config */ + qcom,mode = <1>; /* DIG_OUT */ + qcom,output-type = <0>; /* CMOS */ + qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */ + qcom,src-sel = <0>; /* CONSTANT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,master-en = <1>; /* ENABLE MPP */ + }; + + mpp@a600 { /* MPP 7 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,master-en = <1>; + }; + + mpp@a700 { /* MPP 8 */ + qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */ + qcom,out-strength = <1>; /* QPNP_PIN_OUT_STRENGTH_LOW */ + qcom,master-en = <1>; + }; +}; + +&pm8841_mpps { + + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; +}; + +&slim_msm { + taiko_codec { + qcom,cdc-micbias1-ext-cap; + qcom,cdc-micbias2-ext-cap; + qcom,cdc-micbias4-ext-cap; + }; +}; + +&spi_epm { + epm-adc@0 { + compatible = "cy,epm-adc-cy8c5568lti-114"; + reg = <0>; + interrupt-parent = <&msmgpio>; + spi-max-frequency = <960000>; + qcom,channels = <31>; + qcom,gain = <100 100 100 50 100 100 1 100 1 50 + 1 100 1 100 50 50 50 50 50 50 + 100 50 100 50 50 50 50 50 50 50 + 50>; + qcom,rsense = <2 2 2 200 20 2 1 2 1 30 + 1 10 1 30 50 30 500 30 100 30 + 100 500 20 200 1000 20 1000 1000 70 200 + 50>; + qcom,channel-type = <0x1540>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-regulator.dtsi new file mode 100644 index 000000000..2114686eb --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-regulator.dtsi @@ -0,0 +1,568 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* QPNP controlled regulators: */ + +&spmi_bus { + + qcom,pm8941@1 { + + pm8941_boost: regulator@a000 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + qcom,enable-time = <500>; + status = "okay"; + }; + + pm8941_mvs1: regulator@8300 { + parent-supply = <&pm8941_chg_otg>; + qcom,enable-time = <1000>; + qcom,pull-down-enable = <1>; + interrupts = <0x1 0x83 0x2>; + interrupt-names = "ocp"; + qcom,ocp-enable = <1>; + qcom,ocp-max-retries = <10>; + qcom,ocp-retry-delay = <30>; + qcom,soft-start-enable = <1>; + qcom,vs-soft-start-strength = <0>; + qcom,hpm-enable = <1>; + qcom,auto-mode-enable = <0>; + status = "okay"; + }; + + pm8941_mvs2: regulator@8400 { + parent-supply = <&pm8941_boost>; + qcom,enable-time = <1000>; + qcom,pull-down-enable = <1>; + interrupts = <0x1 0x84 0x2>; + interrupt-names = "ocp"; + qcom,ocp-enable = <1>; + qcom,ocp-max-retries = <10>; + qcom,ocp-retry-delay = <30>; + qcom,soft-start-enable = <1>; + qcom,vs-soft-start-strength = <0>; + qcom,hpm-enable = <1>; + qcom,auto-mode-enable = <0>; + status = "okay"; + }; + }; +}; + +/* RPM controlled regulators: */ + +&rpm_bus { + rpm-regulator-smpb1 { + status = "okay"; + pm8841_s1: regulator-s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8841_s1_ao: regulator-s1-ao { + regulator-name = "8841_s1_ao"; + qcom,set = <1>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + compatible = "qcom,rpm-regulator-smd"; + }; + pm8841_s1_so: regulator-s1-so { + regulator-name = "8841_s1_so"; + qcom,set = <2>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <675000>; + status = "okay"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-smpb2 { + status = "okay"; + pm8841_s2: regulator-s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8841_s2_corner: regulator-s2-corner { + regulator-name = "8841_s2_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + compatible = "qcom,rpm-regulator-smd"; + qcom,consumer-supplies = "vdd_dig", ""; + }; + pm8841_s2_corner_ao: regulator-s2-corner-ao { + regulator-name = "8841_s2_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + compatible = "qcom,rpm-regulator-smd"; + }; + pm8841_s2_floor_corner: regulator-s2-floor-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8841_s2_floor_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-floor-corner; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-smpb3 { + status = "okay"; + pm8841_s3: regulator-s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1050000>; + status = "okay"; + }; + }; + + rpm-regulator-smpb4 { + status = "okay"; + pm8841_s4: regulator-s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + status = "okay"; + }; + pm8841_s4_corner: regulator-s4-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8841_s4_corner"; + qcom,set = <3>; + qcom,use-voltage-corner; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,init-voltage-corner = <3>; /* SVS SOC */ + }; + pm8841_s4_floor_corner: regulator-s4-floor-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8841_s4_floor_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-floor-corner; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-smpa1 { + status = "okay"; + pm8941_s1: regulator-s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa2 { + status = "okay"; + pm8941_s2: regulator-s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + qcom,init-voltage = <2150000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8941_s3: regulator-s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8941_l1: regulator-l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8941_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8941_l3: regulator-l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8941_l4: regulator-l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8941_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8941_l6: regulator-l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8941_l7: regulator-l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8941_l8: regulator-l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8941_l9: regulator-l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8941_l10: regulator-l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8941_l11: regulator-l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8941_l12: regulator-l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + pm8941_l12_ao: regulator-l12-ao { + regulator-name = "8941_l12_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + compatible = "qcom,rpm-regulator-smd"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8941_l13: regulator-l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8941_l14: regulator-l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8941_l15: regulator-l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8941_l16: regulator-l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <2700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8941_l17: regulator-l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8941_l18: regulator-l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8941_l19: regulator-l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + pm8941_l20: regulator-l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + pm8941_l21: regulator-l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8941_l22: regulator-l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + pm8941_l23: regulator-l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + pm8941_l24: regulator-l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-vsa1 { + status = "okay"; + pm8941_lvs1: regulator-lvs1 { + status = "okay"; + }; + }; + + rpm-regulator-vsa2 { + status = "okay"; + pm8941_lvs2: regulator-lvs2 { + status = "okay"; + }; + }; + + rpm-regulator-vsa3 { + status = "okay"; + pm8941_lvs3: regulator-lvs3 { + status = "okay"; + }; + }; +}; + +&soc { + krait_pdn: krait-pdn@f9011000 { + reg = <0xf9011000 0x1000>, + <0xfc4b80b0 8>; + reg-names = "apcs_gcc", "phase-scaling-efuse"; + compatible = "qcom,krait-pdn"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + qcom,pfm-threshold = <73>; + + krait0_vreg: regulator@f9088000 { + compatible = "qcom,krait-regulator"; + regulator-name = "krait0"; + reg = <0xf9088000 0x1000>, /* APCS_ALIAS0_KPSS_ACS */ + <0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */ + reg-names = "acs", "mdd"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,headroom-voltage = <150000>; + qcom,retention-voltage = <675000>; + qcom,ldo-default-voltage = <750000>; + qcom,ldo-threshold-voltage = <850000>; + qcom,ldo-delta-voltage = <50000>; + qcom,cpu-num = <0>; + }; + + krait1_vreg: regulator@f9098000 { + compatible = "qcom,krait-regulator"; + regulator-name = "krait1"; + reg = <0xf9098000 0x1000>, /* APCS_ALIAS1_KPSS_ACS */ + <0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */ + reg-names = "acs", "mdd"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,headroom-voltage = <150000>; + qcom,retention-voltage = <675000>; + qcom,ldo-default-voltage = <750000>; + qcom,ldo-threshold-voltage = <850000>; + qcom,ldo-delta-voltage = <50000>; + qcom,cpu-num = <1>; + }; + + krait2_vreg: regulator@f90a8000 { + compatible = "qcom,krait-regulator"; + regulator-name = "krait2"; + reg = <0xf90a8000 0x1000>, /* APCS_ALIAS2_KPSS_ACS */ + <0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */ + reg-names = "acs", "mdd"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,headroom-voltage = <150000>; + qcom,retention-voltage = <675000>; + qcom,ldo-default-voltage = <750000>; + qcom,ldo-threshold-voltage = <850000>; + qcom,ldo-delta-voltage = <50000>; + qcom,cpu-num = <2>; + }; + + krait3_vreg: regulator@f90b8000 { + compatible = "qcom,krait-regulator"; + regulator-name = "krait3"; + reg = <0xf90b8000 0x1000>, /* APCS_ALIAS3_KPSS_ACS */ + <0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */ + reg-names = "acs", "mdd"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,headroom-voltage = <150000>; + qcom,retention-voltage = <675000>; + qcom,ldo-default-voltage = <750000>; + qcom,ldo-threshold-voltage = <850000>; + qcom,ldo-delta-voltage = <50000>; + qcom,cpu-num = <3>; + }; + }; + + spi_eth_vreg: spi_eth_phy_vreg { + compatible = "regulator-fixed"; + regulator-name = "ethernet_phy"; + gpio = <&pm8941_mpps 5 0>; + enable-active-high; + }; + + /* + * vph_pwr_vreg represents the unregulated battery voltage supply + * VPH_PWR that is present whenever the device is powered on. + */ + vph_pwr_vreg: vph_pwr_vreg { + compatible = "regulator-fixed"; + status = "disabled"; + regulator-name = "vph_pwr"; + regulator-always-on; + }; +}; + +&pm8941_chg { + otg-parent-supply = <&pm8941_boost>; +}; + +&pm8941_chg_boost { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "8941_smbb_boost"; +}; + +&pm8941_chg_otg { + regulator-name = "8941_smbb_otg"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-rumi.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-rumi.dtsi new file mode 100644 index 000000000..c01a4e509 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-rumi.dtsi @@ -0,0 +1,146 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm8974-leds.dtsi" +/include/ "msm8974-camera-sensor-cdp.dtsi" + +&soc { + timer { + clock-frequency = <5000000>; + }; + + serial@f995e000 { + status = "ok"; + }; + + usb@f9a55000 { + status = "disable"; + }; + + qcom,sdcc@f9824000 { + qcom,clk-rates = <400000 19200000>; + }; + + qcom,sdcc@f98a4000 { + qcom,clk-rates = <400000 19200000>; + }; + + qcom,sps@f998000 { + status = "disable"; + }; + + spi@f9924000 { + status = "disable"; + }; + + spi@f9923000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 0>; + spi-max-frequency = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 3 0>, /* CLK */ + <&msmgpio 1 0>, /* MISO */ + <&msmgpio 0 0>; /* MOSI */ + cs-gpios = <&msmgpio 9 0>; + + ethernet-switch@2 { + compatible = "simtec,ks8851"; + reg = <2>; + interrupt-parent = <&msmgpio>; + interrupts = <90 0>; + spi-max-frequency = <5000000>; + }; + }; + + i2c@f9966000 { + status = "disable"; + }; + + i2c@f9967000 { + cell-index = <0>; + compatible = "qcom,i2c-qup"; + reg = <0Xf9967000 0x1000>; + reg-names = "qup_phys_addr"; + interrupts = <0 105 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + gpios = <&msmgpio 83 0>, /* DAT */ + <&msmgpio 84 0>; /* CLK */ + }; + + slim@fe12f000 { + status = "disable"; + }; + + qcom,mdss_dsi@fd922800 { + status = "disable"; + }; + + qcom,spmi@fc4c0000 { + status = "disable"; + }; + + qcom,ssusb@F9200000 { + status = "disable"; + }; + + qcom,lpass@fe200000 { + status = "disable"; + }; + + qcom,pronto@fb21b000 { + status = "disable"; + }; + + qcom,mss@fc880000 { + status = "disable"; + }; + + qcom,kgsl-3d0@fdb00000 { + status = "disabled"; + }; +}; + +&gdsc_venus { + status = "disabled"; +}; + +&gdsc_mdss { + status = "disabled"; +}; + +&gdsc_jpeg { + status = "disabled"; +}; + +&gdsc_vfe { + status = "disabled"; +}; + +&gdsc_oxili_gx { + status = "disabled"; +}; + +&gdsc_oxili_cx { + status = "disabled"; +}; + +&gdsc_usb_hsic { + status = "disabled"; +}; + +&rpm_bus { + rpm-standalone; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-sim.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-sim.dtsi new file mode 100644 index 000000000..24b8d18be --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-sim.dtsi @@ -0,0 +1,93 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "dsi-panel-sim-video.dtsi" +/include/ "msm8974-leds.dtsi" +/include/ "msm8974-camera-sensor-cdp.dtsi" + +&soc { + qcom,mdss_dsi@fd922800 { + qcom,mdss_dsi_sim_video { + status = "ok"; + }; + }; + + serial@f991f000 { + status = "ok"; + }; + + serial@f995e000 { + status = "ok"; + }; +}; + +&jpeg_iommu { + qcom,iommu-ctx@fda6c000 { + interrupts = <0 69 0>; + }; + + qcom,iommu-ctx@fda6d000 { + interrupts = <0 70 0>; + }; + + qcom,iommu-ctx@fda6e000 { + interrupts = <0 71 0>; + }; +}; + +&mdp_iommu { + qcom,iommu-ctx@fd930000 { + interrupts = <0 46 0>; + }; + + qcom,iommu-ctx@fd931000 { + interrupts = <0 47 0>; + }; +}; + +&venus_iommu { + qcom,iommu-ctx@fdc8c000 { + interrupts = <0 43 0>; + }; + + qcom,iommu-ctx@fdc8d000 { + interrupts = <0 42 0>; + }; + + qcom,iommu-ctx@fdc8e000 { + interrupts = <0 41 0>; + }; +}; + +&kgsl_iommu { + qcom,iommu-ctx@fdb18000 { + interrupts = <0 240 0>; + }; + + qcom,iommu-ctx@fdb19000 { + interrupts = <0 241 0>; + }; +}; + +&vfe_iommu { + qcom,iommu-ctx@fda4c000 { + interrupts = <0 64 0>; + }; + + qcom,iommu-ctx@fda4d000 { + interrupts = <0 65 0>; + }; + + qcom,iommu-ctx@fda4e000 { + interrupts = <0 66 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-smp2p.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-smp2p.dtsi new file mode 100644 index 000000000..3921a686a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-smp2p.dtsi @@ -0,0 +1,225 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-wcnss { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <4>; + qcom,irq-bitmask = <0x40000>; + interrupts = <0 143 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + /* SMP2P SSR Driver for inbound entry from lpass. */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* SMP2P SSR Driver for outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_4_in: qcom,smp2pgpio-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_in { + compatible = "qcom,smp2pgpio_test_smp2p_4_in"; + gpios = <&smp2pgpio_smp2p_4_in 0 0>; + }; + + smp2pgpio_smp2p_4_out: qcom,smp2pgpio-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_in: qcom,smp2pgpio-ssr-smp2p-4-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <4>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_4_out: qcom,smp2pgpio-ssr-smp2p-4-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_4_out { + compatible = "qcom,smp2pgpio_test_smp2p_4_out"; + gpios = <&smp2pgpio_smp2p_4_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-cdp.dts new file mode 100644 index 000000000..c3fd98d2b --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-cdp.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8974 CDP"; + compatible = "qcom,msm8974-cdp", "qcom,msm8974", "qcom,cdp"; + qcom,msm-id = <126 1 0>, + <185 1 0>, + <186 1 0>; +}; + +&ehci { + status = "ok"; + vbus-supply = <&usb2_otg_sw>; +}; + +&hsic_host { + qcom,phy-sof-workaround; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-fluid.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-fluid.dts new file mode 100644 index 000000000..2b96ecbd2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-fluid.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-fluid.dtsi" + +/ { + model = "Qualcomm MSM 8974 FLUID"; + compatible = "qcom,msm8974-fluid", "qcom,msm8974", "qcom,fluid"; + qcom,msm-id = <126 3 0>, + <185 3 0>, + <186 3 0>; + +}; + +&pm8941_chg { + qcom,charging-disabled; +}; + +&sdcc1 { + qcom,bus-width = <4>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-iommu-domains.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-iommu-domains.dtsi new file mode 100644 index 000000000..25fca2a54 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-iommu-domains.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,iommu-domains { + compatible = "qcom,iommu-domains"; + + venus_domain_ns: qcom,iommu-domain1 { + label = "venus_ns"; + qcom,iommu-contexts = <&venus_ns>; + qcom,virtual-addr-pool = <0x40000000 0x3f000000 + 0x7f000000 0x1000000>; + }; + + venus_domain_cp: qcom,iommu-domain2 { + label = "venus_cp"; + qcom,iommu-contexts = <&venus_cp>; + qcom,virtual-addr-pool = <0x1000000 0x3f000000>; + qcom,secure-domain; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-iommu.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-iommu.dtsi new file mode 100644 index 000000000..56369dce3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-iommu.dtsi @@ -0,0 +1,40 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm-iommu-v1.dtsi" + +&jpeg_iommu { + status = "ok"; + vdd-supply = <&gdsc_jpeg>; +}; + +&mdp_iommu { + status = "ok"; + vdd-supply = <&gdsc_mdss>; +}; + +&venus_iommu { + status = "ok"; + vdd-supply = <&gdsc_venus>; +}; + +&kgsl_iommu { + status = "ok"; + qcom,needs-alt-core-clk; + vdd-supply = <&gdsc_oxili_cx>; + qcom,alt-vdd-supply = <&gdsc_oxili_gx>; +}; + +&vfe_iommu { + status = "ok"; + vdd-supply = <&gdsc_vfe>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-liquid.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-liquid.dts new file mode 100644 index 000000000..29d6150ba --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-liquid.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-liquid.dtsi" + +/ { + model = "Qualcomm MSM 8974 LIQUID"; + compatible = "qcom,msm8974-liquid", "qcom,msm8974", "qcom,liquid"; + qcom,msm-id = <126 9 0>, + <185 9 0>, + <186 9 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-mtp.dts new file mode 100644 index 000000000..8cbcca05a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-mtp.dts @@ -0,0 +1,28 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8974 MTP"; + compatible = "qcom,msm8974-mtp", "qcom,msm8974", "qcom,mtp"; + qcom,msm-id = <126 8 0>, + <185 8 0>, + <186 8 0>; +}; + +&pm8941_chg { + qcom,charging-disabled; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-pm.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-pm.dtsi new file mode 100644 index 000000000..56a819ecc --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-pm.dtsi @@ -0,0 +1,456 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f9099000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,core-id = <1>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f90a9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,core-id = <2>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f90b9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,core-id = <3>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f9012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9012000 0x1000>; + qcom,core-id = <0xffff>; /* L2/APCS SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x20000400>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-pmic-data0 = <0x02030080>; + qcom,saw2-pmic-data1 = <0x00030000>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + qcom,saw2-spm-cmd-ret = [1f 00 20 03 22 00 0f]; + qcom,saw2-spm-cmd-gdhs = [00 20 32 42 07 44 22 50 02 32 50 0f]; + qcom,saw2-spm-cmd-pc = [00 10 32 b0 11 42 07 01 b0 12 44 + 50 02 32 50 0f]; + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x62706d73>; /* "smpb" */ + qcom,id = <0x02>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <6>; /* Super Turbo */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x62706d73>; /* "smpb" */ + qcom,id = <0x01>; + qcom,key = <0x7675>; /* "uv" */ + qcom,init-value = <1050000>; /* Super Turbo */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + + qcom,lpm-resources@3 { + reg = <0x3>; + qcom,name = "l2"; + qcom,local-resource-type; + qcom,init-value = "l2_cache_retention"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,use-qtimer; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <1>; + qcom,ss-power = <784>; + qcom,energy-overhead = <190000>; + qcom,time-overhead = <100>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "retention"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <75>; + qcom,ss-power = <735>; + qcom,energy-overhead = <77341>; + qcom,time-overhead = <105>; + }; + + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <95>; + qcom,ss-power = <725>; + qcom,energy-overhead = <99500>; + qcom,time-overhead = <130>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_gdhs"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <2000>; + qcom,ss-power = <138>; + qcom,energy-overhead = <1208400>; + qcom,time-overhead = <3200>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3000>; + qcom,ss-power = <110>; + qcom,energy-overhead = <1250300>; + qcom,time-overhead = <3500>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_gdhs"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <3000>; + qcom,ss-power = <68>; + qcom,energy-overhead = <1350200>; + qcom,time-overhead = <4000>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <10300>; + qcom,ss-power = <63>; + qcom,energy-overhead = <2128000>; + qcom,time-overhead = <18200>; + }; + + qcom,lpm-level@7 { + reg = <0x7>; + qcom,mode= "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,latency-us = <18000>; + qcom,ss-power = <10>; + qcom,energy-overhead = <3202600>; + qcom,time-overhead = <27000>; + }; + + qcom,lpm-level@8 { + reg = <0x8>; + qcom,mode= "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <675000>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <20000>; + qcom,ss-power = <2>; + qcom,energy-overhead = <4252000>; + qcom,time-overhead = <32000>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <2 216>, /* tsens_upper_lower_int */ + <47 165>, /* usb30_hs_phy_irq */ + <50 172>, /* usb1_hs_async_wakeup_irq */ + <53 104>, /* mdss_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_low */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr + + <0xff 188>, /* lpass_irq_out_apcs(0) */ + <0xff 189>, /* lpass_irq_out_apcs(1) */ + <0xff 190>, /* lpass_irq_out_apcs(2) */ + <0xff 191>, /* lpass_irq_out_apcs(3) */ + <0xff 192>, /* lpass_irq_out_apcs(4) */ + <0xff 193>, /* lpass_irq_out_apcs(5) */ + <0xff 194>, /* lpass_irq_out_apcs(6) */ + <0xff 195>, /* lpass_irq_out_apcs(7) */ + <0xff 196>, /* lpass_irq_out_apcs(8) */ + <0xff 197>, /* lpass_irq_out_apcs(9) */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <3 102>, + <4 1 >, + <5 5 >, + <6 9 >, + <7 18>, + <8 20>, + <9 24>, + <10 27>, + <11 28>, + <12 34>, + <13 35>, + <14 37>, + <15 42>, + <16 44>, + <17 46>, + <18 50>, + <19 54>, + <20 59>, + <21 61>, + <22 62>, + <23 64>, + <24 65>, + <25 66>, + <26 67>, + <27 68>, + <28 71>, + <29 72>, + <30 73>, + <31 74>, + <32 75>, + <33 77>, + <34 79>, + <35 80>, + <36 82>, + <37 86>, + <38 92>, + <39 93>, + <40 95>, + <41 144>; + }; + + qcom,pm-8x60@fe805664 { + compatible = "qcom,pm-8x60"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfe805664 0x40>; + qcom,pc-mode = "tz_l2_int"; + qcom,use-sync-timer; + }; + + qcom,cpu-sleep-status@f9088008 { + compatible = "qcom,cpu-sleep-status"; + reg = <0xf9088008 0x4>; + qcom,cpu-alias-addr = <0x10000>; + qcom,sleep-status-mask= <0x80000>; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-rumi.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-rumi.dts new file mode 100644 index 000000000..85aab17b1 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-rumi.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-rumi.dtsi" + +/ { + model = "Qualcomm MSM 8974 RUMI"; + compatible = "qcom,msm8974-rumi", "qcom,msm8974", "qcom,rumi"; + qcom,msm-id = <126 15 0>, + <185 15 0>, + <186 15 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-sim.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-sim.dts new file mode 100644 index 000000000..fc9858de7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1-sim.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v1.dtsi" +/include/ "msm8974-sim.dtsi" + +/ { + model = "Qualcomm MSM 8974 Simulator"; + compatible = "qcom,msm8974-sim", "qcom,msm8974", "qcom,sim"; + qcom,msm-id = <126 16 0>, + <185 16 0>, + <186 16 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1.dtsi new file mode 100644 index 000000000..caec2dc1b --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v1.dtsi @@ -0,0 +1,134 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8974.dtsi file. + */ + +/include/ "msm8974.dtsi" +/include/ "msm8974-v1-iommu.dtsi" +/include/ "msm8974-v1-iommu-domains.dtsi" +/include/ "msm8974-v1-pm.dtsi" + +&soc { + android_usb@fc42b0c8 { + compatible = "qcom,android-usb"; + reg = <0xfc42b0c8 0xc8>; + qcom,android-usb-swfi-latency = <1>; + }; + + qcom,msm-imem@fc42b000 { + compatible = "qcom,msm-imem"; + reg = <0xfc42b000 0x1000>; /* Address and size of IMEM */ + }; +}; + +&tsens { + qcom,calibration-less-mode; +}; + +/* I2C clock frequency overrides */ +&i2c_0 { + qcom,i2c-src-freq = <19200000>; +}; + +&i2c_2 { + qcom,i2c-src-freq = <19200000>; +}; + +/* CoreSight */ +&tmc_etr { + qcom,reset-flush-race; +}; + +&stm { + qcom,write-64bit; +}; + +&mdss_mdp { + qcom,mdss-pingpong-off = <0x00021B00 0x00021C00 0x00021D00>; +}; + +&msm_vidc { + qcom,vidc-cp-map = <0x1000000 0x3f000000>; + qcom,vidc-ns-map = <0x40000000 0x40000000>; + qcom,load-freq-tbl = <979200 410000000>, + <783360 410000000>, + <489600 266670000>, + <244800 133330000>; + qcom,reg-presets = <0x80004 0x1>, + <0x80178 0x00001FFF>, + <0x8017c 0x1FFF1FFF>, + <0x800b0 0x10101001>, + <0x800b4 0x10101010>, + <0x800b8 0x10101010>, + <0x800bc 0x00000010>, + <0x800c0 0x1010100f>, + <0x800c4 0x10101010>, + <0x800c8 0x10101010>, + <0x800cc 0x00000010>, + <0x800d0 0x00001010>, + <0x800d4 0x00001010>, + <0x800f0 0x00000030>, + <0x800d8 0x00000707>, + <0x800dc 0x00000707>, + <0x80124 0x00000001>, + <0xE0020 0x5555556>, + <0xE0024 0x0>; + qcom,bus-ports = <1>; + qcom,enc-ocmem-ab-ib = <0 0>, + <138200 1222000>, + <414700 1222000>, + <940000 2444000>, + <1880000 2444000>, + <3008000 3910400>, + <3760000 4888000>; + qcom,dec-ocmem-ab-ib = <0 0>, + <176900 1556640>, + <456200 1556640>, + <864800 1556640>, + <1729600 3113280>, + <2767360 4981248>, + <3459200 6226560>; + qcom,enc-ddr-ab-ib = <0 0>, + <60000 664950>, + <181000 664950>, + <403000 664950>, + <806000 1329900>, + <1289600 2127840>, + <161200 6400000>; + qcom,dec-ddr-ab-ib = <0 0>, + <110000 909000>, + <268000 909000>, + <505000 909000>, + <1010000 1818000>, + <1616000 2908800>, + <2020000 6400000>; + qcom,iommu-groups = <&venus_domain_ns &venus_domain_cp>; + qcom,iommu-group-buffer-types = <0xfff 0x1ff>; + qcom,buffer-type-tz-usage-table = <0x1 0x1>, + <0x1fe 0x2>; +}; + +&sfpb_spinlock { + status = "disable"; +}; + +&ldrex_spinlock { + status = "ok"; +}; + +&usb_otg { + qcom,hsusb-otg-pnoc-errata-fix; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-cdp.dts new file mode 100644 index 000000000..85d478b73 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-cdp.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v2.dtsi" +/include/ "msm8974-cdp.dtsi" + +/ { + model = "Qualcomm MSM 8974v2 CDP"; + compatible = "qcom,msm8974-cdp", "qcom,msm8974", "qcom,cdp"; + qcom,msm-id = <126 1 0x20000>, + <185 1 0x20000>, + <186 1 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-fluid.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-fluid.dts new file mode 100644 index 000000000..d83d13048 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-fluid.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v2.dtsi" +/include/ "msm8974-fluid.dtsi" + +/ { + model = "Qualcomm MSM 8974v2 FLUID"; + compatible = "qcom,msm8974-fluid", "qcom,msm8974", "qcom,fluid"; + qcom,msm-id = <126 3 0x20000>, + <185 3 0x20000>, + <186 3 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-iommu-domains.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-iommu-domains.dtsi new file mode 100644 index 000000000..01c94d0ec --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-iommu-domains.dtsi @@ -0,0 +1,45 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,iommu-domains { + compatible = "qcom,iommu-domains"; + + venus_domain_ns: qcom,iommu-domain1 { + label = "venus_ns"; + qcom,iommu-contexts = <&venus_ns>; + qcom,virtual-addr-pool = <0x5dc00000 0x7f000000 + 0xdcc00000 0x1000000>; + }; + + venus_domain_sec_bitstream: qcom,iommu-domain2 { + label = "venus_sec_bitstream"; + qcom,iommu-contexts = <&venus_sec_bitstream>; + qcom,virtual-addr-pool = <0x4b000000 0x12c00000>; + qcom,secure-domain; + }; + + venus_domain_sec_pixel: qcom,iommu-domain3 { + label = "venus_sec_pixel"; + qcom,iommu-contexts = <&venus_sec_pixel>; + qcom,virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-domain; + }; + + venus_domain_sec_non_pixel: qcom,iommu-domain4 { + label = "venus_sec_non_pixel"; + qcom,iommu-contexts = <&venus_sec_non_pixel>; + qcom,virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-domain; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-iommu.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-iommu.dtsi new file mode 100644 index 000000000..03f7e807e --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-iommu.dtsi @@ -0,0 +1,256 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm-iommu-v1.dtsi" + +&venus_iommu { + status = "ok"; + vdd-supply = <&gdsc_venus>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020 + 0x2024 + 0x2028 + 0x202c + 0x2030 + 0x2034 + 0x2038>; + + qcom,iommu-bfb-data = <0xFFFFFFFF + 0xFFFFFFFF + 0x00000004 + 0x00000008 + 0x00000000 + 0x00013205 + 0x00004000 + 0x00014020 + 0x0 + 0x94 + 0x114 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; + + venus_ns: qcom,iommu-ctx@fdc8c000 { + qcom,iommu-ctx-sids = <0 1 2 3 4 5 7>; + }; + + venus_sec_bitstream: qcom,iommu-ctx@fdc8d000 { + qcom,iommu-ctx-sids = <0x80 0x81 0x82 0x83 0x84>; + label = "venus_sec_bitstream"; + }; + + venus_sec_pixel: qcom,iommu-ctx@fdc8f000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc8f000 0x1000>; + interrupts = <0 42 0>, <0 43 0>; + qcom,iommu-ctx-sids = <0x85>; + label = "venus_sec_pixel"; + qcom,secure-context; + }; + + venus_sec_non_pixel: qcom,iommu-ctx@fdc90000 { + compatible = "qcom,msm-smmu-v1-ctx"; + reg = <0xfdc90000 0x1000>; + interrupts = <0 42 0>, <0 43 0>; + qcom,iommu-ctx-sids = <0x87 0xA0>; + label = "venus_sec_non_pixel"; + qcom,secure-context; + }; +}; + +&jpeg_iommu { + status = "ok"; + vdd-supply = <&gdsc_jpeg>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014>; + + qcom,iommu-bfb-data = <0x3FFF + 0x00000000 + 0x4 + 0x4 + 0x0 + 0x0 + 0x10 + 0x50 + 0x0 + 0x00002804 + 0x00009614 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&mdp_iommu { + status = "ok"; + vdd-supply = <&gdsc_mdss>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xFFFFF + 0x00000000 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00006800 + 0x00006221 + 0x00016231 + 0x0 + 0x34 + 0x74 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; + +&kgsl_iommu { + status = "ok"; + vdd-supply = <&gdsc_oxili_cx>; + qcom,alt-vdd-supply = <&gdsc_oxili_gx>; + qcom,iommu-enable-halt; + qcom,needs-alt-core-clk; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x20ac + 0x215c + 0x220c + 0x2314 + 0x2394 + 0x2414 + 0x2008>; + + qcom,iommu-bfb-data = <0x00000003 + 0x0 + 0x00000004 + 0x00000010 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000020 + 0x0 + 0x1 + 0x81 + 0x0>; +}; + +&vfe_iommu { + status = "ok"; + vdd-supply = <&gdsc_vfe>; + qcom,iommu-enable-halt; + + qcom,iommu-bfb-regs = <0x204c + 0x2050 + 0x2514 + 0x2540 + 0x256c + 0x2314 + 0x2394 + 0x2414 + 0x20ac + 0x215c + 0x220c + 0x2008 + 0x200c + 0x2010 + 0x2014 + 0x2018 + 0x201c + 0x2020>; + + qcom,iommu-bfb-data = <0xffffffff + 0x00000000 + 0x4 + 0x8 + 0x0 + 0x0 + 0x20 + 0x78 + 0x0 + 0x00003c08 + 0x0000b41e + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-liquid.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-liquid.dts new file mode 100644 index 000000000..53983dc1c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-liquid.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v2.dtsi" +/include/ "msm8974-liquid.dtsi" + +/ { + model = "Qualcomm MSM 8974v2 LIQUID"; + compatible = "qcom,msm8974-liquid", "qcom,msm8974", "qcom,liquid"; + qcom,msm-id = <126 9 0x20000>, + <185 9 0x20000>, + <186 9 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-mtp.dts new file mode 100644 index 000000000..792a78cbd --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-mtp.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm8974-v2.dtsi" +/include/ "msm8974-mtp.dtsi" + +/ { + model = "Qualcomm MSM 8974v2 MTP"; + compatible = "qcom,msm8974-mtp", "qcom,msm8974", "qcom,mtp"; + qcom,msm-id = <126 8 0x20000>, + <185 8 0x20000>, + <186 8 0x20000>; +}; + +&usb3 { + interrupt-parent = <&usb3>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0xffffffff>; + interrupt-map = <0x0 0 &intc 0 133 0 + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>; + interrupt-names = "hs_phy_irq", "pmic_id_irq"; + + qcom,misc-ref = <&pm8941_misc>; +}; + +&pm8941_chg { + qcom,bpd-detection = "bpd_thm"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-pm.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-pm.dtsi new file mode 100644 index 000000000..8a46724ae --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2-pm.dtsi @@ -0,0 +1,452 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9089000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9089000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f9099000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9099000 0x1000>; + qcom,core-id = <1>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f90a9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90a9000 0x1000>; + qcom,core-id = <2>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f90b9000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf90b9000 0x1000>; + qcom,core-id = <3>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x01>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [03 0b 0f]; + qcom,saw2-spm-cmd-ret = [42 1b 00 d0 c0 a0 90 03 d0 98 a2 c0 + 0b 00 42 1b 0f]; + qcom,saw2-spm-cmd-spc = [00 20 80 10 90 a0 b0 03 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + qcom,saw2-spm-cmd-pc = [00 20 80 10 90 a0 b0 07 3b 98 a2 b0 82 + 10 0b 30 06 26 30 0f]; + }; + + qcom,spm@f9012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9012000 0x1000>; + qcom,core-id = <0xffff>; /* L2/APCS SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-avs-ctl = <0>; + qcom,saw2-avs-hysteresis = <0>; + qcom,saw2-avs-limit = <0>; + qcom,saw2-avs-dly= <0>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-pmic-data0 = <0x02030080>; + qcom,saw2-pmic-data1 = <0x00030000>; + qcom,vctl-timeout-us = <50>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + qcom,saw2-spm-cmd-ret = [1f 00 03 00 0f]; + qcom,saw2-spm-cmd-gdhs = [00 32 42 07 44 50 02 32 50 0f]; + qcom,saw2-spm-cmd-pc = [00 32 b0 11 42 07 01 b0 44 + 50 02 32 50 0f]; + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x62706d73>; /* "smpb" */ + qcom,id = <0x02>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <6>; /* Super Turbo */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x62706d73>; /* "smpb" */ + qcom,id = <0x01>; + qcom,key = <0x7675>; /* "uv" */ + qcom,init-value = <1050000>; /* Super Turbo */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + + qcom,lpm-resources@3 { + reg = <0x3>; + qcom,name = "l2"; + qcom,local-resource-type; + qcom,init-value = "l2_cache_retention"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,use-qtimer; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <1>; + qcom,ss-power = <715>; + qcom,energy-overhead = <17700>; + qcom,time-overhead = <2>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "retention"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <35>; + qcom,ss-power = <542>; + qcom,energy-overhead = <34920>; + qcom,time-overhead = <40>; + }; + + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <300>; + qcom,ss-power = <476>; + qcom,energy-overhead = <225300>; + qcom,time-overhead = <350>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_gdhs"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <2817>; + qcom,ss-power = <163>; + qcom,energy-overhead = <1577736>; + qcom,time-overhead = <5067>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3922>; + qcom,ss-power = <83>; + qcom,energy-overhead = <2274420>; + qcom,time-overhead = <6605>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,latency-us = <4922>; + qcom,ss-power = <68>; + qcom,energy-overhead = <2568180>; + qcom,time-overhead = <8812>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode= "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* NORMAL */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,latency-us = <5890>; + qcom,ss-power = <60>; + qcom,energy-overhead = <2675900>; + qcom,time-overhead = <10140>; + }; + + qcom,lpm-level@7 { + reg = <0x7>; + qcom,mode= "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <675000>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <8500>; + qcom,ss-power = <18>; + qcom,energy-overhead = <3286600>; + qcom,time-overhead = <15760>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <2 216>, /* tsens_upper_lower_int */ + <47 165>, /* usb30_hs_phy_irq */ + <50 172>, /* usb1_hs_async_wakeup_irq */ + <53 104>, /* mdss_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_low */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr + + <0xff 188>, /* lpass_irq_out_apcs(0) */ + <0xff 189>, /* lpass_irq_out_apcs(1) */ + <0xff 190>, /* lpass_irq_out_apcs(2) */ + <0xff 191>, /* lpass_irq_out_apcs(3) */ + <0xff 192>, /* lpass_irq_out_apcs(4) */ + <0xff 193>, /* lpass_irq_out_apcs(5) */ + <0xff 194>, /* lpass_irq_out_apcs(6) */ + <0xff 195>, /* lpass_irq_out_apcs(7) */ + <0xff 196>, /* lpass_irq_out_apcs(8) */ + <0xff 197>, /* lpass_irq_out_apcs(9) */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <3 102>, + <4 1 >, + <5 5 >, + <6 9 >, + <7 18>, + <8 20>, + <9 24>, + <10 27>, + <11 28>, + <12 34>, + <13 35>, + <14 37>, + <15 42>, + <16 44>, + <17 46>, + <18 50>, + <19 54>, + <20 59>, + <21 61>, + <22 62>, + <23 64>, + <24 65>, + <25 66>, + <26 67>, + <27 68>, + <28 71>, + <29 72>, + <30 73>, + <31 74>, + <32 75>, + <33 77>, + <34 79>, + <35 80>, + <36 82>, + <37 86>, + <38 92>, + <39 93>, + <40 95>, + <41 144>; + }; + + qcom,pm-8x60@fe805664 { + compatible = "qcom,pm-8x60"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xfe805664 0x40>; + qcom,pc-mode = "tz_l2_int"; + qcom,use-sync-timer; + + qcom,pm-snoc-client { + compatible = "qcom,pm-snoc-client"; + qcom,msm-bus,name = "ocimem_snoc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <54 585 0 0>, + <54 585 0 800000>; + }; + }; + + qcom,cpu-sleep-status@f9088008{ + compatible = "qcom,cpu-sleep-status"; + reg = <0xf9088008 0x100>; + qcom,cpu-alias-addr = <0x10000>; + qcom,sleep-status-mask= <0x80000>; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2.dtsi new file mode 100644 index 000000000..96e78ac28 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974-v2.dtsi @@ -0,0 +1,138 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm8974.dtsi file. + */ + +/include/ "msm8974.dtsi" +/include/ "msm8974-v2-iommu.dtsi" +/include/ "msm8974-v2-iommu-domains.dtsi" +/include/ "msm8974-v2-pm.dtsi" + +&soc { + android_usb@fe8050c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8050c8 0xc8>; + qcom,android-usb-swfi-latency = <1>; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; +}; + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x03030001>; + + /* Updated bus bandwidth requirements */ + qcom,msm-bus,vectors-KBps = + /* Off */ + <26 512 0 0>, <89 604 0 0>, + /* SVS */ + <26 512 0 2400000>, <89 604 0 3000000>, + /* Nominal / SVS */ + <26 512 0 4656000>, <89 604 0 3000000>, + /* Nominal */ + <26 512 0 4656000>, <89 604 0 5120000>, + /* Turbo / Nominal */ + <26 512 0 7464000>, <89 604 0 5120000>, + /* Turbo */ + <26 512 0 7464000>, <89 604 0 6400000>; +}; + +&mdss_mdp { + qcom,vbif-settings = <0x0004 0x00000001>; + + qcom,mdss-wb-off = <0x00011100 0x00011500 + 0x00011900 0x00011D00 0x00012100>; + qcom,mdss-intf-off = <0x00012500 0x00012700 + 0x00012900 0x00012b00>; + qcom,mdss-pingpong-off = <0x00012D00 0x00012E00 0x00012F00>; + qcom,mdss-has-bwc; + qcom,mdss-has-decimation; + qcom,mdss-ad-off = <0x0013100 0x00013300>; +}; + +&mdss_hdmi_tx { + reg = <0xfd922100 0x370>, + <0xfd922500 0x7C>, + <0xfc4b8000 0x60F0>; + reg-names = "core_physical", "phy_physical", "qfprom_physical"; +}; + +&msm_vidc { + qcom,vidc-ns-map = <0x40000000 0x40000000>; + qcom,load-freq-tbl = <979200 465000000>, + <783360 465000000>, + <489600 266670000>, + <244800 133330000>; + qcom,reg-presets = <0x80004 0x1>, + <0x80070 0x11FFF>, + <0x80074 0xA4>, + <0x800A8 0x1FFF>, + <0x80124 0x3>, + <0xE0020 0x5555556>, + <0xE0024 0x0>; + qcom,bus-ports = <1>; + qcom,enc-ocmem-ab-ib = <0 0>, + <138000 1034000>, + <414000 1034000>, + <940000 1034000>, + <1880000 2068000>, + <3008000 3309000>, + <3760000 4136000>, + <4468000 2457000>; + qcom,dec-ocmem-ab-ib = <0 0>, + <176000 519000>, + <456000 519000>, + <864000 519000>, + <1728000 1038000>, + <2766000 1661000>, + <3456000 2076000>, + <3662000 2198000>; + qcom,enc-ddr-ab-ib = <0 0>, + <120000 302000>, + <364000 302000>, + <804000 302000>, + <1608000 604000>, + <2576000 967000>, + <4680000 1404000>, + <49880000 1496000>; + qcom,dec-ddr-ab-ib = <0 0>, + <208000 303000>, + <536000 303000>, + <1012000 303000>, + <2024000 606000>, + <3240000 970000>, + <4048000 1212000>, + <4264000 1279000>; + qcom,iommu-groups = <&venus_domain_ns &venus_domain_sec_bitstream + &venus_domain_sec_pixel &venus_domain_sec_non_pixel>; + qcom,iommu-group-buffer-types = <0xfff 0x91 0x42 0x120>; + qcom,buffer-type-tz-usage-table = <0x91 0x1>, + <0x42 0x2>, + <0x120 0x3>; +}; + +&krait_pdn { + qcom,use-phase-switching; +}; + +&tspp { + vdd_cx-supply = <&pm8841_s2_corner>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974.dtsi new file mode 100644 index 000000000..6f164912e --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm8974.dtsi @@ -0,0 +1,1745 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM 8974"; + compatible = "qcom,msm8974"; + interrupt-parent = <&intc>; + + aliases { + spi0 = &spi_0; + spi7 = &spi_7; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + sdhc3 = &sdhc_3; /* SDC3 SDIO slot */ + sdhc4 = &sdhc_4; /* SDC4 SDIO slot */ + + /* smdtty devices */ + smd1 = &smdtty_apps_fm; + smd2 = &smdtty_apps_riva_bt_acl; + smd3 = &smdtty_apps_riva_bt_cmd; + smd4 = &smdtty_mbalbridge; + smd5 = &smdtty_apps_riva_ant_cmd; + smd6 = &smdtty_apps_riva_ant_data; + smd7 = &smdtty_data1; + smd11 = &smdtty_data11; + smd21 = &smdtty_data21; + smd27 = &smdtty_gps_nmea; + smd36 = &smdtty_loopback; + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0x0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0x1>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0x2>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0x3>; + }; + }; + + memory { + secure_mem: secure_region { + linux,contiguous-region; + reg = <0 0xFC00000>; + label = "secure_mem"; + }; + + adsp_mem: adsp_region { + linux,contiguous-region; + reg = <0 0x2F00000>; + label = "adsp_mem"; + }; + + qsecom_mem: qsecom_region { + linux,contiguous-region; + reg = <0 0x1100000>; + label = "qseecom_mem"; + }; + + }; + + soc: soc { }; +}; + +/include/ "msm8974-camera.dtsi" +/include/ "msm8974-coresight.dtsi" +/include/ "msm-gdsc.dtsi" +/include/ "msm8974-ion.dtsi" +/include/ "msm8974-gpu.dtsi" +/include/ "msm8974-mdss.dtsi" +/include/ "msm8974-smp2p.dtsi" +/include/ "msm8974-bus.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@F9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <146>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + wcd9xxx_intc: wcd9xxx-irq { + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&msmgpio>; + interrupts = <72 0>; + interrupt-names = "cdc-int"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + + qcom,mpm2-sleep-counter@fc4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xfc4a3000 0x1000>; + clock-frequency = <32768>; + }; + + msm_vidc: qcom,vidc@fdc00000 { + compatible = "qcom,msm-vidc"; + reg = <0xfdc00000 0xff000>; + interrupts = <0 44 0>; + qcom,hfi = "venus"; + qcom,has-ocmem; + qcom,max-hw-load = <1224450>; /* 4k @ 30 + 1080p @ 30*/ + }; + + qcom,vidc { + compatible = "qcom,msm-vidc"; + qcom,hfi = "q6"; + qcom,max-hw-load = <108000>; /* 720p @ 30 */ + }; + + qcom,wfd { + compatible = "qcom,msm-wfd"; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + serial@f995e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf995e000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + }; + + serial@f991e000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991e000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + + qcom,msm-bus,name = "serial_uart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + }; + + usb_otg: usb@f9a55000 { + compatible = "qcom,hsusb-otg"; + status = "disabled"; + + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0 0 140 0>; + interrupt-names = "core_irq", "async_irq"; + HSUSB_VDDCX-supply = <&pm8841_s2_corner>; + HSUSB_1p8-supply = <&pm8941_l6>; + HSUSB_3p3-supply = <&pm8941_l24>; + qcom,vdd-voltage-level = <1 5 7>; + + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-phy-init-seq = <0x63 0x81 0xffffffff>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <1>; + qcom,hsusb-otg-disable-reset; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 60000 960000>; + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>, + <0xf9824800 0x100>, + <0xf9804000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 123 0>, <0 137 0>; + interrupt-names = "core_irq", "bam_irq"; + vdd-supply = <&pm8941_l20>; + vdd-io-supply = <&pm8941_s3>; + + qcom,vdd-always-on; + qcom,vdd-lpm-sup; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <800 500000>; + + qcom,vdd-io-always-on; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <250 154000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <8>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + qcom,msm-bus,name = "sdcc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1600 3200>, /* 400 KB/s*/ + <78 512 80000 160000>, /* 20 MB/s */ + <78 512 100000 200000>, /* 25 MB/s */ + <78 512 200000 400000>, /* 50 MB/s */ + <78 512 400000 800000>, /* 100 MB/s */ + <78 512 800000 1600000>, /* 200 MB/s */ + <78 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + qcom,dat1-mpm-int = <42>; + status = "disable"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>, + <0xf98a4800 0x100>, + <0xf9884000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + interrupts = <0 125 0>, <0 220 0>; + interrupt-names = "core_irq", "bam_irq"; + vdd-supply = <&pm8941_l21>; + vdd-io-supply = <&pm8941_l13>; + + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <9000 800000>; + + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <4>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + qcom,msm-bus,name = "sdcc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1600 3200>, /* 400 KB/s*/ + <81 512 80000 160000>, /* 20 MB/s */ + <81 512 100000 200000>, /* 25 MB/s */ + <81 512 200000 400000>, /* 50 MB/s */ + <81 512 400000 800000>, /* 100 MB/s */ + <81 512 800000 1600000>, /* 200 MB/s */ + <81 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + qcom,dat1-mpm-int = <44>; + status = "disable"; + }; + + sdcc3: qcom,sdcc@f9864000 { + cell-index = <3>; /* SDC3 SDIO slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9864000 0x800>, + <0xf9864800 0x100>, + <0xf9844000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + #address-cells = <0>; + interrupt-parent = <&sdcc3>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 127 0 + 1 &intc 0 223 0 + 2 &msmgpio 37 0x8>; + interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq"; + + gpios = <&msmgpio 40 0>, /* CLK */ + <&msmgpio 39 0>, /* CMD */ + <&msmgpio 38 0>, /* DATA0 */ + <&msmgpio 37 0>, /* DATA1 */ + <&msmgpio 36 0>, /* DATA2 */ + <&msmgpio 35 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>; + qcom,sup-voltages = <1800 1800>; + qcom,bus-width = <4>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50"; + + qcom,msm-bus,name = "sdcc3"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */ + <79 512 1600 3200>, /* 400 KB/s*/ + <79 512 80000 160000>, /* 20 MB/s */ + <79 512 100000 200000>, /* 25 MB/s */ + <79 512 200000 400000>, /* 50 MB/s */ + <79 512 400000 800000>, /* 100 MB/s */ + <79 512 800000 1600000>, /* 200 MB/s */ + <79 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdcc4: qcom,sdcc@f98e4000 { + cell-index = <4>; /* SDC4 SDIO slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98e4000 0x800>, + <0xf98e4800 0x100>, + <0xf98c4000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + #address-cells = <0>; + interrupt-parent = <&sdcc4>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 129 0 + 1 &intc 0 226 0 + 2 &msmgpio 95 0x8>; + interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq"; + + gpios = <&msmgpio 93 0>, /* CLK */ + <&msmgpio 91 0>, /* CMD */ + <&msmgpio 96 0>, /* DATA0 */ + <&msmgpio 95 0>, /* DATA1 */ + <&msmgpio 94 0>, /* DATA2 */ + <&msmgpio 92 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>; + qcom,sup-voltages = <1800 1800>; + qcom,bus-width = <4>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50"; + + qcom,msm-bus,name = "sdcc4"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <80 512 0 0>, /* No vote */ + <80 512 1600 3200>, /* 400 KB/s*/ + <80 512 80000 160000>, /* 20 MB/s */ + <80 512 100000 200000>, /* 25 MB/s */ + <80 512 200000 400000>, /* 50 MB/s */ + <80 512 400000 800000>, /* 100 MB/s */ + <80 512 800000 1600000>, /* 200 MB/s */ + <80 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdhc_1: sdhci@f9824900 { + qcom,bus-width = <8>; + compatible = "qcom,sdhci-msm"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,cpu-dma-latency-us = <200>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1600 3200>, /* 400 KB/s*/ + <78 512 80000 160000>, /* 20 MB/s */ + <78 512 100000 200000>, /* 25 MB/s */ + <78 512 200000 400000>, /* 50 MB/s */ + <78 512 400000 800000>, /* 100 MB/s */ + <78 512 800000 1600000>, /* 200 MB/s */ + <78 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <200>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1600 3200>, /* 400 KB/s*/ + <81 512 80000 160000>, /* 20 MB/s */ + <81 512 100000 200000>, /* 25 MB/s */ + <81 512 200000 400000>, /* 50 MB/s */ + <81 512 400000 800000>, /* 100 MB/s */ + <81 512 800000 1600000>, /* 200 MB/s */ + <81 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdhc_3: sdhci@f9864900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 127 0>, <0 224 0>; + interrupt-names = "hc_irq", "pwr_irq"; + gpios = <&msmgpio 40 0>, /* CLK */ + <&msmgpio 39 0>, /* CMD */ + <&msmgpio 38 0>, /* DATA0 */ + <&msmgpio 37 0>, /* DATA1 */ + <&msmgpio 36 0>, /* DATA2 */ + <&msmgpio 35 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <200>; + + qcom,msm-bus,name = "sdhc3"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */ + <79 512 1600 3200>, /* 400 KB/s*/ + <79 512 80000 160000>, /* 20 MB/s */ + <79 512 100000 200000>, /* 25 MB/s */ + <79 512 200000 400000>, /* 50 MB/s */ + <79 512 400000 800000>, /* 100 MB/s */ + <79 512 800000 1600000>, /* 200 MB/s */ + <79 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + sdhc_4: sdhci@f98e4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xf98e4900 0x11c>, <0xf98e4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 129 0>, <0 227 0>; + interrupt-names = "hc_irq", "pwr_irq"; + gpios = <&msmgpio 93 0>, /* CLK */ + <&msmgpio 91 0>, /* CMD */ + <&msmgpio 96 0>, /* DATA0 */ + <&msmgpio 95 0>, /* DATA1 */ + <&msmgpio 94 0>, /* DATA2 */ + <&msmgpio 92 0>; /* DATA3 */ + qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <200>; + + qcom,msm-bus,name = "sdhc4"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <80 512 0 0>, /* No vote */ + <80 512 1600 3200>, /* 400 KB/s*/ + <80 512 80000 160000>, /* 20 MB/s */ + <80 512 100000 200000>, /* 25 MB/s */ + <80 512 200000 400000>, /* 50 MB/s */ + <80 512 400000 800000>, /* 100 MB/s */ + <80 512 800000 1600000>, /* 200 MB/s */ + <80 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; + status = "disable"; + }; + + qcom,sps@f9980000 { + compatible = "qcom,msm_sps"; + reg = <0xf9984000 0x15000>, + <0xf9999000 0xb000>; + interrupts = <0 94 0>; + + qcom,bam-dma-res-pipes = <6>; + }; + + spi_7: spi_epm: spi@f9966000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9966000 0x1000>; + interrupts = <0 104 0>; + spi-max-frequency = <19200000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 56 0>, /* CLK */ + <&msmgpio 54 0>, /* MISO */ + <&msmgpio 53 0>; /* MOSI */ + cs-gpios = <&msmgpio 55 0>; + qcom,master-id = <84>; + }; + + tspp: msm_tspp@f99d8000 { + compatible = "qcom,msm_tspp"; + cell-index = <0>; + reg = <0xf99d8000 0x1000>, /* MSM_TSIF0_PHYS */ + <0xf99d9000 0x1000>, /* MSM_TSIF1_PHYS */ + <0xf99da000 0x1000>, /* MSM_TSPP_PHYS */ + <0xf99c4000 0x14000>; /* MSM_TSPP_BAM_PHYS */ + reg-names = "MSM_TSIF0_PHYS", + "MSM_TSIF1_PHYS", + "MSM_TSPP_PHYS", + "MSM_TSPP_BAM_PHYS"; + interrupts = <0 153 0>, /* TSIF_TSPP_IRQ */ + <0 151 0>, /* TSIF0_IRQ */ + <0 152 0>, /* TSIF1_IRQ */ + <0 154 0>; /* TSIF_BAM_IRQ */ + interrupt-names = "TSIF_TSPP_IRQ", + "TSIF0_IRQ", + "TSIF1_IRQ", + "TSIF_BAM_IRQ"; + qcom,tsif-pclk = "iface_clk"; + qcom,tsif-ref-clk = "ref_clk"; + gpios = <&msmgpio 89 0>, /* TSIF0 CLK */ + <&msmgpio 90 0>, /* TSIF0 EN */ + <&msmgpio 91 0>, /* TSIF0 DATA */ + <&msmgpio 92 0>, /* TSIF0 SYNC */ + <&msmgpio 93 0>, /* TSIF1 CLK */ + <&msmgpio 94 0>, /* TSIF1 EN */ + <&msmgpio 95 0>, /* TSIF1 DATA */ + <&msmgpio 96 0>; /* TSIF1 SYNC */ + qcom,gpio-names = "tsif_clk", + "tsif_en", + "tsif_data", + "tsif_sync", + "tsif_clk", + "tsif_en", + "tsif_data", + "tsif_sync"; + qcom,gpios-func = <1>; + + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only = <0>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <82 512 0 0>, /* No vote */ + <82 512 12288 24576>; /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ + }; + + slim_msm: slim@fe12f000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xfe12f000 0x35000>, + <0xfe104000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0 0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + + taiko_codec { + compatible = "qcom,taiko-slim-pgd"; + elemental-addr = [00 01 A0 00 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,cdc-reset-gpio = <&msmgpio 63 0>; + + cdc-vdd-buck-supply = <&pm8941_s2>; + qcom,cdc-vdd-buck-voltage = <2150000 2150000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-vdd-tx-h-supply = <&pm8941_s3>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8941_s3>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pm8941_s3>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-a-1p2v-supply = <&pm8941_l1>; + qcom,cdc-vdd-a-1p2v-voltage = <1225000 1225000>; + qcom,cdc-vdd-a-1p2v-current = <10000>; + + cdc-vddcx-1-supply = <&pm8941_l1>; + qcom,cdc-vddcx-1-voltage = <1225000 1225000>; + qcom,cdc-vddcx-1-current = <10000>; + + cdc-vddcx-2-supply = <&pm8941_l1>; + qcom,cdc-vddcx-2-voltage = <1225000 1225000>; + qcom,cdc-vddcx-2-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1", + "cdc-vdd-a-1p2v", + "cdc-vddcx-1", + "cdc-vddcx-2"; + + qcom,cdc-micbias-ldoh-v = <0x3>; + qcom,cdc-micbias-cfilt1-mv = <1800>; + qcom,cdc-micbias-cfilt2-mv = <2700>; + qcom,cdc-micbias-cfilt3-mv = <1800>; + qcom,cdc-micbias1-cfilt-sel = <0x0>; + qcom,cdc-micbias2-cfilt-sel = <0x1>; + qcom,cdc-micbias3-cfilt-sel = <0x2>; + qcom,cdc-micbias4-cfilt-sel = <0x2>; + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "taiko-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 00 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + }; + }; + + sound { + compatible = "qcom,msm8974-audio-taiko"; + qcom,model = "msm8974-taiko-snd-card"; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "LDO_H", "MCLK", + "AIF4 MAD", "MCLK", + "AMIC1", "MIC BIAS1 Internal1", + "MIC BIAS1 Internal1", "Handset Mic", + "AMIC2", "MIC BIAS2 External", + "MIC BIAS2 External", "Headset Mic", + "AMIC3", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2 External", + "MIC BIAS2 External", "ANCLeft Headset Mic", + "DMIC1", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic1", + "DMIC2", "MIC BIAS1 External", + "MIC BIAS1 External", "Digital Mic2", + "DMIC3", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic3", + "DMIC4", "MIC BIAS3 External", + "MIC BIAS3 External", "Digital Mic4", + "DMIC5", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic5", + "DMIC6", "MIC BIAS4 External", + "MIC BIAS4 External", "Digital Mic6"; + + qcom,cdc-mclk-gpios = <&pm8941_gpios 15 0>; + qcom,taiko-mclk-clk-freq = <9600000>; + qcom,prim-auxpcm-gpio-clk = <&msmgpio 65 0>; + qcom,prim-auxpcm-gpio-sync = <&msmgpio 66 0>; + qcom,prim-auxpcm-gpio-din = <&msmgpio 67 0>; + qcom,prim-auxpcm-gpio-dout = <&msmgpio 68 0>; + qcom,prim-auxpcm-gpio-set = "prim-gpio-prim"; + qcom,sec-auxpcm-gpio-clk = <&msmgpio 79 0>; + qcom,sec-auxpcm-gpio-sync = <&msmgpio 80 0>; + qcom,sec-auxpcm-gpio-din = <&msmgpio 81 0>; + qcom,sec-auxpcm-gpio-dout = <&msmgpio 82 0>; + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0 0 187 0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + i2c_0: i2c@f9967000 { /* BLSP#11 */ + cell-index = <0>; + compatible = "qcom,i2c-qup"; + reg = <0Xf9967000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 105 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <50000000>; + qcom,master-id = <84>; + }; + + i2c_1: i2c@f9923000 { + cell-index = <1>; + compatible = "qcom,i2c-qup"; + reg = <0xf9923000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 95 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <19200000>; + qcom,scl-gpio = <&msmgpio 3 0>; + qcom,sda-gpio = <&msmgpio 2 0>; + qcom,master-id = <86>; + status = "disabled"; + }; + + i2c_2: i2c@f9924000 { + cell-index = <2>; + compatible = "qcom,i2c-qup"; + reg = <0xf9924000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 96 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <100000>; + qcom,i2c-src-freq = <50000000>; + qcom,master-id = <86>; + }; + + spi_0: spi@f9923000 { + compatible = "qcom,spi-qup-v2"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 0>; + spi-max-frequency = <19200000>; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&msmgpio 3 0>, /* CLK */ + <&msmgpio 1 0>, /* MISO */ + <&msmgpio 0 0>; /* MOSI */ + cs-gpios = <&msmgpio 9 0>; + qcom,master-id = <86>; + }; + + qcom,acpuclk@f9000000 { + compatible = "qcom,acpuclk-8974"; + krait0-supply = <&krait0_vreg>; + krait1-supply = <&krait1_vreg>; + krait2-supply = <&krait2_vreg>; + krait3-supply = <&krait3_vreg>; + krait0_mem-supply = <&pm8841_s1_ao>; + krait1_mem-supply = <&pm8841_s1_ao>; + krait2_mem-supply = <&pm8841_s1_ao>; + krait3_mem-supply = <&pm8841_s1_ao>; + krait0_dig-supply = <&pm8841_s2_corner_ao>; + krait1_dig-supply = <&pm8841_s2_corner_ao>; + krait2_dig-supply = <&pm8841_s2_corner_ao>; + krait3_dig-supply = <&pm8841_s2_corner_ao>; + krait0_hfpll-supply = <&pm8941_l12_ao>; + krait1_hfpll-supply = <&pm8941_l12_ao>; + krait2_hfpll-supply = <&pm8941_l12_ao>; + krait3_hfpll-supply = <&pm8941_l12_ao>; + l2_hfpll-supply = <&pm8941_l12_ao>; + }; + + usb3: qcom,ssusb@f9200000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xf9200000 0xfc000>, + <0xfd4ab000 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupts = <0 133 0>; + interrupt-names = "hs_phy_irq"; + ssusb_vdd_dig-supply = <&pm8841_s2_corner>; + SSUSB_1p8-supply = <&pm8941_l6>; + hsusb_vdd_dig-supply = <&pm8841_s2_corner>; + HSUSB_1p8-supply = <&pm8941_l6>; + HSUSB_3p3-supply = <&pm8941_l24>; + vbus_dwc3-supply = <&pm8941_mvs1>; + qcom,dwc-usb3-msm-dbm-eps = <4>; + qcom,vdd-voltage-level = <1 5 7>; + qcom,dwc-hsphy-init = <0x00D195A4>; + + qcom,msm-bus,name = "usb3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <61 512 0 0>, + <61 512 240000 960000>; + dwc3@f9200000 { + compatible = "synopsys,dwc3"; + reg = <0xf9200000 0xfc000>; + interrupt-parent = <&intc>; + interrupts = <0 131 0>, <0 179 0>; + interrupt-names = "irq", "otg_irq"; + tx-fifo-resize; + }; + }; + + ehci: qcom,ehci-host@f9a55000 { + compatible = "qcom,ehci-host"; + status = "disabled"; + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0>, <0 140 0>; + interrupt-names = "core_irq", "async_irq"; + HSUSB_VDDCX-supply = <&pm8841_s2>; + HSUSB_1p8-supply = <&pm8941_l6>; + HSUSB_3p3-supply = <&pm8941_l24>; + qcom,usb2-enable-hsphy2; + qcom,usb2-power-budget = <500>; + }; + + gdsc_oxili_gx: qcom,gdsc@fd8c4024 { + parent-supply = <&pm8841_s4_corner>; + }; + + qcom,lpass@fe200000 { + compatible = "qcom,pil-q6v5-lpass"; + reg = <0xfe200000 0x00100>, + <0xfd485100 0x00010>, + <0xfc4016c0 0x00004>; + reg-names = "qdsp6_base", "halt_base", "restart_reg"; + vdd_cx-supply = <&pm8841_s2_corner>; + interrupts = <0 162 1>; + + qcom,firmware-name = "adsp"; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + }; + + qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + }; + + qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + qcom,msm-pcm-lpa { + compatible = "qcom,msm-pcm-lpa"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + }; + + qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + qcom,msm-dai-q6-hdmi { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <8>; + }; + + qcom,msm-lsm-client { + compatible = "qcom,msm-lsm-client"; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + qcom,msm-dai-q6-sb-0-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16384>; + }; + + qcom,msm-dai-q6-sb-0-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16385>; + }; + + qcom,msm-dai-q6-sb-1-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16386>; + }; + + qcom,msm-dai-q6-sb-1-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16387>; + }; + + qcom,msm-dai-q6-sb-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16388>; + }; + + qcom,msm-dai-q6-sb-2-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16389>; + }; + + qcom,msm-dai-q6-sb-3-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16390>; + }; + + qcom,msm-dai-q6-sb-3-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16391>; + }; + + qcom,msm-dai-q6-sb-4-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16392>; + }; + + qcom,msm-dai-q6-sb-4-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16393>; + }; + + qcom,msm-dai-q6-sb-5-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16395>; + }; + + qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + qcom,msm-auxpcm { + compatible = "qcom,msm-auxpcm-resource"; + qcom,msm-cpudai-auxpcm-clk = "pcm_clk"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-slot = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + + qcom,msm-prim-auxpcm-rx { + qcom,msm-auxpcm-dev-id = <4106>; + compatible = "qcom,msm-auxpcm-dev"; + }; + + qcom,msm-prim-auxpcm-tx { + qcom,msm-auxpcm-dev-id = <4107>; + compatible = "qcom,msm-auxpcm-dev"; + }; + + qcom,msm-sec-auxpcm-rx { + qcom,msm-auxpcm-dev-id = <4108>; + compatible = "qcom,msm-auxpcm-dev"; + }; + + qcom,msm-sec-auxpcm-tx { + qcom,msm-auxpcm-dev-id = <4109>; + compatible = "qcom,msm-auxpcm-dev"; + }; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + qcom,msm-dai-q6-mi2s-quat { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <3>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <2>; + }; + }; + + qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + qcom,msm-ocmem-audio { + compatible = "qcom,msm-ocmem-audio"; + qcom,msm-bus,name = "audio-ocmem"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <11 604 0 0>, + <11 604 32506 32506>; + }; + + qcom,msm-adsp-sensors { + compatible = "qcom,msm-adsp-sensors"; + qcom,src-id = <11>; + qcom,dst-id = <604>; + qcom,ab = <32505856>; + qcom,ib = <32505856>; + }; + + qcom,mss@fc880000 { + compatible = "qcom,pil-q6v5-mss"; + reg = <0xfc880000 0x100>, + <0xfd485000 0x400>, + <0xfc820000 0x020>, + <0xfc401680 0x004>; + reg-names = "qdsp6_base", "halt_base", "rmb_base", + "restart_reg"; + + interrupts = <0 24 1>; + vdd_mss-supply = <&pm8841_s3>; + vdd_cx-supply = <&pm8841_s2_corner>; + vdd_mx-supply = <&pm8841_s1>; + vdd_pll-supply = <&pm8941_l12>; + qcom,vdd_pll = <1800000>; + qcom,firmware-name = "mba"; + qcom,pil-self-auth; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + qcom,pronto@fb21b000 { + compatible = "qcom,pil-pronto"; + reg = <0xfb21b000 0x3000>, + <0xfc401700 0x4>, + <0xfd485300 0xc>; + reg-names = "pmu_base", "clk_base", "halt_base"; + interrupts = <0 149 1>; + vdd_pronto_pll-supply = <&pm8941_l12>; + + qcom,firmware-name = "wcnss"; + + /* GPIO inputs from wcnss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>; + + /* GPIO output to wcnss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>; + }; + + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + + qcom,wcnss-wlan@fb000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xfb000000 0x280000>, + <0xf9011008 0x04>; + reg-names = "wcnss_mmio", "wcnss_fiq"; + interrupts = <0 145 0 0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8841_s1>; + qcom,pronto-vddcx-supply = <&pm8841_s2>; + qcom,pronto-vddpx-supply = <&pm8941_s3>; + qcom,iris-vddxo-supply = <&pm8941_l6>; + qcom,iris-vddrfa-supply = <&pm8941_l11>; + qcom,iris-vddpa-supply = <&pm8941_l19>; + qcom,iris-vdddig-supply = <&pm8941_l3>; + + gpios = <&msmgpio 36 0>, <&msmgpio 37 0>, <&msmgpio 38 0>, <&msmgpio 39 0>, <&msmgpio 40 0>; + qcom,has-48mhz-xo; + qcom,has-pronto-hw; + }; + + qcom,ocmem@fdd00000 { + compatible = "qcom,msm-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfdd02000 0x2000>, + <0xfe039000 0x400>, + <0xfec00000 0x180000>; + reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical"; + interrupts = <0 76 0 0 77 0>; + interrupt-names = "ocmem_irq", "dm_irq"; + qcom,ocmem-num-regions = <0x3>; + qcom,ocmem-num-macros = <0x18>; + qcom,resource-type = <0x706d636f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xfec00000 0x180000>; + + partition@0 { + reg = <0x0 0x100000>; + qcom,ocmem-part-name = "graphics"; + qcom,ocmem-part-min = <0x80000>; + }; + + partition@80000 { + reg = <0x100000 0x80000>; + qcom,ocmem-part-name = "lp_audio"; + qcom,ocmem-part-min = <0x80000>; + }; + + partition@100000 { + reg = <0x100000 0x80000>; + qcom,ocmem-part-name = "video"; + qcom,ocmem-part-min = <0x55000>; + }; + + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,msm-rng@f9bff000 { + compatible = "qcom,msm-rng"; + reg = <0xf9bff000 0x200>; + }; + + qseecom: qcom,qseecom@7f00000 { + compatible = "qcom,qseecom"; + reg = <0x7f00000 0x500000>; + reg-names = "secapp-region"; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,hlos-ce-hw-instance = <1>; + qcom,qsee-ce-hw-instance = <0>; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>, + <55 512 3936000 393600>, + <55 512 3936000 393600>; + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + }; + + qcom,tz-log@fe805720 { + compatible = "qcom,tz-log"; + reg = <0xfe805720 0x1000>; + }; + + qcom,venus@fdce0000 { + compatible = "qcom,pil-venus"; + reg = <0xfdce0000 0x4000>, + <0xfdc80000 0x400>; + reg-names = "wrapper_base", "vbif_base"; + vdd-supply = <&gdsc_venus>; + + qcom,firmware-name = "venus"; + }; + + qcom,cache_erp@f9012000 { + reg = <0xf9012000 0x80>, + <0xf9089000 0x80>, + <0xf9099000 0x80>, + <0xf90a9000 0x80>, + <0xf90b9000 0x80>, + <0xf9088000 0x40>, + <0xf9098000 0x40>, + <0xf90a8000 0x40>, + <0xf90b8000 0x40>; + + reg-names = "l2_saw", + "krait0_saw", + "krait1_saw", + "krait2_saw", + "krait3_saw", + "krait0_acs", + "krait1_acs", + "krait2_acs", + "krait3_acs"; + + compatible = "qcom,cache_erp"; + interrupts = <1 9 0>, <0 2 0>; + interrupt-names = "l1_irq", "l2_irq"; + }; + + qcom,cache_dump { + compatible = "qcom,cache_dump"; + qcom,l1-dump-size = <0x100000>; + qcom,l2-dump-size = <0x500000>; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x600000>; /* 6M EBI1 buffer */ + }; + + tsens: tsens@fc4a8000 { + compatible = "qcom,msm-tsens"; + reg = <0xfc4a8000 0x2000>, + <0xfc4b8000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + qcom,sensors = <11>; + qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200 + 3200 3200>; + qcom,calib-mode = "fuse_map1"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + qcom,msm-contig-mem { + compatible = "qcom,msm-contig-mem"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x280000>; /* 2.5M EBI1 buffer */ + }; + + qcom,qcedev@fd440000 { + compatible = "qcom,qcedev"; + reg = <0xfd440000 0x20000>, + <0xfd444000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 236 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <1>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <56 512 0 0>, + <56 512 3936000 393600>; + }; + + qcom,qcrypto@fd444000 { + compatible = "qcom,qcrypto"; + reg = <0xfd440000 0x20000>, + <0xfd444000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 236 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <1>; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <56 512 0 0>, + <56 512 3936000 393600>; + }; + + qcom,usbbam@f9304000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xf9304000 0x5000>, + <0xf9a44000 0x11000>, + <0xf92f880c 0x4>; + reg-names = "ssusb", "hsusb", "qscratch_ram1_reg"; + interrupts = <0 132 0 0 135 0>; + interrupt-names = "ssusb", "hsusb"; + qcom,usb-bam-num-pipes = <16>; + qcom,usb-bam-fifo-baseaddr = <0xf9200000>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <1>; + qcom,bam-type = <0>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37C000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9304000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0xf0000>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0xf4000>; + qcom,descriptor-fifo-size = <0x1400>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe1 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <1>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37c000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0xf4000>; + qcom,data-fifo-size = <0x1000>; + qcom,descriptor-fifo-offset = <0xf5000>; + qcom,descriptor-fifo-size = <0x400>; + }; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <5>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-control-mask = <0xf>; + qcom,core-limit-temp = <80>; + qcom,core-temp-hysteresis = <10>; + qcom,core-control-mask = <0xe>; + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + qcom,pmic-sw-mode-temp = <85>; + qcom,pmic-sw-mode-temp-hysteresis = <75>; + qcom,pmic-sw-mode-regs = "vdd_dig"; + vdd_dig-supply = <&pm8841_s2_floor_corner>; + vdd_gfx-supply = <&pm8841_s4_floor_corner>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd_dig"; + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + qcom,vdd-gfx-rstr{ + qcom,vdd-rstr-reg = "vdd_gfx"; + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + qcom,vdd-apps-rstr{ + qcom,vdd-rstr-reg = "vdd_apps"; + qcom,levels = <1881600 1958400 2265600>; + qcom,freq-req; + }; + }; + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + qcom,rx-ring-size = <64>; + }; + + memory_hole: qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x7f00000 0x8000000>; /* Address and Size of Hole */ + }; + + uart7: uart@f995d000 { /*BLSP #2, UART #7 */ + compatible = "qcom,msm-hsuart-v14"; + status = "disabled"; + reg = <0xf995d000 0x1000>, + <0xf9944000 0x19000>; + reg-names = "core_mem", "bam_mem"; + interrupts = <0 113 0>, <0 239 0>; + interrupt-names = "core_irq", "bam_irq"; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,msm-bus,name = "uart7"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <84 512 0 0>, + <84 512 500 800>; + }; + + qcom,smem@fa00000 { + compatible = "qcom,smem"; + reg = <0xfa00000 0x200000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1000>; + qcom,pil-string = "modem"; + interrupts = <0 25 1>; + }; + + qcom,smsm-modem { + compatible = "qcom,smsm"; + qcom,smsm-edge = <0>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x2000>; + interrupts = <0 26 1>; + }; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-wcnss { + compatible = "qcom,smd"; + qcom,smd-edge = <6>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x20000>; + qcom,pil-string = "wcnss"; + interrupts = <0 142 1>; + }; + + qcom,smsm-wcnss { + compatible = "qcom,smsm"; + qcom,smsm-edge = <6>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x80000>; + interrupts = <0 144 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; + + qcom,bcl { + compatible = "qcom,bcl"; + }; + + qcom,ssm { + compatible = "qcom,ssm"; + qcom,channel-name = "SSM_RTR"; + }; + + sfpb_spinlock: qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + ldrex_spinlock: qcom,ipc-spinlock@fa00000 { + compatible = "qcom,ipc-spinlock-ldrex"; + reg = <0xfa00000 0x200000>; + status = "disable"; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + qcom,irq-is-percpu; + interrupts = <1 7 0xf00>; + }; + + l2-pmu { + compatible = "qcom,l2-pmu"; + interrupts = <0 1 0>; + }; + + qcom,smdtty { + compatible = "qcom,smdtty"; + + smdtty_apps_fm: qcom,smdtty-apps-fm { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_FM"; + }; + + smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; + }; + + smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; + }; + + smdtty_mbalbridge: qcom,smdtty-mbalbridge { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "MBALBRIDGE"; + }; + + smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; + }; + + smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; + }; + + smdtty_data1: qcom,smdtty-data1 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA1"; + }; + + smdtty_data11: qcom,smdtty-data11 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA11"; + }; + + smdtty_data21: qcom,smdtty-data21 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA21"; + }; + + smdtty_gps_nmea: smdtty-gpsnmea { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "GPSNMEA"; + }; + + smdtty_loopback: smdtty-loopback { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "LOOPBACK"; + qcom,smdtty-dev-name = "LOOPBACK_TTY"; + }; + }; +}; + +&gdsc_venus { + qcom,clock-names = "core_clk"; + qcom,skip-logic-collapse; + status = "ok"; +}; + +&gdsc_mdss { + qcom,clock-names = "core_clk", "lut_clk"; + qcom,retain-periph; + status = "ok"; +}; + +&gdsc_jpeg { + qcom,clock-names = "core0_clk", "core1_clk", "core2_clk"; + status = "ok"; +}; + +&gdsc_vfe { + qcom,clock-names = "core0_clk", "core1_clk", "csi0_clk", "csi1_clk", + "cpp_clk"; + status = "ok"; +}; + +&gdsc_oxili_gx { + qcom,clock-names = "core_clk"; + qcom,retain-mem; + qcom,retain-periph; + status = "ok"; +}; + +&gdsc_oxili_cx { + status = "ok"; +}; + +&gdsc_usb_hsic { + status = "ok"; +}; + +/include/ "msm-pm8x41-rpm-regulator.dtsi" +/include/ "msm-pm8841.dtsi" +/include/ "msm-pm8941.dtsi" +/include/ "msm8974-regulator.dtsi" +/include/ "msm8974-clock.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-cdp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-cdp.dtsi new file mode 100644 index 000000000..6ddb50b82 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-cdp.dtsi @@ -0,0 +1,100 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "msm9625-display.dtsi" +/include/ "qpic-panel-ili-qvga.dtsi" + +&soc { + i2c@f9925000 { + charger@57 { + compatible = "summit,smb137c"; + reg = <0x57>; + summit,chg-current-ma = <1500>; + summit,term-current-ma = <50>; + summit,pre-chg-current-ma = <100>; + summit,float-voltage-mv = <4200>; + summit,thresh-voltage-mv = <3000>; + summit,recharge-thresh-mv = <75>; + summit,system-voltage-mv = <4250>; + summit,charging-timeout = <382>; + summit,pre-charge-timeout = <48>; + summit,therm-current-ua = <10>; + summit,temperature-min = <4>; /* 0 C */ + summit,temperature-max = <3>; /* 45 C */ + }; + }; + + wlan0: qca,wlan { + cell-index = <0>; + compatible = "qca,ar6004-hsic"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; + + qca,wlan_ar6003 { + cell-index = <0>; + compatible = "qca,ar6003-sdio"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; +}; + +/* PM8019 GPIO and MPP configuration */ +&pm8019_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + /* ext_2p95v regulator enable config */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS */ + qcom,invert = <0>; /* Output low */ + qcom,out-strength = <1>; /* Low */ + qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */ + qcom,src-sel = <0>; /* Constant */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; +}; + +&pm8019_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-coresight.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-coresight.dtsi new file mode 100644 index 000000000..3c00ae8c2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-coresight.dtsi @@ -0,0 +1,259 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@fc322000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc322000 0x1000>, + <0xfc37c000 0x3000>; + reg-names = "tmc-base", "bam-base"; + + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x20000>; /* 128K EBI1 buffer */ + + coresight-id = <0>; + coresight-name = "coresight-tmc-etr"; + coresight-nr-inports = <1>; + coresight-ctis = <&cti0 &cti8>; + }; + + tpiu: tpiu@fc318000 { + compatible = "arm,coresight-tpiu"; + reg = <0xfc318000 0x1000>; + reg-names = "tpiu-base"; + + coresight-id = <1>; + coresight-name = "coresight-tpiu"; + coresight-nr-inports = <1>; + + vdd-supply = <&ext_2p95v>; + }; + + replicator: replicator@fc31c000 { + compatible = "qcom,coresight-replicator"; + reg = <0xfc31c000 0x1000>; + reg-names = "replicator-base"; + + coresight-id = <2>; + coresight-name = "coresight-replicator"; + coresight-nr-inports = <1>; + coresight-outports = <0 1>; + coresight-child-list = <&tmc_etr &tpiu>; + coresight-child-ports = <0 0>; + }; + + tmc_etf: tmc@fc307000 { + compatible = "arm,coresight-tmc"; + reg = <0xfc307000 0x1000>; + reg-names = "tmc-base"; + + coresight-id = <3>; + coresight-name = "coresight-tmc-etf"; + coresight-nr-inports = <1>; + coresight-outports = <0>; + coresight-child-list = <&replicator>; + coresight-child-ports = <0>; + coresight-default-sink; + coresight-ctis = <&cti0 &cti8>; + }; + + funnel_merg: funnel@fc31b000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31b000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <4>; + coresight-name = "coresight-funnel-merg"; + coresight-nr-inports = <2>; + coresight-outports = <0>; + coresight-child-list = <&tmc_etf>; + coresight-child-ports = <0>; + }; + + funnel_in0: funnel@fc319000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc319000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <5>; + coresight-name = "coresight-funnel-in0"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <0>; + }; + + funnel_in1: funnel@fc31a000 { + compatible = "arm,coresight-funnel"; + reg = <0xfc31a000 0x1000>; + reg-names = "funnel-base"; + + coresight-id = <6>; + coresight-name = "coresight-funnel-in1"; + coresight-nr-inports = <8>; + coresight-outports = <0>; + coresight-child-list = <&funnel_merg>; + coresight-child-ports = <1>; + }; + + stm: stm@fc321000 { + compatible = "arm,coresight-stm"; + reg = <0xfc321000 0x1000>, + <0xfa280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-id = <7>; + coresight-name = "coresight-stm"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in1>; + coresight-child-ports = <7>; + }; + + etm0: etm@fc332000 { + compatible = "arm,coresight-etm"; + reg = <0xfc332000 0x1000>; + reg-names = "etm-base"; + + coresight-id = <8>; + coresight-name = "coresight-etm0"; + coresight-nr-inports = <0>; + coresight-outports = <0>; + coresight-child-list = <&funnel_in0>; + coresight-child-ports = <4>; + + qcom,round-robin; + }; + + csr: csr@fc302000 { + compatible = "qcom,coresight-csr"; + reg = <0xfc302000 0x1000>; + reg-names = "csr-base"; + + coresight-id = <9>; + coresight-name = "coresight-csr"; + coresight-nr-inports = <0>; + + qcom,blk-size = <1>; + }; + + cti0: cti@fc308000 { + compatible = "arm,coresight-cti"; + reg = <0xfc308000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <10>; + coresight-name = "coresight-cti0"; + coresight-nr-inports = <0>; + }; + + cti1: cti@fc309000 { + compatible = "arm,coresight-cti"; + reg = <0xfc309000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <11>; + coresight-name = "coresight-cti1"; + coresight-nr-inports = <0>; + }; + + cti2: cti@fc30a000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30a000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <12>; + coresight-name = "coresight-cti2"; + coresight-nr-inports = <0>; + }; + + cti3: cti@fc30b000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30b000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <13>; + coresight-name = "coresight-cti3"; + coresight-nr-inports = <0>; + }; + + cti4: cti@fc30c000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30c000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <14>; + coresight-name = "coresight-cti4"; + coresight-nr-inports = <0>; + }; + + cti5: cti@fc30d000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30d000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <15>; + coresight-name = "coresight-cti5"; + coresight-nr-inports = <0>; + }; + + cti6: cti@fc30e000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30e000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <16>; + coresight-name = "coresight-cti6"; + coresight-nr-inports = <0>; + }; + + cti7: cti@fc30f000 { + compatible = "arm,coresight-cti"; + reg = <0xfc30f000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <17>; + coresight-name = "coresight-cti7"; + coresight-nr-inports = <0>; + }; + + cti8: cti@fc310000 { + compatible = "arm,coresight-cti"; + reg = <0xfc310000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <18>; + coresight-name = "coresight-cti8"; + coresight-nr-inports = <0>; + }; + + cti_cpu: cti@fc333000 { + compatible = "arm,coresight-cti"; + reg = <0xfc333000 0x1000>; + reg-names = "cti-base"; + + coresight-id = <19>; + coresight-name = "coresight-cti-cpu"; + coresight-nr-inports = <0>; + }; + + hwevent: hwevent@f9011038 { + compatible = "qcom,coresight-hwevent"; + reg = <0xf9011038 0x8>, + <0xfd4ab160 0x80>; + reg-names = "apcs-mux", "ppss-mux"; + + coresight-id = <20>; + coresight-name = "coresight-hwevent"; + coresight-nr-inports = <0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-display.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-display.dtsi new file mode 100644 index 000000000..287a63aef --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-display.dtsi @@ -0,0 +1,20 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm_qpic@f9ac0000 { + compatible = "qcom,mdss_qpic"; + reg = <0xf9ac0000 0x24000>; + reg-names = "qpic_base"; + interrupts = <0 251 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-ion.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-ion.dtsi new file mode 100644 index 000000000..6f9bb535d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-ion.dtsi @@ -0,0 +1,35 @@ +/* Copyright (c) 2012-2013, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + + qcom,ion-heap@28 { /* AUDIO HEAP */ + compatible = "qcom,msm-ion-reserve"; + reg = <28>; + qcom,heap-align = <0x1000>; + qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */ + qcom,memory-reservation-size = <0xE9000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-mtp.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-mtp.dtsi new file mode 100755 index 000000000..da183fa17 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-mtp.dtsi @@ -0,0 +1,138 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + i2c@f9925000 { + qcom_ssd1306@3C { + compatible = "qcom,ssd1306"; + reg = <0x3C>; + }; + }; + + oled { + compatible = "tp,oled_pt"; + qcom,oled_ssd1306 { + compatible = "qcom,oled_ssd1306_pt"; + qcom,oled-cs-gpio = <&msmgpio 4 0>; + qcom,oled-a0-gpio = <&msmgpio 5 0>; + qcom,oled-res-gpio = <&msmgpio 6 0>; + qcom,oled-boost-en-gpio = <&msmgpio 7 0>; + }; + }; + + wlan0: qca,wlan { + cell-index = <0>; + compatible = "qca,ar6004-hsic"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; + + qca,wlan_ar6003 { + cell-index = <0>; + compatible = "qca,ar6003-sdio"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; + + mp2617 { + cell-index = <0>; + compatible = "mps,mp2617"; + mps,chg-current-ma = <1000>; + mps,chg-vbat-div = <3>; /* Divided by 3 before input */ + mps,chg-en-gpio = <&msmgpio 13 0>; /* refer to board-9625-gpiomux.c */ + mps,chg-ok-gpio = <&msmgpio 70 0>; + mps,chg-m0-gpio = <&msmgpio 16 0>; + mps,chg-m1-gpio = <&msmgpio 17 0>; + + /* The following is for power bank */ + mps,chg-det-resistor = <100>; /* 100m Ohm */ + mps,chg-batt-resistor = <120>; /* 120m Ohm */ + mps,chg-boost-en-gpio = <&msmgpio 14 0>; + }; +}; + +/* PM8019 GPIO and MPP configuration */ +&pm8019_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + /* ext_2p95v regulator enable config */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS */ + qcom,invert = <0>; /* Output low */ + qcom,out-strength = <1>; /* Low */ + qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */ + qcom,src-sel = <0>; /* Constant */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; +}; + +&pm8019_mpps { + /* [linyunfeng] Detect voltage on resistor*/ + mpp@a000 { /* MPP 1 */ + /* channel 16 */ + qcom,mode = <4>; + qcom,ain-route = <0>; /* AMUX 5 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; + + /* [linyunfeng] Detect battery voltage */ + mpp@a100 { /* MPP 2 */ + /* channel 17 */ + qcom,mode = <4>; + qcom,ain-route = <1>; /* AMUX 6 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + /* VADC channel 19 */ + qcom,mode = <4>; + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + /* channel 21 */ + qcom,mode = <4>; + qcom,ain-route = <1>; /* AMUX 6 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-pm.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-pm.dtsi new file mode 100644 index 000000000..673b64053 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-pm.dtsi @@ -0,0 +1,299 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +&soc { + qcom,spm@f9009000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf9009000 0x1000>; + qcom,core-id = <0>; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x101>; + qcom,saw2-spm-dly= <0>; + qcom,saw2-spm-ctl = <0x1>; + qcom,saw2-spm-cmd-wfi = [04 03 04 0f]; + qcom,saw2-spm-cmd-spc = [34 04 44 14 24 54 03 54 44 14 04 24 + 3e 0f]; + qcom,saw2-spm-cmd-pc = [34 04 44 14 24 54 07 54 44 14 04 24 + 3e 0f]; + }; + + qcom,lpm-resources { + compatible = "qcom,lpm-resources"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,lpm-resources@0 { + reg = <0x0>; + qcom,name = "vdd-dig"; + qcom,type = <0x616F646C>; /* "ldoa" */ + qcom,id = <0x0A>; + qcom,key = <0x6e726f63>; /* "corn" */ + qcom,init-value = <5>; /* Super Turbo */ + }; + + qcom,lpm-resources@1 { + reg = <0x1>; + qcom,name = "vdd-mem"; + qcom,type = <0x616F646C>; /* "ldoa" */ + qcom,id = <0x0C>; + qcom,key = <0x7675>; /* "uv" */ + qcom,init-value = <1050000>; /* Super Turbo */ + }; + + qcom,lpm-resources@2 { + reg = <0x2>; + qcom,name = "pxo"; + qcom,type = <0x306b6c63>; /* "clk0" */ + qcom,id = <0x00>; + qcom,key = <0x62616e45>; /* "Enab" */ + qcom,init-value = "xo_on"; + }; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,use-qtimer; + + qcom,lpm-level@0 { + reg = <0x0>; + qcom,mode = "wfi"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <100>; + qcom,ss-power = <8000>; + qcom,energy-overhead = <100000>; + qcom,time-overhead = <1>; + }; + + qcom,lpm-level@1 { + reg = <0x1>; + qcom,mode = "standalone_pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_active"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <2000>; + qcom,ss-power = <5000>; + qcom,energy-overhead = <60100000>; + qcom,time-overhead = <3000>; + }; + + qcom,lpm-level@2 { + reg = <0x2>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_gdhs"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <3500>; + qcom,ss-power = <5000>; + qcom,energy-overhead = <60350000>; + qcom,time-overhead = <6300>; + }; + + qcom,lpm-level@3 { + reg = <0x3>; + qcom,mode = "pc"; + qcom,xo = "xo_on"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <4>; /* NORMAL */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,gpio-detectable; + qcom,latency-us = <4500>; + qcom,ss-power = <5000>; + qcom,energy-overhead = <60350000>; + qcom,time-overhead = <7300>; + }; + + qcom,lpm-level@4 { + reg = <0x4>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <4>; /* NORMAL */ + qcom,irqs-detectable; + qcom,latency-us = <6800>; + qcom,ss-power = <2000>; + qcom,energy-overhead = <71850000>; + qcom,time-overhead = <13300>; + }; + + qcom,lpm-level@5 { + reg = <0x5>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */ + qcom,vdd-mem-lower-bound = <950000>; /* SVS SOC */ + qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */ + qcom,vdd-dig-lower-bound = <3>; /* SVS SOC */ + qcom,irqs-detectable; + qcom,latency-us = <8000>; + qcom,ss-power = <1800>; + qcom,energy-overhead = <71950000>; + qcom,time-overhead = <15300>; + }; + + qcom,lpm-level@6 { + reg = <0x6>; + qcom,mode = "pc"; + qcom,xo = "xo_off"; + qcom,l2 = "l2_cache_pc"; + qcom,vdd-mem-upper-bound = <950000>; /* SVS SOC */ + qcom,vdd-mem-lower-bound = <675000>; /* RETENTION */ + qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */ + qcom,vdd-dig-lower-bound = <1>; /* RETENTION */ + qcom,latency-us = <9800>; + qcom,ss-power = <0>; + qcom,energy-overhead = <76350000>; + qcom,time-overhead = <28300>; + }; + }; + + qcom,pm-boot { + compatible = "qcom,pm-boot"; + qcom,mode = "tz"; + }; + + qcom,mpm@fc4281d0 { + compatible = "qcom,mpm-v2"; + reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = <0 171 1>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = <2 216>, /* tsens_upper_lower_int */ + <47 172>, /* usb2_hsic_async_wakeup_irq */ + <41 180>, /* usb_async_wakeup_irq */ + <62 222>, /* ee0_krait_hlos_spmi_periph_irq */ + <0xff 57>, /* mss_to_apps_irq(0) */ + <0xff 58>, /* mss_to_apps_irq(1) */ + <0xff 59>, /* mss_to_apps_irq(2) */ + <0xff 60>, /* mss_to_apps_irq(3) */ + <0xff 173>, /* o_wcss_apss_smd_hi */ + <0xff 174>, /* o_wcss_apss_smd_med */ + <0xff 175>, /* o_wcss_apss_smd_lo */ + <0xff 176>, /* o_wcss_apss_smsm_irq */ + <0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */ + <0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */ + <0xff 179>, /* o_wcss_apss_asic_intr */ + <0xff 188>, /* q6ss_irq_out(4) */ + <0xff 189>, /* q6ss_irq_out(5) */ + <0xff 190>, /* q6ss_irq_out(6) */ + <0xff 191>, /* q6ss_irq_out(7) */ + <0xff 192>, /* audio_out0_irq */ + <0xff 193>, /* midi_arm_irq */ + <0xff 194>, /* q6ss_wdog_exp_irq */ + <0xff 195>, /* slimbus_core_ee1_irq */ + <0xff 196>, /* bam_irq(1) */ + <0xff 197>, /* qdss_irq_out(7) */ + <0xff 200>, /* rpm_ipc(4) */ + <0xff 201>, /* rpm_ipc(5) */ + <0xff 202>, /* rpm_ipc(6) */ + <0xff 203>, /* rpm_ipc(7) */ + <0xff 204>, /* rpm_ipc(24) */ + <0xff 205>, /* rpm_ipc(25) */ + <0xff 206>, /* rpm_ipc(26) */ + <0xff 207>, /* rpm_ipc(27) */ + <0xff 240>; /* summary_irq_kpss */ + + qcom,gpio-parent = <&msmgpio>; + qcom,gpio-map = <4 0>, + <5 1>, + <6 2>, + <7 3>, + <8 4>, + <9 5>, + <10 6>, + <11 7>, + <12 8>, + <13 9>, + <14 10>, + <15 11>, + <16 12>, + <17 13>, + <18 14>, + <19 15>, + <20 16>, + <21 17>, + <22 18>, + <23 19>, + <24 20>, + <25 21>, + <26 24>, + <27 25>, + <28 51>, + <29 61>, + <30 62>, + <31 63>, + <32 64>, + <33 65>, + <34 66>, + <35 67>, + <36 69>, + <37 71>; + }; + + qcom,pm-8x60 { + compatible = "qcom,pm-8x60"; + qcom,pc-mode = "tz_l2_ext"; + qcom,use-sync-timer; + }; + + qcom,rpm-log@fc19dc00 { + compatible = "qcom,rpm-log"; + reg = <0xfc19dc00 0x4000>; + qcom,rpm-addr-phys = <0xfc000000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-stats@fc19dba0 { + compatible = "qcom,rpm-stats"; + reg = <0xfc19dba0 0x1000>; + reg-names = "phys_addr_base"; + qcom,sleep-stats-version = <2>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-regulator.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-regulator.dtsi new file mode 100644 index 000000000..eb56d1c6a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-regulator.dtsi @@ -0,0 +1,284 @@ +/* Copyright (c) 2012-2013, Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa1 { + status = "okay"; + pm8019_s1: regulator-s1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1050000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa2 { + status = "okay"; + pm8019_s2: regulator-s2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + qcom,init-voltage = <1250000>; + qcom,init-current = <100>; + qcom,system-load = <100000>; + regulator-always-on; + status = "okay"; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8019_s3: regulator-s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + qcom,init-voltage = <1100000>; + qcom,init-current = <100>; + qcom,system-load = <100000>; + regulator-always-on; + status = "okay"; + }; + pm8019_s3_ao: regulator-s3-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_s3_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8019_s4: regulator-s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2075000>; + qcom,init-voltage = <2075000>; + qcom,init-current = <100>; + qcom,system-load = <100000>; + regulator-always-on; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8019_l1: regulator-l1 { + parent-supply = <&pm8019_s2>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8019_l2: regulator-l2 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8019_l3: regulator-l3 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8019_l4: regulator-l4 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8019_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8019_l6: regulator-l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8019_l7: regulator-l7 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8019_l8: regulator-l8 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8019_l9: regulator-l9 { + parent-supply = <&pm8019_s2>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-current = <10>; + qcom,system-load = <10000>; + regulator-always-on; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8019_l10: regulator-l10 { + parent-supply = <&pm8019_s3>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8019_l10_corner: regulator-l10-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l10_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + status = "okay"; + qcom,consumer-supplies = "vdd_dig", ""; + }; + pm8019_l10_corner_ao: regulator-l10-corner-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l10_corner_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-corner; + status = "okay"; + }; + pm8019_l10_floor_corner: regulator-l10-floor-corner { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l10_floor_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + qcom,use-voltage-floor-corner; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8019_l11: regulator-l11 { + parent-supply = <&pm8019_s4>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-current = <10>; + qcom,system-load = <10000>; + regulator-always-on; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8019_l12: regulator-l12 { + parent-supply = <&pm8019_s3>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8019_l12_ao: regulator-l12-ao { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l12_ao"; + qcom,set = <1>; + parent-supply = <&pm8019_s3_ao>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + pm8019_l12_so: regulator-l12-so { + compatible = "qcom,rpm-regulator-smd"; + regulator-name = "8019_l12_so"; + qcom,set = <2>; + parent-supply = <&pm8019_s3>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <675000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8019_l13: regulator-l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8019_l14: regulator-l14 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <2700000>; + status = "okay"; + }; + }; +}; + +&soc { + ext_2p95v: regulator-isl80101 { + compatible = "regulator-fixed"; + regulator-name = "ext_2p95v"; + gpio = <&pm8019_gpios 4 0>; + enable-active-high; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-smp2p.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-smp2p.dtsi new file mode 100644 index 000000000..f8ad351a4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-smp2p.dtsi @@ -0,0 +1,142 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 27 1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + reg = <0xf9011008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_in { + compatible = "qcom,smp2pgpio_test_smp2p_7_in"; + gpios = <&smp2pgpio_smp2p_7_in 0 0>; + }; + + smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_7_out { + compatible = "qcom,smp2pgpio_test_smp2p_7_out"; + gpios = <&smp2pgpio_smp2p_7_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-cdp.dts new file mode 100644 index 000000000..d7537eb35 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-cdp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v1.dtsi" +/include/ "msm9625-cdp.dtsi" + +/ { + model = "Qualcomm MSM 9625V1 CDP"; + compatible = "qcom,msm9625-cdp", "qcom,msm9625", "qcom,cdp"; + qcom,msm-id = <134 1 0>, <152 1 0>, <149 1 0>, <150 1 0>, + <151 1 0>, <148 1 0>, <173 1 0>, <174 1 0>, + <175 1 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-mtp.dts new file mode 100644 index 000000000..a70ec1aa7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-mtp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v1.dtsi" +/include/ "msm9625-mtp.dtsi" + +/ { + model = "Qualcomm MSM 9625V1 MTP"; + compatible = "qcom,msm9625-mtp", "qcom,msm9625", "qcom,mtp"; + qcom,msm-id = <134 7 0>, <152 7 0>, <149 7 0>, <150 7 0>, + <151 7 0>, <148 7 0>, <173 7 0>, <174 7 0>, + <175 7 0>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-rumi.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-rumi.dts new file mode 100644 index 000000000..ef0068143 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1-rumi.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v1.dtsi" + +/ { + model = "Qualcomm MSM 9625V1 RUMI"; + compatible = "qcom,msm9625-rumi", "qcom,msm9625", "qcom,rumi"; + qcom,msm-id = <134 15 0>; + + chosen{ + bootargs = "root=/dev/ram rw init=/init console=ttyHSL0,115200n8 initrd=0x00000000,0x00000000 mem=29M@0x00200000 mem=10M@0x07600000"; + + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1.dtsi new file mode 100644 index 000000000..b238ba549 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v1.dtsi @@ -0,0 +1,67 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm9625.dtsi file. + */ + +/include/ "msm9625.dtsi" + +&soc { + qcom,msm-imem@fc42a800 { + compatible = "qcom,msm-imem"; + reg = <0xfc42a800 0x1000>; /* Address and size of IMEM */ + }; + + android_usb@fc42a8c8 { + compatible = "qcom,android-usb"; + reg = <0xfc42a8c8 0xc8>; + qcom,android-usb-swfi-latency = <100>; + }; + + qcom,bam_dmux@fc834000 { + compatible = "qcom,bam_dmux"; + reg = <0xfc834000 0x7000>; + interrupts = <0 29 1>; + }; +}; + +&hsic_host { + qcom,disable-park-mode; +}; + +&ipa_hw { + qcom,ipa-hw-ver = <1>; /* IPA h-w revision */ +}; + +/* CoreSight */ +&tmc_etr { + qcom,reset-flush-race; +}; + +&stm { + qcom,write-64bit; +}; + +&sfpb_spinlock { + status = "disable"; +}; + +&ldrex_spinlock { + status = "ok"; +}; + +&hsic_host { + qcom,phy-sof-workaround; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2-cdp.dts new file mode 100644 index 000000000..9fbe5ec8a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2-cdp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v2.dtsi" +/include/ "msm9625-cdp.dtsi" + +/ { + model = "Qualcomm MSM 9625V2 CDP"; + compatible = "qcom,msm9625-cdp", "qcom,msm9625", "qcom,cdp"; + qcom,msm-id = <134 1 0x20000>, <152 1 0x20000>, <149 1 0x20000>, + <150 1 0x20000>, <151 1 0x20000>, <148 1 0x20000>, + <173 1 0x20000>, <174 1 0x20000>, <175 1 0x20000>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2-mtp.dts new file mode 100644 index 000000000..27d00664a --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2-mtp.dts @@ -0,0 +1,122 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v2.dtsi" +/include/ "msm9625-mtp.dtsi" + +/ { + model = "Qualcomm MSM 9625V2 MTP"; + compatible = "qcom,msm9625-mtp", "qcom,msm9625", "qcom,mtp"; + qcom,msm-id = <134 7 0x20000>, <152 7 0x20000>, <149 7 0x20000>, + <150 7 0x20000>, <151 7 0x20000>, <148 7 0x20000>, + <173 7 0x20000>, <174 7 0x20000>, <175 7 0x20000>; +}; + +&soc { + i2c@f9925000 { + charger@57 { + compatible = "summit,smb137c"; + reg = <0x57>; + summit,chg-current-ma = <1500>; + summit,term-current-ma = <50>; + summit,pre-chg-current-ma = <100>; + summit,float-voltage-mv = <4200>; + summit,thresh-voltage-mv = <3000>; + summit,recharge-thresh-mv = <75>; + summit,system-voltage-mv = <4250>; + summit,charging-timeout = <382>; + summit,pre-charge-timeout = <48>; + summit,therm-current-ua = <10>; + summit,temperature-min = <4>; /* 0 C */ + summit,temperature-max = <3>; /* 45 C */ + }; + }; + + wlan0: qca,wlan { + cell-index = <0>; + compatible = "qca,ar6004-hsic"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; + + qca,wlan_ar6003 { + cell-index = <0>; + compatible = "qca,ar6003-sdio"; + qca,chip-pwd-l-gpios = <&msmgpio 62 0>; + qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>; + qca,vdd-io-supply = <&pm8019_l11>; + }; +}; + +/* PM8019 GPIO and MPP configuration */ +&pm8019_gpios { + gpio@c000 { /* GPIO 1 */ + }; + + gpio@c100 { /* GPIO 2 */ + }; + + gpio@c200 { /* GPIO 3 */ + }; + + gpio@c300 { /* GPIO 4 */ + /* ext_2p95v regulator enable config */ + qcom,mode = <1>; /* Digital output */ + qcom,output-type = <0>; /* CMOS */ + qcom,invert = <0>; /* Output low */ + qcom,out-strength = <1>; /* Low */ + qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */ + qcom,src-sel = <0>; /* Constant */ + qcom,master-en = <1>; /* Enable GPIO */ + }; + + gpio@c400 { /* GPIO 5 */ + }; + + gpio@c500 { /* GPIO 6 */ + }; +}; + +&pm8019_mpps { + mpp@a000 { /* MPP 1 */ + }; + + mpp@a100 { /* MPP 2 */ + }; + + mpp@a200 { /* MPP 3 */ + }; + + mpp@a300 { /* MPP 4 */ + /* VADC channel 19 */ + qcom,mode = <4>; + qcom,ain-route = <3>; /* AMUX 8 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; + + mpp@a400 { /* MPP 5 */ + }; + + mpp@a500 { /* MPP 6 */ + /* channel 21 */ + qcom,mode = <4>; + qcom,ain-route = <1>; /* AMUX 6 */ + qcom,master-en = <1>; + qcom,src-sel = <0>; /* Function constant */ + qcom,invert = <1>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1-cdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1-cdp.dts new file mode 100644 index 000000000..b64359381 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1-cdp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v2.1.dtsi" +/include/ "msm9625-cdp.dtsi" + +/ { + model = "Qualcomm MSM 9625V2.1 CDP"; + compatible = "qcom,msm9625-cdp", "qcom,msm9625", "qcom,cdp"; + qcom,msm-id = <134 1 0x20001>, <152 1 0x20001>, <149 1 0x20001>, + <150 1 0x20001>, <151 1 0x20001>, <148 1 0x20001>, + <173 1 0x20001>, <174 1 0x20001>, <175 1 0x20001>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1-mtp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1-mtp.dts new file mode 100644 index 000000000..8bbcc0d55 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1-mtp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msm9625-v2.1.dtsi" +/include/ "msm9625-mtp.dtsi" + +/ { + model = "Qualcomm MSM 9625V2.1 MTP"; + compatible = "qcom,msm9625-mtp", "qcom,msm9625", "qcom,mtp"; + qcom,msm-id = <134 7 0x20001>, <152 7 0x20001>, <149 7 0x20001>, + <150 7 0x20001>, <151 7 0x20001>, <148 7 0x20001>, + <173 7 0x20001>, <174 7 0x20001>, <175 7 0x20001>; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1.dtsi new file mode 100644 index 000000000..07548f949 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.1.dtsi @@ -0,0 +1,41 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm9625.dtsi file. + */ + +/include/ "msm9625.dtsi" + +&soc { + qcom,msm-imem@fe807800 { + compatible = "qcom,msm-imem"; + reg = <0xfe807800 0x1000>; /* Address and size of IMEM */ + }; + + android_usb@fe8078c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8078c8 0xc8>; + qcom,android-usb-cdrom; + qcom,android-usb-swfi-latency = <100>; + }; +}; + +&ipa_hw { + qcom,ipa-hw-ver = <2>; /* IPA h-w revision */ +}; + +&hsusb_otg { + qcom,hsusb-l1-supported; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.dtsi new file mode 100644 index 000000000..3eda3f896 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625-v2.dtsi @@ -0,0 +1,54 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. However, device definitions should be placed inside the + * msm9625.dtsi file. + */ + +/include/ "msm9625.dtsi" + +&soc { + qcom,msm-imem@fe807800 { + compatible = "qcom,msm-imem"; + reg = <0xfe807800 0x1000>; /* Address and size of IMEM */ + }; + + android_usb@fe8078c8 { + compatible = "qcom,android-usb"; + reg = <0xfe8078c8 0xc8>; + qcom,android-usb-swfi-latency = <100>; + }; +}; + +&ipa_hw { + qcom,ipa-hw-ver = <2>; /* IPA h-w revision */ +}; + +&hsic_host { + qcom,disable-park-mode; + qcom,phy-susp-sof-workaround; + qcom,phy-reset-sof-workaround; +}; + +&sfpb_spinlock { + status = "disable"; +}; + +&ldrex_spinlock { + status = "ok"; +}; + +&hsusb_otg { + qcom,hsusb-l1-supported; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625.dtsi new file mode 100644 index 000000000..6200b0a8c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msm9625.dtsi @@ -0,0 +1,864 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM 9625"; + compatible = "qcom,msm9625"; + interrupt-parent = <&intc>; + + aliases { + }; + + soc: soc { }; +}; + +/include/ "msm9625-ion.dtsi" +/include/ "msm9625-pm.dtsi" +/include/ "msm9625-coresight.dtsi" +/include/ "msm9625-smp2p.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@F9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xF9000000 0x1000>, + <0xF9002000 0x1000>; + }; + + l2: cache-controller@f9040000 { + compatible = "arm,pl310-cache"; + reg = <0xf9040000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <76>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + qcom,mpm2-sleep-counter@fc4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xfc4a3000 0x1000>; + clock-frequency = <32768>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + + frame@f9029000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0xf9029000 0x1000>; + status = "disabled"; + }; + }; + + qcom,sps@f9980000 { + compatible = "qcom,msm_sps"; + reg = <0xf9984000 0x15000>, + <0xf9999000 0xb000>, + <0xfe803000 0x4800>; + interrupts = <0 94 0>; + qcom,device-type = <2>; + }; + + serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + qcom,msm-bus,name = "blsp1_uart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + }; + + hsusb_otg: usb@f9a55000 { + compatible = "qcom,hsusb-otg"; + reg = <0xf9a55000 0x400>; + interrupts = <0 134 0 0 140 0>; + interrupt-names = "core_irq", "async_irq"; + HSUSB_VDDCX-supply = <&pm8019_l12>; + HSUSB_1p8-supply = <&pm8019_l2>; + HSUSB_3p3-supply = <&pm8019_l4>; + vbus_otg-supply = <&usb_vbus>; + + qcom,hsusb-otg-phy-type = <2>; + qcom,hsusb-otg-mode = <1>; + qcom,hsusb-otg-otg-control = <1>; + qcom,hsusb-otg-disable-reset; + qcom,hsusb-otg-delay-lpm-hndshk-on-disconnect; + qcom,hsusb-otg-delay-lpm; + qcom,hsusb-otg-mpm-dpsehv-int = <49>; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 40000 640000>; + qcom,hsusb-log2-itc = <4>; + }; + + hsic_host: hsic@f9a15000 { + compatible = "qcom,hsic-host"; + reg = <0xf9a15000 0x400>; + interrupts = <0 136 0>, <0 148 0>; + interrupt-names = "core_irq", "async_irq"; + HSIC_VDDCX-supply = <&pm8019_l12>; + HSIC_GDSC-supply = <&gdsc_usb_hsic>; + + qcom,msm-bus,name = "hsic"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <85 512 0 0>, + <85 512 40000 640000>; + qcom,pool-64-bit-align; + qcom,enable-hbm; + hsic,consider-ipa-handshake; + qcom,ahb-async-bridge-bypass; + hsic,disable-cerr; + qcom,disable-internal-clk-gating; + }; + + qcom,usbbam@f9a44000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xf9a44000 0x11000>, + <0xf9a04000 0x11000>; + reg-names = "hsusb", "hsic"; + interrupts = <0 135 0 0 255 0>; + interrupt-names = "hsusb", "hsic"; + qcom,usb-bam-num-pipes = <16>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + + qcom,pipe0 { + label = "hsusb-ipa-out-0"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <0>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a44000>; + qcom,src-bam-pipe-index = <1>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + qcom,pipe1 { + label = "hsusb-ipa-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + qcom,pipe2 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <0>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-physical-address = <0xfc37c000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x4100>; + qcom,data-fifo-size = <0x700>; + qcom,descriptor-fifo-offset = <0x4000>; + qcom,descriptor-fifo-size = <0x100>; + }; + qcom,pipe3 { + label = "hsic-ipa-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a04000>; + qcom,dst-bam-pipe-index = <3>; + qcom,data-fifo-size = <0xF800>; + qcom,descriptor-fifo-size = <0x3A58>; + qcom,reset-bam-on-connect; + }; + qcom,pipe4 { + label = "hsic-ipa-in-1"; + qcom,bam-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <1>; + qcom,peer-bam = <2>; + qcom,usb-bam-mem-type = <2>; + qcom,dst-bam-physical-address = <0xf9a04000>; + qcom,dst-bam-pipe-index = <4>; + qcom,data-fifo-size = <0xF800>; + qcom,descriptor-fifo-size = <0x3A58>; + qcom,reset-bam-on-connect; + }; + qcom,pipe5 { + label = "hsic-ipa-in-2"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <2>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a04000>; + qcom,dst-bam-pipe-index = <5>; + qcom,data-fifo-size = <0xF800>; + qcom,descriptor-fifo-size = <0x3A58>; + qcom,reset-bam-on-connect; + }; + qcom,pipe6 { + label = "hsic-ipa-in-3"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <3>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a04000>; + qcom,dst-bam-pipe-index = <6>; + qcom,data-fifo-size = <0xF800>; + qcom,descriptor-fifo-size = <0x3A58>; + qcom,reset-bam-on-connect; + }; + qcom,pipe7 { + label = "hsic-ipa-out-0"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <2>; + qcom,dir = <0>; + qcom,pipe-num = <0>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a04000>; + qcom,src-bam-pipe-index = <7>; + qcom,data-fifo-size = <0xDFE>; + qcom,descriptor-fifo-size = <0xB30>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe8 { + label = "hsusb-ipa-out-1"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <1>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a44000>; + qcom,src-bam-pipe-index = <5>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe9 { + label = "hsusb-ipa-in-1"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <1>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <4>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe10 { + label = "hsusb-ipa-out-2"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <2>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a44000>; + qcom,src-bam-pipe-index = <7>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe11 { + label = "hsusb-ipa-in-2"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <2>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <6>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe12 { + label = "hsusb-ipa-out-3"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <3>; + qcom,peer-bam = <2>; + qcom,src-bam-physical-address = <0xf9a44000>; + qcom,src-bam-pipe-index = <8>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + + qcom,pipe13 { + label = "hsusb-ipa-in-3"; + qcom,usb-bam-mem-type = <2>; + qcom,bam-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <3>; + qcom,peer-bam = <2>; + qcom,dst-bam-physical-address = <0xf9a44000>; + qcom,dst-bam-pipe-index = <9>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + qcom,reset-bam-on-connect; + }; + }; + + qcom,nand@f9ac0000 { + compatible = "qcom,msm-nand"; + reg = <0xf9ac0000 0x1000>, + <0xf9ac4000 0x8000>; + reg-names = "nand_phys", + "bam_phys"; + interrupts = <0 247 0>; + interrupt-names = "bam_irq"; + }; + + qcom,wdt@f9017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf9017000 0x1000>; + interrupts = <1 2 0>, <1 1 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + spmi_bus: qcom,spmi@fc4c0000 { + cell-index = <0>; + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + /* 190,ee0_krait_hlos_spmi_periph_irq */ + /* 187,channel_0_krait_hlos_trans_done_irq */ + interrupts = <0 190 0 0 187 0>; + qcom,pmic-arb-ee = <0>; + qcom,pmic-arb-channel = <0>; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>, + <0xf98a4800 0x100>, + <0xf9884000 0x7000>; + reg-names = "core_mem", "dml_mem", "bam_mem"; + + vdd-supply = <&ext_2p95v>; + + vdd-io-supply = <&pm8019_l13>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <6 22000>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; + qcom,pad-pull-off = <0x0 0x3 0x3>; + qcom,pad-drv-on = <0x4 0x4 0x4>; + qcom,pad-drv-off = <0x0 0x0 0x0>; + + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + qcom,bus-width = <4>; + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + interrupt-parent = <&sdcc2>; + #address-cells = <0>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 220 0 + 2 &msmgpio 66 0x3>; + interrupt-names = "core_irq", "bam_irq", "status_irq"; + cd-gpios = <&msmgpio 66 0>; + }; + + ipa_hw: qcom,ipa@fd4c0000 { + compatible = "qcom,ipa"; + reg = <0xfd4c0000 0x26000>, + <0xfd4c4000 0x14818>, + <0xfc834000 0x7000>; + reg-names = "ipa-base", "bam-base", "a2-bam-base"; + interrupts = <0 252 0>, + <0 253 0>, + <0 29 1>; + interrupt-names = "ipa-irq", "bam-irq", "a2-bam-irq"; + + qcom,pipe1 { + label = "a2-to-ipa"; + qcom,src-bam-physical-address = <0xfc834000>; + qcom,ipa-bam-mem-type = <0>; + qcom,src-bam-pipe-index = <1>; + qcom,dst-bam-physical-address = <0xfd4c0000>; + qcom,dst-bam-pipe-index = <6>; + qcom,data-fifo-offset = <0x1000>; + qcom,data-fifo-size = <0xd00>; + qcom,descriptor-fifo-offset = <0x1d00>; + qcom,descriptor-fifo-size = <0x300>; + }; + + qcom,pipe2 { + label = "ipa-to-a2"; + qcom,src-bam-physical-address = <0xfd4c0000>; + qcom,ipa-bam-mem-type = <0>; + qcom,src-bam-pipe-index = <7>; + qcom,dst-bam-physical-address = <0xfc834000>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x00>; + qcom,data-fifo-size = <0xd00>; + qcom,descriptor-fifo-offset = <0xd00>; + qcom,descriptor-fifo-size = <0x300>; + }; + }; + + qcom,acpuclk@f9010000 { + compatible = "qcom,acpuclk-9625"; + reg = <0xf9010008 0x10>, + <0xf9008004 0x4>; + reg-names = "rcg_base", "pwr_base"; + a5_cpu-supply = <&pm8019_l10_corner_ao>; + a5_mem-supply = <&pm8019_l12_ao>; + }; + + gdsc_usb_hsic: qcom,gdsc@fc400404 { + compatible = "qcom,gdsc"; + reg = <0xfc400404 0x4>; + regulator-name = "gdsc_usb_hsic"; + }; + + tsens@fc4a8000 { + compatible = "qcom,msm-tsens"; + reg = <0xfc4a8000 0x2000>, + <0xfc4b8000 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>; + qcom,sensors = <5>; + qcom,slope = <3200 3200 3200 3200 3200>; + qcom,calib-mode = "fuse_map1"; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <0>; + qcom,poll-ms = <250>; + qcom,limit-temp = <60>; + qcom,temp-hysteresis = <10>; + qcom,freq-step = <2>; + qcom,freq-control-mask = <0x0>; + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + vdd-dig-supply = <&pm8019_l10_floor_corner>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd-dig"; + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + }; + + qcom,msm-rng@f9bff000 { + compatible = "qcom,msm-rng"; + reg = <0xf9bff000 0x200>; + qcom,msm-rng-iface-clk; + }; + + i2c@f9925000 { + cell-index = <3>; + compatible = "qcom,i2c-qup"; + reg = <0xf9925000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + interrupts = <0 97 0>; + interrupt-names = "qup_err_intr"; + qcom,i2c-bus-freq = <400000>; + qcom,i2c-src-freq = <19200000>; + }; + + qcom,mss { + compatible = "qcom,pil-q6v5-mss"; + interrupts = <0 24 1>; + qcom,is-not-loadable; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + qcom,smem@0 { + compatible = "qcom,smem"; + reg = <0x0 0x100000>, + <0xf9011000 0x1000>, + <0xfc428000 0x4000>; + reg-names = "smem", "irq-reg-base", "aux-mem1"; + + qcom,smd-modem { + compatible = "qcom,smd"; + qcom,smd-edge = <0>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1000>; + qcom,pil-string = "modem"; + interrupts = <0 25 1>; + }; + + qcom,smsm-modem { + compatible = "qcom,smsm"; + qcom,smsm-edge = <0>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x2000>; + interrupts = <0 26 1>; + }; + + qcom,smd-adsp { + compatible = "qcom,smd"; + qcom,smd-edge = <1>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x100>; + qcom,pil-string = "adsp"; + interrupts = <0 156 1>; + }; + + qcom,smsm-adsp { + compatible = "qcom,smsm"; + qcom,smsm-edge = <1>; + qcom,smsm-irq-offset = <0x8>; + qcom,smsm-irq-bitmask = <0x200>; + interrupts = <0 157 1>; + }; + + qcom,smd-rpm { + compatible = "qcom,smd"; + qcom,smd-edge = <15>; + qcom,smd-irq-offset = <0x8>; + qcom,smd-irq-bitmask = <0x1>; + interrupts = <0 168 1>; + qcom,irq-no-suspend; + }; + }; + + qcom,qcedev@fd400000 { + compatible = "qcom,qcedev"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + }; + + qcom,qcrypto@fd440000 { + compatible = "qcom,qcrypto"; + reg = <0xfd400000 0x20000>, + <0xfd404000 0x8000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + }; + + jtag_mm: jtagmm@fc332000 { + compatible = "qcom,jtag-mm"; + reg = <0xfc332000 0x1000>, + <0xfc330000 0x1000>; + reg-names = "etm-base","debug-base"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,memory-reservation-type = "EBI1"; + qcom,memory-reservation-size = <0x1000>; /* 4K EBI1 buffer */ + }; + + qcom,msm-mem-hole { + compatible = "qcom,msm-mem-hole"; + qcom,memblock-remove = <0x1c00000 0x4c00000>; /* Address and Size of Hole */ + }; + + sfpb_spinlock: qcom,ipc-spinlock@fd484000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0xfd484000 0x400>; + qcom,num-locks = <8>; + }; + + ldrex_spinlock: qcom,ipc-spinlock@fa00000 { + compatible = "qcom,ipc-spinlock-ldrex"; + reg = <0xfa00000 0x200000>; + status = "disable"; + }; + + cpu-pmu { + compatible = "arm,cortex-a5-pmu"; + qcom,irq-is-percpu; + interrupts = <1 7 0x00>; + }; + + l2-pmu { + compatible = "qcom,l2-pmu"; + interrupts = <0 1 0>; + }; + + /* [houjihai start] gpio keys */ + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + input-name = "gpio-keys"; + key-back { + label = "RESET"; + linux,code = <158>; + gpios = <&msmgpio 15 1>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + /* [houjihai end] */ +}; + +/include/ "msm-pm8019-rpm-regulator.dtsi" +/include/ "msm-pm8019.dtsi" +/include/ "msm9625-regulator.dtsi" + +&pm8019_vadc { + chan@31 { + label = "batt_id_therm"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + /* [linyunfeng] Detect voltage on resistor*/ + chan@10 { + label = "vol_detect"; + reg = <0x10>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + /* [linyunfeng] Detect battery voltage */ + chan@11 { + label = "vbat"; + reg = <0x11>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@33 { + label = "pa_therm0"; + reg = <0x33>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@34 { + label = "pa_therm1"; + reg = <0x34>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@32 { + label = "xo_therm"; + reg = <0x32>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@3c { + label = "xo_therm_amux"; + reg = <0x3c>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@13 { + label = "case_therm"; + reg = <0x13>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@15 { + label = "ambient_therm"; + reg = <0x15>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8019_adc_tm { + /* Channel Node */ + chan@33 { + label = "pa_therm0"; + reg = <0x33>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x48>; + qcom,thermal-node; + }; + + chan@34 { + label = "pa_therm1"; + reg = <0x34>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmkrypton-sim.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmkrypton-sim.dts new file mode 100644 index 000000000..1872a36b9 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmkrypton-sim.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msmkrypton.dtsi" + +/ { + model = "Qualcomm MSM KRYPTON SIM"; + compatible = "qcom,msmkrypton-sim", "qcom,msmkrypton", "qcom,sim"; + qcom,msm-id = <187 16 0>; +}; + +&uartdm3{ + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmkrypton.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmkrypton.dtsi new file mode 100644 index 000000000..4b032d86d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmkrypton.dtsi @@ -0,0 +1,120 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM KRYPTON"; + compatible = "qcom,msmkrypton"; + interrupt-parent = <&intc>; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <89>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + + frame@f9029000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0xf9029000 0x1000>; + status = "disabled"; + }; + }; + + uartdm3: serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-ion.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-ion.dtsi new file mode 100644 index 000000000..ea954b89c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-ion.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@30 { /* SYSTEM HEAP */ + reg = <30>; + }; + + qcom,ion-heap@21 { /* SYSTEM CONTIG HEAP */ + reg = <21>; + }; + + qcom,ion-heap@25 { /* IOMMU HEAP */ + reg = <25>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-rumi.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-rumi.dts new file mode 100644 index 000000000..9a679a4fd --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-rumi.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msmsamarium.dtsi" + +/ { + model = "Qualcomm MSM SAMARIUM RUMI"; + compatible = "qcom,msmsamarium-rumi", "qcom,msmsamarium", "qcom,rumi"; + qcom,msm-id = <195 0 0>; +}; + +&uartblsp0dm2{ + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-sim.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-sim.dts new file mode 100644 index 000000000..4acffae18 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium-sim.dts @@ -0,0 +1,55 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/include/ "msmsamarium.dtsi" + +/ { + model = "Qualcomm MSM SAMARIUM SIM"; + compatible = "qcom,msmsamarium-sim", "qcom,msmsamarium", "qcom,sim"; + qcom,msm-id = <195 0 0>; +}; + +&uartblsp0dm2{ + status = "ok"; +}; + +&sdcc1 { + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + qcom,nonremovable; + status = "ok"; +}; + +&sdcc2 { + qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; + qcom,sup-voltages = <2950 2950>; + + qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ + qcom,pad-drv-on = <0x4 0x4 0x4>; /* 10mA, 10mA, 10mA */ + qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ + + qcom,xpc; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + qcom,current-limit = <800>; + + status = "ok"; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium.dtsi new file mode 100644 index 000000000..81699b689 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/msmsamarium.dtsi @@ -0,0 +1,90 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM SAMARIUM"; + compatible = "qcom,msmsamarium"; + interrupt-parent = <&intc>; + soc: soc { }; +}; + +/include/ "msmsamarium-ion.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + ngpio = <145>; + interrupts = <0 208 0>; + qcom,direct-connect-irqs = <8>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0 1 3 0>; + clock-frequency = <19200000>; + }; + + uartblsp0dm2: serial@f991f000 { + compatible = "qcom,msm-lsuart-v14"; + reg = <0xf991f000 0x1000>; + interrupts = <0 109 0>; + status = "disabled"; + }; + + qcom,msm-imem@fe805000 { + compatible = "qcom,msm-imem"; + reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ + }; + + sdcc1: qcom,sdcc@f9824000 { + cell-index = <1>; /* SDC1 eMMC slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf9824000 0x800>; + reg-names = "core_mem"; + interrupts = <0 123 0>; + interrupt-names = "core_irq"; + + qcom,bus-width = <8>; + status = "disabled"; + }; + + sdcc2: qcom,sdcc@f98a4000 { + cell-index = <2>; /* SDC2 SD card slot */ + compatible = "qcom,msm-sdcc"; + reg = <0xf98a4000 0x800>; + reg-names = "core_mem"; + interrupts = <0 125 0>; + interrupt-names = "core_irq"; + + qcom,bus-width = <4>; + status = "disabled"; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap2.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap2.dtsi new file mode 100644 index 000000000..f2ab4ea7c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap2.dtsi @@ -0,0 +1,67 @@ +/* + * Device Tree Source for OMAP2 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + cpus { + cpu@0 { + compatible = "arm,arm1136jf-s"; + }; + }; + + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap2-mpu"; + ti,hwmods = "mpu"; + }; + }; + + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@1 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@4806e000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3-beagle.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3-beagle.dts new file mode 100644 index 000000000..9f72cd4cf --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3-beagle.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TI OMAP3 BeagleBoard"; + compatible = "ti,omap3-beagle", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3-evm.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3-evm.dts new file mode 100644 index 000000000..2eee16ec5 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3-evm.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; + compatible = "ti,omap3-evm", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3.dtsi new file mode 100644 index 000000000..c6121357c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap3.dtsi @@ -0,0 +1,117 @@ +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,omap3430", "ti,omap3"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + + iva { + compatible = "ti,iva2.2"; + ti,hwmods = "iva"; + + dsp { + compatible = "ti,omap3-c64"; + }; + }; + }; + + /* + * XXX: Use a flat representation of the OMAP3 interconnect. + * The real OMAP interconnect network is quite complex. + * Since that will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <96>; + reg = <0x48200000 0x1000>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@49020000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + i2c1: i2c@48070000 { + compatible = "ti,omap3-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap3-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap3-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4-panda.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4-panda.dts new file mode 100644 index 000000000..9755ad591 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4-panda.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap4.dtsi" + +/ { + model = "TI OMAP4 PandaBoard"; + compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4-sdp.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4-sdp.dts new file mode 100644 index 000000000..63c6b2b2b --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4-sdp.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap4.dtsi" + +/ { + model = "TI OMAP4 SDP board"; + compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4.dtsi new file mode 100644 index 000000000..3d35559e7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/omap4.dtsi @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Carveout for multimedia usecases + * It should be the last 48MB of the first 512MB memory part + * In theory, it should not even exist. That zone should be reserved + * dynamically during the .reserve callback. + */ +/memreserve/ 0x9d000000 0x03000000; + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,omap4430", "ti,omap4"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap4-mpu"; + ti,hwmods = "mpu"; + }; + + dsp { + compatible = "ti,omap3-c64"; + ti,hwmods = "dsp"; + }; + + iva { + compatible = "ti,ivahd"; + ti,hwmods = "iva"; + }; + }; + + /* + * XXX: Use a flat representation of the OMAP4 interconnect. + * The real OMAP interconnect network is quite complex. + * + * MPU -+-- MPU_PRIVATE - GIC, L2 + * | + * +----------------+----------+ + * | | | + * + +- EMIF - DDR | + * | | | + * | + +--------+ + * | | | + * | +- L4_ABE - AESS, MCBSP, TIMERs... + * | | + * +- L3_MAIN --+- L4_CORE - IPs... + * | + * +- L4_PER - IPs... + * | + * +- L4_CFG -+- L4_WKUP - IPs... + * | | + * | +- IPs... + * +- IPU ----+ + * | | + * +- DSP ----+ + * | | + * +- DSS ----+ + * + * Since that will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp { + compatible = "ti,omap4-l3-noc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; + + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@48020000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@4806e000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + i2c1: i2c@48070000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + + i2c4: i2c@48350000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c4"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc3x2.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc3x2.dtsi new file mode 100644 index 000000000..f0a8c2068 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc3x2.dtsi @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2011 Picochip, Jamie Iles + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/include/ "skeleton.dtsi" +/ { + model = "Picochip picoXcell PC3X2"; + compatible = "picochip,pc3x2"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,1176jz-s"; + clock-frequency = <400000000>; + reg = <0>; + d-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-line-size = <32>; + i-cache-size = <32768>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pclk: clock@0 { + compatible = "fixed-clock"; + clock-outputs = "bus", "pclk"; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + }; + + paxi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80000000 0x400000>; + + emac: gem@30000 { + compatible = "cadence,gem"; + reg = <0x30000 0x10000>; + interrupts = <31>; + }; + + dmac1: dmac@40000 { + compatible = "snps,dw-dmac"; + reg = <0x40000 0x10000>; + interrupts = <25>; + }; + + dmac2: dmac@50000 { + compatible = "snps,dw-dmac"; + reg = <0x50000 0x10000>; + interrupts = <26>; + }; + + vic0: interrupt-controller@60000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x60000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@64000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x64000 0x1000>; + #interrupt-cells = <1>; + }; + + fuse: picoxcell-fuse@80000 { + compatible = "picoxcell,fuse-pc3x2"; + reg = <0x80000 0x10000>; + }; + + ssi: picoxcell-spi@90000 { + compatible = "picoxcell,spi"; + reg = <0x90000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <10>; + }; + + ipsec: spacc@100000 { + compatible = "picochip,spacc-ipsec"; + reg = <0x100000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <24>; + ref-clock = <&pclk>, "ref"; + }; + + srtp: spacc@140000 { + compatible = "picochip,spacc-srtp"; + reg = <0x140000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <23>; + }; + + l2_engine: spacc@180000 { + compatible = "picochip,spacc-l2"; + reg = <0x180000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <22>; + ref-clock = <&pclk>, "ref"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x80000>; + + rtc0: rtc@00000 { + compatible = "picochip,pc3x2-rtc"; + clock-freq = <200000000>; + reg = <0x00000 0xf>; + interrupt-parent = <&vic1>; + interrupts = <8>; + }; + + timer0: timer@10000 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <4>; + clock-freq = <200000000>; + reg = <0x10000 0x14>; + }; + + timer1: timer@10014 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <5>; + clock-freq = <200000000>; + reg = <0x10014 0x14>; + }; + + timer2: timer@10028 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <6>; + clock-freq = <200000000>; + reg = <0x10028 0x14>; + }; + + timer3: timer@1003c { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <7>; + clock-freq = <200000000>; + reg = <0x1003c 0x14>; + }; + + gpio: gpio@20000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-io-width = <4>; + + banka: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <8>; + + regoffset-dat = <0x50>; + regoffset-set = <0x00>; + regoffset-dirout = <0x04>; + }; + + bankb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <8>; + + regoffset-dat = <0x54>; + regoffset-set = <0x0c>; + regoffset-dirout = <0x10>; + }; + }; + + uart0: uart@30000 { + compatible = "snps,dw-apb-uart"; + reg = <0x30000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <10>; + clock-frequency = <3686400>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: uart@40000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <9>; + clock-frequency = <3686400>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + wdog: watchdog@50000 { + compatible = "snps,dw-apb-wdg"; + reg = <0x50000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <11>; + bus-clock = <&pclk>, "bus"; + }; + }; + }; + + rwid-axi { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + ebi@50000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x08000000 + 1 0 0x48000000 0x08000000 + 2 0 0x50000000 0x08000000 + 3 0 0x58000000 0x08000000>; + }; + + axi2pico@c0000000 { + compatible = "picochip,axi2pico-pc3x2"; + reg = <0xc0000000 0x10000>; + interrupts = <13 14 15 16 17 18 19 20 21>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc3x3.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc3x3.dtsi new file mode 100644 index 000000000..daa962d19 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc3x3.dtsi @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2011 Picochip, Jamie Iles + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/include/ "skeleton.dtsi" +/ { + model = "Picochip picoXcell PC3X3"; + compatible = "picochip,pc3x3"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,1176jz-s"; + cpu-clock = <&arm_clk>, "cpu"; + reg = <0>; + d-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-line-size = <32>; + i-cache-size = <32768>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clkgate: clkgate@800a0048 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x800a0048 4>; + compatible = "picochip,pc3x3-clk-gate"; + + tzprot_clk: clock@0 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <0>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + spi_clk: clock@1 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <1>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + dmac0_clk: clock@2 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <2>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + dmac1_clk: clock@3 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <3>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + ebi_clk: clock@4 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <4>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + ipsec_clk: clock@5 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <5>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + l2_clk: clock@6 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <6>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + trng_clk: clock@7 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <7>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + fuse_clk: clock@8 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <8>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + + otp_clk: clock@9 { + compatible = "picochip,pc3x3-gated-clk"; + clock-outputs = "bus"; + picochip,clk-disable-bit = <9>; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + }; + + arm_clk: clock@11 { + compatible = "picochip,pc3x3-pll"; + reg = <0x800a0050 0x8>; + picochip,min-freq = <140000000>; + picochip,max-freq = <700000000>; + ref-clock = <&ref_clk>, "ref"; + clock-outputs = "cpu"; + }; + + pclk: clock@12 { + compatible = "fixed-clock"; + clock-outputs = "bus", "pclk"; + clock-frequency = <200000000>; + ref-clock = <&ref_clk>, "ref"; + }; + }; + + paxi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80000000 0x400000>; + + emac: gem@30000 { + compatible = "cadence,gem"; + reg = <0x30000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <31>; + }; + + dmac1: dmac@40000 { + compatible = "snps,dw-dmac"; + reg = <0x40000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <25>; + }; + + dmac2: dmac@50000 { + compatible = "snps,dw-dmac"; + reg = <0x50000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <26>; + }; + + vic0: interrupt-controller@60000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x60000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@64000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + reg = <0x64000 0x1000>; + #interrupt-cells = <1>; + }; + + fuse: picoxcell-fuse@80000 { + compatible = "picoxcell,fuse-pc3x3"; + reg = <0x80000 0x10000>; + }; + + ssi: picoxcell-spi@90000 { + compatible = "picoxcell,spi"; + reg = <0x90000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <10>; + }; + + ipsec: spacc@100000 { + compatible = "picochip,spacc-ipsec"; + reg = <0x100000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <24>; + ref-clock = <&ipsec_clk>, "ref"; + }; + + srtp: spacc@140000 { + compatible = "picochip,spacc-srtp"; + reg = <0x140000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <23>; + }; + + l2_engine: spacc@180000 { + compatible = "picochip,spacc-l2"; + reg = <0x180000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <22>; + ref-clock = <&l2_clk>, "ref"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x80000>; + + rtc0: rtc@00000 { + compatible = "picochip,pc3x2-rtc"; + clock-freq = <200000000>; + reg = <0x00000 0xf>; + interrupt-parent = <&vic0>; + interrupts = <8>; + }; + + timer0: timer@10000 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <4>; + clock-freq = <200000000>; + reg = <0x10000 0x14>; + }; + + timer1: timer@10014 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <5>; + clock-freq = <200000000>; + reg = <0x10014 0x14>; + }; + + gpio: gpio@20000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg-io-width = <4>; + + banka: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <8>; + + regoffset-dat = <0x50>; + regoffset-set = <0x00>; + regoffset-dirout = <0x04>; + }; + + bankb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <16>; + + regoffset-dat = <0x54>; + regoffset-set = <0x0c>; + regoffset-dirout = <0x10>; + }; + + bankd: gpio-controller@2 { + compatible = "snps,dw-apb-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + gpio-generic,nr-gpio = <30>; + + regoffset-dat = <0x5c>; + regoffset-set = <0x24>; + regoffset-dirout = <0x28>; + }; + }; + + uart0: uart@30000 { + compatible = "snps,dw-apb-uart"; + reg = <0x30000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <10>; + clock-frequency = <3686400>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: uart@40000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <9>; + clock-frequency = <3686400>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + wdog: watchdog@50000 { + compatible = "snps,dw-apb-wdg"; + reg = <0x50000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <11>; + bus-clock = <&pclk>, "bus"; + }; + + timer2: timer@60000 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <6>; + clock-freq = <200000000>; + reg = <0x60000 0x14>; + }; + + timer3: timer@60014 { + compatible = "picochip,pc3x2-timer"; + interrupt-parent = <&vic0>; + interrupts = <7>; + clock-freq = <200000000>; + reg = <0x60014 0x14>; + }; + }; + }; + + rwid-axi { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + ebi@50000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x08000000 + 1 0 0x48000000 0x08000000 + 2 0 0x50000000 0x08000000 + 3 0 0x58000000 0x08000000>; + }; + + axi2pico@c0000000 { + compatible = "picochip,axi2pico-pc3x3"; + reg = <0xc0000000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <13 14 15 16 17 18 19 20 21>; + }; + + otp@ffff8000 { + compatible = "picochip,otp-pc3x3"; + reg = <0xffff8000 0x8000>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc7302-pc3x2.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc7302-pc3x2.dts new file mode 100644 index 000000000..1297414dd --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc7302-pc3x2.dts @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2011 Picochip, Jamie Iles + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "picoxcell-pc3x2.dtsi" +/ { + model = "Picochip PC7302 (PC3X2)"; + compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2"; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + linux,stdout-path = &uart0; + }; + + clocks { + ref_clk: clock@1 { + compatible = "fixed-clock"; + clock-outputs = "ref"; + clock-frequency = <20000000>; + }; + }; + + rwid-axi { + ebi@50000000 { + nand: gpio-nand@2,0 { + compatible = "gpio-control-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <2 0x0000 0x1000>; + bus-clock = <&pclk>, "bus"; + gpio-control-nand,io-sync-reg = + <0x00000000 0x80220000>; + + gpios = <&banka 1 0 /* rdy */ + &banka 2 0 /* nce */ + &banka 3 0 /* ale */ + &banka 4 0 /* cle */ + 0 /* nwp */>; + + boot@100000 { + label = "Boot"; + reg = <0x100000 0x80000>; + }; + + redundant-boot@200000 { + label = "Redundant Boot"; + reg = <0x200000 0x80000>; + }; + + boot-env@300000 { + label = "Boot Evironment"; + reg = <0x300000 0x20000>; + }; + + redundant-boot-env@320000 { + label = "Redundant Boot Environment"; + reg = <0x300000 0x20000>; + }; + + kernel@380000 { + label = "Kernel"; + reg = <0x380000 0x800000>; + }; + + fs@b80000 { + label = "File System"; + reg = <0xb80000 0xf480000>; + }; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc7302-pc3x3.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc7302-pc3x3.dts new file mode 100644 index 000000000..9e317a4f4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/picoxcell-pc7302-pc3x3.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2011 Picochip, Jamie Iles + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/include/ "picoxcell-pc3x3.dtsi" +/ { + model = "Picochip PC7302 (PC3X3)"; + compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3"; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + linux,stdout-path = &uart0; + }; + + clocks { + ref_clk: clock@10 { + compatible = "fixed-clock"; + clock-outputs = "ref"; + clock-frequency = <20000000>; + }; + + clkgate: clkgate@800a0048 { + clock@4 { + picochip,clk-no-disable; + }; + }; + }; + + rwid-axi { + ebi@50000000 { + nand: gpio-nand@2,0 { + compatible = "gpio-control-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <2 0x0000 0x1000>; + bus-clock = <&ebi_clk>, "bus"; + gpio-control-nand,io-sync-reg = + <0x00000000 0x80220000>; + + gpios = <&banka 1 0 /* rdy */ + &banka 2 0 /* nce */ + &banka 3 0 /* ale */ + &banka 4 0 /* cle */ + 0 /* nwp */>; + + boot@100000 { + label = "Boot"; + reg = <0x100000 0x80000>; + }; + + redundant-boot@200000 { + label = "Redundant Boot"; + reg = <0x200000 0x80000>; + }; + + boot-env@300000 { + label = "Boot Evironment"; + reg = <0x300000 0x20000>; + }; + + redundant-boot-env@320000 { + label = "Redundant Boot Environment"; + reg = <0x300000 0x20000>; + }; + + kernel@380000 { + label = "Kernel"; + reg = <0x380000 0x800000>; + }; + + fs@b80000 { + label = "File System"; + reg = <0xb80000 0xf480000>; + }; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/prima2-cb.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/prima2-cb.dts new file mode 100644 index 000000000..34ae3a64b --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/prima2-cb.dts @@ -0,0 +1,424 @@ +/dts-v1/; +/ { + model = "SiRF Prima2 eVB"; + compatible = "sirf,prima2-cb", "sirf,prima2"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + memory { + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1"; + linux,stdout-path = &uart1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* from bootloader */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0x80000000>; + + l2-cache-controller@80040000 { + compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; + reg = <0x80040000 0x1000>; + interrupts = <59>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0 0x40000000>; + }; + + intc: interrupt-controller@80020000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "sirf,prima2-intc"; + reg = <0x80020000 0x1000>; + }; + + sys-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x88000000 0x88000000 0x40000>; + + clock-controller@88000000 { + compatible = "sirf,prima2-clkc"; + reg = <0x88000000 0x1000>; + interrupts = <3>; + }; + + reset-controller@88010000 { + compatible = "sirf,prima2-rstc"; + reg = <0x88010000 0x1000>; + }; + + rsc-controller@88020000 { + compatible = "sirf,prima2-rsc"; + reg = <0x88020000 0x1000>; + }; + }; + + mem-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90000000 0x90000000 0x10000>; + + memory-controller@90000000 { + compatible = "sirf,prima2-memc"; + reg = <0x90000000 0x10000>; + interrupts = <27>; + }; + }; + + disp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90010000 0x90010000 0x30000>; + + display@90010000 { + compatible = "sirf,prima2-lcd"; + reg = <0x90010000 0x20000>; + interrupts = <30>; + }; + + vpp@90020000 { + compatible = "sirf,prima2-vpp"; + reg = <0x90020000 0x10000>; + interrupts = <31>; + }; + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x8000000>; + + graphics@98000000 { + compatible = "powervr,sgx531"; + reg = <0x98000000 0x8000000>; + interrupts = <6>; + }; + }; + + multimedia-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa0000000 0xa0000000 0x8000000>; + + multimedia@a0000000 { + compatible = "sirf,prima2-video-codec"; + reg = <0xa0000000 0x8000000>; + interrupts = <5>; + }; + }; + + dsp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa8000000 0xa8000000 0x2000000>; + + dspif@a8000000 { + compatible = "sirf,prima2-dspif"; + reg = <0xa8000000 0x10000>; + interrupts = <9>; + }; + + gps@a8010000 { + compatible = "sirf,prima2-gps"; + reg = <0xa8010000 0x10000>; + interrupts = <7>; + }; + + dsp@a9000000 { + compatible = "sirf,prima2-dsp"; + reg = <0xa9000000 0x1000000>; + interrupts = <8>; + }; + }; + + peri-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0xb0000000 0x180000>; + + timer@b0020000 { + compatible = "sirf,prima2-tick"; + reg = <0xb0020000 0x1000>; + interrupts = <0>; + }; + + nand@b0030000 { + compatible = "sirf,prima2-nand"; + reg = <0xb0030000 0x10000>; + interrupts = <41>; + }; + + audio@b0040000 { + compatible = "sirf,prima2-audio"; + reg = <0xb0040000 0x10000>; + interrupts = <35>; + }; + + uart0: uart@b0050000 { + cell-index = <0>; + compatible = "sirf,prima2-uart"; + reg = <0xb0050000 0x10000>; + interrupts = <17>; + }; + + uart1: uart@b0060000 { + cell-index = <1>; + compatible = "sirf,prima2-uart"; + reg = <0xb0060000 0x10000>; + interrupts = <18>; + }; + + uart2: uart@b0070000 { + cell-index = <2>; + compatible = "sirf,prima2-uart"; + reg = <0xb0070000 0x10000>; + interrupts = <19>; + }; + + usp0: usp@b0080000 { + cell-index = <0>; + compatible = "sirf,prima2-usp"; + reg = <0xb0080000 0x10000>; + interrupts = <20>; + }; + + usp1: usp@b0090000 { + cell-index = <1>; + compatible = "sirf,prima2-usp"; + reg = <0xb0090000 0x10000>; + interrupts = <21>; + }; + + usp2: usp@b00a0000 { + cell-index = <2>; + compatible = "sirf,prima2-usp"; + reg = <0xb00a0000 0x10000>; + interrupts = <22>; + }; + + dmac0: dma-controller@b00b0000 { + cell-index = <0>; + compatible = "sirf,prima2-dmac"; + reg = <0xb00b0000 0x10000>; + interrupts = <12>; + }; + + dmac1: dma-controller@b0160000 { + cell-index = <1>; + compatible = "sirf,prima2-dmac"; + reg = <0xb0160000 0x10000>; + interrupts = <13>; + }; + + vip@b00C0000 { + compatible = "sirf,prima2-vip"; + reg = <0xb00C0000 0x10000>; + }; + + spi0: spi@b00d0000 { + cell-index = <0>; + compatible = "sirf,prima2-spi"; + reg = <0xb00d0000 0x10000>; + interrupts = <15>; + }; + + spi1: spi@b0170000 { + cell-index = <1>; + compatible = "sirf,prima2-spi"; + reg = <0xb0170000 0x10000>; + interrupts = <16>; + }; + + i2c0: i2c@b00e0000 { + cell-index = <0>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00e0000 0x10000>; + interrupts = <24>; + }; + + i2c1: i2c@b00f0000 { + cell-index = <1>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00f0000 0x10000>; + interrupts = <25>; + }; + + tsc@b0110000 { + compatible = "sirf,prima2-tsc"; + reg = <0xb0110000 0x10000>; + interrupts = <33>; + }; + + gpio: gpio-controller@b0120000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,prima2-gpio-pinmux"; + reg = <0xb0120000 0x10000>; + gpio-controller; + interrupt-controller; + }; + + pwm@b0130000 { + compatible = "sirf,prima2-pwm"; + reg = <0xb0130000 0x10000>; + }; + + efusesys@b0140000 { + compatible = "sirf,prima2-efuse"; + reg = <0xb0140000 0x10000>; + }; + + pulsec@b0150000 { + compatible = "sirf,prima2-pulsec"; + reg = <0xb0150000 0x10000>; + interrupts = <48>; + }; + + pci-iobg { + compatible = "sirf,prima2-pciiobg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x56000000 0x1b00000>; + + sd0: sdhci@56000000 { + cell-index = <0>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56000000 0x100000>; + interrupts = <38>; + }; + + sd1: sdhci@56100000 { + cell-index = <1>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56100000 0x100000>; + interrupts = <38>; + }; + + sd2: sdhci@56200000 { + cell-index = <2>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56200000 0x100000>; + interrupts = <23>; + }; + + sd3: sdhci@56300000 { + cell-index = <3>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56300000 0x100000>; + interrupts = <23>; + }; + + sd4: sdhci@56400000 { + cell-index = <4>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56400000 0x100000>; + interrupts = <39>; + }; + + sd5: sdhci@56500000 { + cell-index = <5>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56500000 0x100000>; + interrupts = <39>; + }; + + pci-copy@57900000 { + compatible = "sirf,prima2-pcicp"; + reg = <0x57900000 0x100000>; + interrupts = <40>; + }; + + rom-interface@57a00000 { + compatible = "sirf,prima2-romif"; + reg = <0x57a00000 0x100000>; + }; + }; + }; + + rtc-iobg { + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80030000 0x10000>; + + gpsrtc@1000 { + compatible = "sirf,prima2-gpsrtc"; + reg = <0x1000 0x1000>; + interrupts = <55 56 57>; + }; + + sysrtc@2000 { + compatible = "sirf,prima2-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <52 53 54>; + }; + + pwrc@3000 { + compatible = "sirf,prima2-pwrc"; + reg = <0x3000 0x1000>; + interrupts = <32>; + }; + }; + + uus-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb8000000 0xb8000000 0x40000>; + + usb0: usb@b00e0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8000000 0x10000>; + interrupts = <10>; + }; + + usb1: usb@b00f0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8010000 0x10000>; + interrupts = <11>; + }; + + sata@b00f0000 { + compatible = "synopsys,dwc-ahsata"; + reg = <0xb8020000 0x10000>; + interrupts = <37>; + }; + + security@b00f0000 { + compatible = "sirf,prima2-security"; + reg = <0xb8030000 0x10000>; + interrupts = <42>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/pxa168-aspenite.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/pxa168-aspenite.dts new file mode 100644 index 000000000..e762facb3 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/pxa168-aspenite.dts @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "pxa168.dtsi" + +/ { + model = "Marvell PXA168 Aspenite Development Board"; + compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; + }; + + memory { + reg = <0x00000000 0x04000000>; + }; + + soc { + apb@d4000000 { + uart1: uart@d4017000 { + status = "okay"; + }; + twsi1: i2c@d4011000 { + status = "okay"; + }; + rtc: rtc@d4010000 { + status = "okay"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/pxa168.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/pxa168.dtsi new file mode 100644 index 000000000..d32d5128f --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/pxa168.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + i2c0 = &twsi1; + i2c1 = &twsi2; + }; + + intc: intc-interrupt-controller@d4282000 { + compatible = "mrvl,mmp-intc", "mrvl,intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + apb@d4000000 { /* APB */ + compatible = "mrvl,apb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + uart1: uart@d4017000 { + compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + reg = <0xd4017000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + uart2: uart@d4018000 { + compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + reg = <0xd4018000 0x1000>; + interrupts = <28>; + status = "disabled"; + }; + + uart3: uart@d4026000 { + compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + reg = <0xd4026000 0x1000>; + interrupts = <29>; + status = "disabled"; + }; + + gpio: gpio@d4019000 { + compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio"; + reg = <0xd4019000 0x1000>; + interrupts = <49>; + interrupt-names = "gpio_mux"; + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; + reg = <0xd4011000 0x1000>; + interrupts = <7>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4025000 { + compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; + reg = <0xd4025000 0x1000>; + interrupts = <58>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <5 6>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/qpic-panel-ili-qvga.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/qpic-panel-ili-qvga.dtsi new file mode 100644 index 000000000..089f1125d --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/qpic-panel-ili-qvga.dtsi @@ -0,0 +1,27 @@ +/* Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,mdss_lcdc_ili9341_qvga { + compatible = "qcom,mdss-qpic-panel"; + label = "ili qvga lcdc panel"; + vdd-supply = <&pm8019_l11>; + avdd-supply = <&pm8019_l14>; + qcom,cs-gpio = <&msmgpio 21 0>; + qcom,te-gpio = <&msmgpio 22 0>; + qcom,rst-gpio = <&msmgpio 23 0>; + qcom,ad8-gpio = <&msmgpio 20 0>; + qcom,mdss-pan-res = <240 320>; + qcom,mdss-pan-bpp = <18>; + qcom,refresh_rate = <60>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/skeleton.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/skeleton.dtsi new file mode 100644 index 000000000..f9988cd78 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/skeleton.dtsi @@ -0,0 +1,18 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { + #address-cells = <1>; + #size-cells = <1>; + device_type = "memory"; + reg = <0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/skeleton64.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/skeleton64.dtsi new file mode 100644 index 000000000..5bf6a82f0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/skeleton64.dtsi @@ -0,0 +1,18 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + chosen { }; + aliases { }; + memory { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + reg = <0 0 0 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/snowball.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/snowball.dts new file mode 100644 index 000000000..359c6d679 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/snowball.dts @@ -0,0 +1,139 @@ +/* + * Copyright 2011 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "db8500.dtsi" + +/ { + model = "Calao Systems Snowball platform with device tree"; + compatible = "calaosystems,snowball-a9500"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <2>; + label = "userpb"; + gpios = <&gpio1 0>; + }; + button@2 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <3>; + label = "userpb"; + gpios = <&gpio4 23>; + }; + button@3 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <4>; + label = "userpb"; + gpios = <&gpio4 23>; + }; + button@4 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <5>; + label = "userpb"; + gpios = <&gpio5 1>; + }; + button@5 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <6>; + label = "userpb"; + gpios = <&gpio5 2>; + }; + }; + + leds { + compatible = "gpio-leds"; + used-led { + label = "user_led"; + gpios = <&gpio4 14>; + }; + }; + + soc-u9500 { + + external-bus@50000000 { + compatible = "simple-bus"; + reg = <0x50000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ethernet@50000000 { + compatible = "smsc,9111"; + reg = <0x50000000 0x10000>; + interrupts = <12>; + interrupt-parent = <&gpio4>; + }; + }; + + sdi@80126000 { + status = "enabled"; + cd-gpios = <&gpio6 26>; + }; + + sdi@80114000 { + status = "enabled"; + }; + + uart@80120000 { + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; + + i2c@80004000 { + tc3589x@42 { + //compatible = "tc3589x"; + reg = <0x42>; + interrupts = <25>; + interrupt-parent = <&gpio6>; + }; + tps61052@33 { + //compatible = "tps61052"; + reg = <0x33>; + }; + }; + + i2c@80128000 { + lp5521@0x33 { + // compatible = "lp5521"; + reg = <0x33>; + }; + lp5521@0x34 { + // compatible = "lp5521"; + reg = <0x34>; + }; + bh1780@0x29 { + // compatible = "rohm,bh1780gli"; + reg = <0x33>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/spear600-evb.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/spear600-evb.dts new file mode 100644 index 000000000..636292e18 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/spear600-evb.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2012 Stefan Roese + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear600.dtsi" + +/ { + model = "ST SPEAr600 Evaluation Board"; + compatible = "st,spear600-evb", "st,spear600"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0 0x10000000>; + }; + + ahb { + gmac: ethernet@e0800000 { + phy-mode = "gmii"; + status = "okay"; + }; + + apb { + serial@d0000000 { + status = "okay"; + }; + + serial@d0080000 { + status = "okay"; + }; + + i2c@d0200000 { + clock-frequency = <400000>; + status = "okay"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/spear600.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/spear600.dtsi new file mode 100644 index 000000000..ebe0885a2 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/spear600.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright 2012 Stefan Roese + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "st,spear600"; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + vic0: interrupt-controller@f1100000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1100000 0x1000>; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@f1000000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1000000 0x1000>; + #interrupt-cells = <1>; + }; + + gmac: ethernet@e0800000 { + compatible = "st,spear600-gmac"; + reg = <0xe0800000 0x8000>; + interrupt-parent = <&vic1>; + interrupts = <24 23>; + interrupt-names = "macirq", "eth_wake_irq"; + status = "disabled"; + }; + + fsmc: flash@d1800000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd1800000 0x1000 /* FSMC Register */ + 0xd2000000 0x4000>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + st,ale-off = <0x20000>; + st,cle-off = <0x10000>; + status = "disabled"; + }; + + smi: flash@fc000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xfc000000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <12>; + status = "disabled"; + }; + + ehci@e1800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe1800000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <27>; + status = "disabled"; + }; + + ehci@e2000000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe2000000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <29>; + status = "disabled"; + }; + + ohci@e1900000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe1900000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <26>; + status = "disabled"; + }; + + ohci@e2100000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe2100000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <28>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + serial@d0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0000000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <24>; + status = "disabled"; + }; + + serial@d0080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0080000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <25>; + status = "disabled"; + }; + + /* local/cpu GPIO */ + gpio0: gpio@f0100000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xf0100000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <18>; + }; + + /* basic GPIO */ + gpio1: gpio@fc980000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xfc980000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <19>; + }; + + /* appl GPIO */ + gpio2: gpio@d8100000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xd8100000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <4>; + }; + + i2c@d0200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xd0200000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <28>; + status = "disabled"; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-cardhu.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-cardhu.dts new file mode 100644 index 000000000..ac3fb7558 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-cardhu.dts @@ -0,0 +1,70 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = < 0x80000000 0x40000000 >; + }; + + serial@70006000 { + clock-frequency = < 408000000 >; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + + i2c@7000c000 { + clock-frequency = <100000>; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + }; + + i2c@7000c700 { + clock-frequency = <100000>; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + }; + + sdhci@78000000 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + }; + + sdhci@78000200 { + status = "disable"; + }; + + sdhci@78000400 { + status = "disable"; + }; + + sdhci@78000400 { + support-8bit; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-harmony.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-harmony.dts new file mode 100644 index 000000000..6e8447dc0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-harmony.dts @@ -0,0 +1,115 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Harmony evaluation board"; + compatible = "nvidia,harmony", "nvidia,tegra20"; + + memory@0 { + reg = < 0x00000000 0x40000000 >; + }; + + pmc@7000f400 { + nvidia,invert-interrupt; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = < 187 0x04 >; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + i2s@70002a00 { + status = "disable"; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-harmony", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Harmony"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ + nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + support-8bit; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-paz00.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-paz00.dts new file mode 100644 index 000000000..6c02abb46 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-paz00.dts @@ -0,0 +1,134 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + memory@0 { + reg = <0x00000000 0x20000000>; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + alc5632: alc5632@1e { + compatible = "realtek,alc5632"; + reg = <0x1e>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "disable"; + }; + + nvec@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,nvec"; + reg = <0x7000C500 0x100>; + interrupts = <0 92 0x04>; + clock-frequency = <80000>; + request-gpios = <&gpio 170 0>; + slave-addr = <138>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + + adt7461@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + + i2s@70002a00 { + status = "disable"; + }; + + sound { + compatible = "nvidia,tegra-audio-alc5632-paz00", + "nvidia,tegra-audio-alc5632"; + + nvidia,model = "Compal PAZ00"; + + nvidia,audio-routing = + "Int Spk", "SPKOUT", + "Int Spk", "SPKOUTN", + "Headset Mic", "MICBIAS1", + "MIC1", "Headset Mic", + "Headset Stereophone", "HPR", + "Headset Stereophone", "HPL", + "DMICDAT", "Digital Mic"; + + nvidia,audio-codec = <&alc5632>; + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + clock-frequency = <216000000>; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + cd-gpios = <&gpio 173 0>; /* gpio PV5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 169 0>; /* gpio PV1 */ + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + support-8bit; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio 79 1>; /* gpio PJ7, active low */ + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wifi { + label = "wifi-led"; + gpios = <&gpio 24 0>; + linux,default-trigger = "rfkill0"; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-seaboard.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-seaboard.dts new file mode 100644 index 000000000..dbf1c5a17 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-seaboard.dts @@ -0,0 +1,175 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Seaboard"; + compatible = "nvidia,seaboard", "nvidia,tegra20"; + + memory { + device_type = "memory"; + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = < 187 0x04 >; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + + adt7461@4c { + compatible = "adt7461"; + reg = <0x4c>; + }; + }; + + i2s@70002a00 { + status = "disable"; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-seaboard", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Seaboard"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1R", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; + + sdhci@c8000600 { + support-8bit; + }; + + usb@c5000000 { + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + dr_mode = "otg"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio 170 1>; /* gpio PV2, active low */ + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + lid { + label = "Lid"; + gpios = <&gpio 23 0>; /* gpio PC7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; + + emc@7000f400 { + emc-table@190000 { + reg = < 190000 >; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 190000 >; + nvidia,emc-registers = < 0x0000000c 0x00000026 + 0x00000009 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x0000059f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000b 0x000000c8 + 0x00000003 0x00000007 0x00000004 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xa06204ae + 0x007dc010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 >; + }; + + emc-table@380000 { + reg = < 380000 >; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 380000 >; + nvidia,emc-registers = < 0x00000017 0x0000004b + 0x00000012 0x00000006 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000b5f + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe044048b + 0x007d8010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 >; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-trimslice.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-trimslice.dts new file mode 100644 index 000000000..252476867 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-trimslice.dts @@ -0,0 +1,77 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + memory@0 { + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "disable"; + }; + + i2s@70002800 { + status = "disable"; + }; + + i2s@70002a00 { + status = "disable"; + }; + + das@70000c00 { + status = "disable"; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 121 0>; + wp-gpios = <&gpio 122 0>; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-ventana.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-ventana.dts new file mode 100644 index 000000000..2dcff8728 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra-ventana.dts @@ -0,0 +1,108 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; + + memory { + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = < 187 0x04 >; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; + }; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + i2s@70002a00 { + status = "disable"; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-ventana", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Ventana"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ + nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; + + sdhci@c8000600 { + support-8bit; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra20.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra20.dtsi new file mode 100644 index 000000000..108e894a8 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra20.dtsi @@ -0,0 +1,210 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra20"; + interrupt-parent = <&intc>; + + pmc@7000f400 { + compatible = "nvidia,tegra20-pmc"; + reg = <0x7000e400 0x400>; + }; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 56 0x04 + 0 57 0x04>; + }; + + apbdma: dma@6000a000 { + compatible = "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1200>; + interrupts = < 0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 0 38 0x04 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 0 84 0x04 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 0 92 0x04 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c-dvc"; + reg = <0x7000D000 0x200>; + interrupts = < 0 53 0x04 >; + }; + + tegra_i2s1: i2s@70002800 { + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002800 0x200>; + interrupts = < 0 13 0x04 >; + nvidia,dma-request-selector = < &apbdma 2 >; + }; + + tegra_i2s2: i2s@70002a00 { + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002a00 0x200>; + interrupts = < 0 3 0x04 >; + nvidia,dma-request-selector = < &apbdma 1 >; + }; + + das@70000c00 { + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 >; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = < 0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8 >; /* Pad control registers */ + }; + + serial@70006000 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 0 36 0x04 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 0 37 0x04 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 0 46 0x04 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 0 90 0x04 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 0 91 0x04 >; + }; + + emc@7000f400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f400 0x200>; + }; + + sdhci@c8000000 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000000 0x200>; + interrupts = < 0 14 0x04 >; + }; + + sdhci@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = < 0 15 0x04 >; + }; + + sdhci@c8000400 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000400 0x200>; + interrupts = < 0 19 0x04 >; + }; + + sdhci@c8000600 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000600 0x200>; + interrupts = < 0 31 0x04 >; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 0 20 0x04 >; + phy_type = "utmi"; + nvidia,has-legacy-mode; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 0 21 0x04 >; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 0 97 0x04 >; + phy_type = "utmi"; + }; +}; + diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra30.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra30.dtsi new file mode 100644 index 000000000..62a7b39f1 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/tegra30.dtsi @@ -0,0 +1,186 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra30"; + interrupt-parent = <&intc>; + + pmc@7000f400 { + compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; + reg = <0x7000e400 0x400>; + }; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 144 0x04 + 0 145 0x04 + 0 146 0x04 + 0 147 0x04>; + }; + + apbdma: dma@6000a000 { + compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1400>; + interrupts = < 0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04 + 0 128 0x04 + 0 129 0x04 + 0 130 0x04 + 0 131 0x04 + 0 132 0x04 + 0 133 0x04 + 0 134 0x04 + 0 135 0x04 + 0 136 0x04 + 0 137 0x04 + 0 138 0x04 + 0 139 0x04 + 0 140 0x04 + 0 141 0x04 + 0 142 0x04 + 0 143 0x04 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 0 38 0x04 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 0 84 0x04 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 0 92 0x04 >; + }; + + i2c@7000c700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = < 0 120 0x04 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x100>; + interrupts = < 0 53 0x04 >; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04 >; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 0 36 0x04 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 0 37 0x04 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 0 46 0x04 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 0 90 0x04 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 0 91 0x04 >; + }; + + sdhci@78000000 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000000 0x200>; + interrupts = < 0 14 0x04 >; + }; + + sdhci@78000200 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000200 0x200>; + interrupts = < 0 15 0x04 >; + }; + + sdhci@78000400 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000400 0x200>; + interrupts = < 0 19 0x04 >; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000600 0x200>; + interrupts = < 0 31 0x04 >; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra30-pinmux"; + reg = < 0x70000868 0xd0 /* Pad control registers */ + 0x70003000 0x3e0 >; /* Mux registers */ + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/testcases/tests-phandle.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/testcases/tests-phandle.dtsi new file mode 100644 index 000000000..0007d3cd7 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/testcases/tests-phandle.dtsi @@ -0,0 +1,39 @@ + +/ { + testcase-data { + phandle-tests { + provider0: provider0 { + #phandle-cells = <0>; + }; + + provider1: provider1 { + #phandle-cells = <1>; + }; + + provider2: provider2 { + #phandle-cells = <2>; + }; + + provider3: provider3 { + #phandle-cells = <3>; + }; + + consumer-a { + phandle-list = <&provider1 1>, + <&provider2 2 0>, + <0>, + <&provider3 4 4 3>, + <&provider2 5 100>, + <&provider0>, + <&provider1 7>; + phandle-list-names = "first", "second", "third"; + + phandle-list-bad-phandle = <12345678 0 0>; + phandle-list-bad-args = <&provider2 1 0>, + <&provider3 0>; + empty-property; + unterminated-string = [40 41 42 43]; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/testcases/tests.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/testcases/tests.dtsi new file mode 100644 index 000000000..a7c506762 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/testcases/tests.dtsi @@ -0,0 +1 @@ +/include/ "tests-phandle.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/usb_a9g20-dab-mmx.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/usb_a9g20-dab-mmx.dtsi new file mode 100644 index 000000000..ad3eca17c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/usb_a9g20-dab-mmx.dtsi @@ -0,0 +1,96 @@ +/* + * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ + +/ { + ahb { + apb { + usart1: serial@fffb4000 { + status = "okay"; + }; + + usart3: serial@fffd0000 { + status = "okay"; + }; + }; + }; + + i2c-gpio@0 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "user_led1"; + gpios = <&pioB 20 1>; + }; + +/* +* led already used by mother board but active as high +* user_led2 { +* label = "user_led2"; +* gpios = <&pioB 21 1>; +* }; +*/ + user_led3 { + label = "user_led3"; + gpios = <&pioB 22 1>; + }; + + user_led4 { + label = "user_led4"; + gpios = <&pioB 23 1>; + }; + + red { + label = "red"; + gpios = <&pioB 24 1>; + }; + + orange { + label = "orange"; + gpios = <&pioB 30 1>; + }; + + green { + label = "green"; + gpios = <&pioB 31 1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb1 { + label = "user_pb1"; + gpios = <&pioB 25 1>; + linux,code = <0x100>; + }; + + user_pb2 { + label = "user_pb2"; + gpios = <&pioB 13 1>; + linux,code = <0x101>; + }; + + user_pb3 { + label = "user_pb3"; + gpios = <&pioA 26 1>; + linux,code = <0x102>; + }; + + user_pb4 { + label = "user_pb4"; + gpios = <&pioC 9 1>; + linux,code = <0x103>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/usb_a9g20.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/usb_a9g20.dts new file mode 100644 index 000000000..7c2399c53 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/usb_a9g20.dts @@ -0,0 +1,130 @@ +/* + * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "at91sam9g20.dtsi" + +/ { + model = "Calao USB A9G20"; + compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 0>; + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xa0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4a0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7ca0000 0x8360000>; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led { + label = "user_led"; + gpios = <&pioB 21 1>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb { + label = "user_pb"; + gpios = <&pioB 10 1>; + linux,code = <28>; + gpio-key,wakeup; + }; + }; + + i2c@0 { + status = "okay"; + + rv3029c2@56 { + compatible = "rv3029c2"; + reg = <0x56>; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/versatile-ab.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/versatile-ab.dts new file mode 100644 index 000000000..e2fe3195c --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/versatile-ab.dts @@ -0,0 +1,192 @@ +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "ARM Versatile AB"; + compatible = "arm,versatile-ab"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + }; + + memory { + reg = <0x0 0x08000000>; + }; + + flash@34000000 { + compatible = "arm,versatile-flash"; + reg = <0x34000000 0x4000000>; + bank-width = <4>; + }; + + i2c0: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + net@10010000 { + compatible = "smsc,lan91c111"; + reg = <0x10010000 0x10000>; + interrupts = <25>; + }; + + lcd@10008000 { + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: intc@10140000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10140000 0x1000>; + }; + + sic: intc@10003000 { + compatible = "arm,versatile-sic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x10003000 0x1000>; + interrupt-parent = <&vic>; + interrupts = <31>; /* Cascaded to vic */ + }; + + dma@10130000 { + compatible = "arm,pl081", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupts = <17>; + }; + + uart0: uart@101f1000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f1000 0x1000>; + interrupts = <12>; + }; + + uart1: uart@101f2000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f2000 0x1000>; + interrupts = <13>; + }; + + uart2: uart@101f3000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x101f3000 0x1000>; + interrupts = <14>; + }; + + smc@10100000 { + compatible = "arm,primecell"; + reg = <0x10100000 0x1000>; + }; + + mpmc@10110000 { + compatible = "arm,primecell"; + reg = <0x10110000 0x1000>; + }; + + display@10120000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x10120000 0x1000>; + interrupts = <16>; + }; + + sctl@101e0000 { + compatible = "arm,primecell"; + reg = <0x101e0000 0x1000>; + }; + + watchdog@101e1000 { + compatible = "arm,primecell"; + reg = <0x101e1000 0x1000>; + interrupts = <0>; + }; + + gpio0: gpio@101e4000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e4000 0x1000>; + gpio-controller; + interrupts = <6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@101e5000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e5000 0x1000>; + interrupts = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rtc@101e8000 { + compatible = "arm,pl030", "arm,primecell"; + reg = <0x101e8000 0x1000>; + interrupts = <10>; + }; + + sci@101f0000 { + compatible = "arm,primecell"; + reg = <0x101f0000 0x1000>; + interrupts = <15>; + }; + + ssp@101f4000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x101f4000 0x1000>; + interrupts = <11>; + }; + + fpga { + compatible = "arm,versatile-fpga", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10000000 0x10000>; + + aaci@4000 { + compatible = "arm,primecell"; + reg = <0x4000 0x1000>; + interrupts = <24>; + }; + mmc@5000 { + compatible = "arm,primecell"; + reg = < 0x5000 0x1000>; + interrupts = <22 34>; + }; + kmi@6000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x6000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <3>; + }; + kmi@7000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x7000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <4>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/versatile-pb.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/versatile-pb.dts new file mode 100644 index 000000000..7e8175269 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/versatile-pb.dts @@ -0,0 +1,50 @@ +/include/ "versatile-ab.dts" + +/ { + model = "ARM Versatile PB"; + compatible = "arm,versatile-pb"; + + amba { + gpio2: gpio@101e6000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e6000 0x1000>; + interrupts = <8>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@101e7000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x101e7000 0x1000>; + interrupts = <9>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + fpga { + uart@9000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x9000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <6>; + }; + sci@a000 { + compatible = "arm,primecell"; + reg = <0xa000 0x1000>; + interrupt-parent = <&sic>; + interrupts = <5>; + }; + mmc@b000 { + compatible = "arm,primecell"; + reg = <0xb000 0x1000>; + interrupts = <23 34>; + }; + }; + }; +}; + +/include/ "testcases/tests.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2m-rs1.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2m-rs1.dtsi new file mode 100644 index 000000000..16076e2d0 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2m-rs1.dtsi @@ -0,0 +1,201 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * RS1 memory map ("ARM Cortex-A Series memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * original variant (vexpress-v2m.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m.dtsi! + */ + +/ { + aliases { + arm,v2m_timer = &v2m_timer01; + }; + + motherboard { + compatible = "simple-bus"; + arm,v2m-memory-map = "rs1"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@1,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <1 0x00000000 0x02000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + }; + + usb@2,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <2 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + }; + + sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@030000 { + compatible = "arm,versatile-i2c"; + reg = <0x030000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@160000 { + compatible = "arm,versatile-i2c"; + reg = <0x160000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + }; + + compact-flash@1a0000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a0000 0x100 + 0x1a0100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2m.dtsi b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2m.dtsi new file mode 100644 index 000000000..a6c9c7c82 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2m.dtsi @@ -0,0 +1,200 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * Original memory map ("Legacy memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m-rs1.dtsi! + */ + +/ { + aliases { + arm,v2m_timer = &v2m_timer01; + }; + + motherboard { + compatible = "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <1 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@2,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <2 0x00000000 0x02000000>; + bank-width = <4>; + }; + + vram@3,00000000 { + compatible = "arm,vexpress-vram"; + reg = <3 0x00000000 0x00800000>; + }; + + ethernet@3,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <3 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + }; + + usb@3,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <3 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@7,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 7 0 0x20000>; + + sysreg@00000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x00000 0x1000>; + }; + + sysctl@01000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x01000 0x1000>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@02000 { + compatible = "arm,versatile-i2c"; + reg = <0x02000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@04000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x04000 0x1000>; + interrupts = <11>; + }; + + mmci@05000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x05000 0x1000>; + interrupts = <9 10>; + }; + + kmi@06000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x06000 0x1000>; + interrupts = <12>; + }; + + kmi@07000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x07000 0x1000>; + interrupts = <13>; + }; + + v2m_serial0: uart@09000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000 0x1000>; + interrupts = <5>; + }; + + v2m_serial1: uart@0a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a000 0x1000>; + interrupts = <6>; + }; + + v2m_serial2: uart@0b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b000 0x1000>; + interrupts = <7>; + }; + + v2m_serial3: uart@0c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c000 0x1000>; + interrupts = <8>; + }; + + wdt@0f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f000 0x1000>; + interrupts = <0>; + }; + + v2m_timer01: timer@11000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x11000 0x1000>; + interrupts = <2>; + }; + + v2m_timer23: timer@12000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x12000 0x1000>; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@16000 { + compatible = "arm,versatile-i2c"; + reg = <0x16000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@17000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x17000 0x1000>; + interrupts = <4>; + }; + + compact-flash@1a000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a000 0x100 + 0x1a100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f000 0x1000>; + interrupts = <14>; + }; + }; + }; +}; diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca15-tc1.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca15-tc1.dts new file mode 100644 index 000000000..941b161ab --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca15-tc1.dts @@ -0,0 +1,157 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A15x2 (version with Test Chip 1) + * Cortex-A15 MPCore (V2P-CA15) + * + * HBI-0237A + */ + +/dts-v1/; + +/ { + model = "V2P-CA15"; + arm,hbi = <0x237>; + compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + hdlcd@2b000000 { + compatible = "arm,hdlcd"; + reg = <0x2b000000 0x1000>; + interrupts = <0 85 4>; + }; + + memory-controller@2b0a0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x2b0a0000 0x1000>; + }; + + wdt@2b060000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x2b060000 0x1000>; + interrupts = <98>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x100>; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x7ffd0000 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + }; + + dma@7ffb0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x7ffb0000 0x1000>; + interrupts = <0 92 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; + interrupts = <0 68 4>, + <0 69 4>; + }; + + motherboard { + ranges = <0 0 0x08000000 0x04000000>, + <1 0 0x14000000 0x04000000>, + <2 0 0x18000000 0x04000000>, + <3 0 0x1c000000 0x04000000>, + <4 0 0x0c000000 0x04000000>, + <5 0 0x10000000 0x04000000>; + + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + }; +}; + +/include/ "vexpress-v2m-rs1.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca5s.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca5s.dts new file mode 100644 index 000000000..6905e66d4 --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca5s.dts @@ -0,0 +1,162 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A5x2 + * Cortex-A5 MPCore (V2P-CA5s) + * + * HBI-0225B + */ + +/dts-v1/; + +/ { + model = "V2P-CA5s"; + arm,hbi = <0x225>; + compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + hdlcd@2a110000 { + compatible = "arm,hdlcd"; + reg = <0x2a110000 0x1000>; + interrupts = <0 85 4>; + }; + + memory-controller@2a150000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x2a150000 0x1000>; + }; + + memory-controller@2a190000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x2a190000 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + }; + + scu@2c000000 { + compatible = "arm,cortex-a5-scu"; + reg = <0x2c000000 0x58>; + }; + + timer@2c000600 { + compatible = "arm,cortex-a5-twd-timer"; + reg = <0x2c000600 0x38>; + interrupts = <1 2 0x304>, + <1 3 0x304>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c000100 0x100>; + }; + + L2: cache-controller@2c0f0000 { + compatible = "arm,pl310-cache"; + reg = <0x2c0f0000 0x1000>; + interrupts = <0 84 4>; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; + interrupts = <0 68 4>, + <0 69 4>; + }; + + motherboard { + ranges = <0 0 0x08000000 0x04000000>, + <1 0 0x14000000 0x04000000>, + <2 0 0x18000000 0x04000000>, + <3 0 0x1c000000 0x04000000>, + <4 0 0x0c000000 0x04000000>, + <5 0 0x10000000 0x04000000>; + + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + }; +}; + +/include/ "vexpress-v2m-rs1.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca9.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca9.dts new file mode 100644 index 000000000..da778693b --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/vexpress-v2p-ca9.dts @@ -0,0 +1,192 @@ +/* + * ARM Ltd. Versatile Express + * + * CoreTile Express A9x4 + * Cortex-A9 MPCore (V2P-CA9) + * + * HBI-0191B + */ + +/dts-v1/; + +/ { + model = "V2P-CA9"; + arm,hbi = <0x191>; + compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupts = <0 44 4>; + }; + + memory-controller@100e0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0x100e0000 0x1000>; + }; + + memory-controller@100e1000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0x100e1000 0x1000>; + interrupts = <0 45 4>, + <0 46 4>; + }; + + timer@100e4000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x100e4000 0x1000>; + interrupts = <0 48 4>, + <0 49 4>; + }; + + watchdog@100e5000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x100e5000 0x1000>; + interrupts = <0 51 4>; + }; + + scu@1e000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000000 0x58>; + }; + + timer@1e000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e000600 0x20>; + interrupts = <1 2 0xf04>, + <1 3 0xf04>; + }; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000100 0x100>; + }; + + L2: cache-controller@1e00a000 { + compatible = "arm,pl310-cache"; + reg = <0x1e00a000 0x1000>; + interrupts = <0 43 4>; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + motherboard { + ranges = <0 0 0x40000000 0x04000000>, + <1 0 0x44000000 0x04000000>, + <2 0 0x48000000 0x04000000>, + <3 0 0x4c000000 0x04000000>, + <7 0 0x10000000 0x00020000>; + + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + }; +}; + +/include/ "vexpress-v2m.dtsi" diff --git a/kernel/arch/arm/boot/dts/tr961-5200l-v2/zynq-ep107.dts b/kernel/arch/arm/boot/dts/tr961-5200l-v2/zynq-ep107.dts new file mode 100644 index 000000000..37ca192fb --- /dev/null +++ b/kernel/arch/arm/boot/dts/tr961-5200l-v2/zynq-ep107.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/ { + model = "Xilinx Zynq EP107"; + compatible = "xlnx,zynq-ep107"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk"; + linux,stdout-path = &uart0; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f8f01000 { + interrupt-controller; + compatible = "arm,gic"; + reg = <0xF8F01000 0x1000>; + #interrupt-cells = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + reg = <0xE0000000 0x1000>; + interrupts = <59 0>; + clock = <50000000>; + }; + }; +}; diff --git a/kernel/arch/arm/configs/m7350-un-v2_defconfig b/kernel/arch/arm/configs/m7350-un-v1_defconfig old mode 100755 new mode 100644 similarity index 99% rename from kernel/arch/arm/configs/m7350-un-v2_defconfig rename to kernel/arch/arm/configs/m7350-un-v1_defconfig index ed7423b3f..624d5d913 --- a/kernel/arch/arm/configs/m7350-un-v2_defconfig +++ b/kernel/arch/arm/configs/m7350-un-v1_defconfig @@ -346,6 +346,6 @@ CONFIG_LIBCRC32C=y CONFIG_TPLINK_PMIC_EXT=y CONFIG_OLED=y CONFIG_OLED_S90319_PT=y -CONFIG_TPLINK_PRODUCT_M7350_UN_V2=y +CONFIG_TPLINK_PRODUCT_M7350_UN_V1=y # [chenchao] Export pm wakelocks to userspace CONFIG_PM_WAKELOCKS=y diff --git a/kernel/arch/arm/configs/m7350-un-v3-perf_defconfig b/kernel/arch/arm/configs/m7350-un-v3-perf_defconfig new file mode 100755 index 000000000..eebcffe14 --- /dev/null +++ b/kernel/arch/arm/configs/m7350-un-v3-perf_defconfig @@ -0,0 +1,339 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MSM=y +CONFIG_ARCH_MSM9625=y +# CONFIG_MSM_STACKED_MEMORY is not set +# CONFIG_MSM_FIQ_SUPPORT is not set +# CONFIG_MSM_PROC_COMM is not set +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_PKG4=y +CONFIG_MSM_BAM_DMUX=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_IPC_LOGGING=y +CONFIG_MSM_IPC_ROUTER=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_RPM_REGULATOR_SMD=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_MSM_DIRECT_SCLK_ACCESS=y +CONFIG_MSM_BUS_SCALING=y +CONFIG_MSM_WATCHDOG_V2=y +CONFIG_MSM_MEMORY_DUMP=y +CONFIG_MSM_DLOAD_MODE=y +CONFIG_MSM_ADSP_LOADER=m +CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y +CONFIG_MSM_UARTDM_Core_v14=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_USE_OF=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IPV6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_DEBUG=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_IP_SET=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_CLS_FW=y +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_MSM_NAND is not set +CONFIG_MTD_MSM_QPIC_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_SCSI_TGT=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# [linyunfeng] Not support ethernet KS8851 +# CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_MSM_RMNET is not set +CONFIG_MSM_RMNET_WWAN=y +CONFIG_ECM_IPA=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_ATH6K_LEGACY_EXT=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_OF=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_HSL=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_QUP=y +CONFIG_MSM_BUSPM_DEV=m +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +CONFIG_MSM_QPNP_INT=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_GPIO_QPNP_PIN_DEBUG=y +CONFIG_POWER_SUPPLY=y +CONFIG_MP2617_CHARGER=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_THERMAL=y +CONFIG_THERMAL_TSENS8974=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_THERMAL_MONITOR=y +CONFIG_WCD9320_CODEC=n +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_QPNP=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_SOUND=n +CONFIG_SND=n +CONFIG_SND_SOC=n +CONFIG_SND_SOC_MDM9625=n +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_EHSET=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_EHCI_MSM_HSIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_CI13XXX_MSM=y +CONFIG_USB_G_ANDROID=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=m +CONFIG_MMC_MSM=y +CONFIG_MMC_MSM_SPS_SUPPORT=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MSM is not set +CONFIG_RTC_DRV_QPNP=y +CONFIG_SPS=y +CONFIG_USB_BAM=y +CONFIG_SPS_SUPPORT_BAMDMA=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_QPNP_POWER_ON=y +CONFIG_IPA=y +CONFIG_EXT3_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_DISABLE_TAGS_ECC=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_OOPS_LOG_BUFFER=y +CONFIG_OOPS_LOG_BUF_SHIFT=14 +CONFIG_DEBUG_USER=y +CONFIG_KEYS=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DEV_QCRYPTO=m +CONFIG_CRYPTO_DEV_QCE=m +CONFIG_CRYPTO_DEV_QCEDEV=m +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y +CONFIG_DEVMEM=n +CONFIG_DEVKMEM=n +# TP-LINK CONFIG +CONFIG_TPLINK_PMIC_EXT=y +CONFIG_OLED=y +CONFIG_OLED_S90319_PT=y +CONFIG_TPLINK_PRODUCT_M7350_UN_V3=y +# [chenchao] Export pm wakelocks to userspace +CONFIG_PM_WAKELOCKS=y diff --git a/kernel/arch/arm/configs/m7350-un-v3_defconfig b/kernel/arch/arm/configs/m7350-un-v3_defconfig new file mode 100755 index 000000000..c081dbcf9 --- /dev/null +++ b/kernel/arch/arm/configs/m7350-un-v3_defconfig @@ -0,0 +1,351 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MSM=y +CONFIG_ARCH_MSM9625=y +# CONFIG_MSM_STACKED_MEMORY is not set +# CONFIG_MSM_FIQ_SUPPORT is not set +# CONFIG_MSM_PROC_COMM is not set +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_PKG4=y +CONFIG_MSM_BAM_DMUX=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_IPC_LOGGING=y +CONFIG_MSM_IPC_ROUTER=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_RPM_REGULATOR_SMD=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_MSM_DIRECT_SCLK_ACCESS=y +CONFIG_MSM_BUS_SCALING=y +CONFIG_MSM_BUSPM_DEV=m +CONFIG_MSM_WATCHDOG_V2=y +CONFIG_MSM_MEMORY_DUMP=y +CONFIG_MSM_DLOAD_MODE=y +CONFIG_MSM_ADSP_LOADER=m +CONFIG_MSM_RTB=y +CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y +CONFIG_MSM_UARTDM_Core_v14=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_USE_OF=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IPV6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_DEBUG=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_IP_SET=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_CLS_FW=y +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_MSM_NAND is not set +CONFIG_MTD_MSM_QPIC_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_SCSI_TGT=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# [linyunfeng] Not support ethernet KS8851 +# CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_MSM_RMNET is not set +CONFIG_MSM_RMNET_WWAN=y +CONFIG_ECM_IPA=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_ATH6K_LEGACY_EXT=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_OF=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_HSL=y +CONFIG_SERIAL_MSM_HSL_CONSOLE=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_QUP=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +CONFIG_MSM_QPNP_INT=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_GPIO_QPNP_PIN_DEBUG=y +CONFIG_POWER_SUPPLY=y +CONFIG_MP2617_CHARGER=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_THERMAL=y +CONFIG_THERMAL_TSENS8974=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_THERMAL_MONITOR=y +CONFIG_WCD9320_CODEC=n +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_QPNP=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_SOUND=n +CONFIG_SND=n +CONFIG_SND_SOC=n +CONFIG_SND_SOC_MDM9625=n +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_EHSET=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_EHCI_MSM_HSIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_CI13XXX_MSM=y +CONFIG_USB_G_ANDROID=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=m +CONFIG_MMC_MSM=y +CONFIG_MMC_MSM_SPS_SUPPORT=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MSM is not set +CONFIG_RTC_DRV_QPNP=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_LOGGER=y +CONFIG_SPS=y +CONFIG_USB_BAM=y +CONFIG_SPS_SUPPORT_BAMDMA=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_QPNP_POWER_ON=y +CONFIG_IPA=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_TMC=y +CONFIG_CORESIGHT_TPIU=y +CONFIG_CORESIGHT_FUNNEL=y +CONFIG_CORESIGHT_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_ETM=y +CONFIG_CORESIGHT_EVENT=m +CONFIG_EXT3_FS=y +CONFIG_FUSE_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_DISABLE_TAGS_ECC=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_OOPS_LOG_BUFFER=y +CONFIG_OOPS_LOG_BUF_SHIFT=14 +CONFIG_DEBUG_USER=y +CONFIG_KEYS=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y +# TP-LINK CONFIG +CONFIG_TPLINK_PMIC_EXT=y +CONFIG_OLED=y +CONFIG_OLED_S90319_PT=y +CONFIG_TPLINK_PRODUCT_M7350_UN_V3=y +# [chenchao] Export pm wakelocks to userspace +CONFIG_PM_WAKELOCKS=y diff --git a/kernel/arch/arm/configs/msm9625_defconfig b/kernel/arch/arm/configs/msm9625_defconfig old mode 100644 new mode 100755 index 624d5d913..ed7423b3f --- a/kernel/arch/arm/configs/msm9625_defconfig +++ b/kernel/arch/arm/configs/msm9625_defconfig @@ -346,6 +346,6 @@ CONFIG_LIBCRC32C=y CONFIG_TPLINK_PMIC_EXT=y CONFIG_OLED=y CONFIG_OLED_S90319_PT=y -CONFIG_TPLINK_PRODUCT_M7350_UN_V1=y +CONFIG_TPLINK_PRODUCT_M7350_UN_V2=y # [chenchao] Export pm wakelocks to userspace CONFIG_PM_WAKELOCKS=y diff --git a/kernel/arch/arm/configs/tr961-2500l-mobile-unicom-v1-perf_defconfig b/kernel/arch/arm/configs/tr961-2500l-mobile-unicom-v1-perf_defconfig index 4b805efe8..2ea52504d 100644 --- a/kernel/arch/arm/configs/tr961-2500l-mobile-unicom-v1-perf_defconfig +++ b/kernel/arch/arm/configs/tr961-2500l-mobile-unicom-v1-perf_defconfig @@ -118,6 +118,7 @@ CONFIG_NETFILTER_XT_MATCH_IPRANGE=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STRING=y CONFIG_IP_SET=y CONFIG_NF_CONNTRACK_IPV4=y CONFIG_IP_NF_IPTABLES=y diff --git a/kernel/arch/arm/configs/tr961-2500l-mobile-unicom-v1_defconfig b/kernel/arch/arm/configs/tr961-2500l-mobile-unicom-v1_defconfig index 828c6abc0..74266330c 100644 --- a/kernel/arch/arm/configs/tr961-2500l-mobile-unicom-v1_defconfig +++ b/kernel/arch/arm/configs/tr961-2500l-mobile-unicom-v1_defconfig @@ -122,6 +122,7 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STRING=y CONFIG_IP_SET=y CONFIG_NF_CONNTRACK_IPV4=y CONFIG_IP_NF_IPTABLES=y diff --git a/kernel/arch/arm/configs/tr961-5200l-v2-perf_defconfig b/kernel/arch/arm/configs/tr961-5200l-v2-perf_defconfig new file mode 100644 index 000000000..b0074161f --- /dev/null +++ b/kernel/arch/arm/configs/tr961-5200l-v2-perf_defconfig @@ -0,0 +1,344 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MSM=y +CONFIG_ARCH_MSM9625=y +# CONFIG_MSM_STACKED_MEMORY is not set +# CONFIG_MSM_FIQ_SUPPORT is not set +# CONFIG_MSM_PROC_COMM is not set +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_PKG4=y +CONFIG_MSM_BAM_DMUX=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_IPC_LOGGING=y +CONFIG_MSM_IPC_ROUTER=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_RPM_REGULATOR_SMD=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_MSM_DIRECT_SCLK_ACCESS=y +CONFIG_MSM_BUS_SCALING=y +CONFIG_MSM_WATCHDOG_V2=y +CONFIG_MSM_MEMORY_DUMP=y +CONFIG_MSM_DLOAD_MODE=y +CONFIG_MSM_ADSP_LOADER=m +CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y +CONFIG_MSM_UARTDM_Core_v14=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_USE_OF=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IPV6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_DEBUG=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_IP_SET=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_CLS_FW=y +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_MSM_NAND is not set +CONFIG_MTD_MSM_QPIC_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_SCSI_TGT=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# [linyunfeng] Not support ethernet KS8851 +# CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_MSM_RMNET is not set +CONFIG_MSM_RMNET_WWAN=y +CONFIG_ECM_IPA=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_ATH6K_LEGACY_EXT=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_OF=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_HSL=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_QUP=y +CONFIG_MSM_BUSPM_DEV=m +# [linyunfeng] Remove SPI module +# CONFIG_SPI=y +# CONFIG_SPI_QUP=y +# CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +CONFIG_MSM_QPNP_INT=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_GPIO_QPNP_PIN_DEBUG=y +CONFIG_POWER_SUPPLY=y +CONFIG_MP2617_CHARGER=y +CONFIG_POWER_BANK_DETECT_SUPPORT=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_THERMAL=y +CONFIG_THERMAL_TSENS8974=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_THERMAL_MONITOR=y +CONFIG_WCD9320_CODEC=n +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_QPNP=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_SOUND=n +CONFIG_SND=n +CONFIG_SND_SOC=n +CONFIG_SND_SOC_MDM9625=n +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_EHSET=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_EHCI_MSM_HSIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_CI13XXX_MSM=y +CONFIG_USB_G_ANDROID=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=m +CONFIG_MMC_MSM=y +CONFIG_MMC_MSM_SPS_SUPPORT=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MSM is not set +CONFIG_RTC_DRV_QPNP=y +CONFIG_SPS=y +CONFIG_USB_BAM=y +CONFIG_SPS_SUPPORT_BAMDMA=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_QPNP_POWER_ON=y +CONFIG_IPA=y +CONFIG_EXT3_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_DISABLE_TAGS_ECC=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_OOPS_LOG_BUFFER=y +CONFIG_OOPS_LOG_BUF_SHIFT=14 +CONFIG_DEBUG_USER=y +CONFIG_KEYS=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DEV_QCRYPTO=m +CONFIG_CRYPTO_DEV_QCE=m +CONFIG_CRYPTO_DEV_QCEDEV=m +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y +CONFIG_DEVMEM=n +CONFIG_DEVKMEM=n +CONFIG_OLED_SSD1306_PT=y +CONFIG_OLED=y +CONFIG_TPLINK_PRODUCT_TR961_5200L_V2=y +# [chenchao] Export pm wakelocks to userspace +CONFIG_PM_WAKELOCKS=y + +# TP-LINK CONFIG +CONFIG_TPLINK_PMIC_EXT=y + diff --git a/kernel/arch/arm/configs/tr961-5200l-v2_defconfig b/kernel/arch/arm/configs/tr961-5200l-v2_defconfig new file mode 100644 index 000000000..96df5f75f --- /dev/null +++ b/kernel/arch/arm/configs/tr961-5200l-v2_defconfig @@ -0,0 +1,356 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MSM=y +CONFIG_ARCH_MSM9625=y +# CONFIG_MSM_STACKED_MEMORY is not set +# CONFIG_MSM_FIQ_SUPPORT is not set +# CONFIG_MSM_PROC_COMM is not set +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_PKG4=y +CONFIG_MSM_BAM_DMUX=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_IPC_LOGGING=y +CONFIG_MSM_IPC_ROUTER=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_RPM_REGULATOR_SMD=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_MSM_DIRECT_SCLK_ACCESS=y +CONFIG_MSM_BUS_SCALING=y +CONFIG_MSM_BUSPM_DEV=m +CONFIG_MSM_WATCHDOG_V2=y +CONFIG_MSM_MEMORY_DUMP=y +CONFIG_MSM_DLOAD_MODE=y +CONFIG_MSM_ADSP_LOADER=m +CONFIG_MSM_RTB=y +CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL=y +CONFIG_MSM_UARTDM_Core_v14=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_USE_OF=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IPV6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_DEBUG=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_IP_SET=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_CLS_FW=y +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_MSM_NAND is not set +CONFIG_MTD_MSM_QPIC_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_SCSI_TGT=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# [linyunfeng] Not support ethernet KS8851 +# CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_MSM_RMNET is not set +CONFIG_MSM_RMNET_WWAN=y +CONFIG_ECM_IPA=y +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_ATH6K_LEGACY_EXT=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_OF=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_HSL=y +CONFIG_SERIAL_MSM_HSL_CONSOLE=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_QUP=y +# [linyunfeng] Remove SPI module +# CONFIG_SPI=y +# CONFIG_SPI_QUP=y +# CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +CONFIG_MSM_QPNP_INT=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_GPIO_QPNP_PIN_DEBUG=y +CONFIG_POWER_SUPPLY=y +CONFIG_MP2617_CHARGER=y +CONFIG_POWER_BANK_DETECT_SUPPORT=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_THERMAL=y +CONFIG_THERMAL_TSENS8974=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_THERMAL_MONITOR=y +CONFIG_WCD9320_CODEC=n +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_QPNP=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_SOUND=n +CONFIG_SND=n +CONFIG_SND_SOC=n +CONFIG_SND_SOC_MDM9625=n +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_EHSET=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_EHCI_MSM_HSIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_CI13XXX_MSM=y +CONFIG_USB_G_ANDROID=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=m +CONFIG_MMC_MSM=y +CONFIG_MMC_MSM_SPS_SUPPORT=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MSM is not set +CONFIG_RTC_DRV_QPNP=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_LOGGER=y +CONFIG_SPS=y +CONFIG_USB_BAM=y +CONFIG_SPS_SUPPORT_BAMDMA=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_QPNP_POWER_ON=y +CONFIG_IPA=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_TMC=y +CONFIG_CORESIGHT_TPIU=y +CONFIG_CORESIGHT_FUNNEL=y +CONFIG_CORESIGHT_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_ETM=y +CONFIG_CORESIGHT_EVENT=m +CONFIG_EXT3_FS=y +CONFIG_FUSE_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_DISABLE_TAGS_ECC=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_OOPS_LOG_BUFFER=y +CONFIG_OOPS_LOG_BUF_SHIFT=14 +CONFIG_DEBUG_USER=y +CONFIG_KEYS=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRC_CCITT=y +CONFIG_LIBCRC32C=y +CONFIG_OLED_SSD1306_PT=y +CONFIG_OLED=y +CONFIG_TPLINK_PRODUCT_TR961_5200L_V2=y +# [chenchao] Export pm wakelocks to userspace +CONFIG_PM_WAKELOCKS=y + +# TP-LINK CONFIG +CONFIG_TPLINK_PMIC_EXT=y + diff --git a/kernel/arch/arm/mach-msm/Kconfig b/kernel/arch/arm/mach-msm/Kconfig index 8236d47c8..7b767545c 100755 --- a/kernel/arch/arm/mach-msm/Kconfig +++ b/kernel/arch/arm/mach-msm/Kconfig @@ -3055,6 +3055,10 @@ config TPLINK_PRODUCT_TR961_5200L_V1 bool "Specify product type tr961-5200l-v1" default n +config TPLINK_PRODUCT_TR961_5200L_V2 + bool "Specify product type tr961-5200l-v2" + default n + config TPLINK_PRODUCT_TR961_2500L_MOBILE_UNICOM_V1 bool "Specify product type tr961-2500l-mobile-unicom-v1" default n @@ -3067,6 +3071,10 @@ config TPLINK_PRODUCT_M7350_UN_V2 bool "Specify product type m7350-un-v2" default n +config TPLINK_PRODUCT_M7350_UN_V3 + bool "Specify product type m7350-un-v3" + default n + config TPLINK_PRODUCT_M7300_UN_V1 bool "Specify product type m7300-un-v1" default n diff --git a/kernel/arch/arm/mach-msm/Makefile b/kernel/arch/arm/mach-msm/Makefile index 3aade82b3..3cdacb838 100755 --- a/kernel/arch/arm/mach-msm/Makefile +++ b/kernel/arch/arm/mach-msm/Makefile @@ -306,6 +306,10 @@ ifdef CONFIG_TPLINK_PRODUCT_TR961_5200L_V1 product_gpio = board-tr961-5200l-v1-gpiomux.o endif +ifdef CONFIG_TPLINK_PRODUCT_TR961_5200L_V2 +product_gpio = board-tr961-5200l-v2-gpiomux.o +endif + ifdef CONFIG_TPLINK_PRODUCT_LTE_MODULE_V1 product_gpio = board-lte-module-v1-gpiomux.o endif @@ -318,6 +322,10 @@ ifdef CONFIG_TPLINK_PRODUCT_M7350_UN_V2 product_gpio = board-m7350-un-v2-gpiomux.o endif +ifdef CONFIG_TPLINK_PRODUCT_M7350_UN_V3 +product_gpio = board-m7350-un-v3-gpiomux.o +endif + ifdef CONFIG_TPLINK_PRODUCT_TR961_2500L_MOBILE_UNICOM_V1 product_gpio = board-tr961-2500l-mobile-unicom-v1-gpiomux.o endif diff --git a/kernel/arch/arm/mach-msm/board-m7350-un-v3-gpiomux.c b/kernel/arch/arm/mach-msm/board-m7350-un-v3-gpiomux.c new file mode 100755 index 000000000..0ce4bc804 --- /dev/null +++ b/kernel/arch/arm/mach-msm/board-m7350-un-v3-gpiomux.c @@ -0,0 +1,381 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +static struct gpiomux_setting gpio_uart_config = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_OUT_HIGH, +}; + +static struct gpiomux_setting gpio_spi_cs_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_12MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting gpio_spi_cs_suspend_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_12MA, + .pull = GPIOMUX_PULL_UP, +}; + +static struct gpiomux_setting gpio_spi_cs_active_up_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_12MA, + .pull = GPIOMUX_PULL_UP, +}; + +static struct gpiomux_setting gpio_spi_config = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_12MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting gpio_i2c_config = { + .func = GPIOMUX_FUNC_3, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting gpio_spi_cs_active_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct msm_gpiomux_config msm_blsp_configs[] __initdata = { + { + .gpio = 4, /* BLSP1 QUP2 SPI_DATA_MOSI */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_spi_config, + }, + }, + { + .gpio = 5, /* BLSP1 QUP2 SPI_DATA_MISO */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_spi_config, + }, + }, + { + .gpio = 6, /* BLSP1 QUP2 SPI_CS_N */ + .settings = { + [GPIOMUX_ACTIVE] = &gpio_spi_cs_active_config, + [GPIOMUX_SUSPENDED] = &gpio_spi_cs_config, + }, + }, + { + .gpio = 7, /* BLSP1 QUP2 SPI_CLK */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_spi_config, + }, + }, + { + .gpio = 8, /* BLSP1 UART TX */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_uart_config, + }, + }, + { + .gpio = 9, /* BLSP1 UART RX */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_uart_config, + }, + }, + { + .gpio = 10, /* BLSP1 QUP3 I2C_DAT */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_i2c_config, + }, + }, + { + .gpio = 11, /* BLSP1 QUP3 I2C_CLK */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_i2c_config, + }, + }, + { + .gpio = 61, + .settings = { + [GPIOMUX_ACTIVE] = &gpio_spi_cs_active_up_config, + [GPIOMUX_SUSPENDED] = &gpio_spi_cs_suspend_config, + }, + }, +}; + +/* [houjihai start] */ +static struct gpiomux_setting key_active_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting key_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; +/* [houjihai end] */ + +/* [houjihai start] gpio14 for wps key and gpio15 for reset*/ +static struct msm_gpiomux_config mdm9625_key_configs[] __initdata = { + { + .gpio = 14, + .settings = { + [GPIOMUX_SUSPENDED] = &key_suspend_cfg, + [GPIOMUX_ACTIVE] = &key_active_cfg, + }, + }, + { + .gpio = 15, + .settings = { + [GPIOMUX_SUSPENDED] = &key_suspend_cfg, + [GPIOMUX_ACTIVE] = &key_active_cfg, + }, + }, +}; +/* [houjihai end] */ + +static struct gpiomux_setting wlan_ath6kl_active_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_OUT_LOW, +}; + +static struct gpiomux_setting wlan_ath6kl_suspend_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_IN, +}; + +static struct msm_gpiomux_config wlan_ath6kl_configs[] __initdata = { + { + .gpio = 62,/* CHIP_PWD_L */ + .settings = { + [GPIOMUX_ACTIVE] = &wlan_ath6kl_active_config, + [GPIOMUX_SUSPENDED] = &wlan_ath6kl_suspend_config, + }, + }, +}; + +static struct gpiomux_setting sdc2_card_det_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + .dir = GPIOMUX_IN, +}; + +struct msm_gpiomux_config sdc2_card_det_config[] __initdata = { + { + .gpio = 66, + .settings = { + [GPIOMUX_ACTIVE] = &sdc2_card_det_cfg, + [GPIOMUX_SUSPENDED] = &sdc2_card_det_cfg, + }, + }, +}; + +#ifdef CONFIG_OLED_S90319_PT +static struct msm_gpiomux_config msm9625_oled_s90319_configs[] __initdata = { + { + .gpio = 20, + .settings = { + [GPIOMUX_ACTIVE] = &gpio_spi_cs_active_up_config, + [GPIOMUX_SUSPENDED] = &gpio_spi_cs_suspend_config, + }, + }, + { + .gpio = 21, + .settings = { + [GPIOMUX_ACTIVE] = &gpio_spi_cs_active_config, + [GPIOMUX_SUSPENDED] = &gpio_spi_cs_config, + }, + }, + { + .gpio = 22, + .settings = { + [GPIOMUX_ACTIVE] = &gpio_spi_cs_active_up_config, + [GPIOMUX_SUSPENDED] = &gpio_spi_cs_suspend_config, + }, + }, + { + .gpio = 23, + .settings = { + [GPIOMUX_ACTIVE] = &gpio_spi_cs_active_up_config, + [GPIOMUX_SUSPENDED] = &gpio_spi_cs_suspend_config, + }, + }, +}; +#endif + +#ifdef CONFIG_FB_MSM_QPIC +static struct gpiomux_setting qpic_lcdc_a_d = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_10MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting qpic_lcdc_cs = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_10MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting qpic_lcdc_rs = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_10MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting qpic_lcdc_te = { + .func = GPIOMUX_FUNC_7, + .drv = GPIOMUX_DRV_10MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct msm_gpiomux_config msm9625_qpic_lcdc_configs[] __initdata = { + { + .gpio = 20, /* a_d */ + .settings = { + [GPIOMUX_SUSPENDED] = &qpic_lcdc_a_d, + }, + }, + { + .gpio = 21, /* cs */ + .settings = { + [GPIOMUX_SUSPENDED] = &qpic_lcdc_cs, + }, + }, + { + .gpio = 22, /* te */ + .settings = { + [GPIOMUX_SUSPENDED] = &qpic_lcdc_te, + }, + }, + { + .gpio = 23, /* rs */ + .settings = { + [GPIOMUX_SUSPENDED] = &qpic_lcdc_rs, + }, + }, +}; + +static void msm9625_disp_init_gpiomux(void) +{ + msm_gpiomux_install(msm9625_qpic_lcdc_configs, + ARRAY_SIZE(msm9625_qpic_lcdc_configs)); +} +#else +static void msm9625_disp_init_gpiomux(void) +{ +} +#endif /* CONFIG_FB_MSM_QPIC */ + +#ifdef CONFIG_MP2617_CHARGER +static struct gpiomux_setting mp2617_gpio_input_active_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_IN, +}; + +static struct gpiomux_setting mp2617_gpio_input_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_IN, +}; + +static struct gpiomux_setting mp2617_gpio_output_active_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting mp2617_gpio_output_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +/* refer to msm9625-mtp.dtsi */ +static struct msm_gpiomux_config msm9625_mp2617_configs[] __initdata = { + { + .gpio = 13, /* Charge Enable, 1: Enable, 0: Disable */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_output_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_output_suspend_cfg, + }, + }, + { + .gpio = 12, /* M0 */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_output_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_output_suspend_cfg, + }, + }, + { + .gpio = 17, /* M1 */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_output_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_output_suspend_cfg, + }, + }, + { + .gpio = 71, /* CHGOK, 0: Charging, 1: Complete */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_input_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_input_suspend_cfg, + }, + }, +}; +#endif + +void __init msm9625_init_gpiomux(void) +{ + int rc; + + rc = msm_gpiomux_init_dt(); + if (rc) { + pr_err("%s failed %d\n", __func__, rc); + return; + } + + msm_gpiomux_install(msm_blsp_configs, ARRAY_SIZE(msm_blsp_configs)); + msm_gpiomux_install(wlan_ath6kl_configs, + ARRAY_SIZE(wlan_ath6kl_configs)); + /* [houjihai start] */ + msm_gpiomux_install(mdm9625_key_configs, + ARRAY_SIZE(mdm9625_key_configs)); + /* [houjihai end] */ + msm_gpiomux_install(sdc2_card_det_config, + ARRAY_SIZE(sdc2_card_det_config)); + msm9625_disp_init_gpiomux(); +#ifdef CONFIG_OLED_S90319_PT + msm_gpiomux_install(msm9625_oled_s90319_configs, + ARRAY_SIZE(msm9625_oled_s90319_configs)); +#endif + +#ifdef CONFIG_MP2617_CHARGER + msm_gpiomux_install(msm9625_mp2617_configs, + ARRAY_SIZE(msm9625_mp2617_configs)); +#endif +} diff --git a/kernel/arch/arm/mach-msm/board-tr961-5200l-v2-gpiomux.c b/kernel/arch/arm/mach-msm/board-tr961-5200l-v2-gpiomux.c new file mode 100755 index 000000000..cd190e639 --- /dev/null +++ b/kernel/arch/arm/mach-msm/board-tr961-5200l-v2-gpiomux.c @@ -0,0 +1,354 @@ +/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +static struct gpiomux_setting gpio_uart_config = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_OUT_HIGH, +}; + +static struct gpiomux_setting gpio_i2c_config = { + .func = GPIOMUX_FUNC_3, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct msm_gpiomux_config msm_blsp_configs[] __initdata = { + { + .gpio = 8, /* BLSP1 UART TX */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_uart_config, + }, + }, + { + .gpio = 9, /* BLSP1 UART RX */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_uart_config, + }, + }, + { + .gpio = 10, /* BLSP1 QUP3 I2C_DAT */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_i2c_config, + }, + }, + { + .gpio = 11, /* BLSP1 QUP3 I2C_CLK */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_i2c_config, + }, + }, +}; + +/* [houjihai start] */ +static struct gpiomux_setting key_active_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting key_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_8MA, + .pull = GPIOMUX_PULL_NONE, +}; +/* [houjihai end] */ + +/* [houjihai start] gpio14 for wps key and gpio15 for reset*/ +static struct msm_gpiomux_config mdm9625_key_configs[] __initdata = { + { + .gpio = 15, + .settings = { + [GPIOMUX_SUSPENDED] = &key_suspend_cfg, + [GPIOMUX_ACTIVE] = &key_active_cfg, + }, + }, +}; +/* [houjihai end] */ + +static struct gpiomux_setting wlan_ath6kl_active_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_OUT_LOW, +}; + +static struct gpiomux_setting wlan_ath6kl_suspend_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_IN, +}; + +static struct msm_gpiomux_config wlan_ath6kl_configs[] __initdata = { + { + .gpio = 62,/* CHIP_PWD_L */ + .settings = { + [GPIOMUX_ACTIVE] = &wlan_ath6kl_active_config, + [GPIOMUX_SUSPENDED] = &wlan_ath6kl_suspend_config, + }, + }, +}; + +static struct gpiomux_setting sdc2_card_det_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_DOWN, + .dir = GPIOMUX_IN, +}; + +struct msm_gpiomux_config sdc2_card_det_config[] __initdata = { + { + .gpio = 66, + .settings = { + [GPIOMUX_ACTIVE] = &sdc2_card_det_cfg, + [GPIOMUX_SUSPENDED] = &sdc2_card_det_cfg, + }, + }, +}; + +#ifdef CONFIG_FB_MSM_QPIC +static struct gpiomux_setting qpic_lcdc_a_d = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_10MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting qpic_lcdc_cs = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_10MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting qpic_lcdc_rs = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_10MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting qpic_lcdc_te = { + .func = GPIOMUX_FUNC_7, + .drv = GPIOMUX_DRV_10MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct msm_gpiomux_config msm9625_qpic_lcdc_configs[] __initdata = { + { + .gpio = 20, /* a_d */ + .settings = { + [GPIOMUX_SUSPENDED] = &qpic_lcdc_a_d, + }, + }, + { + .gpio = 21, /* cs */ + .settings = { + [GPIOMUX_SUSPENDED] = &qpic_lcdc_cs, + }, + }, + { + .gpio = 22, /* te */ + .settings = { + [GPIOMUX_SUSPENDED] = &qpic_lcdc_te, + }, + }, + { + .gpio = 23, /* rs */ + .settings = { + [GPIOMUX_SUSPENDED] = &qpic_lcdc_rs, + }, + }, +}; + +static void msm9625_disp_init_gpiomux(void) +{ + msm_gpiomux_install(msm9625_qpic_lcdc_configs, + ARRAY_SIZE(msm9625_qpic_lcdc_configs)); +} +#else +static void msm9625_disp_init_gpiomux(void) +{ +} +#endif /* CONFIG_FB_MSM_QPIC */ + +#ifdef CONFIG_MP2617_CHARGER +static struct gpiomux_setting mp2617_gpio_input_active_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_IN, +}; + +static struct gpiomux_setting mp2617_gpio_input_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, + .dir = GPIOMUX_IN, +}; + +static struct gpiomux_setting mp2617_gpio_output_active_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting mp2617_gpio_output_suspend_cfg = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +/* refer to msm9625-mtp.dtsi */ +static struct msm_gpiomux_config msm9625_mp2617_configs[] __initdata = { + { + .gpio = 13, /* Charge Enable, 1: Enable, 0: Disable */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_output_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_output_suspend_cfg, + }, + }, + { + .gpio = 16, /* M0 */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_output_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_output_suspend_cfg, + }, + }, + { + .gpio = 17, /* M1 */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_output_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_output_suspend_cfg, + }, + }, + { + .gpio = 70, /* CHGOK, 0: Charging, 1: Complete */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_input_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_input_suspend_cfg, + }, + }, + +#ifdef CONFIG_POWER_BANK_DETECT_SUPPORT + { + .gpio = 14, /* Boost_EN, 0: Disbale, 1: Enable */ + .settings = { + [GPIOMUX_ACTIVE] = &mp2617_gpio_output_active_cfg, + [GPIOMUX_SUSPENDED] = &mp2617_gpio_output_suspend_cfg, + }, + }, +#endif +}; +#endif + +#ifdef CONFIG_OLED_SSD1306_PT +static struct gpiomux_setting oled_ssd1306_gpio_active_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_UP, + .dir = GPIOMUX_OUT_HIGH, +}; + +static struct gpiomux_setting oled_ssd1306_gpio_suspend_config = { + .func = GPIOMUX_FUNC_GPIO, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct gpiomux_setting oled_ssd1306_gpio_cs_config = { + .func = GPIOMUX_FUNC_1, + .drv = GPIOMUX_DRV_2MA, + .pull = GPIOMUX_PULL_NONE, +}; + +static struct msm_gpiomux_config msm9625_oled_ssd1306_configs[] __initdata = { + { + .gpio = 4, /* oled ssd1306 chip select */ + .settings = { + [GPIOMUX_SUSPENDED] = &oled_ssd1306_gpio_suspend_config, + [GPIOMUX_ACTIVE] = &oled_ssd1306_gpio_active_config, + }, + }, + { + .gpio = 5, /* oled ssd1306 a0 */ + .settings = { + [GPIOMUX_SUSPENDED] = &oled_ssd1306_gpio_suspend_config, + [GPIOMUX_ACTIVE] = &oled_ssd1306_gpio_active_config, + }, + }, + { + .gpio = 6, /* oled ssd1306 reset */ + .settings = { + [GPIOMUX_SUSPENDED] = &oled_ssd1306_gpio_cs_config, + [GPIOMUX_ACTIVE] = &oled_ssd1306_gpio_active_config, + }, + }, + { + .gpio = 7, /* oled ssd1306 boost enable */ + .settings = { + [GPIOMUX_SUSPENDED] = &oled_ssd1306_gpio_suspend_config, + [GPIOMUX_ACTIVE] = &oled_ssd1306_gpio_active_config, + }, + }, + { + .gpio = 10, /* oled ssd1306 I2C_DAT */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_i2c_config, + }, + }, + { + .gpio = 11, /* oled ssd1306 I2C_CLK */ + .settings = { + [GPIOMUX_SUSPENDED] = &gpio_i2c_config, + }, + }, +}; +#endif + +void __init msm9625_init_gpiomux(void) +{ + int rc; + + rc = msm_gpiomux_init_dt(); + if (rc) { + pr_err("%s failed %d\n", __func__, rc); + return; + } + + msm_gpiomux_install(msm_blsp_configs, ARRAY_SIZE(msm_blsp_configs)); + msm_gpiomux_install(wlan_ath6kl_configs, + ARRAY_SIZE(wlan_ath6kl_configs)); + /* [houjihai start] */ + msm_gpiomux_install(mdm9625_key_configs, + ARRAY_SIZE(mdm9625_key_configs)); + /* [houjihai end] */ + msm_gpiomux_install(sdc2_card_det_config, + ARRAY_SIZE(sdc2_card_det_config)); + msm9625_disp_init_gpiomux(); + +#ifdef CONFIG_MP2617_CHARGER + msm_gpiomux_install(msm9625_mp2617_configs, + ARRAY_SIZE(msm9625_mp2617_configs)); +#endif + +#ifdef CONFIG_OLED_SSD1306_PT + msm_gpiomux_install(msm9625_oled_ssd1306_configs, + ARRAY_SIZE(msm9625_oled_ssd1306_configs)); +#endif +} diff --git a/kernel/arch/arm/mach-msm/gpiomux.c b/kernel/arch/arm/mach-msm/gpiomux.c index 1f7d56aff..d710214f9 100644 --- a/kernel/arch/arm/mach-msm/gpiomux.c +++ b/kernel/arch/arm/mach-msm/gpiomux.c @@ -67,6 +67,16 @@ int msm_gpiomux_write(unsigned gpio, enum msm_gpiomux_setting which, unsigned long irq_flags; struct gpiomux_setting *new_set; struct msm_gpiomux_rec *rec = msm_gpiomux_recs + gpio; +/* [zhangtao start] */ +#ifdef CONFIG_OLED_SSD1306_PT + enum OLED_SSD1306_GPIO_NUM { + GPIO_OLED_CS = 4, + GPIO_OLED_A0 = 5, + GPIO_OLED_RES = 6, + GPIO_OLED_BOOST_EN = 7, + }; +#endif +/* [zhangtao end] */ ret = msm_gpiomux_store(gpio, which, setting, old_setting); if (ret < 0) @@ -74,8 +84,32 @@ int msm_gpiomux_write(unsigned gpio, enum msm_gpiomux_setting which, spin_lock_irqsave(&gpiomux_lock, irq_flags); +/* [zhangtao start] */ +#ifdef CONFIG_OLED_SSD1306_PT + switch (gpio) + { + case GPIO_OLED_CS: + case GPIO_OLED_A0: + case GPIO_OLED_RES: + case GPIO_OLED_BOOST_EN: + if (old_setting == NULL) { // initialise oled gpio with active config + new_set = rec->sets[GPIOMUX_ACTIVE]; + } else { + new_set = rec->ref ? rec->sets[GPIOMUX_ACTIVE] : + rec->sets[GPIOMUX_SUSPENDED]; + } + break; + + default: + new_set = rec->ref ? rec->sets[GPIOMUX_ACTIVE] : + rec->sets[GPIOMUX_SUSPENDED]; + break; + } +#else new_set = rec->ref ? rec->sets[GPIOMUX_ACTIVE] : rec->sets[GPIOMUX_SUSPENDED]; +#endif +/* [zhangtao end] */ if (new_set) __msm_gpiomux_write(gpio, *new_set); diff --git a/kernel/arch/microblaze/boot/dts/system.dts b/kernel/arch/microblaze/boot/dts/system.dts deleted file mode 100644 index 3f85df2b7..000000000 --- a/kernel/arch/microblaze/boot/dts/system.dts +++ /dev/null @@ -1,367 +0,0 @@ -/* - * Device Tree Generator version: 1.1 - * - * (C) Copyright 2007-2008 Xilinx, Inc. - * (C) Copyright 2007-2009 Michal Simek - * - * Michal SIMEK - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 - * - * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101 - */ - -/dts-v1/; -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,microblaze"; - hard-reset-gpios = <&LEDs_8Bit 2 1>; - model = "testing"; - DDR2_SDRAM: memory@90000000 { - device_type = "memory"; - reg = < 0x90000000 0x10000000 >; - } ; - aliases { - ethernet0 = &Hard_Ethernet_MAC; - serial0 = &RS232_Uart_1; - } ; - chosen { - bootargs = "console=ttyUL0,115200 highres=on"; - linux,stdout-path = "/plb@0/serial@84000000"; - } ; - cpus { - #address-cells = <1>; - #cpus = <0x1>; - #size-cells = <0>; - microblaze_0: cpu@0 { - clock-frequency = <125000000>; - compatible = "xlnx,microblaze-7.10.d"; - d-cache-baseaddr = <0x90000000>; - d-cache-highaddr = <0x9fffffff>; - d-cache-line-size = <0x10>; - d-cache-size = <0x2000>; - device_type = "cpu"; - i-cache-baseaddr = <0x90000000>; - i-cache-highaddr = <0x9fffffff>; - i-cache-line-size = <0x10>; - i-cache-size = <0x2000>; - model = "microblaze,7.10.d"; - reg = <0>; - timebase-frequency = <125000000>; - xlnx,addr-tag-bits = <0xf>; - xlnx,allow-dcache-wr = <0x1>; - xlnx,allow-icache-wr = <0x1>; - xlnx,area-optimized = <0x0>; - xlnx,cache-byte-size = <0x2000>; - xlnx,d-lmb = <0x1>; - xlnx,d-opb = <0x0>; - xlnx,d-plb = <0x1>; - xlnx,data-size = <0x20>; - xlnx,dcache-addr-tag = <0xf>; - xlnx,dcache-always-used = <0x1>; - xlnx,dcache-byte-size = <0x2000>; - xlnx,dcache-line-len = <0x4>; - xlnx,dcache-use-fsl = <0x1>; - xlnx,debug-enabled = <0x1>; - xlnx,div-zero-exception = <0x1>; - xlnx,dopb-bus-exception = <0x0>; - xlnx,dynamic-bus-sizing = <0x1>; - xlnx,edge-is-positive = <0x1>; - xlnx,family = "virtex5"; - xlnx,endianness = <0x1>; - xlnx,fpu-exception = <0x1>; - xlnx,fsl-data-size = <0x20>; - xlnx,fsl-exception = <0x0>; - xlnx,fsl-links = <0x0>; - xlnx,i-lmb = <0x1>; - xlnx,i-opb = <0x0>; - xlnx,i-plb = <0x1>; - xlnx,icache-always-used = <0x1>; - xlnx,icache-line-len = <0x4>; - xlnx,icache-use-fsl = <0x1>; - xlnx,ill-opcode-exception = <0x1>; - xlnx,instance = "microblaze_0"; - xlnx,interconnect = <0x1>; - xlnx,interrupt-is-edge = <0x0>; - xlnx,iopb-bus-exception = <0x0>; - xlnx,mmu-dtlb-size = <0x4>; - xlnx,mmu-itlb-size = <0x2>; - xlnx,mmu-tlb-access = <0x3>; - xlnx,mmu-zones = <0x10>; - xlnx,number-of-pc-brk = <0x1>; - xlnx,number-of-rd-addr-brk = <0x0>; - xlnx,number-of-wr-addr-brk = <0x0>; - xlnx,opcode-0x0-illegal = <0x1>; - xlnx,pvr = <0x2>; - xlnx,pvr-user1 = <0x0>; - xlnx,pvr-user2 = <0x0>; - xlnx,reset-msr = <0x0>; - xlnx,sco = <0x0>; - xlnx,unaligned-exceptions = <0x1>; - xlnx,use-barrel = <0x1>; - xlnx,use-dcache = <0x1>; - xlnx,use-div = <0x1>; - xlnx,use-ext-brk = <0x1>; - xlnx,use-ext-nm-brk = <0x1>; - xlnx,use-extended-fsl-instr = <0x0>; - xlnx,use-fpu = <0x2>; - xlnx,use-hw-mul = <0x2>; - xlnx,use-icache = <0x1>; - xlnx,use-interrupt = <0x1>; - xlnx,use-mmu = <0x3>; - xlnx,use-msr-instr = <0x1>; - xlnx,use-pcmp-instr = <0x1>; - } ; - } ; - mb_plb: plb@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus"; - ranges ; - FLASH: flash@a0000000 { - bank-width = <2>; - compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; - reg = < 0xa0000000 0x2000000 >; - xlnx,family = "virtex5"; - xlnx,include-datawidth-matching-0 = <0x1>; - xlnx,include-datawidth-matching-1 = <0x0>; - xlnx,include-datawidth-matching-2 = <0x0>; - xlnx,include-datawidth-matching-3 = <0x0>; - xlnx,include-negedge-ioregs = <0x0>; - xlnx,include-plb-ipif = <0x1>; - xlnx,include-wrbuf = <0x1>; - xlnx,max-mem-width = <0x10>; - xlnx,mch-native-dwidth = <0x20>; - xlnx,mch-plb-clk-period-ps = <0x1f40>; - xlnx,mch-splb-awidth = <0x20>; - xlnx,mch0-accessbuf-depth = <0x10>; - xlnx,mch0-protocol = <0x0>; - xlnx,mch0-rddatabuf-depth = <0x10>; - xlnx,mch1-accessbuf-depth = <0x10>; - xlnx,mch1-protocol = <0x0>; - xlnx,mch1-rddatabuf-depth = <0x10>; - xlnx,mch2-accessbuf-depth = <0x10>; - xlnx,mch2-protocol = <0x0>; - xlnx,mch2-rddatabuf-depth = <0x10>; - xlnx,mch3-accessbuf-depth = <0x10>; - xlnx,mch3-protocol = <0x0>; - xlnx,mch3-rddatabuf-depth = <0x10>; - xlnx,mem0-width = <0x10>; - xlnx,mem1-width = <0x20>; - xlnx,mem2-width = <0x20>; - xlnx,mem3-width = <0x20>; - xlnx,num-banks-mem = <0x1>; - xlnx,num-channels = <0x0>; - xlnx,priority-mode = <0x0>; - xlnx,synch-mem-0 = <0x0>; - xlnx,synch-mem-1 = <0x0>; - xlnx,synch-mem-2 = <0x0>; - xlnx,synch-mem-3 = <0x0>; - xlnx,synch-pipedelay-0 = <0x2>; - xlnx,synch-pipedelay-1 = <0x2>; - xlnx,synch-pipedelay-2 = <0x2>; - xlnx,synch-pipedelay-3 = <0x2>; - xlnx,tavdv-ps-mem-0 = <0x1adb0>; - xlnx,tavdv-ps-mem-1 = <0x3a98>; - xlnx,tavdv-ps-mem-2 = <0x3a98>; - xlnx,tavdv-ps-mem-3 = <0x3a98>; - xlnx,tcedv-ps-mem-0 = <0x1adb0>; - xlnx,tcedv-ps-mem-1 = <0x3a98>; - xlnx,tcedv-ps-mem-2 = <0x3a98>; - xlnx,tcedv-ps-mem-3 = <0x3a98>; - xlnx,thzce-ps-mem-0 = <0x88b8>; - xlnx,thzce-ps-mem-1 = <0x1b58>; - xlnx,thzce-ps-mem-2 = <0x1b58>; - xlnx,thzce-ps-mem-3 = <0x1b58>; - xlnx,thzoe-ps-mem-0 = <0x1b58>; - xlnx,thzoe-ps-mem-1 = <0x1b58>; - xlnx,thzoe-ps-mem-2 = <0x1b58>; - xlnx,thzoe-ps-mem-3 = <0x1b58>; - xlnx,tlzwe-ps-mem-0 = <0x88b8>; - xlnx,tlzwe-ps-mem-1 = <0x0>; - xlnx,tlzwe-ps-mem-2 = <0x0>; - xlnx,tlzwe-ps-mem-3 = <0x0>; - xlnx,twc-ps-mem-0 = <0x2af8>; - xlnx,twc-ps-mem-1 = <0x3a98>; - xlnx,twc-ps-mem-2 = <0x3a98>; - xlnx,twc-ps-mem-3 = <0x3a98>; - xlnx,twp-ps-mem-0 = <0x11170>; - xlnx,twp-ps-mem-1 = <0x2ee0>; - xlnx,twp-ps-mem-2 = <0x2ee0>; - xlnx,twp-ps-mem-3 = <0x2ee0>; - xlnx,xcl0-linesize = <0x4>; - xlnx,xcl0-writexfer = <0x1>; - xlnx,xcl1-linesize = <0x4>; - xlnx,xcl1-writexfer = <0x1>; - xlnx,xcl2-linesize = <0x4>; - xlnx,xcl2-writexfer = <0x1>; - xlnx,xcl3-linesize = <0x4>; - xlnx,xcl3-writexfer = <0x1>; - } ; - Hard_Ethernet_MAC: xps-ll-temac@81c00000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,compound"; - ranges ; - ethernet@81c00000 { - compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a"; - device_type = "network"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 5 2 >; - llink-connected = <&PIM3>; - local-mac-address = [ 00 0a 35 00 00 00 ]; - reg = < 0x81c00000 0x40 >; - xlnx,bus2core-clk-ratio = <0x1>; - xlnx,phy-type = <0x1>; - xlnx,phyaddr = <0x1>; - xlnx,rxcsum = <0x0>; - xlnx,rxfifo = <0x1000>; - xlnx,temac-type = <0x0>; - xlnx,txcsum = <0x0>; - xlnx,txfifo = <0x1000>; - } ; - } ; - IIC_EEPROM: i2c@81600000 { - compatible = "xlnx,xps-iic-2.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 6 2 >; - reg = < 0x81600000 0x10000 >; - xlnx,clk-freq = <0x7735940>; - xlnx,family = "virtex5"; - xlnx,gpo-width = <0x1>; - xlnx,iic-freq = <0x186a0>; - xlnx,scl-inertial-delay = <0x0>; - xlnx,sda-inertial-delay = <0x0>; - xlnx,ten-bit-adr = <0x0>; - } ; - LEDs_8Bit: gpio@81400000 { - compatible = "xlnx,xps-gpio-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 7 2 >; - reg = < 0x81400000 0x10000 >; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,dout-default = <0x0>; - xlnx,dout-default-2 = <0x0>; - xlnx,family = "virtex5"; - xlnx,gpio-width = <0x8>; - xlnx,interrupt-present = <0x1>; - xlnx,is-bidir = <0x1>; - xlnx,is-bidir-2 = <0x1>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; - #gpio-cells = <2>; - gpio-controller; - } ; - - gpio-leds { - compatible = "gpio-leds"; - - heartbeat { - label = "Heartbeat"; - gpios = <&LEDs_8Bit 4 1>; - linux,default-trigger = "heartbeat"; - }; - - yellow { - label = "Yellow"; - gpios = <&LEDs_8Bit 5 1>; - }; - - red { - label = "Red"; - gpios = <&LEDs_8Bit 6 1>; - }; - - green { - label = "Green"; - gpios = <&LEDs_8Bit 7 1>; - }; - } ; - RS232_Uart_1: serial@84000000 { - clock-frequency = <125000000>; - compatible = "xlnx,xps-uartlite-1.00.a"; - current-speed = <115200>; - device_type = "serial"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 8 0 >; - port-number = <0>; - reg = < 0x84000000 0x10000 >; - xlnx,baudrate = <0x1c200>; - xlnx,data-bits = <0x8>; - xlnx,family = "virtex5"; - xlnx,odd-parity = <0x0>; - xlnx,use-parity = <0x0>; - } ; - SysACE_CompactFlash: sysace@83600000 { - compatible = "xlnx,xps-sysace-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 4 2 >; - reg = < 0x83600000 0x10000 >; - xlnx,family = "virtex5"; - xlnx,mem-width = <0x10>; - } ; - debug_module: debug@84400000 { - compatible = "xlnx,mdm-1.00.d"; - reg = < 0x84400000 0x10000 >; - xlnx,family = "virtex5"; - xlnx,interconnect = <0x1>; - xlnx,jtag-chain = <0x2>; - xlnx,mb-dbg-ports = <0x1>; - xlnx,uart-width = <0x8>; - xlnx,use-uart = <0x1>; - xlnx,write-fsl-ports = <0x0>; - } ; - mpmc@90000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,mpmc-4.02.a"; - ranges ; - PIM3: sdma@84600180 { - compatible = "xlnx,ll-dma-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 2 2 1 2 >; - reg = < 0x84600180 0x80 >; - } ; - } ; - xps_intc_0: interrupt-controller@81800000 { - #interrupt-cells = <0x2>; - compatible = "xlnx,xps-intc-1.00.a"; - interrupt-controller ; - reg = < 0x81800000 0x10000 >; - xlnx,kind-of-intr = <0x100>; - xlnx,num-intr-inputs = <0x9>; - } ; - xps_timer_1: timer@83c00000 { - compatible = "xlnx,xps-timer-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 3 2 >; - reg = < 0x83c00000 0x10000 >; - xlnx,count-width = <0x20>; - xlnx,family = "virtex5"; - xlnx,gen0-assert = <0x1>; - xlnx,gen1-assert = <0x1>; - xlnx,one-timer-only = <0x0>; - xlnx,trig0-assert = <0x1>; - xlnx,trig1-assert = <0x1>; - } ; - } ; -} ; diff --git a/kernel/arch/microblaze/boot/dts/system.dts b/kernel/arch/microblaze/boot/dts/system.dts new file mode 120000 index 000000000..7cb657892 --- /dev/null +++ b/kernel/arch/microblaze/boot/dts/system.dts @@ -0,0 +1 @@ +../../platform/generic/system.dts \ No newline at end of file diff --git a/kernel/drivers/mtd/devices/Kconfig b/kernel/drivers/mtd/devices/Kconfig index bc0576409..6c21bf8e4 100644 --- a/kernel/drivers/mtd/devices/Kconfig +++ b/kernel/drivers/mtd/devices/Kconfig @@ -357,4 +357,8 @@ config MTD_DOCPROBE_55AA LinuxBIOS or if you need to recover a DiskOnChip Millennium on which you have managed to wipe the first block. +config FLASH_TYPE_ETRON + bool "Etron Flash" + default n + endmenu diff --git a/kernel/drivers/mtd/devices/msm_qpic_nand.c b/kernel/drivers/mtd/devices/msm_qpic_nand.c index d1bd7cc34..8ad15a361 100755 --- a/kernel/drivers/mtd/devices/msm_qpic_nand.c +++ b/kernel/drivers/mtd/devices/msm_qpic_nand.c @@ -2068,7 +2068,7 @@ int msm_nand_scan(struct mtd_info *mtd) int flash_id = 0, err = 0; uint32_t i, mtd_writesize; uint8_t dev_found = 0, wide_bus; - uint32_t manid, devid, devcfg; + uint32_t manid = 0, devid = 0, devcfg; uint32_t bad_block_byte; struct nand_flash_dev *flashdev = NULL; struct nand_manufacturers *flashman = NULL; @@ -2107,6 +2107,16 @@ int msm_nand_scan(struct mtd_info *mtd) ((devcfg >> 4) & 0x3); supported_flash->oobsize = (8 << ((devcfg >> 2) & 1)) * (supported_flash->pagesize >> 9); + +#if 0 +#ifdef CONFIG_FLASH_TYPE_ETRON + supported_flash->oobsize = 128; +#endif +#endif + if((manid == ETRON_2G1G_MANID) && (devid == ETRON_2G1G_DEVID)) { + supported_flash->oobsize = 128; + } + } else { supported_flash->widebus = flashdev->options & NAND_BUSWIDTH_16 ? 1 : 0; @@ -2116,6 +2126,7 @@ int msm_nand_scan(struct mtd_info *mtd) } supported_flash->flash_id = flash_id; supported_flash->density = flashdev->chipsize << 20; + //supported_flash->oobsize = 128; } if (dev_found) { @@ -2132,6 +2143,15 @@ int msm_nand_scan(struct mtd_info *mtd) else chip->bch_caps = MSM_NAND_CAP_4_BIT_BCH; +#if 0 +#ifdef CONFIG_FLASH_TYPE_ETRON + chip->bch_caps = MSM_NAND_CAP_8_BIT_BCH; +#endif +#endif + if((manid == ETRON_2G1G_MANID) && (devid == ETRON_2G1G_DEVID)) { + chip->bch_caps = MSM_NAND_CAP_8_BIT_BCH; + } + pr_info("NAND Id: 0x%x Buswidth: %dBits Density: %lld MByte\n", supported_flash->flash_id, (wide_bus) ? 16 : 8, (mtd->size >> 20)); diff --git a/kernel/drivers/mtd/nand/nand_ids.c b/kernel/drivers/mtd/nand/nand_ids.c index 6973e4873..8ad9ccddd 100644 --- a/kernel/drivers/mtd/nand/nand_ids.c +++ b/kernel/drivers/mtd/nand/nand_ids.c @@ -169,7 +169,14 @@ struct nand_flash_dev nand_flash_ids[] = { * Manufacturer ID list */ struct nand_manufacturers nand_manuf_ids[] = { +#if 0 +#ifdef CONFIG_FLASH_TYPE_ETRON + {NAND_MFR_ETRON, "Etron"}, +#else {NAND_MFR_TOSHIBA, "Toshiba"}, +#endif +#endif + {NAND_MFR_ETRON, "Etron"}, {NAND_MFR_SAMSUNG, "Samsung"}, {NAND_MFR_FUJITSU, "Fujitsu"}, {NAND_MFR_NATIONAL, "National"}, diff --git a/kernel/drivers/usb/core/driver.c b/kernel/drivers/usb/core/driver.c index 23826403b..46dc5de92 100644 --- a/kernel/drivers/usb/core/driver.c +++ b/kernel/drivers/usb/core/driver.c @@ -1218,7 +1218,21 @@ static int usb_suspend_both(struct usb_device *udev, pm_message_t msg) } else { udev->can_submit = 0; for (i = 0; i < 16; ++i) { - usb_hcd_flush_endpoint(udev, udev->ep_out[i]); + struct urb *urb; + struct usb_host_endpoint *ep = udev->ep_out[i]; + bool hbm_enabled_ep = false; + if (ep && !list_empty(&ep->urb_list)) { + urb = list_first_entry(&ep->urb_list, + struct urb, urb_list); + if (urb->priv_data) + hbm_enabled_ep = true; + } + if (hbm_enabled_ep) { + pr_info("Not flushing HBM-EP on susp:%p:%p\n", + urb, urb->priv_data); + } else { + usb_hcd_flush_endpoint(udev, udev->ep_out[i]); + } usb_hcd_flush_endpoint(udev, udev->ep_in[i]); } } diff --git a/kernel/drivers/usb/host/ehci-msm-hsic.c b/kernel/drivers/usb/host/ehci-msm-hsic.c index 011450d79..bafed0c72 100644 --- a/kernel/drivers/usb/host/ehci-msm-hsic.c +++ b/kernel/drivers/usb/host/ehci-msm-hsic.c @@ -53,7 +53,7 @@ #define MSM_USB_BASE (hcd->regs) #define USB_REG_START_OFFSET 0x90 -#define USB_REG_END_OFFSET 0x250 +#define USB_REG_END_OFFSET 0x324 static struct workqueue_struct *ehci_wq; struct ehci_timer { @@ -127,6 +127,9 @@ module_param(ep_addr_rxdbg_mask, uint, S_IRUGO | S_IWUSR); static unsigned int ep_addr_txdbg_mask = 9; module_param(ep_addr_txdbg_mask, uint, S_IRUGO | S_IWUSR); +static unsigned int dbg_qh_addr; +module_param(dbg_qh_addr, uint, S_IRUGO | S_IWUSR); + /* Maximum debug message length */ #define DBG_MSG_LEN 128UL @@ -318,6 +321,44 @@ static inline struct usb_hcd *hsic_to_hcd(struct msm_hsic_hcd *mehci) return container_of((void *) mehci, struct usb_hcd, hcd_priv); } +static void dbg_msm_qh(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + struct ehci_qh_hw *hw = qh->hw; + + pr_info("EP:%x qh %p info %x %x c_qtd-%08x\n", + (hw->hw_info1 & 0xF00) >> 8, qh, hw->hw_info1, + hw->hw_info2, hw->hw_current); + pr_info("overlay n%08x %08x t-%08x nak-%x c_err %x\n", + hw->hw_qtd_next, hw->hw_alt_next, + hw->hw_token, + (hw->hw_alt_next & 0xE)>>1, (hw->hw_token & 0xC00) >> 10); +} + +static void dump_msm_qhs(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct ehci_qh *qh, *qh_next; + unsigned long flags; + int i; + + for (i = 0; i < 5; i++) { + pr_info("Dump QHs, iteration:%d\n", i); + spin_lock_irqsave(&ehci->lock, flags); + qh_next = ehci->async->qh_next.qh; + while (qh_next) { + qh = qh_next; + qh_next = qh->qh_next.qh; + + if (!dbg_qh_addr || + ((struct ehci_qh *)dbg_qh_addr) == qh) + dbg_msm_qh(ehci, qh); + } + spin_unlock_irqrestore(&ehci->lock, flags); + usleep_range(5000, 10000); + } +} + + static void dump_hsic_regs(struct usb_hcd *hcd) { int i; @@ -1799,6 +1840,27 @@ const struct file_operations ehci_hsic_msm_dbg_ctrl_fops = { .release = single_release, }; +static int ehci_hsic_msm_qh_show(struct seq_file *s, void *unused) +{ + struct msm_hsic_hcd *mehci = s->private; + + dump_msm_qhs(hsic_to_hcd(mehci)); + + return 0; +} + +static int ehci_hsic_msm_qh_open(struct inode *inode, struct file *f) +{ + return single_open(f, ehci_hsic_msm_qh_show, inode->i_private); +} + +const struct file_operations ehci_hsic_msm_qh_fops = { + .open = ehci_hsic_msm_qh_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + static struct dentry *ehci_hsic_msm_dbg_root; static int ehci_hsic_msm_debugfs_init(struct msm_hsic_hcd *mehci) { @@ -1849,6 +1911,16 @@ static int ehci_hsic_msm_debugfs_init(struct msm_hsic_hcd *mehci) return -ENODEV; } + ehci_hsic_msm_dentry = debugfs_create_file("show_hsic_qh", + S_IRUGO, + ehci_hsic_msm_dbg_root, mehci, + &ehci_hsic_msm_qh_fops); + + if (!ehci_hsic_msm_dentry) { + debugfs_remove_recursive(ehci_hsic_msm_dbg_root); + return -ENODEV; + } + return 0; } diff --git a/kernel/drivers/usb/host/hbm.c b/kernel/drivers/usb/host/hbm.c index 320c6f4f5..89621acc2 100644 --- a/kernel/drivers/usb/host/hbm.c +++ b/kernel/drivers/usb/host/hbm.c @@ -170,10 +170,10 @@ int hbm_pipe_init(u32 QH_addr, u32 pipe_num, bool is_consumer) 1 << pipe_num, 0); /* Reset HBM SideBand */ - hbm_msm_write_reg_field(hbm_ctx->base, USB_OTG_HS_HBM_SB_SW_RST, 1 << 0, - 1); - hbm_msm_write_reg_field(hbm_ctx->base, USB_OTG_HS_HBM_SB_SW_RST, 1 << 0, - 0); + hbm_msm_write_reg_field(hbm_ctx->base, USB_OTG_HS_HBM_SB_SW_RST, + 1 << pipe_num, 1); + hbm_msm_write_reg_field(hbm_ctx->base, USB_OTG_HS_HBM_SB_SW_RST, + 1 << pipe_num, 0); /* map QH(ep) <> pipe */ hbm_msm_write_reg(hbm_ctx->base, @@ -230,7 +230,7 @@ static int hbm_submit_async(struct ehci_hcd *ehci, struct urb *urb, { int epnum; unsigned long flags; - struct ehci_qh *qh = NULL; + struct ehci_qh *qh = (struct ehci_qh *) urb->ep->hcpriv; int rc; struct usb_host_bam_type *bam = (struct usb_host_bam_type *)urb->priv_data; @@ -247,6 +247,9 @@ static int hbm_submit_async(struct ehci_hcd *ehci, struct urb *urb, if (unlikely(rc)) goto done; + if (qh != NULL) + pr_debug("%s: QH NOT NULL (%p)\n", __func__, qh); + qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); if (unlikely(qh == NULL)) { usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); @@ -263,8 +266,10 @@ static int hbm_submit_async(struct ehci_hcd *ehci, struct urb *urb, hbm_pipe_init(qh->qh_dma, bam->pipe_num, bam->dir); - if (likely(qh->qh_state == QH_STATE_IDLE)) + if (likely(qh->qh_state == QH_STATE_IDLE)) { + pr_debug("%s: QH was IDLE (%p)\n", __func__, qh); qh_link_async(ehci, qh); + } /* Start Async Scheduler */ cmd = ehci_readl(ehci, &ehci->regs->command); @@ -277,8 +282,13 @@ static int hbm_submit_async(struct ehci_hcd *ehci, struct urb *urb, done: spin_unlock_irqrestore(&ehci->lock, flags); + + pr_debug("QH:%p urb:%p <--> pipe:%u ep:%d(out:%u)\n", + urb->ep->hcpriv, urb, bam->pipe_num, epnum, bam->dir); + if (unlikely(qh == NULL)) qtd_list_free(ehci, urb, qtd_list); + return rc; } diff --git a/kernel/include/linux/mtd/nand.h b/kernel/include/linux/mtd/nand.h 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brace_group','compound_command',1,'p_compound_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',209), + ('compound_command -> subshell','compound_command',1,'p_compound_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',210), + ('compound_command -> for_clause','compound_command',1,'p_compound_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',211), + ('compound_command -> case_clause','compound_command',1,'p_compound_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',212), + ('compound_command -> if_clause','compound_command',1,'p_compound_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',213), + ('compound_command -> while_clause','compound_command',1,'p_compound_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',214), + ('compound_command -> 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and_or','term',3,'p_term','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',238), + ('term -> and_or','term',1,'p_term','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',239), + ('maybe_for_word -> For','maybe_for_word',1,'p_maybe_for_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',249), + ('for_clause -> for_word name linebreak do_group','for_clause',4,'p_for_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',254), + ('for_clause -> for_word name linebreak in sequential_sep do_group','for_clause',6,'p_for_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',255), + ('for_clause -> for_word name linebreak in wordlist sequential_sep do_group','for_clause',7,'p_for_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',256), + ('name -> token','name',1,'p_name','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',273), + ('in -> In','in',1,'p_in','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',277), + ('wordlist -> wordlist token','wordlist',2,'p_wordlist','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',281), + ('wordlist -> token','wordlist',1,'p_wordlist','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',282), + ('case_clause -> Case token linebreak in linebreak case_list Esac','case_clause',7,'p_case_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',289), + ('case_clause -> Case token linebreak in linebreak case_list_ns Esac','case_clause',7,'p_case_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',290), + ('case_clause -> Case token linebreak in linebreak Esac','case_clause',6,'p_case_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',291), + ('case_list_ns -> case_list case_item_ns','case_list_ns',2,'p_case_list_ns','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',300), + ('case_list_ns -> case_item_ns','case_list_ns',1,'p_case_list_ns','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',301), + ('case_list -> case_list case_item','case_list',2,'p_case_list','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',305), + ('case_list -> case_item','case_list',1,'p_case_list','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',306), + ('case_item_ns -> pattern RPARENS linebreak','case_item_ns',3,'p_case_item_ns','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',313), + ('case_item_ns -> pattern RPARENS compound_list linebreak','case_item_ns',4,'p_case_item_ns','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',314), + ('case_item_ns -> LPARENS pattern RPARENS linebreak','case_item_ns',4,'p_case_item_ns','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',315), + ('case_item_ns -> LPARENS pattern RPARENS compound_list linebreak','case_item_ns',5,'p_case_item_ns','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',316), + ('case_item -> pattern RPARENS linebreak DSEMI linebreak','case_item',5,'p_case_item','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',320), + ('case_item -> pattern RPARENS compound_list DSEMI linebreak','case_item',5,'p_case_item','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',321), + ('case_item -> LPARENS pattern RPARENS linebreak DSEMI linebreak','case_item',6,'p_case_item','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',322), + ('case_item -> LPARENS pattern RPARENS compound_list DSEMI linebreak','case_item',6,'p_case_item','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',323), + ('pattern -> token','pattern',1,'p_pattern','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',337), + ('pattern -> pattern PIPE token','pattern',3,'p_pattern','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',338), + ('maybe_if_word -> If','maybe_if_word',1,'p_maybe_if_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',345), + ('maybe_then_word -> Then','maybe_then_word',1,'p_maybe_then_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',350), + ('if_clause -> if_word compound_list then_word compound_list else_part Fi','if_clause',6,'p_if_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',355), + ('if_clause -> if_word compound_list then_word compound_list Fi','if_clause',5,'p_if_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',356), + ('else_part -> Elif compound_list then_word compound_list else_part','else_part',5,'p_else_part','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',363), + ('else_part -> Elif compound_list then_word compound_list','else_part',4,'p_else_part','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',364), + ('else_part -> Else compound_list','else_part',2,'p_else_part','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',365), + ('while_clause -> While compound_list do_group','while_clause',3,'p_while_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',375), + ('maybe_until_word -> Until','maybe_until_word',1,'p_maybe_until_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',379), + ('until_clause -> until_word compound_list do_group','until_clause',3,'p_until_clause','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',384), + ('function_definition -> fname LPARENS RPARENS linebreak function_body','function_definition',5,'p_function_definition','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',388), + ('function_body -> compound_command','function_body',1,'p_function_body','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',392), + ('function_body -> compound_command redirect_list','function_body',2,'p_function_body','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',393), + ('fname -> TOKEN','fname',1,'p_fname','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',399), + ('brace_group -> Lbrace compound_list Rbrace','brace_group',3,'p_brace_group','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',403), + ('maybe_done_word -> Done','maybe_done_word',1,'p_maybe_done_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',407), + ('maybe_do_word -> Do','maybe_do_word',1,'p_maybe_do_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',412), + ('do_group -> do_word compound_list done_word','do_group',3,'p_do_group','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',416), + ('simple_command -> cmd_prefix cmd_word cmd_suffix','simple_command',3,'p_simple_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',421), + ('simple_command -> cmd_prefix cmd_word','simple_command',2,'p_simple_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',422), + ('simple_command -> cmd_prefix','simple_command',1,'p_simple_command','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',423), + ('simple_command -> cmd_name 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('cmd_suffix -> maybe_for_word','cmd_suffix',1,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',479), + ('cmd_suffix -> cmd_suffix maybe_for_word','cmd_suffix',2,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',480), + ('cmd_suffix -> maybe_done_word','cmd_suffix',1,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',481), + ('cmd_suffix -> cmd_suffix maybe_done_word','cmd_suffix',2,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',482), + ('cmd_suffix -> maybe_do_word','cmd_suffix',1,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',483), + ('cmd_suffix -> cmd_suffix maybe_do_word','cmd_suffix',2,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',484), + ('cmd_suffix -> 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maybe_then_word','cmd_suffix',1,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',491), + ('cmd_suffix -> cmd_suffix maybe_then_word','cmd_suffix',2,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',492), + ('cmd_suffix -> maybe_bang_word','cmd_suffix',1,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',493), + ('cmd_suffix -> cmd_suffix maybe_bang_word','cmd_suffix',2,'p_cmd_suffix','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',494), + ('redirect_list -> io_redirect','redirect_list',1,'p_redirect_list','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',512), + ('redirect_list -> redirect_list io_redirect','redirect_list',2,'p_redirect_list','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',513), + ('io_redirect -> io_file','io_redirect',1,'p_io_redirect','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',520), + ('io_redirect -> IO_NUMBER io_file','io_redirect',2,'p_io_redirect','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',521), + ('io_redirect -> io_here','io_redirect',1,'p_io_redirect','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',522), + ('io_redirect -> IO_NUMBER io_here','io_redirect',2,'p_io_redirect','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',523), + ('io_file -> LESS filename','io_file',2,'p_io_file','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',530), + ('io_file -> LESSAND filename','io_file',2,'p_io_file','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',531), + ('io_file -> GREATER filename','io_file',2,'p_io_file','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',532), + ('io_file -> GREATAND filename','io_file',2,'p_io_file','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',533), + ('io_file -> DGREAT filename','io_file',2,'p_io_file','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',534), + ('io_file -> LESSGREAT filename','io_file',2,'p_io_file','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',535), + ('io_file -> CLOBBER filename','io_file',2,'p_io_file','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',536), + ('filename -> TOKEN','filename',1,'p_filename','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',542), + ('io_here -> DLESS here_end','io_here',2,'p_io_here','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',547), + ('io_here -> DLESSDASH here_end','io_here',2,'p_io_here','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',548), + ('here_end -> HERENAME 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-> AMP','separator_op',1,'p_separator_op','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',573), + ('separator -> separator_op linebreak','separator',2,'p_separator','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',577), + ('separator -> newline_list','separator',1,'p_separator','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',578), + ('sequential_sep -> COMMA linebreak','sequential_sep',2,'p_sequential_sep','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',587), + ('sequential_sep -> newline_list','sequential_sep',1,'p_sequential_sep','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',588), + ('for_word -> maybe_for_word','for_word',1,'p_for_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',595), + ('if_word -> maybe_if_word','if_word',1,'p_if_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',599), + ('then_word -> maybe_then_word','then_word',1,'p_then_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',603), + ('done_word -> maybe_done_word','done_word',1,'p_done_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',607), + ('do_word -> maybe_do_word','do_word',1,'p_do_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',611), + ('until_word -> maybe_until_word','until_word',1,'p_until_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',615), + ('assignment_word -> maybe_assignment_word','assignment_word',1,'p_assignment_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',619), + ('bang_word -> maybe_bang_word','bang_word',1,'p_bang_word','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',623), + ('token -> TOKEN','token',1,'p_token','/home/lxw2010/M7350v2/apps_proc/oe-core/bitbake/lib/bb/pysh/pyshyacc.py',627), + ('token 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2f4688746..b87ccdf45 100644 --- a/oe-core/build/conf/sanity_info +++ b/oe-core/build/conf/sanity_info @@ -1,3 +1,3 @@ SANITY_VERSION 1 -TMPDIR /home/lxw2010/M7350v1_v2/apps_proc/oe-core/build/tmp-eglibc -SSTATE_DIR /home/lxw2010/M7350v1_v2/apps_proc/oe-core/build/sstate-cache +TMPDIR /home/lxw2010/M7350v2/apps_proc/oe-core/build/tmp-eglibc +SSTATE_DIR /home/lxw2010/M7350v2/apps_proc/oe-core/build/sstate-cache diff --git a/oe-core/build/downloads/tp-domain.bb b/oe-core/build/downloads/tp-domain.bb new file mode 100644 index 000000000..659182ad1 --- /dev/null +++ b/oe-core/build/downloads/tp-domain.bb @@ -0,0 +1 @@ + <body>Your browse does not support frame!</body> \ No newline at end of file diff --git a/oe-core/build/downloads/tp-domain.bb.done b/oe-core/build/downloads/tp-domain.bb.done new file mode 100644 index 000000000..e69de29bb diff --git a/oe-core/meta-msm/recipes/compat-wireless/files/ath6kl_ctrl_wlan b/oe-core/meta-msm/recipes/compat-wireless/files/ath6kl_ctrl_wlan index af19b21df..141006355 100644 --- a/oe-core/meta-msm/recipes/compat-wireless/files/ath6kl_ctrl_wlan +++ b/oe-core/meta-msm/recipes/compat-wireless/files/ath6kl_ctrl_wlan @@ -119,6 +119,16 @@ do_ctrl_ar6004_hsic () { return 1 fi + # Disable HSIC suspend + ## HSIC host side may go wrong when resuming and + ## cause bam failure. + echo on > /sys/devices/msm_hsic_host/power/control + + # Clear caches to reduce chance of mem allocation failure. + ## Kernel panic may occur when loading ath6kl drivers if + ## dma allocation failure happens previously. + echo "3" > /proc/sys/vm/drop_caches + set -e insmod $MODULE_BASE/compat/compat.ko insmod $MODULE_BASE/net/wireless/cfg80211.ko diff --git a/oe-core/meta-msm/recipes/hostap-daemon/hostap-daemon-ath6kl_git.bb b/oe-core/meta-msm/recipes/hostap-daemon/hostap-daemon-ath6kl_git.bb old mode 100644 new mode 100755 index c62b45b18..4e65bccd1 --- a/oe-core/meta-msm/recipes/hostap-daemon/hostap-daemon-ath6kl_git.bb +++ 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