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2024-09-09 08:59:52 +00:00
parent f75098198c
commit 46ba6f09ec
1372 changed files with 1231198 additions and 1184 deletions
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0
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXCfg.h Executable file
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468
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXDM.c Executable file
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/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXDM.c
Abstract:
Defined RTL88XX HAL common Function
Major Change History:
When Who What
---------- --------------- -------------------------------
2013-08-19 Filen Create.
--*/
#include "../HalPrecomp.h"
#if CFG_HAL_MACDM
typedef enum _MACDM_STATE_CHANGE_{
MACDM_STATE_CHANGE_NO = 0,
MACDM_STATE_CHANGE_UP,
MACDM_STATE_CHANGE_DOWN
} MACDM_STATE_CHANGE, *PMACDM_STATE_CHANGE;
static
RSSI_LVL_DM_88XX
TranslateRSSI88XX(
u4Byte rssi
)
{
// TODO:
return RSSI_LVL_LOW;
}
static
BOOLEAN
LoadMACDMTable(
IN HAL_PADAPTER Adapter,
IN u4Byte MACDM_State,
IN u4Byte rssi_lvl
)
{
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
u4Byte offset, value, tbl_idx = 0;
while(1) {
offset = pHalData->MACDM_Table[MACDM_State][rssi_lvl][tbl_idx].offset;
value = pHalData->MACDM_Table[MACDM_State][rssi_lvl][tbl_idx].value;
if (offset == 0xFFFF) {
break;
}
HAL_RTL_W32(offset, value);
tbl_idx++;
// TODO: timeout machinsm, to avoid hanging here
}
return _TRUE;
}
VOID
InitMACDM88XX(
IN HAL_PADAPTER Adapter
)
{
//PHAL_INTERFACE pHalFunc = GET_HAL_INTERFACE(Adapter);
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
pu1Byte pRegFileStart;
u4Byte RegFileLen;
u4Byte stateThrs[MACDM_TP_THRS_MAX_NUM*RSSI_LVL_MAX_NUM+1]; //1: EOF
u4Byte thrs_idx,rssi_idx;
pHalData->MACDM_State = MACDM_TP_STATE_DEFAULT;
// TODO: should load from mib
pHalData->MACDM_Mode_Sel = MACDM_MODE_MAX_TP;
pHalData->MACDM_preRssiLvl = RSSI_LVL_LOW;
//Load Raise/Fall state criteria from the para.c (translation from txt file)
HAL_memset(stateThrs, 0, sizeof(stateThrs));
HAL_memset(pHalData->MACDM_stateThrs, 0, sizeof(pHalData->MACDM_stateThrs));
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_CRITERIA_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_CRITERIA_SIZE, (pu1Byte)&RegFileLen);
LoadFileToOneParaTable(pRegFileStart,
RegFileLen,
(pu1Byte)stateThrs,
(MACDM_TP_THRS_MAX_NUM*RSSI_LVL_MAX_NUM+1));
//one-way arrary translate to two-way arrary
for(thrs_idx=0; thrs_idx<MACDM_TP_THRS_MAX_NUM; thrs_idx++) {
for (rssi_idx=0; rssi_idx<RSSI_LVL_MAX_NUM; rssi_idx++){
pHalData->MACDM_stateThrs[thrs_idx][rssi_idx] = stateThrs[thrs_idx*RSSI_LVL_MAX_NUM + rssi_idx];
}
}
#if 0 //Filen: for verification
RT_TRACE(COMP_INIT, DBG_LOUD, ("pRegFileStart(0x%p), RegFileLen(0x%x)\n", pRegFileStart, RegFileLen) );
RT_TRACE(COMP_INIT, DBG_LOUD, ("0: value(0x%x)\n", pHalData->MACDM_stateThrs[0]));
RT_TRACE(COMP_INIT, DBG_LOUD, ("1: value(0x%x)\n", pHalData->MACDM_stateThrs[1]));
RT_TRACE(COMP_INIT, DBG_LOUD, ("2: value(0x%x)\n", pHalData->MACDM_stateThrs[2]));
RT_TRACE(COMP_INIT, DBG_LOUD, ("3: value(0x%x)\n", pHalData->MACDM_stateThrs[3]));
RT_TRACE(COMP_INIT, DBG_LOUD, ("4: value(0x%x)\n", pHalData->MACDM_stateThrs[4]));
#endif
//Load Table parameter from the para.c (translation from txt file)
HAL_memset(pHalData->MACDM_Table, 0, sizeof(pHalData->MACDM_Table));
//(default, low)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_LOW_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_LOW_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW],
MAX_MACDM_REG_NUM);
//(default, normal)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_NORMAL_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_NORMAL_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_NORMAL],
MAX_MACDM_REG_NUM);
//(default, high)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_HIGH_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_DEF_HIGH_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_HIGH],
MAX_MACDM_REG_NUM);
//(general, low)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_LOW_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_LOW_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_LOW],
MAX_MACDM_REG_NUM);
//(general, normal)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_NORMAL_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_NORMAL_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_NORMAL],
MAX_MACDM_REG_NUM);
//(general, high)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_HIGH_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_GEN_HIGH_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_GENERAL][RSSI_LVL_HIGH],
MAX_MACDM_REG_NUM);
//(txop, low)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_LOW_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_LOW_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_LOW],
MAX_MACDM_REG_NUM);
//(general, normal)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_NORMAL_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_NORMAL_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_NORMAL],
MAX_MACDM_REG_NUM);
//(general, high)
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_HIGH_START, (pu1Byte)&pRegFileStart);
GET_HAL_INTERFACE(Adapter)->GetHwRegHandler(Adapter, HW_VAR_MACDM_TXOP_HIGH_SIZE, (pu1Byte)&RegFileLen);
LoadFileToIORegTable(pRegFileStart,
RegFileLen,
pHalData->MACDM_Table[MACDM_TP_STATE_TXOP][RSSI_LVL_HIGH],
MAX_MACDM_REG_NUM);
#if 0 //Filen: for verification
RT_TRACE(COMP_INIT, DBG_LOUD, ("pRegFileStart(0x%p), RegFileLen(0x%x)\n", pRegFileStart, RegFileLen) );
RT_TRACE(COMP_INIT, DBG_LOUD, ("0: offset(0x%x), value(0x%x)\n",
pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][0].offset,
pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][0].value)
);
RT_TRACE(COMP_INIT, DBG_LOUD, ("1: offset(0x%x), value(0x%x)\n",
pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][1].offset,
pHalData->MACDM_Table[MACDM_TP_STATE_DEFAULT][RSSI_LVL_LOW][1].value)
);
#endif
//Load MACDM table by initial value
LoadMACDMTable(Adapter, pHalData->MACDM_State, pHalData->MACDM_preRssiLvl);
}
static
MACDM_STATE_CHANGE
CheckMACDMThrs(
IN HAL_PADAPTER Adapter,
IN u4Byte MACDM_State,
IN u4Byte TP,
IN u4Byte rssi_lvl
)
{
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
switch(MACDM_State) {
case MACDM_TP_STATE_DEFAULT:
if (TP > pHalData->MACDM_stateThrs[MACDM_TP_THRS_DEF_TO_GEN][rssi_lvl]) {
return MACDM_STATE_CHANGE_UP;
}
break;
case MACDM_TP_STATE_GENERAL:
if (TP < pHalData->MACDM_stateThrs[MACDM_TP_THRS_GEN_TO_DEF][rssi_lvl]) {
return MACDM_STATE_CHANGE_DOWN;
}
else if (TP > pHalData->MACDM_stateThrs[MACDM_TP_THRS_GEN_TO_TXOP][rssi_lvl]) {
return MACDM_STATE_CHANGE_UP;
}
break;
case MACDM_TP_STATE_TXOP:
if (TP < pHalData->MACDM_stateThrs[MACDM_TP_THRS_TXOP_TO_GEN][rssi_lvl]) {
return MACDM_STATE_CHANGE_DOWN;
}
break;
default:
break;
}
return MACDM_STATE_CHANGE_NO;
}
static
BOOLEAN
MACDM_Core88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte TP, // Mbps
IN u4Byte rssi,
IN u4Byte CurTxRate //Data Rate Index
)
{
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
u4Byte rssi_lvl = TranslateRSSI88XX(rssi);
BOOLEAN StateChange = _FALSE;
MACDM_STATE_CHANGE stateChange;
stateChange = CheckMACDMThrs(Adapter, pHalData->MACDM_State, TP, rssi_lvl);
switch(pHalData->MACDM_State) {
case MACDM_TP_STATE_DEFAULT:
if (MACDM_STATE_CHANGE_UP == stateChange) {
pHalData->MACDM_State = MACDM_TP_STATE_GENERAL;
LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl);
RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n",
MACDM_TP_STATE_DEFAULT,
pHalData->MACDM_State));
StateChange = _TRUE;
}
else if (MACDM_STATE_CHANGE_NO == stateChange) {
if (pHalData->MACDM_preRssiLvl != rssi_lvl) {
LoadMACDMTable(Adapter, MACDM_TP_STATE_DEFAULT, rssi_lvl);
}
}
else {
//Error, impossible
}
break;
case MACDM_TP_STATE_GENERAL:
if (MACDM_STATE_CHANGE_UP == stateChange) {
pHalData->MACDM_State = MACDM_TP_STATE_TXOP;
LoadMACDMTable(Adapter, MACDM_TP_STATE_TXOP, rssi_lvl);
RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n",
MACDM_TP_STATE_GENERAL,
pHalData->MACDM_State));
StateChange = _TRUE;
}
else if (MACDM_STATE_CHANGE_DOWN == stateChange) {
pHalData->MACDM_State = MACDM_TP_STATE_DEFAULT;
LoadMACDMTable(Adapter, MACDM_TP_STATE_DEFAULT, rssi_lvl);
RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n",
MACDM_TP_STATE_GENERAL,
pHalData->MACDM_State));
StateChange = _TRUE;
}
else {
//MACDM_STATE_CHANGE_NO
if (pHalData->MACDM_preRssiLvl != rssi_lvl) {
LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl);
}
}
break;
case MACDM_TP_STATE_TXOP:
if (MACDM_STATE_CHANGE_DOWN == stateChange) {
pHalData->MACDM_State = MACDM_TP_STATE_GENERAL;
LoadMACDMTable(Adapter, MACDM_TP_STATE_GENERAL, rssi_lvl);
RT_TRACE_F(COMP_DBG, DBG_LOUD, ("state(%d -> %d)\n",
MACDM_TP_STATE_TXOP,
pHalData->MACDM_State));
StateChange = _TRUE;
}
else if (MACDM_STATE_CHANGE_NO == stateChange) {
if (pHalData->MACDM_preRssiLvl != rssi_lvl) {
LoadMACDMTable(Adapter, MACDM_TP_STATE_TXOP, rssi_lvl);
}
}
else {
//Error, impossible
}
break;
default:
//impossible
break;
};
//Record last one RSSI Level
pHalData->MACDM_preRssiLvl = rssi_lvl;
return StateChange;
}
VOID
Timer1SecDM88XX(
IN HAL_PADAPTER Adapter
)
{
HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter);
u4Byte idx = 0;
HAL_PSTAINFO pEntry = findNextSTA(Adapter, &idx);
//RT_TRACE_F(COMP_DBG, DBG_LOUD, ("mode(%d)\n", pHalData->MACDM_Mode_Sel));
switch(pHalData->MACDM_Mode_Sel) {
case MACDM_MODE_MAX_TP:
{
u4Byte tmpTotal_tp = 0;
u4Byte highest_tp = 0;
HAL_PSTAINFO pstat_highest = NULL;
while(pEntry) {
if(pEntry && pEntry->expire_to) {
tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17; //unit: bytes -> Mb
if (tmpTotal_tp > highest_tp) {
highest_tp = tmpTotal_tp;
pstat_highest = pEntry;
}
}
pEntry = findNextSTA(Adapter, &idx);
};
// TODO: current_tx_rate is not correct, we should get this value from FW
// TODO: transform current_tx_rate format
if (pstat_highest) {
MACDM_Core88XX(Adapter,
highest_tp,
pstat_highest->rssi,
pstat_highest->current_tx_rate
);
}
}
break;
case MACDM_MODE_AVERAGE:
{
u4Byte tmpTotal_tp = 0, Total_tp = 0, average_tp = 0;
u4Byte LinkedStaNum = 0;
u4Byte Total_rssi = 0, average_rssi = 0;
u4Byte Min_CurTxRate = 0xFFFFFFFF;
while(pEntry) {
if(pEntry && pEntry->expire_to) {
LinkedStaNum++;
//accumulate throughput
tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17;//unit: bytes -> Mb
Total_tp += tmpTotal_tp;
//accumulate RSSI
Total_rssi += pEntry->rssi;
//find lowest rate of all linked sta
if (pEntry->current_tx_rate < Min_CurTxRate) {
Min_CurTxRate = pEntry->current_tx_rate;
}
}
pEntry = findNextSTA(Adapter, &idx);
};
if (LinkedStaNum != 0) {
average_tp = Total_tp / LinkedStaNum;
average_rssi = Total_rssi / LinkedStaNum;
// TODO: current_tx_rate is not correct, we should get this value from FW
// TODO: transform current_tx_rate format
MACDM_Core88XX(Adapter,
average_tp,
average_rssi,
Min_CurTxRate
);
}
}
break;
case MACDM_MODE_MIN_TP:
{
u4Byte tmpTotal_tp = 0;
u4Byte lowest_tp = 0xffffffff;
HAL_PSTAINFO pstat_lowest = NULL;
while(pEntry) {
if(pEntry && pEntry->expire_to) {
tmpTotal_tp = (pEntry->tx_avarage /*+ pEntry->rx_avarage*/)>>17; //unit: bytes -> Mb
//find lowest sta
if (tmpTotal_tp < lowest_tp) {
lowest_tp = tmpTotal_tp;
pstat_lowest = pEntry;
}
}
pEntry = findNextSTA(Adapter, &idx);
};
// TODO: current_tx_rate is not correct, we should get this value from FW
// TODO: transform current_tx_rate format
if (pstat_lowest) {
MACDM_Core88XX(Adapter,
lowest_tp,
pstat_lowest->rssi,
pstat_lowest->current_tx_rate
);
}
}
break;
case MACDM_MODE_STOP:
default:
break;
}
}
#endif //#if CFG_HAL_MACDM

72
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXDM.h Executable file
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#ifndef __HAL88XX_DM_H__
#define __HAL88XX_DM_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXDM.h
Abstract:
Defined HAL 88XX Dynamic Mechanism Related Define & Marco
Major Change History:
When Who What
---------- --------------- -------------------------------
2013-08-19 Filen Create.
--*/
typedef enum _RSSI_LVL_DM_88XX_ {
RSSI_LVL_LOW = 0,
RSSI_LVL_NORMAL = 1,
RSSI_LVL_HIGH = 2,
RSSI_LVL_MAX_NUM
}RSSI_LVL_DM_88XX, *PRSSI_LVL_DM_88XX;
typedef enum _MACDM_MODE_88XX_ {
MACDM_MODE_STOP = 0,
MACDM_MODE_MAX_TP = 1,
MACDM_MODE_AVERAGE = 2,
MACDM_MODE_MIN_TP = 3,
MACDM_MODE_MAX_NUM
}MACDM_MODE_88XX, *PMACDM_MODE_88XX;
typedef enum _MACDM_TP_STATE_88XX_ {
MACDM_TP_STATE_DEFAULT = 0,
MACDM_TP_STATE_GENERAL = 1,
MACDM_TP_STATE_TXOP = 2,
MACDM_TP_STATE_MAX_NUM
}MACDM_TP_STATE_88XX, *PMACDM_TP_STATE_88XX;
typedef enum _MACDM_TP_THRS_88XX_ {
MACDM_TP_THRS_DEF_TO_GEN = 0,
MACDM_TP_THRS_GEN_TO_DEF = 1,
MACDM_TP_THRS_GEN_TO_TXOP = 2,
MACDM_TP_THRS_TXOP_TO_GEN = 3,
MACDM_TP_THRS_MAX_NUM
}MACDM_TP_THRS_88XX, *PMACDM_TP_THRS_88XX;
VOID
InitMACDM88XX(
IN HAL_PADAPTER Adapter
);
VOID
Timer1SecDM88XX(
IN HAL_PADAPTER Adapter
);
#endif //__HAL88XX_DM_H__

65
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXDebug.h Executable file
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#ifndef __HAL88XXDEBUG_H__
#define __HAL88XXDEBUG_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXDebug.h
Abstract:
Defined HAL 88XX debug reigster
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-09-07 Eric Create.
--*/
//
//**Note**:
// If one of these register is used, we should register MACRO at RTL88XXX_debug.h.
//
// Range List:
// 1.) 0x5FE ~ 0x5FF : there are no control circuit. But these register can be R/W.
//1 Debug Register Location (from different IC)
// 4 Bytes
#define REG_DRV_DBG REG_PAGE5_DUMMY
#define REG_DBG_DWORD_0 REG_DRV_DBG
//3 Register Debug register for our purpose
// 1.) Driver Component Error
#define REGDUMP_DRV_ERR0 REG_DBG_DWORD_0
//REGDUMP_DRV_ERR0
typedef enum _DRV_ERR0_STATUS_
{
DRV_ER_INIT_PON = BIT0,
DRV_ER_INIT_MAC = BIT1,
DRV_ER_INIT_HCIDMA = BIT2,
DRV_ER_INIT_MACPHYREGFILE = BIT3,
DRV_ER_INIT_BBEGFILE = BIT4,
DRV_ER_INIT_PHYRF = BIT5,
DRV_ER_INIT_DLFW = BIT6,
DRV_ER_INIT_RSVD_0 = BIT7,
DRV_ER_INIT_RSVD_1 = BIT8,
DRV_ER_INIT_RSVD_2 = BIT9,
DRV_ER_CLOSE_STOP_HW = BIT10,
DRV_ER_RSVD_0 = BIT11,
DRV_ER_RSVD_1 = BIT12,
DRV_ER_RSVD_2 = BIT13,
DRV_ER_RSVD_3 = BIT14,
DRV_ER_RSVD_4 = BIT15,
DRV_ER_RSVD_5 = BIT16,
}DRV_ERR0_STATUS, *PDRV_ERR0_STATUS;
#endif // __HAL88XXDEBUG_H__

265
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXDef.h Executable file
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@@ -0,0 +1,265 @@
#ifndef __HAL88XX_DEF_H__
#define __HAL88XX_DEF_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXDef.h
Abstract:
Defined HAL 88XX common data structure & Define
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-03-23 Filen Create.
--*/
#ifdef WLAN_HAL_INTERNAL_USED
MIMO_TR_STATUS
GetChipIDMIMO88XX(
IN HAL_PADAPTER Adapter
);
VOID
CAMEmptyEntry88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte index
);
u4Byte
CAMFindUsable88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte for_begin
);
VOID
CAMReadMACConfig88XX
(
IN HAL_PADAPTER Adapter,
IN u1Byte index,
OUT pu1Byte pMacad,
OUT PCAM_ENTRY_CFG pCfg
);
VOID
CAMProgramEntry88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte index,
IN pu1Byte macad,
IN pu1Byte key128,
IN u2Byte config
);
VOID
SetHwReg88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte variable,
IN pu1Byte val
);
VOID
GetHwReg88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte variable,
OUT pu1Byte val
);
RT_STATUS
GetMACIDQueueInTXPKTBUF88XX(
IN HAL_PADAPTER Adapter,
OUT pu1Byte MACIDList
);
RT_STATUS
SetMACIDSleep88XX(
IN HAL_PADAPTER Adapter,
IN BOOLEAN bSleep,
IN u4Byte aid
);
#if (IS_RTL8881A_SERIES || IS_RTL8192E_SERIES)
RT_STATUS
InitLLT_Table88XX(
IN HAL_PADAPTER Adapter
);
#endif //#if (IS_RTL8881A_SERIES || IS_RTL8192E_SERIES)
#if IS_RTL8814A_SERIES
RT_STATUS
InitLLT_Table88XX_V1(
IN HAL_PADAPTER Adapter
);
#endif //#if IS_RTL8814A_SERIES
RT_STATUS
InitMAC88XX(
IN HAL_PADAPTER Adapter
);
VOID
InitIMR88XX(
IN HAL_PADAPTER Adapter,
IN RT_OP_MODE OPMode
);
VOID
InitVAPIMR88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte VapSeq
);
RT_STATUS
InitHCIDMAMem88XX(
IN HAL_PADAPTER Adapter
);
RT_STATUS
InitHCIDMAReg88XX(
IN HAL_PADAPTER Adapter
);
VOID
StopHCIDMASW88XX(
IN HAL_PADAPTER Adapter
);
VOID
StopHCIDMAHW88XX(
IN HAL_PADAPTER Adapter
);
#if CFG_HAL_SUPPORT_MBSSID
VOID
InitMBSSID88XX(
IN HAL_PADAPTER Adapter
);
VOID
InitMBIDCAM88XX(
IN HAL_PADAPTER Adapter
);
VOID
StopMBSSID88XX(
IN HAL_PADAPTER Adapter
);
#endif //CFG_HAL_SUPPORT_MBSSID
RT_STATUS
SetMBIDCAM88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte MBID_Addr,
IN u1Byte IsRoot
);
RT_STATUS
StopMBIDCAM88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte MBID_Addr
);
RT_STATUS
ResetHWForSurprise88XX(
IN HAL_PADAPTER Adapter
);
#ifdef MULTI_MAC_CLONE
VOID
McloneSetMBSSID88XX(
IN HAL_PADAPTER Adapter,
IN pu1Byte macAddr,
IN int entIdx
);
VOID
McloneStopMBSSID88XX(
IN HAL_PADAPTER Adapter,
IN int entIdx
);
#endif
RT_STATUS
StopHW88XX(
IN HAL_PADAPTER Adapter
);
RT_STATUS
StopSW88XX(
IN HAL_PADAPTER Adapter
);
VOID
DisableVXDAP88XX(
IN HAL_PADAPTER Adapter
);
VOID
Timer1Sec88XX(
IN HAL_PADAPTER Adapter
);
RT_STATUS
GetTxRPTBuf88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte macID,
IN u1Byte variable,
OUT pu1Byte val
);
RT_STATUS
SetTxRPTBuf88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte macID,
IN u1Byte variable,
IN pu1Byte val
);
u4Byte
CheckHang88XX(
IN HAL_PADAPTER Adapter
);
VOID
SetCRC5ToRPTBuffer88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte val,
IN u4Byte macID,
IN u1Byte bValid
);
VOID
SetCRC5ValidBit88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte group,
IN u1Byte bValid
);
VOID
SetCRC5EndBit88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte group,
IN u1Byte bEnd
);
VOID
InitMACIDSearch88XX(
IN HAL_PADAPTER Adapter
);
#endif //WLAN_HAL_INTERNAL_USED
#endif //__HAL88XX_DEF_H__

54
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXDesc.h Executable file
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#ifndef __HAL88XXDESC_H__
#define __HAL88XXDESC_H__
#define SET_MEM_OP(Dw, Value32, Mask, Shift) \
(((Dw) & ~((Mask)<<(Shift)))|(((Value32)&(Mask))<<(Shift)))
#if CFG_HAL_CHECK_SWAP
//No Clear First
#define SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \
Dw |= (_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \
(HAL_cpu_to_le32(((Value32)&(Mask))<<(Shift))): \
(((Value32)&(Mask))<<(Shift));
//3 Note: Performance bad, don't use as possible
//Clear first then set
#define SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \
{ \
u4Byte lDw = Dw; \
Dw = (_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \
(HAL_cpu_to_le32(SET_MEM_OP(HAL_le32_to_cpu(lDw), Value32, Mask, Shift))) : \
(SET_MEM_OP(lDw, Value32, Mask, Shift)); \
}
#define GET_DESC_FIELD(Dw, Mask, Shift) \
((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? \
((HAL_le32_to_cpu(Dw)>>(Shift)) & (Mask)) : \
(((Dw)>>(Shift)) & (Mask)))
#define GET_DESC(val) ((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? HAL_le32_to_cpu(val) : val)
#define SET_DESC(val) ((_GET_HAL_DATA(Adapter)->AccessSwapCtrl & HAL_ACCESS_SWAP_MEM) ? HAL_cpu_to_le32(val) : val)
#else
#define SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \
Dw |= (HAL_cpu_to_le32(((Value32)&(Mask))<<(Shift)));
#define SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \
Dw = (HAL_cpu_to_le32(SET_MEM_OP(HAL_le32_to_cpu(Dw), Value32, Mask, Shift)));
#define GET_DESC_FIELD(Dw, Mask, Shift) \
((HAL_le32_to_cpu(Dw)>>(Shift)) & (Mask))
#define GET_DESC(val) (val)
#define SET_DESC(val) (val)
#endif
#endif // __HAL88XXDESC_H__

2225
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXFirmware.c Executable file
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371
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXFirmware.h Executable file
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#ifndef __HAL88XX_FIRMWARE_H__
#define __HAL88XX_FIRMWARE_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXFirmware.h
Abstract:
Defined HAL 88XX Firmware data structure & Define
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-04-11 Filen Create.
--*/
/**********************/
// Mapping C2H callback function
typedef enum _RTL88XX_C2H_EVT
{
C2H_88XX_DBG = 0,
C2H_88XX_LB = 1,
C2H_88XX_TXBF = 2,
C2H_88XX_TX_REPORT = 3,
C2H_88XX_TX_RATE =4,
C2H_88XX_BT_INFO = 9,
C2H_88XX_BT_MP = 11,
C2H_88XX_RA_PARA_RPT=14,
C2H_88XX_RA_DYNAMIC_TX_PATH_RPT = 15,
C2H_88XX_EXTEND_IND = 0xFF,
MAX_88XX_C2HEVENT
}RTL88XX_C2H_EVT;
typedef enum _RTL88XX_EXTEND_C2H_EVT
{
EXTEND_C2H_88XX_DBG_PRINT = 0
}RTL88XX_EXTEND_C2H_EVT;
typedef struct _TXRPT_
{
u1Byte RPT_MACID;
u2Byte RPT_TXOK;
u2Byte RPT_TXFAIL;
u1Byte RPT_InitialRate;
}__attribute__ ((packed)) TXRPT,*PTXRPT ;
typedef struct _APREQTXRPT_
{
TXRPT txrpt[2];
}__attribute__ ((packed)) APREQTXRPT,*PAPREQTXRPT ;
#define GEN_FW_CMD_HANDLER(size, cmd) {size, cmd##Handler},
//void h2csetdsr(void);
struct cmdobj {
u4Byte parmsize;
VOID (*c2hfuns)(IN HAL_PADAPTER Adapter,u1Byte *pbuf);
};
//-----------------------------------------------------
//
// 0x1200h ~ 0x12FFh DDMA CTRL
//
//-----------------------------------------------------
#define DDMA_LEN_MASK 0x0001FFFF
#define DDMA_CH_CHKSUM_CNT BIT(24)
#define DDMA_RST_CHKSUM_STS BIT(25)
#define DDMA_MODE_BLOCK_CPU BIT(26)
#define DDMA_CHKSUM_FAIL BIT(27)
#define DDMA_DA_W_DISABLE BIT(28)
#define DDMA_CHKSUM_EN BIT(29)
#define DDMA_CH_OWN BIT(31)
typedef struct _RTL88XX_FW_HDR_
{
u2Byte signature;
u1Byte category;
u1Byte function;
u2Byte version;
u1Byte subversion;
u1Byte rsvd1;
u1Byte month; //human easy reading format
u1Byte day; //human easy reading format
u1Byte hour; //human easy reading format
u1Byte minute; //human easy reading format
u2Byte ram_code_size;
u1Byte Foundry; //0: TSMC, 1:UMC, 2:SMIC
u1Byte rsvd3;
u4Byte svnidx;
u4Byte rsvd5;
u4Byte rsvd6;
u4Byte rsvd7;
}RTL88XX_FW_HDR, *PRTL88XX_FW_HDR;
typedef struct _RTL88XX_MIPS_FW_HDR_
{
//offset0
u2Byte signature;
u1Byte category;
u1Byte function;
u2Byte version;
u1Byte Subversion;
u1Byte sub_index;
//offset8
u4Byte SVN_index;
u4Byte rsvd1;
//offset16
u1Byte Month;
u1Byte Date;
u1Byte Hour;
u1Byte Min;
u2Byte Year;
u1Byte Foundry;
u1Byte rsvd2;
//offset24
u1Byte MEM_USAGE__DL_from:1;
u1Byte MEM_USAGE__BOOT_from:1;
u1Byte MEM_USAGE__BOOT_LOADER:1;
u1Byte MEM_USAGE__IRAM:1;
u1Byte MEM_USAGE__ERAM:1;
u1Byte MEM_USAGE__rsvd4:3;
u1Byte rsvd3;
u2Byte BOOT_LOADER_SZ;
u4Byte rsvd5;
//offset32
u4Byte TOTAL_DMEM_SZ;
u2Byte FW_CFG_SZ;
u2Byte FW_ATTR_SZ;
//offset40
u4Byte IROM_SZ;
u4Byte EROM_SZ;
//offset 48
u4Byte IRAM_SZ;
u4Byte ERAM_SZ;
//offset 56
u4Byte rsvd6;
u4Byte rsvd7;
}RTL88XX_MIPS_FW_HDR, *PRTL88XX_MIPS_FW_HDR;
// TODO: Filen, check below
typedef enum _RTL88XX_H2C_CMD
{
// H2C_88XX_RSVDPAGE = 0,
H2C_88XX_MSRRPT = 0x1,
// H2C_88XX_KEEP_ALIVE_CTRL = 0x3,
// H2C_88XX_WO_WLAN = 0x5, // Wake on Wlan.
// H2C_88XX_REMOTE_WAKEUP = 0x7,
H2C_88XX_AP_OFFLOAD = 0x8,
H2C_88XX_BCN_RSVDPAGE = 0x9,
H2C_88XX_PROBE_RSVDPAGE = 0xa,
H2C_88XX_WAKEUP_PIN = 0x13,
// H2C_88XX_SETPWRMODE = 0x20,
// H2C_88XX_P2P_PS_MODE = 0x24,
#if defined(SOFTAP_PS_DURATION) || defined(CONFIG_POWER_SAVE)
H2C_88XX_SAP_PS = 0x26,
#endif
H2C_88XX_RA_MASK = 0x40,
H2C_88XX_RSSI_REPORT = 0x42,
H2C_88XX_AP_REQ_TXREP = 0x43,
H2C_88XX_RA_MASK_3SS = 0x46,
H2C_88XX_RA_PARA_ADJUST = 0x47,
H2C_88XX_DYNAMIC_TX_PATH = 0x48,
H2C_88XX_FW_TRACE_EN = 0x49,
H2C_88XX_NHM = 0xC1,
H2C_88XX_BCN_IGNORE_EDCCA = 0xC2,
H2C_88XX_REPEAT_WAKE_PULSE = 0xC4,
MAX_88XX_H2CCMD
}RTL88XX_H2C_CMD;
typedef enum _RTL88XX_C2H_CMD
{
// C2H_88XX_DBG = 0,
// C2H_88XX_C2H_LB = 0x1,
// C2H_88XX_SND_TXBF = 0x2,
// C2H_88XX_CCXRPT = 0x3,
C2H_88XX_APREQTXRPT = 0x4,
// C2H_88XX_INITIALRATE = 0x5,
// C2H_88XX_PSD_RPT = 0x6,
// C2H_88XX_SCAN_COMPLETE = 0x7,
// C2H_88XX_PSD_CONTROL = 0x8,
// C2H_88XX_BT_INFO = 0x9,
// C2H_88XX_BT_LOOPBACK = 0xa,
MAX_88XX_C2HCMD
}RTL88XX_C2H_CMD;
VOID
ReadMIPSFwHdr88XX(
IN HAL_PADAPTER Adapter
);
RT_STATUS
InitMIPSFirmware88XX(
IN HAL_PADAPTER Adapter
);
RT_STATUS
InitFirmware88XX(
IN HAL_PADAPTER Adapter
);
#if 0
typedef struct _H2C_CONTENT_
{
u4Byte content;
u2Byte ext_content;
}H2C_CONTENT, *PH2C_CONTENT;
BOOLEAN
IsH2CBufOccupy88XX(
IN HAL_PADAPTER Adapter
);
BOOLEAN
SigninH2C88XX(
IN HAL_PADAPTER Adapter,
IN PH2C_CONTENT pH2CContent
);
#else
BOOLEAN
CheckFwReadLastH2C88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte BoxNum
);
RT_STATUS
FillH2CCmd88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
);
#endif
VOID
UpdateHalRAMask88XX(
IN HAL_PADAPTER Adapter,
HAL_PSTAINFO pEntry,
u1Byte rssi_level
);
void
UpdateHalMSRRPT88XX(
IN HAL_PADAPTER Adapter,
HAL_PSTAINFO pEntry,
u1Byte opmode
);
//#ifdef SDIO_AP_OFFLOAD
void
SetAPOffload88XX(
IN HAL_PADAPTER Adapter,
u1Byte bEn,
#ifdef CONFIG_POWER_SAVE
u1Byte bOn,
#endif
u1Byte numOfAP,
u1Byte bHidden,
u1Byte bDenyAny,
pu1Byte loc_bcn,
pu1Byte loc_probe
);
#if defined(SOFTAP_PS_DURATION) || defined(CONFIG_POWER_SAVE)
VOID
SetSAPPS88XX
(
IN HAL_PADAPTER Adapter,
u1Byte en,
#ifdef CONFIG_POWER_SAVE
u1Byte en_32K,
u1Byte lps,
#endif
u1Byte duration
);
#endif // SOFTAP_PS_DURATION || CONFIG_POWER_SAVE
//#endif // SDIO_AP_OFFLOAD
VOID
SetRsvdPage88XX
(
IN IN HAL_PADAPTER Adapter,
IN pu1Byte prsp,
IN pu1Byte beaconbuf,
IN u4Byte pktLen,
IN u4Byte bigPktLen
);
u4Byte
GetRsvdPageLoc88XX
(
IN IN HAL_PADAPTER Adapter,
IN u4Byte frlen,
OUT pu1Byte loc_page
);
BOOLEAN
DownloadRsvdPage88XX
(
IN HAL_PADAPTER Adapter,
IN pu4Byte beaconbuf,
IN u4Byte beaconPktLen,
IN u1Byte bReDownload
);
void C2HHandler88XX(
IN HAL_PADAPTER Adapter
);
void C2HPacket88XX(
IN HAL_PADAPTER Adapter,
IN pu1Byte pBuf,
IN u1Byte length
);
VOID
C2HEventHandler88XX
(
IN HAL_PADAPTER Adapter,
IN u1Byte c2hCmdId,
IN u1Byte c2hCmdLen,
IN pu1Byte tmpBuf
);
VOID
C2HExtEventHandler88XX
(
IN HAL_PADAPTER Adapter,
IN u1Byte c2hCmdId,
IN u1Byte c2hCmdLen,
IN pu1Byte tmpBuf
);
#ifdef BEAMFORMING_SUPPORT
VOID
C2HTxBeamformingHandler88XX(
struct rtl8192cd_priv *priv,
pu1Byte CmdBuf,
u1Byte CmdLen
);
#endif
#endif //__HAL88XX_FIRMWARE_H__

5072
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXGen.c Executable file
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0
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXHWImg.c Executable file
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0
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXHWImg.h Executable file
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652
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXIsr.c Executable file
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/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXIsr.c
Abstract:
Defined RTL88XX HAL common Function
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-04-30 Filen Create.
--*/
#include "../HalPrecomp.h"
VOID
EnableIMR88XX(
IN HAL_PADAPTER Adapter
)
{
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
RT_TRACE_F(COMP_INIT, DBG_LOUD, ("\n"));
HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]);
HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]);
#if IS_EXIST_RTL8814AE
if ( IS_HARDWARE_TYPE_8814AE(Adapter) ) {
HAL_RTL_W32(REG_HIMR2, pHalData->IntMask[2]);
HAL_RTL_W32(REG_HIMR3, pHalData->IntMask[3]);
}
#endif //#if IS_EXIST_RTL8814AE
}
//
// Description:
// Recognize the interrupt content by reading the interrupt register or content and masking interrupt mask (IMR)
// if it is our NIC's interrupt. After recognizing, we may clear the all interrupts (ISR).
// Arguments:
// [in] Adapter -
// The adapter context.
// [in] pContent -
// Under PCI interface, this field is ignord.
// Under USB interface, the content is the interrupt content pointer.
// Under SDIO interface, this is the interrupt type which is Local interrupt or system interrupt.
// [in] ContentLen -
// The length in byte of pContent.
// Return:
// If any interrupt matches the mask (IMR), return TRUE, and return FALSE otherwise.
//
HAL_IMEM
BOOLEAN
InterruptRecognized88XX(
IN HAL_PADAPTER Adapter,
IN PVOID pContent,
IN u4Byte ContentLen
)
{
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
u1Byte result;
pHalData->IntArray_bak[0] = pHalData->IntArray[0];
pHalData->IntArray_bak[1] = pHalData->IntArray[1];
pHalData->IntArray[0] = HAL_RTL_R32(REG_HISR0);
pHalData->IntArray[0] &= pHalData->IntMask[0];
HAL_RTL_W32(REG_HISR0, pHalData->IntArray[0]);
pHalData->IntArray[1] = HAL_RTL_R32(REG_HISR1);
pHalData->IntArray[1] &= pHalData->IntMask[1];
HAL_RTL_W32(REG_HISR1, pHalData->IntArray[1]);
result = (pHalData->IntArray[0]!=0 || pHalData->IntArray[1]!=0);
#if IS_EXIST_RTL8814AE
if ( IS_HARDWARE_TYPE_8814AE(Adapter) ) {
pHalData->IntArray[2] = HAL_RTL_R32(REG_HISR2);
pHalData->IntArray[2] &= pHalData->IntMask[2];
HAL_RTL_W32(REG_HISR2, pHalData->IntArray[2]);
pHalData->IntArray[3] = HAL_RTL_R32(REG_HISR3);
pHalData->IntArray[3] &= pHalData->IntMask[3];
HAL_RTL_W32(REG_HISR3, pHalData->IntArray[3]);
result = (result || (pHalData->IntArray[2]!=0 || pHalData->IntArray[3]!=0 ));
}
#endif // #if IS_EXIST_RTL8814AE
return result;
}
//
// Description:
// Check the interrupt content (read from previous process) in HAL.
// Arguments:
// [in] pAdapter -
// The adapter context pointer.
// [in] intType -
// The HAL interrupt type for querying.
// Return:
// If the corresponding interrupt content (bit) is toggled, return TRUE.
// If the input interrupt type isn't recognized or this corresponding
// hal interupt isn't toggled, return FALSE.
// Note:
// We don't perform I/O here to read interrupt such as ISR here, so the
// interrupt content shall be read before this handler.
//
HAL_IMEM
BOOLEAN
GetInterrupt88XX(
IN HAL_PADAPTER Adapter,
IN HAL_INT_TYPE intType
)
{
HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter);
BOOLEAN bResult = FALSE;
switch(intType)
{
default:
// Unknown interrupt type, no need to alarm because this IC may not
// support this interrupt.
RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType));
break;
case HAL_INT_TYPE_ANY:
bResult = (pHalData->IntArray[0] || pHalData->IntArray[1]) ? TRUE : FALSE;
break;
//4 // ========== DWORD 0 ==========
case HAL_INT_TYPE_BCNDERR0:
bResult = (pHalData->IntArray[0] & BIT_BCNDERR0) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_TBDOK:
bResult = (pHalData->IntArray[0] & BIT_TXBCN0OK) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_TBDER:
bResult = (pHalData->IntArray[0] & BIT_TXBCN0ERR) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt:
bResult = (pHalData->IntArray[0] & BIT_BCNDMAINT0) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_PSTIMEOUT:
bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_PSTIMEOUT1:
bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT1) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_PSTIMEOUT2:
bResult = (pHalData->IntArray[0] & BIT_PSTIMEOUT2) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_C2HCMD:
bResult = (pHalData->IntArray[0] & BIT_C2HCMD) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_VIDOK:
bResult = (pHalData->IntArray[0] & BIT_VIDOK) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_VODOK:
bResult = (pHalData->IntArray[0] & BIT_VODOK) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BEDOK:
bResult = (pHalData->IntArray[0] & BIT_BEDOK) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BKDOK:
bResult = (pHalData->IntArray[0] & BIT_BKDOK) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_MGNTDOK:
bResult = (pHalData->IntArray[0] & BIT_MGTDOK) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_HIGHDOK:
bResult = (pHalData->IntArray[0] & BIT_HIGHDOK) ? TRUE : FALSE;
break;
#if 0 //Filen: removed
case HAL_INT_TYPE_BDOK:
bResult = (pHalData->IntArray[0] & IMR_BCNDOK0_88E) ? TRUE : FALSE;
break;
#endif
case HAL_INT_TYPE_CPWM:
bResult = (pHalData->IntArray[0] & BIT_CPWM) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_TSF_BIT32_TOGGLE:
bResult = (pHalData->IntArray[0] & BIT_TSF_BIT32_TOGGLE) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_RX_OK:
bResult = (pHalData->IntArray[0] & BIT_RXOK) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_RDU:
bResult = (pHalData->IntArray[0] & BIT_RDU) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_CTWEND:
#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES)
if (IS_HARDWARE_TYPE_8192E(Adapter) || IS_HARDWARE_TYPE_8881A(Adapter)) {
bResult = (pHalData->IntArray[0] & BIT_CTWEND) ? TRUE : FALSE;
}
#endif //(IS_RTL8192E_SERIES || IS_RTL8881A_SERIES)
#if IS_RTL8814A_SERIES
if (IS_HARDWARE_TYPE_8814A(Adapter))
{
//this interrupt is removed at 8814A
bResult = FALSE;
}
#endif // IS_RTL8192E_SERIES
break;
//4 // ========== DWORD 1 ==========
case HAL_INT_TYPE_RXFOVW:
bResult = (pHalData->IntArray[1] & BIT_FOVW) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_TXFOVW:
bResult = (pHalData->IntArray[1] & BIT_TXFOVW) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_RXERR:
bResult = (pHalData->IntArray[1] & BIT_RXERR_INT) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_TXERR:
bResult = (pHalData->IntArray[1] & BIT_TXERR_INT) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt_MBSSID:
bResult = ((pHalData->IntArray[1] & (BIT_BCNDMAINT1|BIT_BCNDMAINT2|BIT_BCNDMAINT3|BIT_BCNDMAINT4|
BIT_BCNDMAINT5|BIT_BCNDMAINT6|BIT_BCNDMAINT7)) ||
(pHalData->IntArray[0] & BIT_BCNDMAINT0)
) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt1:
bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT1) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt2:
bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT2) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt3:
bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT3) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt4:
bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT4) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt5:
bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT5) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt6:
bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT6) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_BcnInt7:
bResult = (pHalData->IntArray[1] & BIT_BCNDMAINT7) ? TRUE : FALSE;
break;
#if IS_EXIST_RTL8814AE
if ( IS_HARDWARE_TYPE_8814AE(Adapter) ) {
case HAL_INT_TYPE_PwrInt0:
bResult = (pHalData->IntArray[3] & BIT_PWR_INT_31to0) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_PwrInt1:
bResult = (pHalData->IntArray[3] & BIT_PWR_INT_63to32) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_PwrInt2:
bResult = (pHalData->IntArray[3] & BIT_PWR_INT_95to64) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_PwrInt3:
bResult = (pHalData->IntArray[3] & BIT_PWR_INT_126to96) ? TRUE : FALSE;
break;
case HAL_INT_TYPE_PwrInt4:
bResult = (pHalData->IntArray[3] & BIT_PWR_INT_127) ? TRUE : FALSE;
break;
}
#endif // #if IS_EXIST_RTL8814AE
}
return bResult;
}
// TODO: Pedro, we can set several IMR combination for different scenario. Ex: 1) AP, 2) Client, 3) ....
// TODO: this can avoid to check non-necessary interrupt in __wlan_interrupt(..)...
VOID
AddInterruptMask88XX(
IN HAL_PADAPTER Adapter,
IN HAL_INT_TYPE intType
)
{
HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter);
switch(intType)
{
default:
// Unknown interrupt type, no need to alarm because this IC may not
// support this interrupt.
RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType));
break;
case HAL_INT_TYPE_ANY:
pHalData->IntMask[0] = 0xFFFFFFFF;
pHalData->IntMask[1] = 0xFFFFFFFF;
break;
//4 // ========== DWORD 0 ==========
case HAL_INT_TYPE_BCNDERR0:
pHalData->IntMask[0] |= BIT_BCNDERR0;
break;
case HAL_INT_TYPE_TBDOK:
pHalData->IntMask[0] |= BIT_TXBCN0OK;
break;
case HAL_INT_TYPE_TBDER:
pHalData->IntMask[0] |= BIT_TXBCN0ERR;
break;
case HAL_INT_TYPE_BcnInt:
pHalData->IntMask[0] |= BIT_BCNDMAINT0;
break;
case HAL_INT_TYPE_PSTIMEOUT:
pHalData->IntMask[0] |= BIT_PSTIMEOUT;
break;
case HAL_INT_TYPE_PSTIMEOUT1:
pHalData->IntMask[0] |= BIT_PSTIMEOUT1;
break;
case HAL_INT_TYPE_PSTIMEOUT2:
pHalData->IntMask[0] |= BIT_PSTIMEOUT2;
break;
case HAL_INT_TYPE_C2HCMD:
pHalData->IntMask[0] |= BIT_C2HCMD;
break;
case HAL_INT_TYPE_VIDOK:
pHalData->IntMask[0] |= BIT_VIDOK;
break;
case HAL_INT_TYPE_VODOK:
pHalData->IntMask[0] |= BIT_VODOK;
break;
case HAL_INT_TYPE_BEDOK:
pHalData->IntMask[0] |= BIT_BEDOK;
break;
case HAL_INT_TYPE_BKDOK:
pHalData->IntMask[0] |= BIT_BKDOK;
break;
case HAL_INT_TYPE_MGNTDOK:
pHalData->IntMask[0] |= BIT_MGTDOK;
break;
case HAL_INT_TYPE_HIGHDOK:
pHalData->IntMask[0] |= BIT_HIGHDOK;
break;
#if 0 //Filen: removed
case HAL_INT_TYPE_BDOK:
pHalData->IntMask[0] |= IMR_BCNDOK0_88E;
break;
#endif
case HAL_INT_TYPE_CPWM:
pHalData->IntMask[0] |= BIT_CPWM;
break;
case HAL_INT_TYPE_TSF_BIT32_TOGGLE:
pHalData->IntMask[0] |= BIT_TSF_BIT32_TOGGLE;
break;
case HAL_INT_TYPE_RX_OK:
pHalData->IntMask[0] |= BIT_RXOK;
break;
case HAL_INT_TYPE_RDU:
pHalData->IntMask[0] |= BIT_RDU;
break;
//4 // ========== DWORD 1 ==========
case HAL_INT_TYPE_RXFOVW:
pHalData->IntMask[1] |= BIT_FOVW;
break;
case HAL_INT_TYPE_TXFOVW:
pHalData->IntMask[1] |= BIT_TXFOVW;
break;
case HAL_INT_TYPE_RXERR:
pHalData->IntMask[1] |= BIT_RXERR_INT;
break;
case HAL_INT_TYPE_TXERR:
pHalData->IntMask[1] |= BIT_TXERR_INT;
break;
#if IS_EXIST_RTL8814AE
if ( IS_HARDWARE_TYPE_8814AE(Adapter) ) {
case HAL_INT_TYPE_PwrInt0:
pHalData->IntMask[3] |= BIT_PWR_INT_31to0;
break;
case HAL_INT_TYPE_PwrInt1:
pHalData->IntMask[3] |= BIT_PWR_INT_63to32;
break;
case HAL_INT_TYPE_PwrInt2:
pHalData->IntMask[3] |= BIT_PWR_INT_95to64;
break;
case HAL_INT_TYPE_PwrInt3:
pHalData->IntMask[3] |= BIT_PWR_INT_126to96;
break;
case HAL_INT_TYPE_PwrInt4:
pHalData->IntMask[3] |= BIT_PWR_INT_127;
break;
}
#endif // #if IS_EXIST_RTL8814AE
}
}
VOID
RemoveInterruptMask88XX(
IN HAL_PADAPTER Adapter,
IN HAL_INT_TYPE intType
)
{
HAL_DATA_TYPE *pHalData = _GET_HAL_DATA(Adapter);
switch(intType)
{
default:
// Unknown interrupt type, no need to alarm because this IC may not
// support this interrupt.
RT_TRACE_F(COMP_SYSTEM, DBG_WARNING, ("Unkown intType: %d!\n", intType));
break;
case HAL_INT_TYPE_ANY:
pHalData->IntMask[0] &= ~0xFFFFFFFF;
pHalData->IntMask[1] &= ~0xFFFFFFFF;
break;
//4 // ========== DWORD 0 ==========
case HAL_INT_TYPE_BCNDERR0:
pHalData->IntMask[0] &= ~BIT_BCNDERR0;
break;
case HAL_INT_TYPE_TBDOK:
pHalData->IntMask[0] &= ~BIT_TXBCN0OK;
break;
case HAL_INT_TYPE_TBDER:
pHalData->IntMask[0] &= ~BIT_TXBCN0ERR;
break;
case HAL_INT_TYPE_BcnInt:
pHalData->IntMask[0] &= ~BIT_BCNDMAINT0;
break;
case HAL_INT_TYPE_PSTIMEOUT:
pHalData->IntMask[0] &= ~BIT_PSTIMEOUT;
break;
case HAL_INT_TYPE_PSTIMEOUT1:
pHalData->IntMask[0] &= ~BIT_PSTIMEOUT1;
break;
case HAL_INT_TYPE_PSTIMEOUT2:
pHalData->IntMask[0] &= ~BIT_PSTIMEOUT2;
break;
case HAL_INT_TYPE_C2HCMD:
pHalData->IntMask[0] &= ~BIT_C2HCMD;
break;
case HAL_INT_TYPE_VIDOK:
pHalData->IntMask[0] &= ~BIT_VIDOK;
break;
case HAL_INT_TYPE_VODOK:
pHalData->IntMask[0] &= ~BIT_VODOK;
break;
case HAL_INT_TYPE_BEDOK:
pHalData->IntMask[0] &= ~BIT_BEDOK;
break;
case HAL_INT_TYPE_BKDOK:
pHalData->IntMask[0] &= ~BIT_BKDOK;
break;
case HAL_INT_TYPE_MGNTDOK:
pHalData->IntMask[0] &= ~BIT_MGTDOK;
break;
case HAL_INT_TYPE_HIGHDOK:
pHalData->IntMask[0] &= ~BIT_HIGHDOK;
break;
#if 0 //Filen: removed
case HAL_INT_TYPE_BDOK:
pHalData->IntMask[0] &= ~IMR_BCNDOK0_88E;
break;
#endif
case HAL_INT_TYPE_CPWM:
pHalData->IntMask[0] &= ~BIT_CPWM;
break;
case HAL_INT_TYPE_TSF_BIT32_TOGGLE:
pHalData->IntMask[0] &= ~BIT_TSF_BIT32_TOGGLE;
break;
case HAL_INT_TYPE_RX_OK:
pHalData->IntMask[0] &= ~BIT_RXOK;
break;
case HAL_INT_TYPE_RDU:
pHalData->IntMask[0] &= ~BIT_RDU;
break;
//4 // ========== DWORD 1 ==========
case HAL_INT_TYPE_RXFOVW:
pHalData->IntMask[1] &= ~BIT_FOVW;
break;
case HAL_INT_TYPE_TXFOVW:
pHalData->IntMask[1] &= ~BIT_TXFOVW;
break;
case HAL_INT_TYPE_RXERR:
pHalData->IntMask[1] &= ~BIT_RXERR_INT;
break;
case HAL_INT_TYPE_TXERR:
pHalData->IntMask[1] &= ~BIT_TXERR_INT;
break;
#if IS_EXIST_RTL8814AE
if ( IS_HARDWARE_TYPE_8814AE(Adapter) ) {
case HAL_INT_TYPE_PwrInt0:
pHalData->IntMask[3] &= ~BIT_PWR_INT_31to0;
break;
case HAL_INT_TYPE_PwrInt1:
pHalData->IntMask[3] &= ~BIT_PWR_INT_63to32;
break;
case HAL_INT_TYPE_PwrInt2:
pHalData->IntMask[3] &= ~BIT_PWR_INT_95to64;
break;
case HAL_INT_TYPE_PwrInt3:
pHalData->IntMask[3] &= ~BIT_PWR_INT_126to96;
break;
case HAL_INT_TYPE_PwrInt4:
pHalData->IntMask[3] &= ~BIT_PWR_INT_127;
break;
}
#endif // #if IS_EXIST_RTL8814AE
}
}
HAL_IMEM
VOID
DisableRxRelatedInterrupt88XX(
IN HAL_PADAPTER Adapter
)
{
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
HAL_PADAPTER priv = Adapter;
ULONG flags;
#if 0
HAL_SAVE_INT_AND_CLI(flags);
pHalData->IntMask_RxINTBackup[0] = pHalData->IntMask[0];
pHalData->IntMask_RxINTBackup[1] = pHalData->IntMask[1];
pHalData->IntMask[0] &= ~BIT_RXOK;
pHalData->IntMask[1] &= ~BIT_FOVW;
HAL_RESTORE_INT(flags);
HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]);
HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]);
#else
HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0] & ~ (BIT_RXOK | BIT_RDU));
HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1] & ~BIT_FOVW);
#endif
}
HAL_IMEM
VOID
EnableRxRelatedInterrupt88XX(
IN HAL_PADAPTER Adapter
)
{
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
HAL_PADAPTER priv = Adapter;
ULONG flags;
#if 0
HAL_SAVE_INT_AND_CLI(flags);
pHalData->IntMask[0] = pHalData->IntMask_RxINTBackup[0];
pHalData->IntMask[1] = pHalData->IntMask_RxINTBackup[1];
HAL_RESTORE_INT(flags);
#endif
HAL_RTL_W32(REG_HIMR0, pHalData->IntMask[0]);
HAL_RTL_W32(REG_HIMR1, pHalData->IntMask[1]);
}

88
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXIsr.h Executable file
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#ifndef __HAL88XX_ISR_H__
#define __HAL88XX_ISR_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXIsr.h
Abstract:
Defined HAL 88XX Interrupt Service Routine Related Define & Marco
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-04-30 Filen Create.
--*/
VOID
EnableIMR88XX(
IN HAL_PADAPTER Adapter
);
BOOLEAN
InterruptRecognized88XX(
IN HAL_PADAPTER Adapter,
IN PVOID pContent,
IN u4Byte ContentLen
);
BOOLEAN
GetInterrupt88XX(
IN HAL_PADAPTER Adapter,
IN HAL_INT_TYPE intType
);
VOID
AddInterruptMask88XX(
IN HAL_PADAPTER Adapter,
IN HAL_INT_TYPE intType
);
VOID
RemoveInterruptMask88XX(
IN HAL_PADAPTER Adapter,
IN HAL_INT_TYPE intType
);
VOID
DisableRxRelatedInterrupt88XX(
IN HAL_PADAPTER Adapter
);
VOID
EnableRxRelatedInterrupt88XX(
IN HAL_PADAPTER Adapter
);
#endif //__HAL88XX_ISR_H__

3469
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXPhyCfg.c Executable file
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289
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXPhyCfg.h Executable file
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#ifndef __HAL88XXPHYCFG_H__
#define __HAL88XXPHYCFG_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXPhyCfg.h
Abstract:
Defined HAL 88XX PHY BB setting functions
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-11-14 Eric Create.
--*/
typedef enum _RF88XX_RADIO_PATH_ {
RF88XX_PATH_A = 0, //Radio Path A
RF88XX_PATH_B = 1, //Radio Path B
RF88XX_PATH_MAX //Max RF number
} RFRF88XX_RADIO_PATH_E, *PRFRF88XX_RADIO_PATH_E;
typedef enum _BAND_TYPE{
RF88XX_BAND_ON_2_4G = 0,
RF88XX_BAND_ON_5G,
RF88XX_BAND_ON_BOTH,
RF88XX_BANDMAX
}RF88XX_BAND_TYPE,*PRF88XX_BAND_TYPE;
typedef enum _RF88XX_HT_CHANNEL_WIDTH {
RF88XX_HT_CHANNEL_WIDTH_20 = 0,
RF88XX_HT_CHANNEL_WIDTH_20_40 = 1,
RF88XX_HT_CHANNEL_WIDTH_80 = 2,
RF88XX_HT_CHANNEL_WIDTH_160 = 3,
RF88XX_HT_CHANNEL_WIDTH_10 = 4
}RF88XX_HT_CHANNEL_WIDTH,*PRF88XXHT_CHANNEL_WIDTH;
typedef enum _RF88XX_HT_CHANNEL_WIDTH_AC {
RF88XX_HT_CHANNEL_WIDTH_AC_20 = 0,
RF88XX_HT_CHANNEL_WIDTH_AC_40 = 1,
RF88XX_HT_CHANNEL_WIDTH_AC_80 = 2,
RF88XX_HT_CHANNEL_WIDTH_AC_160 = 3,
RF88XX_HT_CHANNEL_WIDTH_AC_10 = 4,
RF88XX_HT_CHANNEL_WIDTH_AC_5 = 5
}RF88XX_HT_CHANNEL_WIDTH_AC,*PRF88XX_HT_CHANNEL_WIDTH_AC;
u4Byte
phy_CalculateBitShift_88XX(
IN u4Byte BitMask
);
u4Byte
PHY_QueryBBReg_88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
void
PHY_SetBBReg_88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
void
PHY_SetRFReg_88XX_AC
(
IN HAL_PADAPTER Adapter,
IN u4Byte eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
PHY_QueryRFReg_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
void
SwBWMode88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte bandwidth,
IN s4Byte offset
);
void
SetChannelPara88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte channel,
IN s4Byte offset
);
void
CheckBand88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte RequestChannel
);
void SwitchWirelessBand88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte RequestChannel,
IN u1Byte Band
);
void UpdateBBRFVal88XX_AC(
IN HAL_PADAPTER Adapter,
IN u1Byte channel,
IN s4Byte offset
);
RT_STATUS
PHYSetCCKTxPower88XX_AC(
IN HAL_PADAPTER Adapter,
IN u1Byte channel
);
RT_STATUS
PHYSetOFDMTxPower88XX_AC(
IN HAL_PADAPTER Adapter,
IN u1Byte channel
);
void
CalOFDMTxPower5G_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u1Byte ch_idx
);
void
CalOFDMTxPower2G_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u1Byte ch_idx
);
s1Byte
convert_diff_88XX_AC(
IN s1Byte value
);
void
Write_1S_A_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte writeVal
);
void
Write_2S_A_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte writeVal
);
void
Write_OFDM_A_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte writeVal
);
void
Write_OFDM_B_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte writeVal
);
void
Write_1S_B_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte writeVal
);
void
Write_2S_B_88XX_AC(
IN HAL_PADAPTER Adapter,
IN u4Byte writeVal
);
void
use_DefaultOFDMTxPowerPathA88XX_AC(
IN HAL_PADAPTER Adapter
);
void
use_DefaultOFDMTxPowerPathB88XX_AC(
IN HAL_PADAPTER Adapter
);
RT_STATUS
PHYSetOFDMTxPower88XX_N(
IN HAL_PADAPTER Adapter,
IN u1Byte channel
);
RT_STATUS
PHYSetCCKTxPower88XX_N(
IN HAL_PADAPTER Adapter,
IN u1Byte channel
);
void
SwBWMode88XX_N(
IN HAL_PADAPTER Adapter,
IN u4Byte bandwidth,
IN s4Byte offset
);
void
PHY_SetRFReg_88XX_N
(
IN HAL_PADAPTER Adapter,
IN u4Byte eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
PHY_QueryRFReg_88XX_N
(
IN HAL_PADAPTER Adapter,
IN u4Byte eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
#if 0
s4Byte
get_tx_tracking_index_88XX(
IN HAL_PADAPTER Adapter,
IN s4Byte channel,
IN s4Byte i,
IN s4Byte delta,
IN s4Byte is_decrease,
IN s4Byte is_CCK
);
void
set_CCK_swing_index_88XX(
IN HAL_PADAPTER Adapter,
IN s2Byte CCK_index
);
void TXPowerTracking_ThermalMeter_88XX
(
IN HAL_PADAPTER Adapter
);
#endif
RT_STATUS
AddTxPower88XX_AC(
IN HAL_PADAPTER Adapter,
IN s1Byte index
);
#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES)
BOOLEAN
IsBBRegRange88XX
(
IN HAL_PADAPTER Adapter,
IN u4Byte RegAddr
);
#endif //#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES)
#if (IS_RTL8814A_SERIES)
BOOLEAN
IsBBRegRange88XX_V1
(
IN HAL_PADAPTER Adapter,
IN u4Byte RegAddr
);
#endif //#if (IS_RTL8814A_SERIES)
#endif // #ifndef __HAL88XXPHYCFG_H__

150
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.c Executable file
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/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXPwrSeqCmd.c
Abstract:
Implement HW Power sequence configuration CMD handling routine for Realtek devices.
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-04-03 Filen Create.
--*/
#include "../HalPrecomp.h"
//
// Description:
// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
// Assumption:
// We should follow specific format which was released from HW SD.
//
// 2011.07.07, added by Roger.
//
BOOLEAN
HalPwrSeqCmdParsing88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte CutVersion,
IN u1Byte FabVersion,
IN u1Byte InterfaceType,
IN WLAN_PWR_CFG PwrSeqCmd[]
)
{
WLAN_PWR_CFG PwrCfgCmd = {0};
u32 bPollingBit = _FALSE;
u32 AryIdx=0;
u8 value = 0;
u32 offset = 0;
u32 pollingCount = 0; // polling autoload done.
u32 maxPollingCnt = 5000;
do {
PwrCfgCmd=PwrSeqCmd[AryIdx];
RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, ENTRY, offset:0x%x, cut_msk:0x%x, fab_msk:0x%x, if_msk:0x%x, base:0x%x, cmd:0x%x, msk:0x%x, value:0x%x\n",
__FUNCTION__, __LINE__, GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
GET_PWR_CFG_FAB_MASK(PwrCfgCmd), GET_PWR_CFG_INTF_MASK(PwrCfgCmd), GET_PWR_CFG_BASE(PwrCfgCmd),
GET_PWR_CFG_CMD(PwrCfgCmd), GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd)) );
HAL_delay_us(600);
//2 Only Handle the command whose FAB, CUT, and Interface are matched
if((GET_PWR_CFG_FAB_MASK(PwrCfgCmd)&FabVersion)&&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd)&CutVersion)&&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd)&InterfaceType)) {
switch(GET_PWR_CFG_CMD(PwrCfgCmd))
{
case PWR_CMD_READ:
RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_READ\n", __FUNCTION__, __LINE__));
break;
case PWR_CMD_WRITE:
RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_WRITE\n", __FUNCTION__, __LINE__));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_SDIO_HCI
//
// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
// 2011.07.07.
//
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
{
// Read Back SDIO Local value
value = SdioLocalCmd52Read1Byte(Adapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write Back SDIO Local value
SdioLocalCmd52Write1Byte(Adapter, offset, value);
}
else
#endif
{
//Read the value from system register
value = HAL_RTL_R8(offset);
value = value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
value = value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
//Write the value back to sytem register
HAL_RTL_W8(offset, value);
}
break;
case PWR_CMD_POLLING:
RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_POLLING\n", __FUNCTION__, __LINE__));
bPollingBit = _FALSE;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
do {
#ifdef CONFIG_SDIO_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
value = SdioLocalCmd52Read1Byte(Adapter, offset);
else
#endif
value = HAL_RTL_R8(offset);
value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
if(value==(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd)))
bPollingBit = _TRUE;
else
HAL_delay_us(20);
if(pollingCount++ > maxPollingCnt){
RT_TRACE(COMP_INIT, DBG_WARNING, ("%s %d, PWR_CMD_POLLING, Fail to polling Offset[0x%x]\n", __FUNCTION__, __LINE__, offset));
return _FALSE;
}
}while(!bPollingBit);
break;
case PWR_CMD_DELAY:
RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_DELAY\n", __FUNCTION__, __LINE__));
if(GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
HAL_delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else
HAL_delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
break;
case PWR_CMD_END:
// When this command is parsed, end the process
RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_END\n", __FUNCTION__, __LINE__));
return _TRUE;
break;
default:
RT_TRACE(COMP_INIT, DBG_SERIOUS, ("%s %d, Unknown CMD!!\n", __FUNCTION__, __LINE__));
break;
}
}
AryIdx++;//Add Array Index
}while(1);
return _TRUE;
}

132
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.h Executable file
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#ifndef __HAL88XX_PWRSEQCMD_H__
#define __HAL88XX_PWRSEQCMD_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXPwrSeqCmd.h
Abstract:
Defined HAL 88XX Power Sequence Command
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-04-03 Filen Create.
--*/
#if 0
/*---------------------------------------------*/
//3 The value of cmd: 4 bits
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
// offset: the read register offset
// msk: the mask of the read value
// value: N/A, left by 0
// note: dirver shall implement this function by read & msk
#define PWR_CMD_WRITE 0x01
// offset: the read register offset
// msk: the mask of the write bits
// value: write value
// note: driver shall implement this cmd by read & msk after write
#define PWR_CMD_POLLING 0x02
// offset: the read register offset
// msk: the mask of the polled value
// value: the value to be polled, masked by the msd field.
// note: driver shall implement this cmd by
// do{
// if( (Read(offset) & msk) == (value & msk) )
// break;
// } while(not timeout);
#define PWR_CMD_DELAY 0x03
// offset: the value to delay
// msk: N/A
// value: the unit of delay, 0: us, 1: ms
#define PWR_CMD_END 0x04
// offset: N/A
// msk: N/A
// value: N/A
/*---------------------------------------------*/
//3 The value of base: 4 bits
/*---------------------------------------------*/
// define the base address of each block
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
//3 The value of interface_msk: 4 bits
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of fab_msk: 4 bits
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3The value of cut_msk: 8 bits
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
{
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
} PWRSEQ_DELAY_UNIT;
typedef struct _WL_PWR_CFG_
{
unsigned short offset;
unsigned char cut_msk;
unsigned char fab_msk:4;
unsigned char interface_msk:4;
unsigned char base:4;
unsigned char cmd:4;
unsigned char msk;
unsigned char value;
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
#else
#include "../../HalPwrSeqCmd.h"
#endif
BOOLEAN
HalPwrSeqCmdParsing88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte CutVersion,
IN u1Byte FabVersion,
IN u1Byte InterfaceType,
IN WLAN_PWR_CFG PwrSeqCmd[]
);
#endif //#define __HAL88XX_PWRSEQCMD_H__

25
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXReg.h Executable file
View File

@@ -0,0 +1,25 @@
#ifndef __RTL88XX_REG_H__
#define __RTL88XX_REG_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXReg.h
Abstract:
Defined RTL88XX Register Offset & Marco & Bit define
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-03-23 Filen Create.
2012-03-29 Lun-Wu Yeh Add Tx/Rx Desc Reg
--*/
/*--------------------------Define -------------------------------------------*/
#endif //__RTL88XX_REG_H__

748
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXRxDesc.c Executable file
View File

@@ -0,0 +1,748 @@
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXRxDesc.c
Abstract:
Defined RTL88XX HAL rx desc common function
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-03-29 Lun-Wu Yeh Add PrepareRxDesc88XX().
--*/
#include "../HalPrecomp.h"
#if (HAL_DEV_BUS_TYPE & (HAL_RT_EMBEDDED_INTERFACE | HAL_RT_PCI_INTERFACE))
#ifdef CONFIG_RTL_PROC_NEW
#define PROC_PRINT(fmt, arg...) seq_printf(s, fmt, ## arg)
#else
#define PROC_PRINT printk
#endif
void DumpRxBDesc88XX(
IN HAL_PADAPTER Adapter,
#ifdef CONFIG_RTL_PROC_NEW
IN struct seq_file *s,
#endif
IN u4Byte q_num
)
{
PHCI_RX_DMA_MANAGER_88XX prx_dma;
int i=0;
prx_dma = (PHCI_RX_DMA_MANAGER_88XX)(_GET_HAL_DATA(Adapter)->PRxDMA88XX);
#ifdef NOT_RTK_BSP
if (NULL == prx_dma->rx_queue[q_num].pRXBD_head)
return;
#endif
#if RXBD_READY_CHECK_METHOD
PROC_PRINT(" q_num:%d, hw_idx=%d,host_idx= %d,cur_host_idx:%d, rxtag_seq_num:%d\n", q_num,
prx_dma->rx_queue[q_num].hw_idx, prx_dma->rx_queue[q_num].host_idx,
prx_dma->rx_queue[q_num].cur_host_idx, prx_dma->rx_queue[q_num].rxtag_seq_num);
#else
PROC_PRINT(" q_num:%d, hw_idx=%d,host_idx= %d,cur_host_idx:%d\n", q_num,
prx_dma->rx_queue[q_num].hw_idx, prx_dma->rx_queue[q_num].host_idx,
prx_dma->rx_queue[q_num].cur_host_idx);
#endif
PROC_PRINT("total_rxbd_num=%d,avail_rxbd_num= %d,reg_rwptr_idx:%x\n",
prx_dma->rx_queue[q_num].total_rxbd_num, prx_dma->rx_queue[q_num].avail_rxbd_num, prx_dma->rx_queue[q_num].reg_rwptr_idx);
PROC_PRINT("RWreg(%x):%08x\n", REG_RXQ_RXBD_IDX, HAL_RTL_R32(REG_RXQ_RXBD_IDX));
#ifdef CONFIG_NET_PCI
if (HAL_IS_PCIBIOS_TYPE(Adapter)) {
PROC_PRINT("pRXBD_head=%08x, %08lx, reg(%x):%08x\n",
(u4Byte)prx_dma->rx_queue[q_num].pRXBD_head ,
prx_dma->rx_queue[q_num].rxbd_dma_addr,
REG_RXQ_RXBD_DESA, HAL_RTL_R32(REG_RXQ_RXBD_DESA));
for (i=0;i<RX_Q_RXBD_NUM;i++ ){
PROC_PRINT("pRXBD_head[%d], addr:%08x,%08lx: Dword0: 0x%x, Dword1: 0x%x\n",
i,
(u4Byte)&prx_dma->rx_queue[q_num].pRXBD_head[i],
prx_dma->rx_queue[q_num].rxbd_dma_addr + sizeof(RX_BUFFER_DESCRIPTOR)*i,
(u4Byte)GET_DESC(prx_dma->rx_queue[q_num].pRXBD_head[i].Dword0),
(u4Byte)GET_DESC(prx_dma->rx_queue[q_num].pRXBD_head[i].Dword1) );
}
} else
#endif
{
PROC_PRINT("pRXBD_head=%p, %08lx, reg(%x):%08x\n",
prx_dma->rx_queue[q_num].pRXBD_head ,
HAL_VIRT_TO_BUS1(Adapter, (PVOID)prx_dma->rx_queue[q_num].pRXBD_head,sizeof(RX_BUFFER_DESCRIPTOR) * RX_Q_RXBD_NUM, PCI_DMA_TODEVICE),
REG_RXQ_RXBD_DESA, HAL_RTL_R32(REG_RXQ_RXBD_DESA));
for (i=0;i<RX_Q_RXBD_NUM;i++ ){
PROC_PRINT("pRXBD_head[%d], addr:%08x,%08x: Dword0: 0x%x, Dword1: 0x%x\n",
i,
(u4Byte)&prx_dma->rx_queue[q_num].pRXBD_head[i],
(u4Byte)HAL_VIRT_TO_BUS1(Adapter, (PVOID)&prx_dma->rx_queue[q_num].pRXBD_head[i],sizeof(RX_BUFFER_DESCRIPTOR), PCI_DMA_TODEVICE),
(u4Byte)GET_DESC(prx_dma->rx_queue[q_num].pRXBD_head[i].Dword0),
(u4Byte)GET_DESC(prx_dma->rx_queue[q_num].pRXBD_head[i].Dword1) );
}
}
}
typedef void (*INIT_RXBUF_FUNC)(HAL_PADAPTER Adapter, PVOID pSkb, u2Byte rxbd_idx, pu4Byte pBufAddr, pu4Byte pBufLen);
//
// bufferLen: SKB Buffer Size (Linux, SKB Format)(RXDESC + Payload)
//
RT_STATUS
PrepareRXBD88XX(
IN HAL_PADAPTER Adapter,
IN u2Byte bufferLen,
IN PVOID Callback // callback function
)
{
PHCI_RX_DMA_MANAGER_88XX prx_dma;
HCI_RX_DMA_QUEUE_88XX q_num;
u2Byte rxbd_idx;
pu1Byte pdesc_dma_buf, desc_dma_buf_start;
u4Byte value32 = 0;
PHAL_BUF pbuf;
u4Byte RXBD_NUM[HCI_RX_DMA_QUEUE_MAX_NUM] =
{
RX_Q_RXBD_NUM
};
u4Byte RXBD_Reg[HCI_RX_DMA_QUEUE_MAX_NUM] =
{
REG_RXQ_RXBD_DESA
};
u4Byte RXBD_RWPtr_Reg[HCI_RX_DMA_QUEUE_MAX_NUM] =
{
REG_RXQ_RXBD_IDX
};
prx_dma = (PHCI_RX_DMA_MANAGER_88XX)(_GET_HAL_DATA(Adapter)->PRxDMA88XX);
PlatformZeroMemory(prx_dma, sizeof(HCI_RX_DMA_MANAGER_88XX));
#ifdef CONFIG_NET_PCI
if (HAL_IS_PCIBIOS_TYPE(Adapter)) {
unsigned long tmp_dma_ring_addr =0;
PlatformZeroMemory((void*)_GET_HAL_DATA(Adapter)->alloc_dma_buf, DESC_DMA_PAGE_SIZE_MAX_HAL);
pdesc_dma_buf = (pu1Byte)(_GET_HAL_DATA(Adapter)->ring_virt_addr);
printk("%s(%d):size=%d, ring_dma_addr:%08lx, alloc_dma_buf:%08lx, ring_virt_addr:%08lx\n",
__FUNCTION__,__LINE__, DESC_DMA_PAGE_SIZE_MAX_HAL,
_GET_HAL_DATA(Adapter)->ring_dma_addr, _GET_HAL_DATA(Adapter)->alloc_dma_buf,
_GET_HAL_DATA(Adapter)->ring_virt_addr);
for (q_num = 0; q_num < HCI_RX_DMA_QUEUE_MAX_NUM; q_num++)
{
prx_dma->rx_queue[q_num].hw_idx = 0;
prx_dma->rx_queue[q_num].host_idx = 0;
prx_dma->rx_queue[q_num].cur_host_idx = 0;
#if RXBD_READY_CHECK_METHOD
prx_dma->rx_queue[q_num].rxtag_seq_num = 0;
#endif
#if CFG_HAL_DELAY_REFILL_RX_BUF
prx_dma->rx_queue[q_num].rxbd_ok_cnt = 0;
#endif
prx_dma->rx_queue[q_num].total_rxbd_num = RXBD_NUM[q_num];
prx_dma->rx_queue[q_num].avail_rxbd_num = RXBD_NUM[q_num];
prx_dma->rx_queue[q_num].reg_rwptr_idx = RXBD_RWPtr_Reg[q_num];
if ( 0 == q_num ) {
prx_dma->rx_queue[q_num].pRXBD_head = (PRX_BUFFER_DESCRIPTOR)pdesc_dma_buf;
tmp_dma_ring_addr = _GET_HAL_DATA(Adapter)->ring_dma_addr;
}
else {
prx_dma->rx_queue[q_num].pRXBD_head = prx_dma->rx_queue[q_num-1].pRXBD_head + \
sizeof(RX_BUFFER_DESCRIPTOR) * RXBD_NUM[q_num-1];
tmp_dma_ring_addr = tmp_dma_ring_addr + sizeof(RX_BUFFER_DESCRIPTOR) * RXBD_NUM[q_num-1];
}
prx_dma->rx_queue[q_num].rxbd_dma_addr = tmp_dma_ring_addr;
printk ("QNum: 0x%x, RXBDHead: 0x%p, tmp_dma_ring_addr:0x%08lx\n",
(u4Byte)q_num, prx_dma->rx_queue[q_num].pRXBD_head, tmp_dma_ring_addr);
HAL_RTL_W32(RXBD_Reg[q_num], tmp_dma_ring_addr);
//Init Read/Write Pointer for RX queue
HAL_RTL_W32(RXBD_RWPtr_Reg[q_num], 0);
for(rxbd_idx = 0; rxbd_idx < RXBD_NUM[q_num]; rxbd_idx++)
{
pbuf = HAL_OS_malloc(Adapter, bufferLen, _SKB_RX_, TRUE);
if ( NULL == pbuf ) {
panic_printk("%s:%d Allocate HAL Memory Failed\n", __FUNCTION__, __LINE__);
return RT_STATUS_FAILURE;
}
else {
UpdateRXBDInfo88XX(Adapter, q_num, rxbd_idx, (pu1Byte)pbuf, Callback, _TRUE);
#if 0
RT_TRACE_F(COMP_INIT, DBG_TRACE, ("pRXBD_head[%d]: Dword0: 0x%lx, Dword1: 0x%lx\n", \
rxbd_idx, \
(u4Byte)GET_DESC(prx_dma->rx_queue[q_num].pRXBD_head[rxbd_idx].Dword0), \
(u4Byte)GET_DESC(prx_dma->rx_queue[q_num].pRXBD_head[rxbd_idx].Dword1) \
));
#endif
}
}
}
//DumpRxBDesc88XX(Adapter, 0);
return RT_STATUS_SUCCESS;
}
#endif
desc_dma_buf_start = _GET_HAL_DATA(Adapter)->desc_dma_buf;
PlatformZeroMemory(desc_dma_buf_start, _GET_HAL_DATA(Adapter)->desc_dma_buf_len);
#ifdef TRXBD_CACHABLE_REGION
_dma_cache_wback((unsigned long)((PVOID)(desc_dma_buf_start)-CONFIG_LUNA_SLAVE_PHYMEM_OFFSET), _GET_HAL_DATA(Adapter)->desc_dma_buf_len);
#endif
pdesc_dma_buf = (pu1Byte)(((unsigned long)desc_dma_buf_start) + \
(HAL_PAGE_SIZE - (((unsigned long)desc_dma_buf_start) & (HAL_PAGE_SIZE-1))));
//Transfer to Non-cachable address
#ifndef TRXBD_CACHABLE_REGION
pdesc_dma_buf = (pu1Byte)HAL_TO_NONCACHE_ADDR((u4Byte)pdesc_dma_buf);
#endif
for (q_num = 0; q_num < HCI_RX_DMA_QUEUE_MAX_NUM; q_num++)
{
prx_dma->rx_queue[q_num].hw_idx = 0;
prx_dma->rx_queue[q_num].host_idx = 0;
prx_dma->rx_queue[q_num].cur_host_idx = 0;
#if RXBD_READY_CHECK_METHOD
prx_dma->rx_queue[q_num].rxtag_seq_num = 0;
#endif
#if CFG_HAL_DELAY_REFILL_RX_BUF
prx_dma->rx_queue[q_num].rxbd_ok_cnt = 0;
#endif
prx_dma->rx_queue[q_num].total_rxbd_num = RXBD_NUM[q_num];
prx_dma->rx_queue[q_num].avail_rxbd_num = RXBD_NUM[q_num];
prx_dma->rx_queue[q_num].reg_rwptr_idx = RXBD_RWPtr_Reg[q_num];
if ( 0 == q_num ) {
prx_dma->rx_queue[q_num].pRXBD_head = (PRX_BUFFER_DESCRIPTOR)pdesc_dma_buf;
}
else {
prx_dma->rx_queue[q_num].pRXBD_head = prx_dma->rx_queue[q_num-1].pRXBD_head + \
sizeof(RX_BUFFER_DESCRIPTOR) * RXBD_NUM[q_num-1];
}
RT_TRACE_F(COMP_INIT, DBG_TRACE, ("QNum: 0x%lx, RXBDHead: 0x%lx\n", \
(u4Byte)q_num, \
(u4Byte)(prx_dma->rx_queue[q_num].pRXBD_head) \
));
HAL_RTL_W32(RXBD_Reg[q_num], \
HAL_VIRT_TO_BUS1(Adapter, (PVOID)prx_dma->rx_queue[q_num].pRXBD_head, \
sizeof(RX_BUFFER_DESCRIPTOR) * RXBD_NUM[q_num], HAL_PCI_DMA_TODEVICE) + CONFIG_LUNA_SLAVE_PHYMEM_OFFSET_HAL);
//Init Read/Write Pointer for RX queue
HAL_RTL_W32(RXBD_RWPtr_Reg[q_num], 0);
for(rxbd_idx = 0; rxbd_idx < RXBD_NUM[q_num]; rxbd_idx++)
{
pbuf = HAL_OS_malloc(Adapter, bufferLen, _SKB_RX_, TRUE);
if ( NULL == pbuf ) {
panic_printk("%s:%d [%d]Allocate HAL Memory Failed\n", __FUNCTION__, __LINE__, rxbd_idx);
return RT_STATUS_FAILURE;
}
else {
UpdateRXBDInfo88XX(Adapter, q_num, rxbd_idx, (pu1Byte)pbuf, Callback, _TRUE);
/* RT_TRACE_F(COMP_INIT, DBG_TRACE, ("pRXBD_head[%d]: Dword0: 0x%lx, Dword1: 0x%lx\n",
rxbd_idx,
(u4Byte)GET_DESC(prx_dma->rx_queue[q_num].pRXBD_head[rxbd_idx].Dword0),
(u4Byte)GET_DESC(prx_dma->rx_queue[q_num].pRXBD_head[rxbd_idx].Dword1)
)); */
}
}
}
return RT_STATUS_SUCCESS;
}
HAL_IMEM
RT_STATUS
UpdateRXBDInfo88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX
IN u2Byte rxbd_idx,
IN pu1Byte pBuf,
IN PVOID Callback, // callback function
IN BOOLEAN bInit
)
{
PHCI_RX_DMA_MANAGER_88XX prx_dma;
INIT_RXBUF_FUNC InitRXDescFunc = (INIT_RXBUF_FUNC)Callback;
u4Byte bufAddr;
u4Byte bufLen;
unsigned long dma_addr;
prx_dma = (PHCI_RX_DMA_MANAGER_88XX)(_GET_HAL_DATA(Adapter)->PRxDMA88XX);
InitRXDescFunc(Adapter, pBuf, rxbd_idx, &bufAddr, &bufLen);
#if 0
//#ifdef CFG_HAL_DBG
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("rxbd_idx:0x%lx, bufAddr:0x%lx, phy(bufAddr):0x%lx\n",
rxbd_idx, bufAddr, HAL_VIRT_TO_BUS1(Adapter, (PVOID)bufAddr, bufLen, HAL_PCI_DMA_TODEVICE)));
#endif
#if 0 //Filen_test
if ( _TRUE == bInit ) {
SET_DESC_FIELD_CLR(prx_dma->rx_queue[queueIndex].pRXBD_head[rxbd_idx].Dword0,
bufLen,
RXBD_DW0_RXBUFSIZE_MSK, RXBD_DW0_RXBUFSIZE_SH);
}
#else
SET_DESC_FIELD_CLR(prx_dma->rx_queue[queueIndex].pRXBD_head[rxbd_idx].Dword0,
bufLen,
RXBD_DW0_RXBUFSIZE_MSK, RXBD_DW0_RXBUFSIZE_SH);
#endif
#if defined(CONFIG_NET_PCI) && defined(NOT_RTK_BSP)
dma_addr = GET_HW(Adapter)->rx_infoL[rxbd_idx].paddr;
#else
dma_addr = HAL_VIRT_TO_BUS1(Adapter, (PVOID)bufAddr, bufLen, HAL_PCI_DMA_TODEVICE);
#endif
SET_DESC_FIELD_CLR(prx_dma->rx_queue[queueIndex].pRXBD_head[rxbd_idx].Dword1,
dma_addr + CONFIG_LUNA_SLAVE_PHYMEM_OFFSET_HAL,
RXBD_DW1_PHYADDR_LOW_MSK, RXBD_DW1_PHYADDR_LOW_SH);
#if RXBD_READY_CHECK_METHOD
if ( _TRUE == bInit ) {
SET_DESC_FIELD_CLR(prx_dma->rx_queue[queueIndex].pRXBD_head[rxbd_idx].Dword0,
0xFFFF, RXBD_DW0_TOTALRXPKTSIZE_MSK, RXBD_DW0_TOTALRXPKTSIZE_SH);
}
#else
SET_DESC_FIELD_CLR(prx_dma->rx_queue[queueIndex].pRXBD_head[rxbd_idx].Dword0,
0, RXBD_DW0_TOTALRXPKTSIZE_MSK, RXBD_DW0_TOTALRXPKTSIZE_SH);
#endif //RXBD_READY_CHECK_METHOD
#ifdef CONFIG_NET_PCI
if (HAL_IS_PCIBIOS_TYPE(Adapter)) {
HAL_CACHE_SYNC_WBACK(Adapter,
prx_dma->rx_queue[queueIndex].rxbd_dma_addr + rxbd_idx * sizeof(RX_BUFFER_DESCRIPTOR),
sizeof(RX_BUFFER_DESCRIPTOR), HAL_PCI_DMA_TODEVICE);
} else
#endif
#ifdef TRXBD_CACHABLE_REGION
_dma_cache_wback((unsigned long)((PVOID)(prx_dma->rx_queue[queueIndex].pRXBD_head + rxbd_idx)-CONFIG_LUNA_SLAVE_PHYMEM_OFFSET), sizeof(RX_BUFFER_DESCRIPTOR));
#else
HAL_CACHE_SYNC_WBACK(Adapter,
HAL_VIRT_TO_BUS1(Adapter, (PVOID)(prx_dma->rx_queue[queueIndex].pRXBD_head + rxbd_idx), sizeof(RX_BUFFER_DESCRIPTOR), HAL_PCI_DMA_TODEVICE),
sizeof(RX_BUFFER_DESCRIPTOR), HAL_PCI_DMA_TODEVICE);
#endif
if ( 0 == GET_DESC(prx_dma->rx_queue[queueIndex].pRXBD_head[rxbd_idx].Dword1) ) {
RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Address(0x%lx) Error\n", prx_dma->rx_queue[queueIndex].pRXBD_head[rxbd_idx].Dword1));
return RT_STATUS_FAILURE;
}
return RT_STATUS_SUCCESS;
}
void
DumpRxPktContent88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex //HCI_RX_DMA_QUEUE_88XX
)
{
#if 0
PHCI_RX_DMA_MANAGER_88XX prx_dma;
PHCI_RX_DMA_QUEUE_STRUCT_88XX cur_q;
PRX_DESC_88XX prx_desc;
// TODO: no initial value for prx_desc
prx_dma = (PHCI_RX_DMA_MANAGER_88XX)(_GET_HAL_DATA(Adapter)->PRxDMA88XX);
cur_q = &(prx_dma->rx_queue[queueIndex]);
//RXBD
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("\n\nRXBD[%ld]:\nDword0=0x%lx, Dword1=0x%lx \n", \
(u4Byte)cur_q->cur_host_idx, \
(u4Byte)GET_DESC(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0), \
(u4Byte)GET_DESC(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword1) \
));
//RXDESC
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "RXDESC:\n", prx_desc, sizeof(RX_DESC_88XX));
//PHYStatus
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "PHYStatus:\n", ((pu1Byte)prx_desc + SIZE_RXDESC_88XX), (GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_DRV_INFO_SIZE_MSK, RX_DW0_DRV_INFO_SIZE_SH)<<3) + GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_SHIFT_MSK, RX_DW0_SHIFT_SH));
//RXPkt
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "Payload:\n", (pu1Byte)prx_desc + SIZE_RXDESC_88XX + (GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_DRV_INFO_SIZE_MSK, RX_DW0_DRV_INFO_SIZE_SH)<<3) + GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_SHIFT_MSK, RX_DW0_SHIFT_SH), \
GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_PKT_LEN_MSK, RX_DW0_PKT_LEN_SH));
#endif
}
#define RXBD_RXTAG_POLLING_CNT 100
#define RXBD_RXTAG_MASK 0x1FFF
HAL_IMEM
RT_STATUS
QueryRxDesc88XX (
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX
IN pu1Byte pBufAddr,
OUT PVOID pRxDescStatus
)
{
BOOLEAN bResult = SUCCESS;
u4Byte PollingCnt = 0;
PHCI_RX_DMA_MANAGER_88XX prx_dma;
PHCI_RX_DMA_QUEUE_STRUCT_88XX cur_q;
PRX_DESC_STATUS_88XX prx_desc_status;
PRX_DESC_88XX prx_desc;
#if CFG_HAL_DBG
u4Byte crc32;
pu1Byte pFrame;
u2Byte frameLen;
BOOLEAN bDivisionCRC = _FALSE;
u2Byte cnt = 0;
u2Byte shift = 0;
u1Byte tempByte;
u4Byte rx_crc32;
#endif
prx_dma = (PHCI_RX_DMA_MANAGER_88XX)(_GET_HAL_DATA(Adapter)->PRxDMA88XX);
cur_q = &(prx_dma->rx_queue[queueIndex]);
prx_desc_status = (PRX_DESC_STATUS_88XX)pRxDescStatus;
#ifdef CONFIG_NET_PCI
unsigned long rxbd_dma_addr = cur_q->rxbd_dma_addr + sizeof(RX_BUFFER_DESCRIPTOR)*cur_q->cur_host_idx;
#endif
do {
#ifdef CONFIG_NET_PCI
if (HAL_IS_PCIBIOS_TYPE(Adapter)) {
HAL_CACHE_SYNC_WBACK(Adapter, rxbd_dma_addr, sizeof(RX_BUFFER_DESCRIPTOR), HAL_PCI_DMA_FROMDEVICE);
}
#endif
#if RXBD_READY_CHECK_METHOD
#ifdef TRXBD_CACHABLE_REGION
_dma_cache_inv((unsigned long)((&(cur_q->pRXBD_head[cur_q->cur_host_idx]))-CONFIG_LUNA_SLAVE_PHYMEM_OFFSET),
sizeof(RX_BUFFER_DESCRIPTOR));
#endif
if ( cur_q->rxtag_seq_num != GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0, RXBD_DW0_TOTALRXPKTSIZE_MSK, RXBD_DW0_TOTALRXPKTSIZE_SH) ) {
RT_TRACE(COMP_RECV, DBG_WARNING, ("Polling failed(cnt: %d), keep trying, DW0(0x%x), RXBDCheckRdySeqNum(0x%x) FS,LS(0x%x,0x%x)\n",
PollingCnt,
GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0, RXBD_DW0_TOTALRXPKTSIZE_MSK, RXBD_DW0_TOTALRXPKTSIZE_SH),
cur_q->rxtag_seq_num,
GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0, RXBD_DW0_FS_MSK, RXBD_DW0_FS_SH),
GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0, RXBD_DW0_LS_MSK, RXBD_DW0_LS_SH)
));
}
else {
break;
}
#else
if (0 == GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0, RXBD_DW0_TOTALRXPKTSIZE_MSK, RXBD_DW0_TOTALRXPKTSIZE_SH)) {
RT_TRACE(COMP_RECV, DBG_WARNING, ("Polling failed(cnt: %d), keep trying, DW0(0x%x)\n", PollingCnt, GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0, RXBD_DW0_TOTALRXPKTSIZE_MSK, RXBD_DW0_TOTALRXPKTSIZE_SH)));
}
else {
break;
}
#endif //RXBD_READY_CHECK_METHOD
PollingCnt++;
//HAL_delay_ms(1);
} while(PollingCnt < RXBD_RXTAG_POLLING_CNT);
if ( PollingCnt >= RXBD_RXTAG_POLLING_CNT ) {
RT_TRACE(COMP_RECV, DBG_SERIOUS, ("Polling failed(0x%x)\n", Adapter->pshare->RxTagPollingCount));
Adapter->pshare->RxTagPollingCount++;
Adapter->pshare->RxTagMismatchCount++;
#if CFG_HAL_DBG
//code below in order to dump packet
bResult = FAIL;
prx_desc_status->FS = 1;
prx_desc_status->LS = 1;
goto _RXPKT_DUMP;
#else
// return RT_STATUS_FAILURE;
#if RXBD_READY_CHECK_METHOD
cur_q->rxtag_seq_num = GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0, RXBD_DW0_TOTALRXPKTSIZE_MSK, RXBD_DW0_TOTALRXPKTSIZE_SH);
#endif
#endif //#if CFG_HAL_DBG
}
else {
Adapter->pshare->RxTagPollingCount=0;
}
#if RXBD_READY_CHECK_METHOD
cur_q->rxtag_seq_num++;
cur_q->rxtag_seq_num &= RXBD_RXTAG_MASK;
#endif //#if RXBD_READY_CHECK_METHOD
#if 0
//Cache flush for current RXDESC, becuase we don't flush rxdesc in some cases. ex. memory allocate fail then reuse
// TODO: move to other better place
HAL_CACHE_SYNC_WBACK(Adapter,
HAL_VIRT_TO_BUS1(Adapter, (PVOID)prx_desc, sizeof(RX_DESC_88XX), HAL_PCI_DMA_TODEVICE),
sizeof(RX_DESC_88XX), HAL_PCI_DMA_TODEVICE);
#endif
#if 0
HAL_CACHE_SYNC_WBACK(Adapter,
HAL_VIRT_TO_BUS1(Adapter, (PVOID)(prx_desc), 2048, HAL_PCI_DMA_TODEVICE),
2048, HAL_PCI_DMA_TODEVICE);
#endif
// get rxbd
prx_desc_status->FS = GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0,
RXBD_DW0_FS_MSK, RXBD_DW0_FS_SH);
prx_desc_status->LS = GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0,
RXBD_DW0_LS_MSK, RXBD_DW0_LS_SH);
prx_desc_status->RXBuffSize = GET_DESC_FIELD(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0,
RXBD_DW0_RXBUFSIZE_MSK, RXBD_DW0_RXBUFSIZE_SH);
if ( prx_desc_status->FS==0x01 ) {
#ifdef CONFIG_NET_PCI
if (HAL_IS_PCIBIOS_TYPE(Adapter)) {
HAL_CACHE_SYNC_WBACK(Adapter, GET_HW(Adapter)->rx_infoL[cur_q->cur_host_idx].paddr, sizeof(RX_DESC_88XX), HAL_PCI_DMA_FROMDEVICE);
}
#endif
#ifdef TRXBD_CACHABLE_REGION
_dma_cache_inv((unsigned long)(pBufAddr-CONFIG_LUNA_SLAVE_PHYMEM_OFFSET), sizeof(RX_DESC_88XX));
#endif
prx_desc = (PRX_DESC_88XX)pBufAddr;
// get rx desc
prx_desc_status->PKT_LEN = GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_PKT_LEN_MSK, RX_DW0_PKT_LEN_SH);
prx_desc_status->CRC32 = GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_CRC32_MSK, RX_DW0_CRC32_SH);
prx_desc_status->ICVERR = GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_ICVERR_MSK, RX_DW0_ICVERR_SH);
prx_desc_status->DRV_INFO_SIZE = GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_DRV_INFO_SIZE_MSK, RX_DW0_DRV_INFO_SIZE_SH)<<3;
prx_desc_status->SHIFT = GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_SHIFT_MSK, RX_DW0_SHIFT_SH);
prx_desc_status->PHYST = GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_PHYST_MSK, RX_DW0_PHYST_SH);
prx_desc_status->SWDEC = GET_DESC_FIELD(prx_desc->Dword0, RX_DW0_SWDEC_MSK, RX_DW0_SWDEC_SH);
prx_desc_status->PAGGR = GET_DESC_FIELD(prx_desc->Dword1, RX_DW1_PAGGR_MSK, RX_DW1_PAGGR_SH);
prx_desc_status->C2HPkt = GET_DESC_FIELD(prx_desc->Dword2, RX_DW2_C2HPKT_MSK, RX_DW2_C2HPKT_SH);
prx_desc_status->RX_RATE = GET_DESC_FIELD(prx_desc->Dword3, RX_DW3_RX_RATE_MSK, RX_DW3_RX_RATE_SH);
#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES)
if (IS_HARDWARE_TYPE_8192E(Adapter) || IS_HARDWARE_TYPE_8881A(Adapter)) {
prx_desc_status->OFDM_SGI = GET_DESC_FIELD(prx_desc->Dword4, RX_DW4_OFDM_SGI_MSK, RX_DW4_OFDM_SGI_SH);
}
#endif //#if (IS_RTL8192E_SERIES || IS_RTL8881A_SERIES)
prx_desc_status->BW = GET_DESC_FIELD(prx_desc->Dword4, RX_DW4_BW_MSK, RX_DW4_BW_SH);
#if CFG_HAL_HW_FILL_MACID
if (IS_HARDWARE_TYPE_8814A(Adapter)) {
prx_desc_status->rxMACID = GET_DESC_FIELD(prx_desc->Dword4, RX_DW4_MACID_MSK, RX_DW4_MACID_SH);
}
#endif //#if IS_RTL8814A_SERIES
#if 0 //CFG_HAL_DBG
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("pBufAddr: 0x%lx\n", (u4Byte)pBufAddr));
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("RXBuffSize: 0x%lx, fs,ls:(0x%lx,0x%lx), PKT_LEN:0x%lx, DRV_INFO:0x%lx, SHIFT:0x%lx\n", \
prx_desc_status->RXBuffSize, prx_desc_status->FS, prx_desc_status->LS, \
prx_desc_status->PKT_LEN, prx_desc_status->DRV_INFO_SIZE, prx_desc_status->SHIFT));
#endif
}
_RXPKT_DUMP:
#if 0 // CFG_HAL_DBG
//RXBD
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("RXBD[%ld]:\nDword0=0x%lx, Dword1=0x%lx \n",
(u4Byte)cur_q->cur_host_idx,
(u4Byte)GET_DESC(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword0),
(u4Byte)GET_DESC(cur_q->pRXBD_head[cur_q->cur_host_idx].Dword1)
));
if ( prx_desc_status->FS==0x01 && prx_desc_status->LS==0x01 ) {
//RXDESC
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "RXDESC:(FS=1 & LS=1)\n", prx_desc, sizeof(RX_DESC_88XX));
//PHYStatus
// RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "PHYStatus:\n", ((pu1Byte)prx_desc + SIZE_RXDESC_88XX), prx_desc_status->DRV_INFO_SIZE + prx_desc_status->SHIFT);
//RXPkt
pFrame = (pu1Byte)prx_desc + SIZE_RXDESC_88XX + prx_desc_status->DRV_INFO_SIZE + prx_desc_status->SHIFT;
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "Payload:\n", pFrame, prx_desc_status->PKT_LEN);
#if 0
crc32 = 0;
SoftwareCRC32(pFrame, prx_desc_status->PKT_LEN - _CRCLNG_, &crc32);
if (HAL_memcmp(pFrame + prx_desc_status->PKT_LEN - _CRCLNG_, (PVOID)&crc32, _CRCLNG_)) {
RT_TRACE_F(COMP_RECV, DBG_WARNING, ("SW CRC32 error. 0x%lx\n", crc32));
} else {
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("SW CRC32 ok. 0x%lx\n", crc32) );
}
#endif
}
else if ( prx_desc_status->FS==0x01 && prx_desc_status->LS==0x0 ) {
//RXDESC
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "RXDESC:(FS=1 & LS=0)\n", prx_desc, sizeof(RX_DESC_88XX));
//PHYStatus
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "PHYStatus:\n", ((pu1Byte)prx_desc + SIZE_RXDESC_88XX), prx_desc_status->DRV_INFO_SIZE + prx_desc_status->SHIFT);
//Partial RXPkt
pFrame = (pu1Byte)prx_desc + SIZE_RXDESC_88XX + prx_desc_status->DRV_INFO_SIZE + prx_desc_status->SHIFT;
frameLen = prx_desc_status->RXBuffSize - SIZE_RXDESC_88XX - prx_desc_status->DRV_INFO_SIZE - prx_desc_status->SHIFT;
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "Payload:\n", pFrame, frameLen);
prx_desc_status->pktNum = 0;
prx_desc_status->pktBufAddr[prx_desc_status->pktNum] = pFrame;
prx_desc_status->pktBufLen[prx_desc_status->pktNum] = frameLen;
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("pktBufLen[0x%lx]:0x%lx,%d\n", \
prx_desc_status->pktNum, prx_desc_status->pktBufLen[prx_desc_status->pktNum], prx_desc_status->pktBufLen[prx_desc_status->pktNum]) );
prx_desc_status->pktNum++;
prx_desc_status->remaining_pkt_len = SIZE_RXDESC_88XX + prx_desc_status->DRV_INFO_SIZE + prx_desc_status->SHIFT + \
prx_desc_status->PKT_LEN - prx_desc_status->RXBuffSize;
}
else if ( prx_desc_status->FS==0x0 && prx_desc_status->LS==0x0 ) {
// No RXDESC
//Partial RXPkt
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "Payload:(FS=0 & LS=0)\n", (pu1Byte)pBufAddr, prx_desc_status->RXBuffSize);
prx_desc_status->pktBufAddr[prx_desc_status->pktNum] = pBufAddr;
prx_desc_status->pktBufLen[prx_desc_status->pktNum] = prx_desc_status->RXBuffSize;
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("pktBufLen[0x%lx]:0x%lx,%d\n", \
prx_desc_status->pktNum, prx_desc_status->pktBufLen[prx_desc_status->pktNum], prx_desc_status->pktBufLen[prx_desc_status->pktNum]) );
prx_desc_status->pktNum++;
prx_desc_status->remaining_pkt_len -= prx_desc_status->RXBuffSize;
}
else if ( prx_desc_status->FS==0x0 && prx_desc_status->LS==0x1 ) {
// No RXDESC
//Partial RXPkt
RT_PRINT_DATA(COMP_RECV, DBG_TRACE, "Payload:(FS=0 & LS=1)\n", (pu1Byte)pBufAddr, prx_desc_status->remaining_pkt_len);
prx_desc_status->pktBufAddr[prx_desc_status->pktNum] = pBufAddr;
prx_desc_status->pktBufLen[prx_desc_status->pktNum] = prx_desc_status->remaining_pkt_len;
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("pktBufLen[0x%lx]:0x%lx,%d\n", \
prx_desc_status->pktNum, prx_desc_status->pktBufLen[prx_desc_status->pktNum], prx_desc_status->pktBufLen[prx_desc_status->pktNum]) );
prx_desc_status->pktNum++;
crc32 = 0;
// for special case: CRC in last one and two packets...
if (prx_desc_status->pktBufLen[prx_desc_status->pktNum-1] < _CRCLNG_) {
prx_desc_status->pktBufLen[prx_desc_status->pktNum-2] = prx_desc_status->pktBufLen[prx_desc_status->pktNum-2] + prx_desc_status->pktBufLen[prx_desc_status->pktNum-1] - _CRCLNG_;
prx_desc_status->pktBufLen[prx_desc_status->pktNum-1] = 0;
bDivisionCRC = _TRUE;
printk("special case: CRC in last one and two packets.\n");
} else {
prx_desc_status->pktBufLen[prx_desc_status->pktNum-1] -= _CRCLNG_;
}
SoftwareCRC32_RXBuffGather(&(prx_desc_status->pktBufAddr[0]), &(prx_desc_status->pktBufLen[0]), prx_desc_status->pktNum, &crc32);
if (bDivisionCRC == _TRUE) {
while(cnt < (_CRCLNG_ - prx_desc_status->remaining_pkt_len)) {
tempByte = *((pu1Byte)prx_desc_status->pktBufAddr[prx_desc_status->pktNum-2] + \
prx_desc_status->pktBufLen[prx_desc_status->pktNum-2] + cnt);
HAL_memcpy((pu1Byte)&rx_crc32+shift, (pu1Byte)&tempByte, sizeof(tempByte));
cnt++;
shift++;
}
cnt = 0;
while(cnt < prx_desc_status->remaining_pkt_len) {
tempByte = *((pu1Byte)prx_desc_status->pktBufAddr[prx_desc_status->pktNum-1] + cnt);
HAL_memcpy((pu1Byte)&rx_crc32+shift, (pu1Byte)&tempByte, sizeof(tempByte));
cnt++;
shift++;
}
if ( HAL_memcmp( (PVOID)&rx_crc32, (PVOID)&crc32, _CRCLNG_) ) {
RT_TRACE_F(COMP_RECV, DBG_WARNING, ("SW CRC32 error in division case. 0x%lx\n", crc32));
} else {
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("SW CRC32 ok in division case. 0x%lx\n", crc32) );
}
} else {
if (HAL_memcmp(pBufAddr + prx_desc_status->remaining_pkt_len - _CRCLNG_, (PVOID)&crc32, _CRCLNG_)) {
RT_TRACE_F(COMP_RECV, DBG_WARNING, ("SW CRC32 error. 0x%lx\n", crc32));
} else {
RT_TRACE_F(COMP_RECV, DBG_TRACE, ("SW CRC32 ok. 0x%lx\n", crc32) );
}
}
}
#endif
if ( SUCCESS == bResult ) {
#ifdef TRXBD_CACHABLE_REGION
_dma_cache_inv((unsigned long)( (pBufAddr)-CONFIG_LUNA_SLAVE_PHYMEM_OFFSET),
sizeof(RX_DESC_88XX) + prx_desc_status->DRV_INFO_SIZE + prx_desc_status->SHIFT + prx_desc_status->PKT_LEN);
#endif
return RT_STATUS_SUCCESS;
}
else {
return RT_STATUS_FAILURE;
}
}
HAL_IMEM
u2Byte
UpdateRXBDHWIdx88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex //HCI_RX_DMA_QUEUE_88XX
)
{
PHCI_RX_DMA_MANAGER_88XX prx_dma;
PHCI_RX_DMA_QUEUE_STRUCT_88XX cur_q;
prx_dma = (PHCI_RX_DMA_MANAGER_88XX)(_GET_HAL_DATA(Adapter)->PRxDMA88XX);
cur_q = &(prx_dma->rx_queue[queueIndex]);
cur_q->hw_idx = HAL_RTL_R16(cur_q->reg_rwptr_idx + 2) & 0xFFF;
return cur_q->hw_idx;
}
HAL_IMEM
VOID
UpdateRXBDHostIdx88XX (
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX
IN u4Byte count
)
{
PHCI_RX_DMA_MANAGER_88XX prx_dma;
PHCI_RX_DMA_QUEUE_STRUCT_88XX cur_q;
prx_dma = (PHCI_RX_DMA_MANAGER_88XX)(_GET_HAL_DATA(Adapter)->PRxDMA88XX);
cur_q = &(prx_dma->rx_queue[queueIndex]);
if ( 0 != count ) {
cur_q->host_idx = (cur_q->host_idx + count) % cur_q->total_rxbd_num;
HAL_RTL_W16(cur_q->reg_rwptr_idx, (cur_q->host_idx & 0xFFF));
// RT_TRACE_F(COMP_RECV, DBG_TRACE, ("host_idx:0x%lx\n", cur_q->host_idx));
}
else {
// RT_TRACE_F(COMP_RECV, DBG_LOUD, ("count = 0\n"));
}
}
#endif // (HAL_DEV_BUS_TYPE & (HAL_RT_EMBEDDED_INTERFACE | HAL_RT_PCI_INTERFACE))

165
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXRxDesc.h Executable file
View File

@@ -0,0 +1,165 @@
#ifndef __HAL88XXRXDESC_H__
#define __HAL88XXRXDESC_H__
#if defined(_PC_) || defined(_PUMA6_)
#ifdef FS
#undef FS
#endif
#endif
typedef struct _RX_DESC_88XX_
{
volatile u4Byte Dword0;
volatile u4Byte Dword1;
volatile u4Byte Dword2;
volatile u4Byte Dword3;
volatile u4Byte Dword4;
volatile u4Byte Dword5;
} RX_DESC_88XX, *PRX_DESC_88XX;
#define SIZE_RXDESC_88XX 24
typedef enum _HCI_RX_DMA_QUEUE_88XX_
{
HCI_RX_DMA_QUEUE_Q0 = 0,
HCI_RX_DMA_QUEUE_MAX_NUM
} HCI_RX_DMA_QUEUE_88XX, *PHCI_RX_DMA_QUEUE_88XX;
typedef struct _RX_BUFFER_DESCRIPTOR_
{
u4Byte Dword0;
u4Byte Dword1;
#if TXBD_SEG_32_64_SEL
u4Byte Dword2;
u4Byte Dword3;
#endif
} RX_BUFFER_DESCRIPTOR, *PRX_BUFFER_DESCRIPTOR;
typedef struct _HCI_RX_DMA_QUEUE_STRUCT_88XX_
{
PRX_BUFFER_DESCRIPTOR pRXBD_head;
#ifdef CONFIG_NET_PCI
unsigned long rxbd_dma_addr;
#endif
u2Byte hw_idx; //Mapping to HW register
u2Byte host_idx; //Mapping to HW register
//Special case:
// If we can't allocate a new SKB(RXDESC+Payload) to mapping RXBD,
// we still need to maintain a pointer in order to recieve RxPkt continuously
u2Byte cur_host_idx; // the index to indicate the next location that we have received RxPkt
#if CFG_HAL_DELAY_REFILL_RX_BUF
u2Byte rxbd_ok_cnt;
#endif
u2Byte total_rxbd_num;
u2Byte avail_rxbd_num;
u4Byte reg_rwptr_idx;
#if RXBD_READY_CHECK_METHOD
// reset signal from 0x100[1], CR[HCI_RXDMA_EN]
u2Byte rxtag_seq_num;
#endif
} HCI_RX_DMA_QUEUE_STRUCT_88XX, *PHCI_RX_DMA_QUEUE_STRUCT_88XX;
typedef struct _HCI_RX_DMA_MANAGER_88XX_
{
HCI_RX_DMA_QUEUE_STRUCT_88XX rx_queue[HCI_RX_DMA_QUEUE_MAX_NUM];
} HCI_RX_DMA_MANAGER_88XX, *PHCI_RX_DMA_MANAGER_88XX;
typedef struct _RX_DESC_STATUS_88XX_
{
// RXBD
BOOLEAN FS;
BOOLEAN LS;
u2Byte RXBuffSize;
#if CFG_HAL_DBG
u2Byte remaining_pkt_len;
u4Byte pktBufAddr[32];
u2Byte pktBufLen[32];
u2Byte pktNum;
#endif
//4 Note: value below Only valid in FS=1
// Dword0
u2Byte PKT_LEN;
BOOLEAN CRC32;
BOOLEAN ICVERR;
u1Byte DRV_INFO_SIZE;
u1Byte SECURITY;
u1Byte SHIFT;
BOOLEAN PHYST;
BOOLEAN SWDEC;
BOOLEAN EOR;
// Dword 1
BOOLEAN PAGGR;
// Dword 2
BOOLEAN C2HPkt;
// Dowrd 3
u1Byte RX_RATE;
// Dword 4
BOOLEAN OFDM_SGI;
BOOLEAN CCK_SPLCP;
BOOLEAN LDPC;
BOOLEAN STBC;
BOOLEAN NOT_SOUNDING;
u1Byte BW;
#if CFG_HAL_HW_FILL_MACID
u1Byte rxMACID;
#endif
} RX_DESC_STATUS_88XX, *PRX_DESC_STATUS_88XX;
RT_STATUS
QueryRxDesc88XX (
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex,
IN pu1Byte pBufAddr,
OUT PVOID pRxDescStatus
);
RT_STATUS
UpdateRXBDInfo88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex, //HCI_RX_DMA_QUEUE_88XX
IN u2Byte rxbd_idx,
IN pu1Byte pBuf,
IN PVOID Callback, // callback function
IN BOOLEAN bInit
);
u2Byte
UpdateRXBDHWIdx88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex
);
VOID
UpdateRXBDHostIdx88XX (
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex, //HCI_TX_DMA_QUEUE_88XX
IN u4Byte Count
);
RT_STATUS
PrepareRXBD88XX(
IN HAL_PADAPTER Adapter,
IN u2Byte bufferLen,
IN PVOID Callback // callback function
);
void DumpRxBDesc88XX(
IN HAL_PADAPTER Adapter,
#ifdef CONFIG_RTL_PROC_NEW
IN struct seq_file *s,
#endif
IN u4Byte q_num
);
#endif //#ifndef __HAL88XXRXDESC_H__

2239
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXTxDesc.c Executable file
View File

File diff suppressed because it is too large Load Diff

333
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXTxDesc.h Executable file
View File

@@ -0,0 +1,333 @@
#ifndef __HAL88XX_TXDESC_H__
#define __HAL88XX_TXDESC_H__
typedef struct _TX_DESC_88XX_
{
volatile u4Byte Dword0;
volatile u4Byte Dword1;
volatile u4Byte Dword2;
volatile u4Byte Dword3;
volatile u4Byte Dword4;
volatile u4Byte Dword5;
volatile u4Byte Dword6;
volatile u4Byte Dword7;
volatile u4Byte Dword8;
volatile u4Byte Dword9;
} TX_DESC_88XX, *PTX_DESC_88XX;
#define SIZE_TXDESC_88XX 40
typedef enum _HCI_TX_DMA_QUEUE_88XX_
{
//MGT
HCI_TX_DMA_QUEUE_MGT = 0,
//QoS
HCI_TX_DMA_QUEUE_BK,
HCI_TX_DMA_QUEUE_BE,
HCI_TX_DMA_QUEUE_VI,
HCI_TX_DMA_QUEUE_VO,
//HI
HCI_TX_DMA_QUEUE_HI0,
HCI_TX_DMA_QUEUE_HI1,
HCI_TX_DMA_QUEUE_HI2,
HCI_TX_DMA_QUEUE_HI3,
HCI_TX_DMA_QUEUE_HI4,
HCI_TX_DMA_QUEUE_HI5,
HCI_TX_DMA_QUEUE_HI6,
HCI_TX_DMA_QUEUE_HI7,
// Beacon
HCI_TX_DMA_QUEUE_BCN,
HCI_TX_DMA_QUEUE_MAX_NUM //14
} HCI_TX_DMA_QUEUE_88XX, *PHCI_TX_DMA_QUEUE_88XX;
#if 0
// TODO: endian....
#ifdef _BIG_ENDIAN_
typedef struct _TXBD_ELEMENT_DW0_
{
u4Byte Rsvd_31 :1;
u4Byte PsbLen :15;
u4Byte Rsvd_14_15 :2;
u4Byte Len :14;
} TXBD_ELEMENT_DW0,*PTXBD_ELEMENT_DW0;
typedef struct _TXBD_ELEMENT_DW_
{
u4Byte AmpduEn :1;
u4Byte Rsvd16To30 :15;
u4Byte Len :16;
} TXBD_ELEMENT_DW,*PTXBD_ELEMENT_DW;
#else // _LITTLE_ENDIAN_
typedef struct _TXBD_ELEMENT_DW0_
{
u4Byte Len :14;
u4Byte Rsvd_14_15 :2;
u4Byte PsbLen :15;
u4Byte Rsvd_31 :1;
} TXBD_ELEMENT_DW0,*PTXBD_ELEMENT_DW0;
typedef struct _TXBD_ELEMENT_DW_
{
u4Byte Len :16;
u4Byte Rsvd16To30 :15;
u4Byte AmpduEn :1;
} TXBD_ELEMENT_DW,*PTXBD_ELEMENT_DW;
#endif
#endif
typedef struct _TXBD_ELEMENT_
{
u4Byte Dword0;
u4Byte Dword1;
#if TXBD_SEG_32_64_SEL
u4Byte Dword2;
u4Byte Dword3;
#endif //TXBD_SEG_32_64_SEL
} TXBD_ELEMENT,*PTXBD_ELEMENT;
typedef struct _TX_BUFFER_DESCRIPTOR_
{
TXBD_ELEMENT TXBD_ELE[TXBD_ELE_NUM];
} TX_BUFFER_DESCRIPTOR, *PTX_BUFFER_DESCRIPTOR;
typedef struct _HCI_TX_DMA_QUEUE_STRUCT_88XX_
{
//TXBD
PTX_BUFFER_DESCRIPTOR pTXBD_head;
//TXBD Queue management
u2Byte hw_idx;
u2Byte host_idx;
//Two Method:
// 1.) TXDESC Only
// 2.) TXDESC + Payload
PVOID ptx_desc_head;
u2Byte total_txbd_num;
u2Byte avail_txbd_num;
// RWPtr IDX Reg
u4Byte reg_rwptr_idx;
} HCI_TX_DMA_QUEUE_STRUCT_88XX, *PHCI_TX_DMA_QUEUE_STRUCT_88XX;
typedef struct _HCI_TX_DMA_MANAGER_88XX_
{
HCI_TX_DMA_QUEUE_STRUCT_88XX tx_queue[HCI_TX_DMA_QUEUE_MAX_NUM];
} HCI_TX_DMA_MANAGER_88XX, *PHCI_TX_DMA_MANAGER_88XX;
//typedef struct _TXBD_INFO_
//{
// u4Byte Length;
// u4Byte AddrLow;
//} TXBD_INFO_88XX, *PTXBD_INFO_88XX;
typedef struct _TX_DESC_DATA_88XX_
{
// header
pu1Byte pHdr;
u4Byte hdrLen;
u4Byte llcLen;
// frame
pu1Byte pBuf;
u4Byte frLen;
// encryption
pu1Byte pMic;
pu1Byte pIcv;
// TXDESC Dword 1
u4Byte rateId;
u1Byte macId;
u1Byte tid;
BOOLEAN moreData;
// TXDESC Dword 2
BOOLEAN aggEn;
u1Byte ampduDensity;
BOOLEAN frag;
BOOLEAN bk;
u4Byte p_aid;
BOOLEAN g_id;
#if CFG_HAL_HW_AES_IV
BOOLEAN hwAESIv;
#endif
// TXDESC Dword 3
BOOLEAN RTSEn;
BOOLEAN HWRTSEn;
BOOLEAN CTS2Self;
BOOLEAN useRate;
BOOLEAN disRTSFB;
BOOLEAN disDataFB;
u1Byte maxAggNum;
BOOLEAN navUseHdr;
BOOLEAN ndpa;
// TXDESC Dword 4
u1Byte RTSRate;
u1Byte RTSRateFBLmt;
u1Byte dataRate;
BOOLEAN rtyLmtEn;
u1Byte dataRtyLmt;
u1Byte dataRateFBLmt;
// TXDESC Dword 5
u1Byte dataBW;
u1Byte dataSC;
u1Byte RTSSC;
u1Byte dataStbc;
u1Byte dataLdpc;
u1Byte dataShort;
u1Byte RTSShort;
u1Byte TXPowerOffset;
u1Byte TXAnt;
#if (CFG_HAL_HW_TX_SHORTCUT_REUSE_TXDESC || CFG_HAL_HW_TX_SHORTCUT_HDR_CONV)
// TXDESC Dword 8
BOOLEAN smhEn;
BOOLEAN stwEn;
BOOLEAN stwAntDis;
BOOLEAN stwRateDis;
BOOLEAN stwRbDis;
BOOLEAN stwPktReDis;
BOOLEAN macCp;
BOOLEAN txwifiCp;
#endif
// encrypt
u4Byte iv;
u4Byte icv;
u4Byte mic;
u4Byte secType;
BOOLEAN swCrypt;
} TX_DESC_DATA_88XX, *PTX_DESC_DATA_88XX;
VOID
TxPolling88XX(
IN HAL_PADAPTER Adapter,
IN u1Byte QueueIndex
);
VOID
SigninBeaconTXBD88XX
(
IN HAL_PADAPTER Adapter,
IN pu4Byte beaconbuf,
IN u2Byte frlen
);
VOID
SetBeaconDownload88XX (
IN HAL_PADAPTER Adapter,
IN u4Byte Value
);
u2Byte
GetTxQueueHWIdx88XX
(
IN HAL_PADAPTER Adapter,
IN u4Byte q_num //enum _TX_QUEUE_
);
BOOLEAN
FillTxHwCtrl88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex, //HCI_TX_DMA_QUEUE_88XX
IN PVOID pDescData
);
RT_STATUS
SyncSWTXBDHostIdxToHW88XX (
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex //HCI_TX_DMA_QUEUE_88XX
);
BOOLEAN
QueryTxConditionMatch88XX(
IN HAL_PADAPTER Adapter
);
RT_STATUS
PrepareTXBD88XX(
IN HAL_PADAPTER Adapter
);
VOID
FillBeaconDesc88XX
(
IN HAL_PADAPTER Adapter,
IN PVOID _pdesc,
IN PVOID data_content,
IN u2Byte txLength,
IN BOOLEAN bForceUpdate
);
VOID
GetBeaconTXBDTXDESC88XX(
IN HAL_PADAPTER Adapter,
OUT PTX_BUFFER_DESCRIPTOR *pTXBD,
OUT PTX_DESC_88XX *ptx_desc
);
#if CFG_HAL_TX_SHORTCUT
#if 0
PVOID
GetShortCutTxDesc88XX(
IN HAL_PADAPTER Adapter
);
VOID
ReleaseShortCutTxDesc88XX(
IN HAL_PADAPTER Adapter,
IN PVOID pTxDesc
);
#endif
VOID
SetShortCutTxBuffSize88XX(
IN HAL_PADAPTER Adapter,
IN PVOID pTxDesc,
IN u2Byte txPktSize
);
u2Byte
GetShortCutTxBuffSize88XX(
IN HAL_PADAPTER Adapter,
IN PVOID pTxDesc
);
PVOID
CopyShortCutTxDesc88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex, //HCI_TX_DMA_QUEUE_88XX
IN PVOID pTxDesc,
IN u4Byte direction
);
BOOLEAN
FillShortCutTxHwCtrl88XX(
IN HAL_PADAPTER Adapter,
IN u4Byte queueIndex, //HCI_TX_DMA_QUEUE_88XX
IN PVOID pDescData,
IN PVOID pTxDesc,
IN u4Byte direction
);
#endif // CFG_HAL_TX_SHORTCUT
void DumpTxBDesc88XX(
IN HAL_PADAPTER Adapter,
#ifdef CONFIG_RTL_PROC_NEW
IN struct seq_file *s,
#endif
IN u4Byte q_num
);
#endif //#ifndef __HAL88XX_TXDESC_H__

0
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXVerify.c Executable file
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0
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/Hal88XXVerify.h Executable file
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141
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/RTL8192E/Hal8192EDef.h Executable file
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#ifndef __HAL8192E_DEF_H__
#define __HAL8192E_DEF_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal8192EDef.h
Abstract:
Defined HAL 8192E data structure & Define
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-04-16 Filen Create.
--*/
extern u1Byte *data_AGC_TAB_8192E_start, *data_AGC_TAB_8192E_end;
extern u1Byte *data_MAC_REG_8192E_start, *data_MAC_REG_8192E_end;
extern u1Byte *data_PHY_REG_8192E_start, *data_PHY_REG_8192E_end;
//extern u1Byte *data_PHY_REG_1T_8192E_start, *data_PHY_REG_1T_8192E_end;
extern u1Byte *data_PHY_REG_MP_8192E_start, *data_PHY_REG_MP_8192E_end;
#ifdef TXPWR_LMT_92EE
extern u1Byte *data_PHY_REG_PG_8192E_new_start, *data_PHY_REG_PG_8192E_new_end;
#endif
extern u1Byte *data_PHY_REG_PG_8192E_start, *data_PHY_REG_PG_8192E_end;
extern u1Byte *data_RadioA_8192E_start, *data_RadioA_8192E_end;
extern u1Byte *data_RadioB_8192E_start, *data_RadioB_8192E_end;
//High Power
#if CFG_HAL_HIGH_POWER_EXT_PA
#ifdef PWR_BY_RATE_92E_HP
extern u1Byte *data_PHY_REG_PG_8192Emp_hp_start, *data_PHY_REG_PG_8192Emp_hp_end;
#endif
#if CFG_HAL_HIGH_POWER_EXT_LNA
#if IS_EXIST_PCI
extern u1Byte *data_AGC_TAB_8192E_hp_start, *data_AGC_TAB_8192E_hp_end;
extern u1Byte *data_PHY_REG_8192E_hp_start, *data_PHY_REG_8192E_hp_end;
extern u1Byte *data_RadioA_8192E_hp_start, *data_RadioA_8192E_hp_end;
extern u1Byte *data_RadioB_8192E_hp_start, *data_RadioB_8192E_hp_end;
#endif
#if IS_EXIST_SDIO
extern u1Byte *data_AGC_TAB_8192ES_hp_start, *data_AGC_TAB_8192ES_hp_end;
extern u1Byte *data_PHY_REG_8192ES_hp_start, *data_PHY_REG_8192ES_hp_end;
extern u1Byte *data_RadioA_8192ES_hp_start, *data_RadioA_8192ES_hp_end;
extern u1Byte *data_RadioB_8192ES_hp_start, *data_RadioB_8192ES_hp_end;
#endif
#endif
extern u1Byte *data_AGC_TAB_8192E_extpa_start, *data_AGC_TAB_8192E_extpa_end;
extern u1Byte *data_PHY_REG_8192E_extpa_start, *data_PHY_REG_8192E_extpa_end;
extern u1Byte *data_RadioA_8192E_extpa_start, *data_RadioA_8192E_extpa_end;
extern u1Byte *data_RadioB_8192E_extpa_start, *data_RadioB_8192E_extpa_end;
#endif
#if CFG_HAL_HIGH_POWER_EXT_LNA
#if IS_EXIST_PCI
extern u1Byte *data_AGC_TAB_8192E_extlna_start, *data_AGC_TAB_8192E_extlna_end;
extern u1Byte *data_PHY_REG_8192E_extlna_start, *data_PHY_REG_8192E_extlna_end;
extern u1Byte *data_RadioA_8192E_extlna_start, *data_RadioA_8192E_extlna_end;
extern u1Byte *data_RadioB_8192E_extlna_start, *data_RadioB_8192E_extlna_end;
#endif
#if IS_EXIST_SDIO
extern u1Byte *data_AGC_TAB_8192ES_extlna_start, *data_AGC_TAB_8192ES_extlna_end;
extern u1Byte *data_PHY_REG_8192ES_extlna_start, *data_PHY_REG_8192ES_extlna_end;
extern u1Byte *data_RadioA_8192ES_extlna_start, *data_RadioA_8192ES_extlna_end;
extern u1Byte *data_RadioB_8192ES_extlna_start, *data_RadioB_8192ES_extlna_end;
#endif
#endif
// B-cut support
extern u1Byte *data_MAC_REG_8192Eb_start, *data_MAC_REG_8192Eb_end;
extern u1Byte *data_PHY_REG_8192Eb_start, *data_PHY_REG_8192Eb_end;
#if IS_EXIST_PCI
extern u1Byte *data_RadioA_8192Eb_start, *data_RadioA_8192Eb_end;
extern u1Byte *data_RadioB_8192Eb_start, *data_RadioB_8192Eb_end;
#endif
// MP chip
#if IS_EXIST_PCI
extern u1Byte *data_AGC_TAB_8192Emp_start, *data_AGC_TAB_8192Emp_end;
extern u1Byte *data_RadioA_8192Emp_start, *data_RadioA_8192Emp_end;
extern u1Byte *data_RadioB_8192Emp_start, *data_RadioB_8192Emp_end;
extern u1Byte *data_RadioA_8192EmpA_start, *data_RadioA_8192EmpA_end;
extern u1Byte *data_RadioB_8192EmpA_start, *data_RadioB_8192EmpA_end;
#endif
#if IS_EXIST_SDIO
extern u1Byte *data_AGC_TAB_8192ES_start, *data_AGC_TAB_8192ES_end;
extern u1Byte *data_RadioA_8192ES_start, *data_RadioA_8192ES_end;
extern u1Byte *data_RadioB_8192ES_start, *data_RadioB_8192ES_end;
#endif
extern u1Byte *data_PHY_REG_MP_8192Emp_start, *data_PHY_REG_MP_8192Emp_end;
extern u1Byte *data_PHY_REG_PG_8192Emp_start, *data_PHY_REG_PG_8192Emp_end;
extern u1Byte *data_MAC_REG_8192Emp_start, *data_MAC_REG_8192Emp_end;
extern u1Byte *data_PHY_REG_8192Emp_start, *data_PHY_REG_8192Emp_end;
// FW
extern u1Byte *data_rtl8192Efw_start, *data_rtl8192Efw_end;
extern u1Byte *data_rtl8192EfwMP_start, *data_rtl8192EfwMP_end;
// Power Tracking
extern u1Byte *data_TxPowerTrack_AP_start, *data_TxPowerTrack_AP_end;
#ifdef TXPWR_LMT_92EE
extern unsigned char *data_TXPWR_LMT_92EE_new_start, *data_TXPWR_LMT_92EE_new_end;
#ifdef PWR_BY_RATE_92E_HP
#if CFG_HAL_HIGH_POWER_EXT_PA
extern unsigned char *data_TXPWR_LMT_92EE_hp_start, *data_TXPWR_LMT_92EE_hp_end;
#endif
#endif
#endif
//3 MACDM
//default
extern u1Byte *data_MACDM_def_high_8192E_start, *data_MACDM_def_high_8192E_end;
extern u1Byte *data_MACDM_def_low_8192E_start, *data_MACDM_def_low_8192E_end;
extern u1Byte *data_MACDM_def_normal_8192E_start, *data_MACDM_def_normal_8192E_end;
//general
extern u1Byte *data_MACDM_gen_high_8192E_start, *data_MACDM_gen_high_8192E_end;
extern u1Byte *data_MACDM_gen_low_8192E_start, *data_MACDM_gen_low_8192E_end;
extern u1Byte *data_MACDM_gen_normal_8192E_start, *data_MACDM_gen_normal_8192E_end;
//txop
extern u1Byte *data_MACDM_txop_high_8192E_start, *data_MACDM_txop_high_8192E_end;
extern u1Byte *data_MACDM_txop_low_8192E_start, *data_MACDM_txop_low_8192E_end;
extern u1Byte *data_MACDM_txop_normal_8192E_start, *data_MACDM_txop_normal_8192E_end;
//criteria
extern u1Byte *data_MACDM_state_criteria_8192E_start, *data_MACDM_state_criteria_8192E_end;
#endif //__HAL8192E_DEF_H__

240
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/RTL8192E/Hal8192EGen.c Executable file
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/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal8192EGen.c
Abstract:
Defined RTL8192E HAL Function
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-04-16 Filen Create.
--*/
#include "../../HalPrecomp.h"
#include "../../../data_AGC_TAB_8192E.c"
#include "../../../data_MAC_REG_8192E.c"
#include "../../../data_PHY_REG_8192E.c"
//#include "../../../data_PHY_REG_1T_8192E.c"
#include "../../../data_PHY_REG_MP_8192E.c"
#include "../../../data_PHY_REG_PG_8192E.c"
#ifdef TXPWR_LMT_92EE
#include "../../../data_PHY_REG_PG_8192E_new.c"
#endif
#include "../../../data_RadioA_8192E.c"
#include "../../../data_RadioB_8192E.c"
#include "../../../data_rtl8192Efw.c"
//#include "data_RTL8192EFW_Test_T.c"
// High Power
#if CFG_HAL_HIGH_POWER_EXT_PA
#ifdef PWR_BY_RATE_92E_HP
#include "../../../data_PHY_REG_PG_8192Emp_hp.c"
#endif
#if CFG_HAL_HIGH_POWER_EXT_LNA
#if IS_EXIST_PCI
#include "../../../data_AGC_TAB_8192E_hp.c"
#include "../../../data_PHY_REG_8192E_hp.c"
#include "../../../data_RadioA_8192E_hp.c"
#include "../../../data_RadioB_8192E_hp.c"
#endif
#if IS_EXIST_SDIO
#include "../../../data_AGC_TAB_8192ES_hp.c"
#include "../../../data_PHY_REG_8192ES_hp.c"
#include "../../../data_RadioA_8192ES_hp.c"
#include "../../../data_RadioB_8192ES_hp.c"
#endif
#endif
#include "../../../data_AGC_TAB_8192E_extpa.c"
#include "../../../data_PHY_REG_8192E_extpa.c"
#include "../../../data_RadioA_8192E_extpa.c"
#include "../../../data_RadioB_8192E_extpa.c"
#endif
#if CFG_HAL_HIGH_POWER_EXT_LNA
#if IS_EXIST_PCI
#include "../../../data_AGC_TAB_8192E_extlna.c"
#include "../../../data_PHY_REG_8192E_extlna.c"
#include "../../../data_RadioA_8192E_extlna.c"
#include "../../../data_RadioB_8192E_extlna.c"
#endif
#if IS_EXIST_SDIO
#include "../../../data_AGC_TAB_8192ES_extlna.c"
#include "../../../data_PHY_REG_8192ES_extlna.c"
#include "../../../data_RadioA_8192ES_extlna.c"
#include "../../../data_RadioB_8192ES_extlna.c"
#endif
#endif
// B-cut
#include "../../../data_MAC_REG_8192Eb.c"
#include "../../../data_PHY_REG_8192Eb.c"
#if IS_EXIST_PCI
#include "../../../data_RadioA_8192Eb.c"
#include "../../../data_RadioB_8192Eb.c"
#endif
//
// MP
#if IS_EXIST_PCI
#include "../../../data_AGC_TAB_8192Emp.c"
#include "../../../data_RadioA_8192Emp.c"
#include "../../../data_RadioB_8192Emp.c"
#include "../../../data_RadioA_8192EmpA.c"
#include "../../../data_RadioB_8192EmpA.c"
#endif
#if IS_EXIST_SDIO
#include "../../../data_AGC_TAB_8192ES.c"
#include "../../../data_RadioA_8192ES.c"
#include "../../../data_RadioB_8192ES.c"
#endif
#include "../../../data_MAC_REG_8192Emp.c"
#include "../../../data_PHY_REG_8192Emp.c"
#include "../../../data_PHY_REG_MP_8192Emp.c"
#include "../../../data_PHY_REG_PG_8192Emp.c"
#include "../../../data_rtl8192EfwMP.c"
// Power Tracking
#include "../../../data_TxPowerTrack_AP.c"
//3 MACDM
//default
#include "../../../data_MACDM_def_high_8192E.c"
#include "../../../data_MACDM_def_low_8192E.c"
#include "../../../data_MACDM_def_normal_8192E.c"
//general
#include "../../../data_MACDM_gen_high_8192E.c"
#include "../../../data_MACDM_gen_low_8192E.c"
#include "../../../data_MACDM_gen_normal_8192E.c"
//txop
#include "../../../data_MACDM_txop_high_8192E.c"
#include "../../../data_MACDM_txop_low_8192E.c"
#include "../../../data_MACDM_txop_normal_8192E.c"
//criteria
#include "../../../data_MACDM_state_criteria_8192E.c"
#define VAR_MAPPING(dst,src) \
u1Byte *data_##dst##_start = &data_##src[0]; \
u1Byte *data_##dst##_end = &data_##src[sizeof(data_##src)];
VAR_MAPPING(AGC_TAB_8192E, AGC_TAB_8192E);
VAR_MAPPING(MAC_REG_8192E, MAC_REG_8192E);
VAR_MAPPING(PHY_REG_8192E, PHY_REG_8192E);
//VAR_MAPPING(PHY_REG_1T_8192E, PHY_REG_1T_8192E);
VAR_MAPPING(PHY_REG_PG_8192E, PHY_REG_PG_8192E);
VAR_MAPPING(PHY_REG_MP_8192E, PHY_REG_MP_8192E);
VAR_MAPPING(RadioA_8192E, RadioA_8192E);
VAR_MAPPING(RadioB_8192E, RadioB_8192E);
VAR_MAPPING(rtl8192Efw, rtl8192Efw);
#ifdef TXPWR_LMT_92EE
VAR_MAPPING(PHY_REG_PG_8192E_new, PHY_REG_PG_8192E_new);
#endif
// High Power
#if CFG_HAL_HIGH_POWER_EXT_PA
#ifdef PWR_BY_RATE_92E_HP
VAR_MAPPING(PHY_REG_PG_8192Emp_hp, PHY_REG_PG_8192Emp_hp);
#endif
#if CFG_HAL_HIGH_POWER_EXT_LNA
#if IS_EXIST_PCI
VAR_MAPPING(AGC_TAB_8192E_hp, AGC_TAB_8192E_hp);
VAR_MAPPING(PHY_REG_8192E_hp, PHY_REG_8192E_hp);
VAR_MAPPING(RadioA_8192E_hp, RadioA_8192E_hp);
VAR_MAPPING(RadioB_8192E_hp, RadioB_8192E_hp);
#endif
#if IS_EXIST_SDIO
VAR_MAPPING(AGC_TAB_8192ES_hp, AGC_TAB_8192ES_hp);
VAR_MAPPING(PHY_REG_8192ES_hp, PHY_REG_8192ES_hp);
VAR_MAPPING(RadioA_8192ES_hp, RadioA_8192ES_hp);
VAR_MAPPING(RadioB_8192ES_hp, RadioB_8192ES_hp);
#endif
#endif
VAR_MAPPING(AGC_TAB_8192E_extpa, AGC_TAB_8192E_extpa);
VAR_MAPPING(PHY_REG_8192E_extpa, PHY_REG_8192E_extpa);
VAR_MAPPING(RadioA_8192E_extpa, RadioA_8192E_extpa);
VAR_MAPPING(RadioB_8192E_extpa, RadioB_8192E_extpa);
#endif
#if CFG_HAL_HIGH_POWER_EXT_LNA
#if IS_EXIST_PCI
VAR_MAPPING(AGC_TAB_8192E_extlna, AGC_TAB_8192E_extlna);
VAR_MAPPING(PHY_REG_8192E_extlna, PHY_REG_8192E_extlna);
VAR_MAPPING(RadioA_8192E_extlna, RadioA_8192E_extlna);
VAR_MAPPING(RadioB_8192E_extlna, RadioB_8192E_extlna);
#endif
#if IS_EXIST_SDIO
VAR_MAPPING(AGC_TAB_8192ES_extlna, AGC_TAB_8192ES_extlna);
VAR_MAPPING(PHY_REG_8192ES_extlna, PHY_REG_8192ES_extlna);
VAR_MAPPING(RadioA_8192ES_extlna, RadioA_8192ES_extlna);
VAR_MAPPING(RadioB_8192ES_extlna, RadioB_8192ES_extlna);
#endif
#endif
// B-cut
VAR_MAPPING(MAC_REG_8192Eb, MAC_REG_8192Eb);
VAR_MAPPING(PHY_REG_8192Eb, PHY_REG_8192Eb);
#if IS_EXIST_PCI
VAR_MAPPING(RadioA_8192Eb, RadioA_8192Eb);
VAR_MAPPING(RadioB_8192Eb, RadioB_8192Eb);
#endif
// MP
#if IS_EXIST_PCI
VAR_MAPPING(AGC_TAB_8192Emp, AGC_TAB_8192Emp);
VAR_MAPPING(RadioA_8192Emp, RadioA_8192Emp);
VAR_MAPPING(RadioB_8192Emp, RadioB_8192Emp);
VAR_MAPPING(RadioA_8192EmpA, RadioA_8192EmpA);
VAR_MAPPING(RadioB_8192EmpA, RadioB_8192EmpA);
#endif
#if IS_EXIST_SDIO
VAR_MAPPING(AGC_TAB_8192ES, AGC_TAB_8192ES);
VAR_MAPPING(RadioA_8192ES, RadioA_8192ES);
VAR_MAPPING(RadioB_8192ES, RadioB_8192ES);
#endif
VAR_MAPPING(MAC_REG_8192Emp, MAC_REG_8192Emp);
VAR_MAPPING(PHY_REG_8192Emp, PHY_REG_8192Emp);
VAR_MAPPING(PHY_REG_PG_8192Emp, PHY_REG_PG_8192Emp);
VAR_MAPPING(PHY_REG_MP_8192Emp, PHY_REG_MP_8192Emp);
VAR_MAPPING(rtl8192EfwMP, rtl8192EfwMP);
// Power Tracking
VAR_MAPPING(TxPowerTrack_AP, TxPowerTrack_AP);
#ifdef TXPWR_LMT_92EE
#include "../../../data_TXPWR_LMT_92EE_new.c"
VAR_MAPPING(TXPWR_LMT_92EE_new,TXPWR_LMT_92EE_new);
#ifdef PWR_BY_RATE_92E_HP
#if CFG_HAL_HIGH_POWER_EXT_PA
#include "../../../data_TXPWR_LMT_92EE_hp.c"
VAR_MAPPING(TXPWR_LMT_92EE_hp,TXPWR_LMT_92EE_hp);
#endif
#endif
#endif
//3 MACDM
VAR_MAPPING(MACDM_def_high_8192E, MACDM_def_high_8192E);
VAR_MAPPING(MACDM_def_low_8192E, MACDM_def_low_8192E);
VAR_MAPPING(MACDM_def_normal_8192E, MACDM_def_normal_8192E);
VAR_MAPPING(MACDM_gen_high_8192E, MACDM_gen_high_8192E);
VAR_MAPPING(MACDM_gen_low_8192E, MACDM_gen_low_8192E);
VAR_MAPPING(MACDM_gen_normal_8192E, MACDM_gen_normal_8192E);
VAR_MAPPING(MACDM_txop_high_8192E, MACDM_txop_high_8192E);
VAR_MAPPING(MACDM_txop_low_8192E, MACDM_txop_low_8192E);
VAR_MAPPING(MACDM_txop_normal_8192E, MACDM_txop_normal_8192E);
VAR_MAPPING(MACDM_state_criteria_8192E, MACDM_state_criteria_8192E);

19
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.c Executable file
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@@ -0,0 +1,19 @@
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal8192EPhyCfg.c
Abstract:
Defined HAL 92E PHY BB setting functions
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-11-22 Eric Create.
--*/

23
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.h Executable file
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@@ -0,0 +1,23 @@
#ifndef __HAL8192EPHYCFG_H__
#define __HAL8192EPHYCFG_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal8192EPhyCfg.h
Abstract:
Defined HAL 92E PHY BB setting functions
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-11-22 Eric Create.
--*/
#endif //__HAL8192EPHYCFG_H__

97
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.c Executable file
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@@ -0,0 +1,97 @@
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal8192EAPwrSeqCmd.c
Abstract:
This file includes all kinds of Power Action event for RTL8192E and
corresponding hardware configurtions which are released from HW SD.
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-04-16 Filen Create.
--*/
#include "../../HalPrecomp.h"
/*
* drivers should parse below arrays and do the corresponding actions
*/
/* Power on Array */
WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192E_TRANS_END_STEPS]=
{
RTL8192E_TRANS_CARDEMU_TO_ACT
RTL8192E_TRANS_END
};
/* Radio off Array */
WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_END_STEPS]=
{
RTL8192E_TRANS_ACT_TO_CARDEMU
RTL8192E_TRANS_END
};
/* Card Disable Array */
WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]=
{
RTL8192E_TRANS_ACT_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_CARDDIS
RTL8192E_TRANS_END
};
/* Card Enable Array */
WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]=
{
RTL8192E_TRANS_CARDDIS_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_ACT
RTL8192E_TRANS_END
};
/* Suspend Array */
WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192E_TRANS_END_STEPS]=
{
RTL8192E_TRANS_ACT_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_SUS
RTL8192E_TRANS_END
};
/* Resume Array */
WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192E_TRANS_END_STEPS]=
{
RTL8192E_TRANS_SUS_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_ACT
RTL8192E_TRANS_END
};
/* HWPDN Array */
WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS]=
{
RTL8192E_TRANS_ACT_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_PDN
RTL8192E_TRANS_END
};
/* Enter LPS */
WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS+RTL8192E_TRANS_END_STEPS]=
{
//FW behavior
RTL8192E_TRANS_ACT_TO_LPS
RTL8192E_TRANS_END
};
/* Leave LPS */
WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS+RTL8192E_TRANS_END_STEPS]=
{
//FW behavior
RTL8192E_TRANS_LPS_TO_ACT
RTL8192E_TRANS_END
};

211
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.h Executable file
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#ifndef REALTEK_POWER_SEQUENCE_8192E
#define REALTEK_POWER_SEQUENCE_8192E
/*
Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 20
#define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8192E_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8192E_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8192E_TRANS_END_STEPS 1
#define RTL8192E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
/*{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3A},*/ /*0x7A = 0x3A start BT*/\
#define RTL8192E_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},*/ /*0x04[9] = 1 turn off MAC by HW state machine*/ \
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0},*/ /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x23}, \
{0x0009, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x30}, \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x53}, \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xb2}, \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xc0}, \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x71}, \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
#define RTL8192E_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8192E_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#ifndef NOT_RTK_BSP
#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x90[24] = 1*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[24] = 1*/ \
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#else
#ifdef DONT_DISABLE_XTAL_ON_CLOSE
#define PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x90[24] = 1*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[24] = 1*/
#else
#define PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE
#endif
#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
PWRSEQ_DONT_DISABLE_XTAL_ON_CLOSE \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
/* {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},*/ /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
/* {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},*/ /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#endif
#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8192E_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8192E_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8192E_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
/*{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},*//*Reset MAC TRX*/ \
/*{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},*//*check if removed later*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, \
{0x0102, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, \
{0x0103, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8192E_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8192E_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/\
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS+RTL8192E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS+RTL8192E_TRANS_END_STEPS];
#endif

119
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/RTL8192E/RTL8192ES/Hal8192ESDef.h Executable file
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@@ -0,0 +1,119 @@
#ifndef __HAL8192EE_DEF_H__
#define __HAL8192EE_DEF_H__
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal8192EEDef.h
Abstract:
Defined HAL 8192EE data structure & Define
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-03-23 Filen Create.
--*/
/*
RT_STATUS
InitPON8192EE(
IN HAL_PADAPTER Adapter,
IN u4Byte ClkSel
);
RT_STATUS
StopHW8192EE(
IN HAL_PADAPTER Adapter
);
RT_STATUS
hal_Associate_8192EE(
HAL_PADAPTER Adapter,
BOOLEAN IsDefaultAdapter
);
*/
struct _RT_BEAMFORMING_INFO;
VOID
SetBeamformRfMode92E(
struct rtl8192cd_priv *priv,
struct _RT_BEAMFORMING_INFO *pBeamformingInfo
);
VOID
SetBeamformEnter92E(
struct rtl8192cd_priv *priv,
u1Byte Idx
);
VOID
SetBeamformLeave92E(
struct rtl8192cd_priv *priv,
u1Byte Idx
);
VOID
SetBeamformStatus92E(
struct rtl8192cd_priv *priv,
u1Byte Idx
);
VOID
Beamforming_NDPARate_92E(
struct rtl8192cd_priv *priv,
BOOLEAN Mode,
u1Byte BW,
u1Byte Rate
);
VOID
C2HTxBeamformingHandler_92E(
struct rtl8192cd_priv *priv,
pu1Byte CmdBuf,
u1Byte CmdLen
);
VOID
_C2HContentParsing92E(
struct rtl8192cd_priv *priv,
u1Byte c2hCmdId,
u1Byte c2hCmdLen,
pu1Byte tmpBuf
);
VOID
C2HPacketHandler_92E(
struct rtl8192cd_priv *priv,
pu1Byte Buffer,
u1Byte Length
);
VOID HW_VAR_HW_REG_TIMER_START_92E(
struct rtl8192cd_priv *priv
);
VOID HW_VAR_HW_REG_TIMER_INIT_92E(
struct rtl8192cd_priv *priv,
u2Byte t
);
VOID HW_VAR_HW_REG_TIMER_STOP_92E(
struct rtl8192cd_priv *priv
);
RT_STATUS
hal_Associate_8192ES(
struct rtl8192cd_priv *priv,
BOOLEAN IsDefaultAdapter
);
#endif //__HAL8192EE_DEF_H__

910
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/RTL88XX/RTL8192E/RTL8192ES/Hal8192ESGen.c Executable file
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@@ -0,0 +1,910 @@
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal88XXGen.c
Abstract:
Defined RTL8192EE HAL Function
Major Change History:
When Who What
---------- --------------- -------------------------------
2012-03-23 Filen Create.
--*/
#include "../../../HalPrecomp.h"
#include "../../../../8192cd.h"
typedef enum _RTL8192E_C2H_EVT
{
C2H_8192E_DBG = 0,
C2H_8192E_LB = 1,
C2H_8192E_TXBF = 2,
C2H_8192E_TX_REPORT = 3,
C2H_8192E_TX_RATE =4,
C2H_8192E_BT_INFO = 9,
C2H_8192E_BT_MP = 11,
C2H_8192E_RA_RPT = 12,
#ifdef TXRETRY_CNT
C2H_8192E_TX_RETRY = 13, //0x0D
#endif
C2H_8192E_RA_PARA_RPT=14,
C2H_8192E_EXTEND_IND = 0xFF,
MAX_8192E_C2HEVENT
}RTL8192E_C2H_EVT;
typedef enum _RTL8192E_EXTEND_C2H_EVT
{
EXTEND_C2H_8192E_DBG_PRINT = 0
}RTL8192E_EXTEND_C2H_EVT;
RT_STATUS
StopHW_8192ES(
IN HAL_PADAPTER Adapter
);
RT_STATUS
InitPON_8192ES(
IN HAL_PADAPTER Adapter,
IN u4Byte ClkSel
)
{
u32 bytetmp;
u32 retry;
u8 redo = 0;
RT_TRACE_F( COMP_INIT, DBG_LOUD, ("\n"));
HAL_RTL_W8(REG_RSV_CTRL, 0x00);
// Add by Eric 2013/01/24
// For 92E MP chip, power on sometimes crystal clk setting error
// clk set 25M, value 0x00
if(ClkSel == XTAL_CLK_SEL_25M) {
HAL_RTL_W16(REG_AFE_CTRL4, 0x002a);
HAL_RTL_W8(REG_AFE_CTRL2, 5);
} else if (ClkSel == XTAL_CLK_SEL_40M){
HAL_RTL_W16(REG_AFE_CTRL4, 0x002a);
HAL_RTL_W8(REG_AFE_CTRL2, 1);
}
//pattern Patching EQC fail IC(AFE issue)
//Setting is suggested by SD1-Pisa
//Set 0x78[21] = 0, 0x28[6] = 0
//0x28[6] = 0 is done by XTAL seletion 0x28[6] = 0
HAL_RTL_W32(REG_AFE_CTRL4, HAL_RTL_R32(REG_AFE_CTRL4) & ~BIT21);
redo_pon:
/* enable power cut first */
HAL_RTL_W16(0x20, HAL_RTL_R16(0x20) | BIT0 | BIT8);
printk("start power seq \n");
msleep(10);//HAL_delay_ms(5);
if (!HalPwrSeqCmdParsing88XX(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
PWR_INTF_SDIO_MSK, rtl8192E_card_enable_flow))
{
RT_TRACE( COMP_INIT, DBG_SERIOUS, ("%s %d, HalPwrSeqCmdParsing init fail!!!\n", __FUNCTION__, __LINE__));
if (redo < 5) {
redo++;
StopHW_8192ES(Adapter);
goto redo_pon;
}
return RT_STATUS_FAILURE;
}
// Power on when re-enter from IPS/Radio off/card disable
HAL_RTL_W8(REG_AFE_CTRL1, HAL_RTL_R8(REG_AFE_CTRL1) | BIT0);
bytetmp = HAL_RTL_R16(REG_SYS_PW_CTRL);
bytetmp &= 0xE7ff;
bytetmp |= 0x0800;
HAL_RTL_W16(REG_SYS_PW_CTRL, bytetmp);
while (!((bytetmp = HAL_RTL_R32(REG_SYS_PW_CTRL)) & 0x00020000)) ;
bytetmp = HAL_RTL_R16(REG_SYS_PW_CTRL);
bytetmp &= 0x7FFF;
HAL_RTL_W16(REG_SYS_PW_CTRL, bytetmp);
bytetmp = HAL_RTL_R16(REG_SYS_PW_CTRL);
bytetmp &= 0xE7ff;
bytetmp |= 0x0000;
HAL_RTL_W16(REG_SYS_PW_CTRL, bytetmp);
HAL_delay_ms(1);
// auto enable WLAN
// Power On Reset for MAC Block
bytetmp = HAL_RTL_R8(REG_SYS_PW_CTRL+1) | BIT(0);
HAL_delay_us(2);
HAL_RTL_W8(REG_SYS_PW_CTRL+1, bytetmp);
HAL_delay_us(2);
bytetmp = HAL_RTL_R8(REG_SYS_PW_CTRL+1);
HAL_delay_us(2);
retry = 0;
while((bytetmp & BIT(0)) && retry < 1000){
retry++;
HAL_delay_us(50);
bytetmp = HAL_RTL_R8(REG_SYS_PW_CTRL+1);
HAL_delay_us(50);
}
RT_TRACE(COMP_INIT, DBG_WARNING, ("%s: RTL_R8(APS_FSMCO+1) retry times=%d\n", (char *)__FUNCTION__, retry) );
RT_TRACE(COMP_INIT, DBG_TRACE, ("FSMCO11=0x%x\n", HAL_RTL_R32(REG_SYS_PW_CTRL)) );
if (bytetmp & BIT(0)) {
RT_TRACE(COMP_INIT, DBG_SERIOUS, ("%s ERROR: auto enable WLAN failed!!(0x%02X)\n", __FUNCTION__, bytetmp) );
}
HAL_RTL_W8(REG_RSV_CTRL+1, HAL_RTL_R8(REG_RSV_CTRL+1) & ~BIT0);
HAL_RTL_W16(REG_SYS_FUNC_EN, HAL_RTL_R16(REG_SYS_FUNC_EN) & ~BIT_FEN_CPUEN);
HAL_delay_us(2);
// check LDO mode
if (HAL_RTL_R32(REG_SYS_CFG1) & BIT24) {
// LDO mode set 0x7C
HAL_RTL_W8(REG_LDO_SWR_CTRL, 0xc3);
} else {
// SPS mode
HAL_RTL_W8(REG_LDO_SWR_CTRL, 0x83);
}
return RT_STATUS_SUCCESS;
}
RT_STATUS
StopHW8192EE(
IN HAL_PADAPTER Adapter
)
{
// TODO:
return RT_STATUS_SUCCESS;
}
VOID
InitIMR_8192ES(
IN HAL_PADAPTER Adapter,
IN RT_OP_MODE OPMode
)
{
InitSdioInterrupt(Adapter);
}
VOID
EnableIMR_8192ES(
IN HAL_PADAPTER Adapter
)
{
EnableSdioInterrupt(Adapter);
}
RT_STATUS
StopHW_8192ES(
IN HAL_PADAPTER Adapter
)
{
HAL_RTL_W8(REG_RSV_CTRL, HAL_RTL_R8(REG_RSV_CTRL)& ~BIT(1));//unlock reg0x00~0x03 for 8881a, 92e
//MCU reset
HAL_RTL_W8(REG_RSV_CTRL+1, HAL_RTL_R8(REG_RSV_CTRL+1) & ~BIT0);
HAL_RTL_W16(REG_SYS_FUNC_EN, HAL_RTL_R16(REG_SYS_FUNC_EN) & ~BIT10);
// Run LPS WL RFOFF flow
if (_FALSE == HalPwrSeqCmdParsing88XX(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
PWR_INTF_SDIO_MSK, rtl8192E_enter_lps_flow)) {
RT_TRACE(COMP_INIT, DBG_SERIOUS, ("rtl8192E_enter_lps_flow\n"));
}
// Disable CMD53 R/W Operation
GET_HAL_INTF_DATA(Adapter)->bMacPwrCtrlOn = FALSE;
// Card disable power action flow
if (_FALSE == HalPwrSeqCmdParsing88XX(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
PWR_INTF_SDIO_MSK, rtl8192E_card_disable_flow)) {
RT_TRACE(COMP_INIT, DBG_SERIOUS, ("rtl8192E_card_disable_flow\n"));
}
// Reset IO Wraper
HAL_RTL_W8(REG_RSV_CTRL+1, HAL_RTL_R8(REG_RSV_CTRL+1) & ~BIT(3));
HAL_RTL_W8(REG_RSV_CTRL+1, HAL_RTL_R8(REG_RSV_CTRL+1) | BIT(3));
// lock ISO/CLK/Power control register
HAL_RTL_W8(REG_RSV_CTRL, 0x0e);
return RT_STATUS_SUCCESS;
}
#if CFG_HAL_SUPPORT_MBSSID
VOID
InitMBSSID_8192ES(
IN HAL_PADAPTER Adapter
)
{
rtl8192cd_init_mbssid(Adapter);
}
VOID
StopMBSSID_8192ES(
IN HAL_PADAPTER Adapter
)
{
rtl8192cd_stop_mbssid(Adapter);
}
#endif
RT_STATUS
SetMACIDSleep_8192ES(
IN HAL_PADAPTER Adapter,
IN BOOLEAN bSleep,
IN u4Byte aid
)
{
notify_macid_pause_change(Adapter, aid, bSleep);
return RT_STATUS_SUCCESS;
}
void
UpdateHalMSRRPT_8192ES(
IN HAL_PADAPTER Adapter,
HAL_PSTAINFO pEntry,
u1Byte opmode
)
{
UpdateHalMSRRPT88XX(Adapter, pEntry, opmode);
}
RT_STATUS
hal_Associate_8192ES(
HAL_PADAPTER Adapter,
BOOLEAN IsDefaultAdapter
)
{
PHAL_INTERFACE pHalFunc = GET_HAL_INTERFACE(Adapter);
PHAL_DATA_TYPE pHalData = _GET_HAL_DATA(Adapter);
//
//Initialization Related
//
pHalData->AccessSwapCtrl = HAL_ACCESS_SWAP_MEM;
pHalFunc->InitPONHandler = InitPON_8192ES;
pHalFunc->InitMACHandler = InitMAC88XX;
pHalFunc->InitFirmwareHandler = InitFirmware88XX;
#if CFG_HAL_SUPPORT_MBSSID
pHalFunc->InitMBSSIDHandler = InitMBSSID_8192ES;
pHalFunc->InitMBIDCAMHandler = InitMBIDCAM88XX;
#endif //CFG_HAL_SUPPORT_MBSSID
pHalFunc->InitLLT_TableHandler = InitLLT_Table88XX;
#ifdef MULTI_MAC_CLONE
pHalFunc->McloneSetMBSSIDHandler = McloneSetMBSSID88XX;
pHalFunc->McloneStopMBSSIDHandler = McloneStopMBSSID88XX;
#endif
pHalFunc->SetMBIDCAMHandler = SetMBIDCAM88XX;
pHalFunc->InitVAPIMRHandler = InitVAPIMR88XX;
//
//Stop Related
//
#if CFG_HAL_SUPPORT_MBSSID
pHalFunc->StopMBSSIDHandler = StopMBSSID_8192ES;
#endif //CFG_HAL_SUPPORT_MBSSID
pHalFunc->StopHWHandler = StopHW_8192ES;
pHalFunc->StopSWHandler = StopSW88XX;
pHalFunc->DisableVXDAPHandler = DisableVXDAP88XX;
pHalFunc->StopMBIDCAMHandler = StopMBIDCAM88XX;
pHalFunc->ResetHWForSurpriseHandler = ResetHWForSurprise88XX;
//
//ISR Related
//
pHalFunc->InitIMRHandler = InitIMR_8192ES;
pHalFunc->EnableIMRHandler = EnableIMR_8192ES;
//
//Tx Related
//
//
//Rx Related
//
//
// General operation
//
pHalFunc->GetChipIDMIMOHandler = GetChipIDMIMO88XX;
pHalFunc->SetHwRegHandler = SetHwReg88XX;
pHalFunc->GetHwRegHandler = GetHwReg88XX;
pHalFunc->SetMACIDSleepHandler = SetMACIDSleep_8192ES;
pHalFunc->CheckHangHandler = CheckHang88XX;
pHalFunc->GetMACIDQueueInTXPKTBUFHandler= GetMACIDQueueInTXPKTBUF88XX;
//
// Timer Related
//
pHalFunc->Timer1SecHandler = Timer1Sec88XX;
#if CFG_HAL_MACDM
InitMACDM88XX(Adapter);
pHalFunc->Timer1SecDMHandler = Timer1SecDM88XX;
#endif //CFG_HAL_MACDM
//
// Security Related
//
pHalFunc->CAMReadMACConfigHandler = CAMReadMACConfig88XX;
pHalFunc->CAMEmptyEntryHandler = CAMEmptyEntry88XX;
pHalFunc->CAMFindUsableHandler = CAMFindUsable88XX;
pHalFunc->CAMProgramEntryHandler = CAMProgramEntry88XX;
//
// PHY/RF Related
//
pHalFunc->PHYSetCCKTxPowerHandler = PHYSetCCKTxPower88XX_N;
pHalFunc->PHYSetOFDMTxPowerHandler = PHYSetOFDMTxPower88XX_N;
pHalFunc->PHYSwBWModeHandler = SwBWMode88XX_N;
//pHalFunc->TXPowerTrackingHandler = TXPowerTracking_ThermalMeter_88XX;
pHalFunc->PHYSSetRFRegHandler = PHY_SetRFReg_88XX_N;
pHalFunc->PHYQueryRFRegHandler = PHY_QueryRFReg_88XX_N;
pHalFunc->IsBBRegRangeHandler = IsBBRegRange88XX;
//
// Firmware CMD IO related
//
pHalData->H2CBufPtr88XX = 0;
pHalData->bFWReady = _FALSE;
pHalFunc->FillH2CCmdHandler = FillH2CCmd88XX;
pHalFunc->UpdateHalRAMaskHandler = UpdateHalRAMask88XX;
pHalFunc->UpdateHalMSRRPTHandler = UpdateHalMSRRPT_8192ES;
#ifdef SDIO_AP_OFFLOAD
#if defined(SOFTAP_PS_DURATION) || defined(CONFIG_POWER_SAVE)
pHalFunc->SetSAPPsHandler = SetSAPPS88XX;
#endif
pHalFunc->SetAPOffloadHandler = SetAPOffload88XX;
pHalFunc->SetRsvdPageHandler = SetRsvdPage88XX;
pHalFunc->GetRsvdPageLocHandler = GetRsvdPageLoc88XX;
#endif // SDIO_AP_OFFLOAD
// pHalFunc->DownloadRsvdPageHandler = DownloadRsvdPage88XX;
pHalFunc->C2HHandler = C2HHandler88XX;
pHalFunc->C2HPacketHandler = C2HPacketHandler_92E;
return RT_STATUS_SUCCESS;
}
void
InitMAC8192EE(
IN HAL_PADAPTER Adapter
)
{
}
VOID
C2HTxTxReportHandler_92E(
struct rtl8192cd_priv *priv,
pu1Byte CmdBuf,
u1Byte CmdLen
)
{
struct tx_rpt rpt1;
int k=0, j=0;
for(j=0; j<2; j++) {
rpt1.macid= CmdBuf[k];
rpt1.txok = CmdBuf[k+1] | ((short)CmdBuf[k+2]<<8);
rpt1.txfail = CmdBuf[k+3] | ((short)CmdBuf[k+4]<<8);
rpt1.initil_tx_rate = CmdBuf[k+5];
if(rpt1.macid != 0xff)
txrpt_handler(priv, &rpt1);
k+=6;
}
}
VOID
_C2HContentParsing92E(
struct rtl8192cd_priv *priv,
u1Byte c2hCmdId,
u1Byte c2hCmdLen,
pu1Byte tmpBuf
)
{
switch(c2hCmdId)
{
case C2H_8192E_TXBF:
#ifdef BEAMFORMING_SUPPORT
C2HTxBeamformingHandler_92E(priv, tmpBuf, c2hCmdLen);
#endif
break;
case C2H_8192E_TX_RATE:
#ifdef TXREPORT
C2HTxTxReportHandler_92E(priv, tmpBuf, c2hCmdLen);
//requestTxReport88XX(priv);
notify_request_tx_report(priv);
#endif
break;
default:
if(!(phydm_c2H_content_parsing(ODMPTR, c2hCmdId, c2hCmdLen, tmpBuf))) {
printk("[C2H], Unkown packet!! CmdId(%#X)!\n", c2hCmdId);
}
break;
}
}
VOID
C2HPacketHandler_92E(
struct rtl8192cd_priv *priv,
pu1Byte Buffer,
u1Byte Length
)
{
u1Byte c2hCmdId=0, c2hCmdSeq=0, c2hCmdLen=0;
pu1Byte tmpBuf=NULL;
c2hCmdId = Buffer[0];
c2hCmdSeq = Buffer[1];
/*
if(c2hCmdId==C2H_88XX_EXTEND_IND)
{
c2hCmdLen = Length;
tmpBuf = Buffer;
C2HExtEventHandler88XX(NULL, c2hCmdId, c2hCmdLen, tmpBuf);
}
else
*/
{
c2hCmdLen = Length -2;
tmpBuf = Buffer+2;
_C2HContentParsing92E(priv, c2hCmdId, c2hCmdLen, tmpBuf);
}
}
#ifdef BEAMFORMING_SUPPORT
VOID
SetBeamformRfMode92E(
struct rtl8192cd_priv *priv,
PRT_BEAMFORMING_INFO pBeamformingInfo
)
{
u1Byte i;
BOOLEAN bSelfBeamformer = FALSE;
BOOLEAN bSelfBeamformee = FALSE;
RT_BEAMFORMING_ENTRY BeamformEntry;
BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE;
BeamformCap = Beamforming_GetBeamCap(pBeamformingInfo);
if(BeamformCap == pBeamformingInfo->BeamformCap)
return;
else
pBeamformingInfo->BeamformCap = BeamformCap;
if(get_rf_mimo_mode(priv) == MIMO_1T1R)
return;
PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_WE_LUT, 0x80000,0x1); // RF Mode table write enable
PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_WE_LUT, 0x80000,0x1); // RF Mode table write enable
bSelfBeamformer = BeamformCap & BEAMFORMER_CAP;
bSelfBeamformee = BeamformCap & BEAMFORMEE_CAP;
if(bSelfBeamformer)
{
// Path_A
PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_RCK_OS, 0xfffff,0x18000); // Select RX mode 0x30=0x18000
PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_TXPA_G1, 0xfffff,0x0000f); // Set Table data
PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff,0x77fc2); // Enable TXIQGEN in RX mode
// Path_B
PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_RCK_OS, 0xfffff,0x18000); // Select RX mode
PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_TXPA_G1, 0xfffff,0x0000f); // Set Table data
PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_TXPA_G2, 0xfffff,0x77fc2); // Enable TXIQGEN in RX mode
}
else
{
// Paath_A
PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_RCK_OS, 0xfffff,0x18000); // Select RX mode
PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_TXPA_G1, 0xfffff,0x0000f); // Set Table data
PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff,0x77f82); // Disable TXIQGEN in RX mode
// Path_B
PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_RCK_OS, 0xfffff,0x18000); // Select RX mode
PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_TXPA_G1, 0xfffff,0x0000f); // Set Table data
PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_TXPA_G2, 0xfffff,0x77f82); // Disable TXIQGEN in RX mode
}
PHY_SetRFReg(priv, ODM_RF_PATH_A, RF_WE_LUT, 0x80000,0x0); // RF Mode table write disable
PHY_SetRFReg(priv, ODM_RF_PATH_B, RF_WE_LUT, 0x80000,0x0); // RF Mode table write disable
if(bSelfBeamformer){
PHY_SetBBReg(priv, 0x90c, 0xffffffff, 0x83321333);
PHY_SetBBReg(priv, 0xa04, BIT31|BIT30, 0x3);
#ifdef RF_MIMO_SWITCH
priv->pshare->rf_phy_bb_backup[19] = 0x83321333;
priv->pshare->rf_phy_bb_backup[22] |= BIT31|BIT30;
#endif
}
else {
PHY_SetBBReg(priv, 0x90c, 0xffffffff, 0x81121313);
#ifdef RF_MIMO_SWITCH
priv->pshare->rf_phy_bb_backup[19] = 0x81121313;
#endif
}
}
VOID
SetBeamformEnter92E(
struct rtl8192cd_priv *priv,
u1Byte BFerBFeeIdx
)
{
u1Byte i = 0;
u1Byte BFerIdx = (BFerBFeeIdx & 0xF0)>>4;
u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);
u4Byte CSI_Param;
PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo);
RT_BEAMFORMING_ENTRY BeamformeeEntry;
RT_BEAMFORMER_ENTRY BeamformerEntry;
u2Byte STAid = 0;
SetBeamformRfMode92E(priv, pBeamformingInfo);
if(get_rf_mimo_mode(priv) == MIMO_2T2R)
RTL_W32(0xD80, 0x01081008);
if((pBeamformingInfo->BeamformCap & BEAMFORMEE_CAP) && (BFerIdx < BEAMFORMER_ENTRY_NUM))
{
BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
//eric-8813
if (IS_TEST_CHIP(priv))
RTL_W8( REG_SND_PTCL_CTRL, 0x1B); // Disable SIG-B CRC8 check
else
RTL_W8( REG_SND_PTCL_CTRL, 0xCB);
// MAC addresss/Partial AID of Beamformer
if(BFerIdx == 0)
{
for(i = 0; i < 6 ; i++)
RTL_W8( (REG_ASSOCIATED_BFMER0_INFO+i), BeamformerEntry.MacAddr[i]);
RTL_W16( REG_ASSOCIATED_BFMER0_INFO+6, BeamformerEntry.P_AID);
}
else
{
for(i = 0; i < 6 ; i++)
RTL_W8( (REG_ASSOCIATED_BFMER1_INFO+i), BeamformerEntry.MacAddr[i]);
RTL_W16( REG_ASSOCIATED_BFMER1_INFO+6, BeamformerEntry.P_AID);
}
// CSI report parameters of Beamformer
CSI_Param = 0x03090309;//Nc =2, V matrix
RTL_W32( REG_TX_CSI_RPT_PARAM_BW20, CSI_Param);
RTL_W32( REG_TX_CSI_RPT_PARAM_BW40, CSI_Param);
// Timeout value for MAC to leave NDP_RX_standby_state 60 us
// RTL_W8( REG_SND_PTCL_CTRL_8812+3, 0x3C);
RTL_W8( REG_SND_PTCL_CTRL+3, 0x50); // // ndp_rx_standby_timer
}
if((pBeamformingInfo->BeamformCap & BEAMFORMER_CAP) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM))
{
BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
if(OPMODE & WIFI_ADHOC_STATE)
STAid = BeamformeeEntry.AID;
else
STAid = BeamformeeEntry.P_AID;
// P_AID of Beamformee & enable NDPA transmission
if(BFeeIdx == 0)
{
RTL_W16( REG_TXBF_CTRL, STAid);
RTL_W8( REG_TXBF_CTRL+3, RTL_R8( REG_TXBF_CTRL+3)|BIT6|BIT7|BIT4);
}
else
{
RTL_W16( REG_TXBF_CTRL+2, STAid |BIT14| BIT15|BIT12);
}
// CSI report parameters of Beamformee
if(BFeeIdx == 0)
{
// Get BIT24 & BIT25
u1Byte tmp = RTL_R8( REG_ASSOCIATED_BFMEE_SEL+3) & 0x3;
RTL_W8( REG_ASSOCIATED_BFMEE_SEL+3, tmp | 0x60);
RTL_W16( REG_ASSOCIATED_BFMEE_SEL, STAid | BIT9);
}
else
{
// Set BIT25
RTL_W16( REG_ASSOCIATED_BFMEE_SEL+2, STAid | 0xE200);
}
// if(pHalData->bIsMPChip == FALSE)
if (IS_TEST_CHIP(priv))
{
// VHT category value
RTL_W8( REG_SND_PTCL_CTRL+1, ACT_CAT_VHT);
// NDPA subtype
RTL_W8( REG_SND_PTCL_CTRL+2, Type_NDPA >> 4);
}
Beamforming_Notify(priv);
}
}
VOID
SetBeamformLeave92E(
struct rtl8192cd_priv *priv,
u1Byte Idx
)
{
PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo);
RT_BEAMFORMING_ENTRY BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx];
RT_BEAMFORMER_ENTRY BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx];
/* Clear P_AID of Beamformee
* Clear MAC addresss of Beamformer
* Clear Associated Bfmee Sel
*/
if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE)
{
if(Idx == 0)
{
RTL_W16( REG_TXBF_CTRL, 0);
RTL_W16( REG_ASSOCIATED_BFMEE_SEL, 0);
}
else
{
RTL_W16( REG_TXBF_CTRL+2, RTL_R16( REG_TXBF_CTRL+2) & 0xF000);
RTL_W16( REG_ASSOCIATED_BFMEE_SEL+2, RTL_R16( REG_ASSOCIATED_BFMEE_SEL+2) & 0x60);
}
}
if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE)
{
if(Idx == 0)
{
RTL_W32( REG_ASSOCIATED_BFMER0_INFO, 0);
RTL_W16( REG_ASSOCIATED_BFMER0_INFO+4, 0);
}
else
{
RTL_W32( REG_ASSOCIATED_BFMER1_INFO, 0);
RTL_W16( REG_ASSOCIATED_BFMER1_INFO+4, 0);
}
}
if(((pBeamformingInfo->BeamformerEntry[0]).BeamformEntryCap == BEAMFORMING_CAP_NONE)
&& ((pBeamformingInfo->BeamformerEntry[1]).BeamformEntryCap == BEAMFORMING_CAP_NONE)){
ODM_RT_TRACE(ODMPTR, BEAMFORMING_DEBUG, ODM_DBG_LOUD, ("[Beamforming]@%s, All BeamformerEntryCap == NONE, STOP feedback CSI\n", __FUNCTION__));
RTL_W8( REG_SND_PTCL_CTRL, 0xC8);
}
}
VOID
SetBeamformStatus92E(
struct rtl8192cd_priv *priv,
u1Byte Idx
)
{
u2Byte BeamCtrlVal;
u4Byte BeamCtrlReg;
// PRT_BEAMFORMING_INFO pBeamformingInfo = GET_BEAMFORM_INFO(&(Adapter->MgntInfo));
PRT_BEAMFORMING_INFO pBeamformingInfo = &(priv->pshare->BeamformingInfo);
RT_BEAMFORMING_ENTRY BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx];
// if(ACTING_AS_IBSS(Adapter))
if(OPMODE & WIFI_ADHOC_STATE)
BeamCtrlVal = BeamformEntry.MacId;
else
BeamCtrlVal = BeamformEntry.P_AID;
if(Idx == 0)
BeamCtrlReg = REG_TXBF_CTRL;
else
{
BeamCtrlReg = REG_TXBF_CTRL+2;
BeamCtrlVal |= BIT12 | BIT14|BIT15;
}
// debug
#if 1
if(BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED)
{
// panic_printk("%d%s BW = %d\n",__LINE__,__FUNCTION__,BeamformEntry.BW);
if(BeamformEntry.BW == HT_CHANNEL_WIDTH_20)
BeamCtrlVal |= BIT9;
else if(BeamformEntry.BW == HT_CHANNEL_WIDTH_20_40)
BeamCtrlVal |= (BIT9 | BIT10);
else if(BeamformEntry.BW == HT_CHANNEL_WIDTH_80)
BeamCtrlVal |= (BIT9 | BIT10 | BIT11);
}
#endif
else
{
BeamCtrlVal &= ~(BIT9|BIT10|BIT11);
}
// PlatformEFIOWrite2Byte(Adapter, BeamCtrlReg, BeamCtrlVal);
RTL_W16(BeamCtrlReg, BeamCtrlVal);
// panic_printk("%s Idx %d BeamCtrlReg %x BeamCtrlVal %x, bw=%d\n", __FUNCTION__, Idx, BeamCtrlReg, BeamCtrlVal, BeamformEntry.BW);
}
//2REG_C2HEVT_CLEAR
#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message
#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver.
VOID Beamforming_NDPARate_92E(
struct rtl8192cd_priv *priv,
BOOLEAN Mode,
u1Byte BW,
u1Byte Rate)
{
#if 1
u2Byte NDPARate = Rate;
if(NDPARate == 0)
{
// ???
#if 0
if(Mode == 1 || Mode == 4)
NDPARate = 0x0c; //MGN_MCS0;
else
NDPARate = 0x2c; //MGN_VHT1SS_MCS0;
#else
if(priv->pshare->rssi_min > 30) // link RSSI > 30%
NDPARate = 8; //MGN_24M
else
NDPARate = 4; //MGN_6M
#endif
}
if(NDPARate < 0x0c)
BW = HT_CHANNEL_WIDTH_20;
RTL_W8(REG_NDPA_OPT_CTRL, (NDPARate<<2) | (BW & 0x03));
#else
{
if(mode ==0) {
#if 1
rate = 11; // 54M
BW = 0;
#else
rate = 0x0c; //_MCS0_RATE_;
if(BW ==3)
BW= 2;
#endif
}
else {
rate = 0x2c; //_NSS1_MCS0_RATE_;
}
}
RTL_W8(0x45f, (rate<<2) | (BW & 0x03));
#endif
}
// V1
#if 0
void TXBF_timer_callback(unsigned long task_priv)
{
struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv;
struct stat_info *pstat;
struct list_head *phead, *plist;
unsigned long flags;
if(!priv->pmib->dot11RFEntry.txbf)
return;
SAVE_INT_AND_CLI(flags);
phead = &priv->asoc_list;
plist = phead->next;
// panic_printk(".");
// VAP ?
while(plist != phead)
{
pstat = list_entry(plist, struct stat_info, asoc_list);
// if(priv->pmib->dot11RFEntry.txbf == 1)
if((pstat->ht_cap_len && (pstat->ht_cap_buf.txbf_cap)) ||
(pstat->vht_cap_len && (cpu_to_le32(pstat->vht_cap_buf.vht_cap_info) & BIT(SU_BFEE_S))))
{
// BeamformingInit(priv, pstat->hwaddr, pstat->aid);
if(pstat->vht_cap_len) //_eric_txbf
BeamformingControl(priv, pstat->hwaddr, pstat->aid, 2, pstat->tx_bw);
else
BeamformingControl(priv, pstat->hwaddr, pstat->aid, 3, pstat->tx_bw);
}
if (plist == plist->next)
break;
plist = plist->next;
};
RESTORE_INT(flags);
mod_timer(&priv->txbf_timer, jiffies + priv->pshare->rf_ft_var.soundingPeriod);
}
#endif
VOID
C2HTxBeamformingHandler_92E(
struct rtl8192cd_priv *priv,
pu1Byte CmdBuf,
u1Byte CmdLen
)
{
u1Byte status = (CmdBuf[0] & BIT0);
// panic_printk("%d%s status = %d \n",__LINE__,__FUNCTION__,status);
Beamforming_End(priv, status);
}
VOID HW_VAR_HW_REG_TIMER_START_92E(struct rtl8192cd_priv *priv)
{
panic_printk("[%d][%s]\n",__LINE__,__FUNCTION__);
RTL_W8(0x15F, 0x0);
RTL_W8(0x15F, 0x5);
}
VOID HW_VAR_HW_REG_TIMER_INIT_92E(struct rtl8192cd_priv *priv, u2Byte t)
{
panic_printk("[%d][%s]\n",__LINE__,__FUNCTION__);
RTL_W8(0x164, 1);
RTL_W16(0x15C, t);
}
VOID HW_VAR_HW_REG_TIMER_STOP_92E(struct rtl8192cd_priv *priv)
{
panic_printk("[%d][%s]\n",__LINE__,__FUNCTION__);
RTL_W8(0x15F, 0);
}
#endif