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M7350v7_en_gpl

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2024-09-09 08:59:52 +00:00
parent f75098198c
commit 46ba6f09ec
1372 changed files with 1231198 additions and 1184 deletions
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20872
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/HalHeader/HalComBit.h Executable file
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/HalHeader/HalComPhyBit.h Executable file
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#ifndef __INC_HALCOMPHYBIT_H
#define __INC_HALCOMPHYBIT_H
/*-------------------------Modification Log-----------------------------------
-------------------------Modification Log-----------------------------------*/
/*--------------------------Include File--------------------------------------*/
//3 ============Programming guide Start=====================
/*
BB BIT define rules
1. For all bit define, it should be prefixed by "BIT_BB"
2. For all bit mask, it should be prefixed by "BIT_MASK_BB"
3. For all bit shift, it should be prefixed by "BIT_SHIFT_BB"
4. For other case, prefix is not needed
RF BIT define rules
1. For all bit define, it should be prefixed by "BIT_RF"
2. For all bit mask, it should be prefixed by "BIT_MASK_RF"
3. For all bit shift, it should be prefixed by "BIT_SHIFT_RF"
4. For other case, prefix is not needed
SET BIT define rules
1. Setting byte mask for BB or RF, it should be prefixed by "BIT_SET"
Suffixed BIT define rules
1. For AC chip, it should be suffixed by "_AC"
2. For N chip, it should be suffixed by "_N"
3. For Common bit define, it should be suffixed by "_COMMON"
*/
#if IS_RTL88XX_AC
/**** page 8 ****/
//REG_BB_RCCKENABLE_AC offset:0x808
#define BIT_MASK_BB_BOFDMEN_AC 0x20000000
#define BIT_MASK_BB_BCCKEN_AC 0x10000000
#define BIT_MASK_BB_BRXPATH_AC 0xff
//REG_BB_RTXPATH_AC offset:0x80c
#define BIT_MASK_BB_BTXPATH_AC 0x0fffffff
//REG_BB_RAGC_TABLE_AC offset:0x82c // AGC tabel select
#define BIT_MASK_BB_BAGC_TABLE_AC 0x3
//REG_BB_CCAONSEC_AC offset:0x838
#define BIT_MASK_BB_CCA_AC 0xf
//REG_BB_REDCCA_AC offset:0x8a4 // EDCCA
#define BIT_MASK_BB_BEDCCA_AC 0xffff
//REG_BB_RHSSIREAD_AC offset:0x8b0 // RF read addr
#define BIT_MASK_BB_BHSSIREAD_ADDR_AC 0xff
/**** page 9 ****/
/**** page a ****/
//REG_BB_RCCK_SYSTEM_AC offset: 0xa00 // for cck sideband
#define BIT_MASK_BB_BCCK_SYSTEM_AC 0x10
//REG_BB_RCCK_RX_AC offset: 0xa04 // for cck rx path selection
#define BIT_MASK_BB_BCCK_RX_AC 0x0c000000
//REG_BB_RCCK_CCA_AC offset: 0xa08 // cca threshold
#define BIT_MASK_BB_BCCK_CCA_AC 0x00ff0000
// REG_BB_RCCK_TXFILTER1_AC offset: 0xa20
#define BIT_MASK_BB_BCCK_TXFILTER1_C0_AC 0x00ff0000
#define BIT_MASK_BB_BCCK_TXFILTER1_C1_AC 0xff000000
//REG_BB_RCCK_TXFILTER2_AC offset: 0xa24
#define BIT_MASK_BB_BCCK_TXFILTER2_C2_AC 0x000000ff
#define BIT_MASK_BB_BCCK_TXFILTER2_C3_AC 0x0000ff00
#define BIT_MASK_BB_BCCK_TXFILTER2_C4_AC 0x00ff0000
#define BIT_MASK_BB_BCCK_TXFILTER2_C5_AC 0xff000000
//REG_BB_RCCK_TXFILTER3_AC offset: 0xa28
#define BIT_MASK_BB_BCCK_TXFILTER3_C6_AC 0x000000ff
#define BIT_MASK_BB_BCCK_TXFILTER3_C7_AC 0x0000ff00
//REG_BB_RCCK_FALSEALARM_AC offset: 0xa5c // counter for cck false alarm
#define BIT_MASK_BB_B_FALSEALARM_AC 0xffff
/**** page b ****/
/**** page c ****/
//REG_BB_AGC_TABLE_AC_V1 0xc1c
#define BIT_MASK_BB_BAGC_TABLE_AC_V1 0x00000f00
//REG_BB_A_LSSIWRITE_AC offset :0xc90
#define BIT_MASK_BB_LSSIWRITE_AC 0xf0000000
/**** page d ****/
/**** page e ****/
#endif //#if IS_RTL88XX_AC
#if IS_RTL88XX_N
//
// 2. Page8(0x800)
//
#define BIT_MASK_BB_RFMOD_N_N 0x1 // Reg 0x800 rFPGA0_RFMOD
#define BIT_MASK_BB_JAPANMODE_N 0x2
#define BIT_MASK_BB_CCKTXSC_N 0x30
#define BIT_MASK_BB_CCKEN_N 0x1000000
#define BIT_MASK_BB_OFDMEN_N 0x2000000
#define BIT_MASK_BB_OFDMRXADCPHASE_N 0x10000 // Useless now
#define BIT_MASK_BB_OFDMTXDACPHASE_N 0x40000
#define BIT_MASK_BB_XATXAGC_N 0x3f
#define BIT_MASK_BB_XBTXAGC_N 0xf00 // Reg 80c rFPGA0_TxGainStage
/*
#define BIT_MASK_BB_XCTXAGC_N 0xf000
#define BIT_MASK_BB_XDTXAGC_N 0xf0000
*/
#define BIT_MASK_BB_PASTART_N 0xf0000000 // Useless now
#define BIT_MASK_BB_TRSTART_N 0x00f00000
#define BIT_MASK_BB_RFSTART_N 0x0000f000
#define BIT_MASK_BB_BBSTART_N 0x000000f0
#define BIT_MASK_BB_BBCCKSTART_N 0x0000000f
#define BIT_MASK_BB_PAEND_N 0xf //Reg0x814
#define BIT_MASK_BB_TREND_N 0x0f000000
#define BIT_MASK_BB_RFEND_N 0x000f0000
#define BIT_MASK_BB_CCAMASK_N 0x000000f0 //T2R
#define BIT_MASK_BB_R2RCCAMASK_N 0x00000f00
#define BIT_MASK_BB_HSSI_R2TDELAY_N 0xf8000000
#define BIT_MASK_BB_HSSI_T2RDELAY_N 0xf80000
#define BIT_MASK_BB_CONTTXHSSI_N 0x400 //chane gain at continue Tx
#define BIT_MASK_BB_IGFROMCCK_N 0x200
#define BIT_MASK_BB_AGCADDRESS_N 0x3f
#define BIT_MASK_BB_RXHPTX_N 0x7000
#define BIT_MASK_BB_RXHPT2R_N 0x38000
#define BIT_MASK_BB_RXHPCCKINI_N 0xc0000
#define BIT_MASK_BB_AGCTXCODE_N 0xc00000
#define BIT_MASK_BB_AGCRXCODE_N 0x300000
#define BIT_MASK_BB_3WIREDATALENGTH_N 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define BIT_MASK_BB_3WIREADDRESSLENGTH_N 0x400
#define BIT_MASK_BB_3WIRERFPOWERDOWN_N 0x1 // Useless now
#define BIT_MASK_BB_5GPAPEPOLARITY_N 0x40000000
#define BIT_MASK_BB_2GPAPEPOLARITY_N 0x80000000
#define BIT_MASK_BB_RFSW_TXDEFAULTANT_N 0x3
#define BIT_MASK_BB_RFSW_TXOPTIONANT_N 0x30
#define BIT_MASK_BB_RFSW_RXDEFAULTANT_N 0x300
#define BIT_MASK_BB_RFSW_RXOPTIONANT_N 0x3000
#define BIT_MASK_BB_RFSI_3WIREDATA_N 0x1
#define BIT_MASK_BB_RFSI_3WIRECLOCK_N 0x2
#define BIT_MASK_BB_RFSI_3WIRELOAD_N 0x4
#define BIT_MASK_BB_RFSI_3WIRERW_N 0x8
#define BIT_MASK_BB_RFSI_3WIRE_N 0xf
#define BIT_MASK_BB_RFSI_RFENV_N 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define BIT_MASK_BB_RFSI_TRSW_N 0x20 // Useless now
#define BIT_MASK_BB_RFSI_TRSWB_N 0x40
#define BIT_MASK_BB_RFSI_ANTSW_N 0x100
#define BIT_MASK_BB_RFSI_ANTSWB_N 0x200
#define BIT_MASK_BB_RFSI_PAPE_N 0x400
#define BIT_MASK_BB_RFSI_PAPE5G_N 0x800
#define BIT_MASK_BB_BANDSELECT_N 0x1
#define BIT_MASK_BB_HTSIG2_GI_N 0x80
#define BIT_MASK_BB_HTSIG2_SMOOTHING_N 0x01
#define BIT_MASK_BB_HTSIG2_SOUNDING_N 0x02
#define BIT_MASK_BB_HTSIG2_AGGREATON_N 0x08
#define BIT_MASK_BB_HTSIG2_STBC_N 0x30
#define BIT_MASK_BB_HTSIG2_ADVCODING_N 0x40
#define BIT_MASK_BB_HTSIG2_NUMOFHTLTF_N 0x300
#define BIT_MASK_BB_HTSIG2_CRC8_N 0x3fc
#define BIT_MASK_BB_HTSIG1_MCS_N 0x7f
#define BIT_MASK_BB_HTSIG1_BANDWIDTH_N 0x80
#define BIT_MASK_BB_HTSIG1_HTLENGTH_N 0xffff
#define BIT_MASK_BB_LSIG_RATE_N 0xf
#define BIT_MASK_BB_LSIG_RESERVED_N 0x10
#define BIT_MASK_BB_LSIG_LENGTH_N 0x1fffe
#define BIT_MASK_BB_LSIG_PARITY_N 0x20
#define BIT_MASK_BB_CCKRXPHASE_N 0x4
//#define BIT_MASK_BB_LSSIREADADDRESS 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2
#define BIT_MASK_BB_LSSIREADADDRESS_N 0x7f800000 // T65 RF
#define BIT_MASK_BB_LSSIREADEDGE_N 0x80000000 //LSSI "Read" edge signal
//#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack
#define BIT_MASK_BB_LSSIREADBACKDATA_N 0xfffff // T65 RF
#define BIT_MASK_BB_LSSIREADOKFLAG_N 0x1000 // Useless now
#define BIT_MASK_BB_CCKSAMPLERATE_N 0x8 //0: 44MHz, 1:88MHz
#define BIT_MASK_BB_REGULATOR0STANDBY_N 0x1
#define BIT_MASK_BB_REGULATORPLLSTANDBY_N 0x2
#define BIT_MASK_BB_REGULATOR1STANDBY_N 0x4
#define BIT_MASK_BB_PLLPOWERUP_N 0x8
#define BIT_MASK_BB_DPLLPOWERUP_N 0x10
#define BIT_MASK_BB_DA10POWERUP_N 0x20
#define BIT_MASK_BB_AD7POWERUP_N 0x200
#define BIT_MASK_BB_DA6POWERUP_N 0x2000
#define BIT_MASK_BB_XTALPOWERUP_N 0x4000
#define BIT_MASK_BB_40MDCLKPOWERUP_N 0x8000
#define BIT_MASK_BB_DA6DEBUGMODE_N 0x20000
#define BIT_MASK_BB_DA6SWING_N 0x380000
#define BIT_MASK_BB_ADCLKPHASE_N 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define BIT_MASK_BB_80MCLKDELAY_N 0x18000000 // Useless
#define BIT_MASK_BB_AFEWATCHDOGENABLE_N 0x20000000
#define BIT_MASK_BB_XTALCAP01_N 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define BIT_MASK_BB_XTALCAP23_N 0x3
#define BIT_MASK_BB_XTALCAP92X_N 0x0f000000
#define BIT_MASK_BB_INTDIFCLKENABLE_N 0x400 // Useless
#define BIT_MASK_BB_EXTSIGCLKENABLE_N 0x800
#define BIT_MASK_BB_BANDGAPMBIASPOWERUP_N 0x10000
#define BIT_MASK_BB_AD11SHGAIN_N 0xc0000
#define BIT_MASK_BB_AD11INPUTRANGE_N 0x700000
#define BIT_MASK_BB_AD11OPCURRENT_N 0x3800000
#define BIT_MASK_BB_IPATHLOOPBACK_N 0x4000000
#define BIT_MASK_BB_QPATHLOOPBACK_N 0x8000000
#define BIT_MASK_BB_AFELOOPBACK_N 0x10000000
#define BIT_MASK_BB_DA10SWING_N 0x7e0
#define BIT_MASK_BB_DA10REVERSE_N 0x800
#define BIT_MASK_BB_DACLKSOURCE_N 0x1000
#define BIT_MASK_BB_AD7INPUTRANGE_N 0x6000
#define BIT_MASK_BB_AD7GAIN_N 0x38000
#define BIT_MASK_BB_AD7OUTPUTCMMODE_N 0x40000
#define BIT_MASK_BB_AD7INPUTCMMODE_N 0x380000
#define BIT_MASK_BB_AD7CURRENT_N 0xc00000
#define BIT_MASK_BB_REGULATORADJUST_N 0x7000000
#define BIT_MASK_BB_AD11POWERUPATTX_N 0x1
#define BIT_MASK_BB_DA10PSATTX_N 0x10
#define BIT_MASK_BB_AD11POWERUPATRX_N 0x100
#define BIT_MASK_BB_DA10PSATRX_N 0x1000
#define BIT_MASK_BB_CCKRXAGCFORMAT_N 0x200
#define BIT_MASK_BB_PSDFFTSAMPLEPPOINT_N 0xc000
#define BIT_MASK_BB_PSDAVERAGENUM_N 0x3000
#define BIT_MASK_BB_IQPATHCONTROL_N 0xc00
#define BIT_MASK_BB_PSDFREQ_N 0x3ff
#define BIT_MASK_BB_PSDANTENNAPATH_N 0x30
#define BIT_MASK_BB_PSDIQSWITCH_N 0x40
#define BIT_MASK_BB_PSDRXTRIGGER_N 0x400000
#define BIT_MASK_BB_PSDTXTRIGGER_N 0x80000000
#define BIT_MASK_BB_PSDSINETONESCALE_N 0x7f000000
#define BIT_MASK_BB_PSDREPORT_N 0xffff
//
// 3. Page9(0x900)
//
#define BIT_MASK_BB_OFDMTXSC_N 0x30000000 // Useless
#define BIT_MASK_BB_CCKTXON_N 0x1
#define BIT_MASK_BB_OFDMTXON_N 0x2
#define BIT_MASK_BB_DEBUGPAGE_N 0xfff //reset debug page and also HWord, LWord
#define BIT_MASK_BB_DEBUGITEM_N 0xff //reset debug page and LWord
#define BIT_MASK_BB_ANTL_N 0x10
#define BIT_MASK_BB_ANTNONHT_N 0x100
#define BIT_MASK_BB_ANTHT1_N 0x1000
#define BIT_MASK_BB_ANTHT2_N 0x10000
#define BIT_MASK_BB_ANTHT1S1_N 0x100000
#define BIT_MASK_BB_ANTNONHTS1_N 0x1000000
//
// 4. PageA(0xA00)
//
#define BIT_MASK_BB_CCKBBMODE_N 0x3 // Useless
#define BIT_MASK_BB_CCKTXPOWERSAVING_N 0x80
#define BIT_MASK_BB_CCKRXPOWERSAVING_N 0x40
#define BIT_MASK_BB_CCKSIDEBAND_N 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
#define BIT_MASK_BB_CCKSCRAMBLE_N 0x8 // Useless
#define BIT_MASK_BB_CCKANTDIVERSITY_N 0x8000
#define BIT_MASK_BB_CCKCARRIERRECOVERY_N 0x4000
#define BIT_MASK_BB_CCKTXRATE_N 0x3000
#define BIT_MASK_BB_CCKDCCANCEL_N 0x0800
#define BIT_MASK_BB_CCKISICANCEL_N 0x0400
#define BIT_MASK_BB_CCKMATCHFILTER_N 0x0200
#define BIT_MASK_BB_CCKEQUALIZER_N 0x0100
#define BIT_MASK_BB_CCKPREAMBLEDETECT_N 0x800000
#define BIT_MASK_BB_CCKFASTFALSECCA_N 0x400000
#define BIT_MASK_BB_CCKCHESTSTART_N 0x300000
#define BIT_MASK_BB_CCKCCACOUNT_N 0x080000
#define BIT_MASK_BB_CCKCS_LIM_N 0x070000
#define BIT_MASK_BB_CCKBISTMODE_N 0x80000000
#define BIT_MASK_BB_CCKCCAMASK_N 0x40000000
#define BIT_MASK_BB_CCKTXDACPHASE_N 0x4
#define BIT_MASK_BB_CCKRXADCPHASE_N 0x20000000 //r_rx_clk
#define BIT_MASK_BB_CCKR_CP_MODE0_N 0x0100
#define BIT_MASK_BB_CCKTXDCOFFSET_N 0xf0
#define BIT_MASK_BB_CCKRXDCOFFSET_N 0xf
#define BIT_MASK_BB_CCKCCAMODE_N 0xc000
#define BIT_MASK_BB_CCKFALSECS_LIM_N 0x3f00
#define BIT_MASK_BB_CCKCS_RATIO_N 0xc00000
#define BIT_MASK_BB_CCKCORGBIT_SEL_N 0x300000
#define BIT_MASK_BB_CCKPD_LIM_N 0x0f0000
#define BIT_MASK_BB_CCKNEWCCA_N 0x80000000
#define BIT_MASK_BB_CCKRXHPOFIG_N 0x8000
#define BIT_MASK_BB_CCKRXIG_N 0x7f00
#define BIT_MASK_BB_CCKLNAPOLARITY_N 0x800000
#define BIT_MASK_BB_CCKRX1STGAIN_N 0x7f0000
#define BIT_MASK_BB_CCKRFEXTEND_N 0x20000000 //CCK Rx Iinital gain polarity
#define BIT_MASK_BB_CCKRXAGCSATLEVEL_N 0x1f000000
#define BIT_MASK_BB_CCKRXAGCSATCOUNT_N 0xe0
#define BIT_MASK_BB_CCKRXRFSETTLE_N 0x1f //AGCsamp_dly
#define BIT_MASK_BB_CCKFIXEDRXAGC_N 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define BIT_MASK_BB_CCKANTENNAPOLARITY_N 0x2000
#define BIT_MASK_BB_CCKTXFILTERTYPE_N 0x0c00
#define BIT_MASK_BB_CCKRXAGCREPORTTYPE_N 0x0300
#define BIT_MASK_BB_CCKRXDAGCEN_N 0x80000000
#define BIT_MASK_BB_CCKRXDAGCPERIOD_N 0x20000000
#define BIT_MASK_BB_CCKRXDAGCSATLEVEL_N 0x1f000000
#define BIT_MASK_BB_CCKTIMINGRECOVERY_N 0x800000
#define BIT_MASK_BB_CCKTXC0_N 0x3f0000
#define BIT_MASK_BB_CCKTXC1_N 0x3f000000
#define BIT_MASK_BB_CCKTXC2_N 0x3f
#define BIT_MASK_BB_CCKTXC3_N 0x3f00
#define BIT_MASK_BB_CCKTXC4_N 0x3f0000
#define BIT_MASK_BB_CCKTXC5_N 0x3f000000
#define BIT_MASK_BB_CCKTXC6_N 0x3f
#define BIT_MASK_BB_CCKTXC7_N 0x3f00
#define BIT_MASK_BB_CCKDEBUGPORT_N 0xff0000
#define BIT_MASK_BB_CCKDACDEBUG_N 0x0f000000
#define BIT_MASK_BB_CCKFALSEALARMENABLE_N 0x8000
#define BIT_MASK_BB_CCKFALSEALARMREAD_N 0x4000
#define BIT_MASK_BB_CCKTRSSI_N 0x7f
#define BIT_MASK_BB_CCKRXAGCREPORT_N 0xfe
#define BIT_MASK_BB_CCKRXREPORT_ANTSEL_N 0x80000000
#define BIT_MASK_BB_CCKRXREPORT_MFOFF_N 0x40000000
#define BIT_MASK_BB_CCKRXRXREPORT_SQLOSS_N 0x20000000
#define BIT_MASK_BB_CCKRXREPORT_PKTLOSS_N 0x10000000
#define BIT_MASK_BB_CCKRXREPORT_LOCKEDBIT_N 0x08000000
#define BIT_MASK_BB_CCKRXREPORT_RATEERROR_N 0x04000000
#define BIT_MASK_BB_CCKRXREPORT_RXRATE_N 0x03000000
#define BIT_MASK_BB_CCKRXFACOUNTERLOWER_N 0xff
#define BIT_MASK_BB_CCKRXFACOUNTERUPPER_N 0xff000000
#define BIT_MASK_BB_CCKRXHPAGCSTART_N 0xe000
#define BIT_MASK_BB_CCKRXHPAGCFINAL_N 0x1c00
#define BIT_MASK_BB_CCKRXFALSEALARMENABLE_N 0x8000
#define BIT_MASK_BB_CCKFACOUNTERFREEZE_N 0x4000
#define BIT_MASK_BB_CCKTXPATHSEL_N 0x10000000
#define BIT_MASK_BB_CCKDEFAULTRXPATH_N 0xc000000
#define BIT_MASK_BB_CCKOPTIONRXPATH_N 0x3000000
//
// 5. PageC(0xC00)
//
#define BIT_MASK_BB_NUMOFSTF_N 0x3 // Useless
#define BIT_MASK_BB_SHIFT_L_N 0xc0
#define BIT_MASK_BB_GI_TH_N 0xc
#define BIT_MASK_BB_RXPATHA_N 0x1
#define BIT_MASK_BB_RXPATHB_N 0x2
#define BIT_MASK_BB_RXPATHC_N 0x4
#define BIT_MASK_BB_RXPATHD_N 0x8
#define BIT_MASK_BB_TXPATHA_N 0x1
#define BIT_MASK_BB_TXPATHB_N 0x2
#define BIT_MASK_BB_TXPATHC_N 0x4
#define BIT_MASK_BB_TXPATHD_N 0x8
#define BIT_MASK_BB_TRSSIFREQ_N 0x200
#define BIT_MASK_BB_ADCBACKOFF_N 0x3000
#define BIT_MASK_BB_DFIRBACKOFF_N 0xc000
#define BIT_MASK_BB_TRSSILATCHPHASE_N 0x10000
#define BIT_MASK_BB_RXIDCOFFSET_N 0xff
#define BIT_MASK_BB_RXQDCOFFSET_N 0xff00
#define BIT_MASK_BB_RXDFIRMODE_N 0x1800000
#define BIT_MASK_BB_RXDCNFTYPE_N 0xe000000
#define BIT_MASK_BB_RXIQIMB_A_N 0x3ff
#define BIT_MASK_BB_RXIQIMB_B_N 0xfc00
#define BIT_MASK_BB_RXIQIMB_C_N 0x3f0000
#define BIT_MASK_BB_RXIQIMB_D_N 0xffc00000
#define BIT_MASK_BB_DC_DC_NOTCH_N 0x60000
#define BIT_MASK_BB_RXNBINOTCH_N 0x1f000000
#define BIT_MASK_BB_PD_TH_N 0xf
#define BIT_MASK_BB_PD_TH_OPT2_N 0xc000
#define BIT_MASK_BB_PWED_TH_N 0x700
#define BIT_MASK_BB_IFMF_WIN_L_N 0x800
#define BIT_MASK_BB_PD_OPTION_N 0x1000
#define BIT_MASK_BB_MF_WIN_L_N 0xe000
#define BIT_MASK_BB_BW_SEARCH_L_N 0x30000
#define BIT_MASK_BB_WIN_ENH_L_N 0xc0000
#define BIT_MASK_BB_BW_TH_N 0x700000
#define BIT_MASK_BB_ED_TH2_N 0x3800000
#define BIT_MASK_BB_BW_OPTION_N 0x4000000
#define BIT_MASK_BB_RATIO_TH_N 0x18000000
#define BIT_MASK_BB_WINDOW_L_N 0xe0000000
#define BIT_MASK_BB_SBD_OPTION_N 0x1
#define BIT_MASK_BB_FRAME_TH_N 0x1c
#define BIT_MASK_BB_FS_OPTION_N 0x60
#define BIT_MASK_BB_DC_SLOPE_CHECK_N 0x80
#define BIT_MASK_BB_FGUARD_COUNTER_DC_L_N 0xe00
#define BIT_MASK_BB_FRAME_WEIGHT_SHORT_N 0x7000
#define BIT_MASK_BB_SUB_TUNE_N 0xe00000
#define BIT_MASK_BB_FRAME_DC_LENGTH_N 0xe000000
#define BIT_MASK_BB_SBD_START_OFFSET_N 0x30000000
#define BIT_MASK_BB_FRAME_TH_2_N 0x7
#define BIT_MASK_BB_FRAME_GI2_TH_N 0x38
#define BIT_MASK_BB_GI2_SYNC_EN_N 0x40
#define BIT_MASK_BB_SARCH_SHORT_EARLY_N 0x300
#define BIT_MASK_BB_SARCH_SHORT_LATE_N 0xc00
#define BIT_MASK_BB_SARCH_GI2_LATE_N 0x70000
#define BIT_MASK_BB_CFOANTSUM_N 0x1
#define BIT_MASK_BB_CFOACC_N 0x2
#define BIT_MASK_BB_CFOSTARTOFFSET_N 0xc
#define BIT_MASK_BB_CFOLOOKBACK_N 0x70
#define BIT_MASK_BB_CFOSUMWEIGHT_N 0x80
#define BIT_MASK_BB_DAGCENABLE_N 0x10000
#define BIT_MASK_BB_TXIQIMB_A_N 0x3ff
#define BIT_MASK_BB_TXIQIMB_B_N 0xfc00
#define BIT_MASK_BB_TXIQIMB_C_N 0x3f0000
#define BIT_MASK_BB_TXIQIMB_D_N 0xffc00000
#define BIT_MASK_BB_TXIDCOFFSET_N 0xff
#define BIT_MASK_BB_TXQDCOFFSET_N 0xff00
#define BIT_MASK_BB_TXDFIRMODE_N 0x10000
#define BIT_MASK_BB_TXPESUDONOISEON_N 0x4000000
#define BIT_MASK_BB_TXPESUDONOISE_A_N 0xff
#define BIT_MASK_BB_TXPESUDONOISE_B_N 0xff00
#define BIT_MASK_BB_TXPESUDONOISE_C_N 0xff0000
#define BIT_MASK_BB_TXPESUDONOISE_D_N 0xff000000
#define BIT_MASK_BB_CCADROPOPTION_N 0x20000
#define BIT_MASK_BB_CCADROPTHRES_N 0xfff00000
#define BIT_MASK_BB_EDCCA_H_N 0xf
#define BIT_MASK_BB_EDCCA_L_N 0xf0
#define BIT_MASK_BB_LAMBDA_ED_N 0x300
#define BIT_MASK_BB_RXINITIALGAIN_N 0x7f
#define BIT_MASK_BB_RXANTDIVEN_N 0x80
#define BIT_MASK_BB_RXAGCADDRESSFORLNA_N 0x7f00
#define BIT_MASK_BB_RXHIGHPOWERFLOW_N 0x8000
#define BIT_MASK_BB_RXAGCFREEZETHRES_N 0xc0000
#define BIT_MASK_BB_RXFREEZESTEP_AGC1_N 0x300000
#define BIT_MASK_BB_RXFREEZESTEP_AGC2_N 0xc00000
#define BIT_MASK_BB_RXFREEZESTEP_AGC3_N 0x3000000
#define BIT_MASK_BB_RXFREEZESTEP_AGC0_N 0xc000000
#define BIT_MASK_BB_RXRSSI_CMP_EN_N 0x10000000
#define BIT_MASK_BB_RXQUICKAGCEN_N 0x20000000
#define BIT_MASK_BB_RXAGCFREEZETHRESMODE_N 0x40000000
#define BIT_MASK_BB_RXOVERFLOWCHECKTYPE_N 0x80000000
#define BIT_MASK_BB_RXAGCSHIFT_N 0x7f
#define BIT_MASK_BB_TRSW_TRI_ONLY_N 0x80
#define BIT_MASK_BB_POWERTHRES_N 0x300
#define BIT_MASK_BB_RXAGCEN_N 0x1
#define BIT_MASK_BB_RXAGCTOGETHEREN_N 0x2
#define BIT_MASK_BB_RXAGCMIN_N 0x4
#define BIT_MASK_BB_RXHP_INI_N 0x7
#define BIT_MASK_BB_RXHP_TRLNA_N 0x70
#define BIT_MASK_BB_RXHP_RSSI_N 0x700
#define BIT_MASK_BB_RXHP_BBP1_N 0x7000
#define BIT_MASK_BB_RXHP_BBP2_N 0x70000
#define BIT_MASK_BB_RXHP_BBP3_N 0x700000
#define BIT_MASK_BB_RSSI_H_N 0x7f0000 //the threshold for high power
#define BIT_MASK_BB_RSSI_GEN_N 0x7f000000 //the threshold for ant diversity
#define BIT_MASK_BB_RXSETTLE_TRSW_N 0x7
#define BIT_MASK_BB_RXSETTLE_LNA_N 0x38
#define BIT_MASK_BB_RXSETTLE_RSSI_N 0x1c0
#define BIT_MASK_BB_RXSETTLE_BBP_N 0xe00
#define BIT_MASK_BB_RXSETTLE_RXHP_N 0x7000
#define BIT_MASK_BB_RXSETTLE_ANTSW_RSSI_N 0x38000
#define BIT_MASK_BB_RXSETTLE_ANTSW_N 0xc0000
#define BIT_MASK_BB_RXPROCESSTIME_DAGC_N 0x300000
#define BIT_MASK_BB_RXSETTLE_HSSI_N 0x400000
#define BIT_MASK_BB_RXPROCESSTIME_BBPPW_N 0x800000
#define BIT_MASK_BB_RXANTENNAPOWERSHIFT_N 0x3000000
#define BIT_MASK_BB_RSSITABLESELECT_N 0xc000000
#define BIT_MASK_BB_RXHP_FINAL_N 0x7000000
#define BIT_MASK_BB_RXHTSETTLE_BBP_N 0x7
#define BIT_MASK_BB_RXHTSETTLE_HSSI_N 0x8
#define BIT_MASK_BB_RXHTSETTLE_RXHP_N 0x70
#define BIT_MASK_BB_RXHTSETTLE_BBPPW_N 0x80
#define BIT_MASK_BB_RXHTSETTLE_IDLE_N 0x300
#define BIT_MASK_BB_RXHTSETTLE_RESERVED_N 0x1c00
#define BIT_MASK_BB_RXHTRXHPEN_N 0x8000
#define BIT_MASK_BB_RXHTAGCFREEZETHRES_N 0x30000
#define BIT_MASK_BB_RXHTAGCTOGETHEREN_N 0x40000
#define BIT_MASK_BB_RXHTAGCMIN_N 0x80000
#define BIT_MASK_BB_RXHTAGCEN_N 0x100000
#define BIT_MASK_BB_RXHTDAGCEN_N 0x200000
#define BIT_MASK_BB_RXHTRXHP_BBP_N 0x1c00000
#define BIT_MASK_BB_RXHTRXHP_FINAL_N 0xe0000000
#define BIT_MASK_BB_RXPWRATIOTH_N 0x3
#define BIT_MASK_BB_RXPWRATIOEN_N 0x4
#define BIT_MASK_BB_RXMFHOLD_N 0x3800
#define BIT_MASK_BB_RXPD_DELAY_TH1_N 0x38
#define BIT_MASK_BB_RXPD_DELAY_TH2_N 0x1c0
#define BIT_MASK_BB_RXPD_DC_COUNT_MAX_N 0x600
//#define bRxMF_Hold 0x3800
#define BIT_MASK_BB_RxPD_Delay_TH_N 0x8000
#define BIT_MASK_BB_RxProcess_Delay_N 0xf0000
#define BIT_MASK_BB_RxSearchrange_GI2_Early_N 0x700000
#define BIT_MASK_BB_RxFrame_Guard_Counter_L_N 0x3800000
#define BIT_MASK_BB_RxSGI_Guard_L_N 0xc000000
#define BIT_MASK_BB_RxSGI_Search_L_N 0x30000000
#define BIT_MASK_BB_RxSGI_TH_N 0xc0000000
#define BIT_MASK_BB_DFSCnt0_N 0xff
#define BIT_MASK_BB_DFSCnt1_N 0xff00
#define BIT_MASK_BB_DFSFlag_N 0xf0000
#define BIT_MASK_BB_MFWeightSum_N 0x300000
#define BIT_MASK_BB_MinIdxTH_N 0x7f000000
#define BIT_MASK_BB_DAFormat_N 0x40000
#define BIT_MASK_BB_TxChEmuEnable_N 0x01000000
#define BIT_MASK_BB_TRSWIsolation_A_N 0x7f
#define BIT_MASK_BB_TRSWIsolation_B_N 0x7f00
/*
#define BIT_MASK_BB_TRSWIsolation_C_N 0x7f0000
#define BIT_MASK_BB_TRSWIsolation_D_N 0x7f000000
*/
#define BIT_MASK_BB_ExtLNAGain_N 0x7c00
//
// 6. PageE(0xE00)
//
#define BIT_MASK_BB_STBCEN_N 0x4 // Useless
#define BIT_MASK_BB_ANTENNAMAPPING_N 0x10
#define BIT_MASK_BB_NSS_N 0x20
#define BIT_MASK_BB_CFOANTSUMD_N 0x200
#define BIT_MASK_BB_OFDMDISPWSAVTX_N 0x400000
#define BIT_MASK_BB_PHYCOUNTERRESET_N 0x8000000
#define BIT_MASK_BB_CFOREPORTGET_N 0x4000000
#define BIT_MASK_BB_OFDMCONTINUETX_N 0x10000000
#define BIT_MASK_BB_OFDMSINGLECARRIER_N 0x20000000
#define BIT_MASK_BB_OFDMSINGLETONE_N 0x40000000
/*
#define bRxPath1 0x01
#define bRxPath2 0x02
#define bRxPath3 0x04
#define bRxPath4 0x08
#define bTxPath1 0x10
#define bTxPath2 0x20
*/
#define BIT_MASK_BB_HTDETECT_N 0x100
#define BIT_MASK_BB_CFOEN_N 0x10000
#define BIT_MASK_BB_CFOVALUE_N 0xfff00000
#define BIT_MASK_BB_SIGTONE_RE_N 0x3f
#define BIT_MASK_BB_SIGTONE_IM_N 0x7f00
#define BIT_MASK_BB_COUNTER_CCA_N 0xffff
#define BIT_MASK_BB_COUNTER_PARITYFAIL_N 0xffff0000
#define BIT_MASK_BB_COUNTER_RATEILLEGAL_N 0xffff
#define BIT_MASK_BB_COUNTER_CRC8FAIL_N 0xffff0000
#define BIT_MASK_BB_COUNTER_MCSNOSUPPORT_N 0xffff
#define BIT_MASK_BB_COUNTER_FASTSYNC_N 0xffff
#define BIT_MASK_BB_SHORTCFO_N 0xfff
#define BIT_MASK_BB_SHORTCFOTLENGTH_N 12 //total
#define BIT_MASK_BB_SHORTCFOFLENGTH_N 11 //fraction
#define BIT_MASK_BB_LONGCFO_N 0x7ff
#define BIT_MASK_BB_LONGCFOTLENGTH_N 11
#define BIT_MASK_BB_LONGCFOFLENGTH_N 11
#define BIT_MASK_BB_TAILCFO_N 0x1fff
#define BIT_MASK_BB_TAILCFOTLENGTH_N 13
#define BIT_MASK_BB_TAILCFOFLENGTH_N 12
#define BIT_MASK_BB_MAX_EN_PWDB_N 0xffff
#define BIT_MASK_BB_CC_POWER_DB_N 0xffff0000
#define BIT_MASK_BB_NOISE_PWDB_N 0xffff
#define BIT_MASK_BB_POWERMEASTLENGTH_N 10
#define BIT_MASK_BB_POWERMEASFLENGTH_N 3
#define BIT_MASK_BB_RX_HT_BW_N 0x1
#define BIT_MASK_BB_RXSC_N 0x6
#define BIT_MASK_BB_RX_HT_N 0x8
#define BIT_MASK_BB_NB_INTF_DET_ON_N 0x1
#define BIT_MASK_BB_INTF_WIN_LEN_CFG_N 0x30
#define BIT_MASK_BB_NB_INTF_TH_CFG_N 0x1c0
#define BIT_MASK_BB_RFGAIN_N 0x3f
#define BIT_MASK_BB_TABLESEL_N 0x40
#define BIT_MASK_BB_TRSW_N 0x80
#define BIT_MASK_BB_RXSNR_A_N 0xff
#define BIT_MASK_BB_RXSNR_B_N 0xff00
/*
#define BIT_MASK_BB_RXSNR_C_N 0xff0000
#define BIT_MASK_BB_RXSNR_D_N 0xff000000
*/
#define BIT_MASK_BB_SNREVMTLENGTH_N 8
#define BIT_MASK_BB_SNREVMFLENGTH_N 1
#define BIT_MASK_BB_CSI1ST_N 0xff
#define BIT_MASK_BB_CSI2ND_N 0xff00
#define BIT_MASK_BB_RXEVM1ST_N 0xff0000
#define BIT_MASK_BB_RXEVM2ND_N 0xff000000
#define BIT_MASK_BB_SIGEVM_N 0xff
#define BIT_MASK_BB_PWDB_N 0xff00
#define BIT_MASK_BB_SGIEN_N 0x10000
#define BIT_MASK_BB_SFACTORQAM1_N 0xf // Useless
#define BIT_MASK_BB_SFACTORQAM2_N 0xf0
#define BIT_MASK_BB_SFACTORQAM3_N 0xf00
#define BIT_MASK_BB_SFACTORQAM4_N 0xf000
#define BIT_MASK_BB_SFACTORQAM5_N 0xf0000
#define BIT_MASK_BB_SFACTORQAM6_N 0xf0000
#define BIT_MASK_BB_SFACTORQAM7_N 0xf00000
#define BIT_MASK_BB_SFACTORQAM8_N 0xf000000
#define BIT_MASK_BB_SFACTORQAM9_N 0xf0000000
#define BIT_MASK_BB_CSISCHEME_N 0x100000
#define BIT_MASK_BB_NOISELVLTOPSET_N 0x3 // Useless
#define BIT_MASK_BB_CHSMOOTH_N 0x4
#define BIT_MASK_BB_CHSMOOTHCFG1_N 0x38
#define BIT_MASK_BB_CHSMOOTHCFG2_N 0x1c0
#define BIT_MASK_BB_CHSMOOTHCFG3_N 0xe00
#define BIT_MASK_BB_CHSMOOTHCFG4_N 0x7000
#define BIT_MASK_BB_MRCMODE_N 0x800000
#define BIT_MASK_BB_THEVMCFG_N 0x7000000
#define BIT_MASK_BB_LOOPFITTYPE_N 0x1 // Useless
#define BIT_MASK_BB_UPDCFO_N 0x40
#define BIT_MASK_BB_UPDCFOOFFDATA_N 0x80
#define BIT_MASK_BB_ADVUPDCFO_N 0x100
#define BIT_MASK_BB_ADVTIMECTRL_N 0x800
#define BIT_MASK_BB_UPDCLKO_N 0x1000
#define BIT_MASK_BB_FC_N 0x6000
#define BIT_MASK_BB_TRACKINGMODE_N 0x8000
#define BIT_MASK_BB_PHCMPENABLE_N 0x10000
#define BIT_MASK_BB_UPDCLKOLTF_N 0x20000
#define BIT_MASK_BB_COMCHCFO_N 0x40000
#define BIT_MASK_BB_CSIESTIMODE_N 0x80000
#define BIT_MASK_BB_ADVUPDEQZ_N 0x100000
#define BIT_MASK_BB_UCHCFG_N 0x7000000
#define BIT_MASK_BB_UPDEQZ_N 0x8000000
#define BIT_MASK_BB_TXAGCRATE18_06_N 0x7f7f7f7f // Useless
#define BIT_MASK_BB_TXAGCRATE54_24_N 0x7f7f7f7f
#define BIT_MASK_BB_TXAGCRATEMCS32_N 0x7f
#define BIT_MASK_BB_TXAGCRATECCK_N 0x7f00
#define BIT_MASK_BB_TXAGCRATEMCS3_MCS0_N 0x7f7f7f7f
#define BIT_MASK_BB_TXAGCRATEMCS7_MCS4_N 0x7f7f7f7f
#define BIT_MASK_BB_TXAGCRATEMCS11_MCS8_N 0x7f7f7f7f
#define BIT_MASK_BB_TXAGCRATEMCS15_MCS12_N 0x7f7f7f7f
//Rx Pseduo noise
#define BIT_MASK_BB_RXPESUDONOISEON_N 0x20000000 // Useless
#define BIT_MASK_BB_RXPESUDONOISE_A_N 0xff
#define BIT_MASK_BB_RXPESUDONOISE_B_N 0xff00
/*
#define BIT_MASK_BB_RXPESUDONOISE_C_N 0xff0000
#define BIT_MASK_BB_RXPESUDONOISE_D_N 0xff000000
*/
#define BIT_MASK_BB_PESUDONOISESTATE_A_N 0xffff
#define BIT_MASK_BB_PESUDONOISESTATE_B_N 0xffff0000
/*
#define BIT_MASK_BB_PESUDONOISESTATE_C_N 0xffff
#define BIT_MASK_BB_PESUDONOISESTATE_D_N 0xffff0000
*/
//
//7. RF Register
//
//Zebra1
#define BIT_MASK_RF_ZEBRA1_HSSIENABLE_N 0x8 // Useless
#define BIT_MASK_RF_ZEBRA1_TRXCONTROL_N 0xc00
#define BIT_MASK_RF_ZEBRA1_TRXGAINSETTING_N 0x07f
#define BIT_MASK_RF_ZEBRA1_RXCORNER_N 0xc00
#define BIT_MASK_RF_ZEBRA1_TXCHARGEPUMP_N 0x38
#define BIT_MASK_RF_ZEBRA1_RXCHARGEPUMP_N 0x7
#define BIT_MASK_RF_ZEBRA1_CHANNELNUM_N 0xf80
#define BIT_MASK_RF_ZEBRA1_TXLPFBW_N 0x400
#define BIT_MASK_RF_ZEBRA1_RXLPFBW_N 0x600
//Zebra4
#define BIT_MASK_RF_RTL8256REGMODECTRL1_N 0x100 // Useless
#define BIT_MASK_RF_RTL8256REGMODECTRL0_N 0x40
#define BIT_MASK_RF_RTL8256_TXLPFBW_N 0x18
#define BIT_MASK_RF_RTL8256_RXLPFBW_N 0x600
//RTL8258
#define BIT_MASK_RF_RTL8258_TXLPFBW_N 0xc // Useless
#define BIT_MASK_RF_RTL8258_RXLPFBW_N 0xc00
#define BIT_MASK_RF_RTL8258_RSSILPFBW_N 0xc0
#endif //#if IS_RTL88XX_N
// Other Common setting bit define
//byte endable for sb_write
#define BIT_MASK_SET_BYTE0_COMMON 0x1 // Useless
#define BIT_MASK_SET_BYTE1_COMMON 0x2
#define BIT_MASK_SET_BYTE2_COMMON 0x4
#define BIT_MASK_SET_BYTE3_COMMON 0x8
#define BIT_MASK_SET_WORD0_COMMON 0x3
#define BIT_MASK_SET_WORD1_COMMON 0xc
#define BIT_MASK_SET_DWORD_COMMON 0xf
//for PutRegsetting & GetRegSetting BitMask
#define BIT_MASK_SET_MASKBYTE0_COMMON 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
#define BIT_MASK_SET_MASKBYTE1_COMMON 0xff00
#define BIT_MASK_SET_MASKBYTE2_COMMON 0xff0000
#define BIT_MASK_SET_MASKBYTE3_COMMON 0xff000000
#define BIT_MASK_SET_MASKHWORD_COMMON 0xffff0000
#define BIT_MASK_SET_MASKLWORD_COMMON 0x0000ffff
#define BIT_MASK_SET_MASKDWORD_COMMON 0xffffffff
#define BIT_MASK_SET_MASKH4BITS_COMMON 0xf0000000
#define BIT_MASK_SET_MASKH3BYTES_COMMON 0xffffff00
#define BIT_MASK_SET_MASKOFDM_D_COMMON 0xffc00000
#define BIT_MASK_SET_MASKCCK_COMMON 0x3f3f3f3f
//for PutRFRegsetting & GetRFRegSetting BitMask
#define BIT_MASK_SET_MASK12BITS_COMMON 0xfff // RF Reg mask bits
#define BIT_MASK_SET_MASK20BITS_COMMON 0xfffff // RF Reg mask bits T65 RF
#endif//__INC_HALCOMPHYBIT_H

430
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/HalHeader/HalComPhyReg.h Executable file
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@ -0,0 +1,430 @@
#ifndef __INC_HALCOMPHYREG_BB_H
#define __INC_HALCOMPHYREG_BB_H
#if IS_RTL88XX_AC
//
// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
// 3. RF register 0x00-2E
// 4. Bit Mask for BB/RF register
// 5. Other defintion for BB/RF R/W
//
//============Programming guide Start=====================
/*
BB REG define rules
1. For all reg define, it should be prefixed by " REG_BB"
RF REG define rules
1. For all reg define, it should be prefixed by " REG_RF"
*/
/**** page 8 ****/
#define REG_BB_CCKENABLE_AC 0x808 // OFDM/CCK block enable
#define REG_BB_RXPATH_AC 0x808 // Rx antenna
#define REG_BB_TXPATH_AC 0x80c // Tx antenna
#define REG_BB_AGC_TABLE_AC 0x82c // AGC tabel select
#define REG_BB_PWED_TH_AC 0x830
#define REG_BB_BWINDICATION_AC 0x834
#define REG_BB_CCAONSEC_AC 0x838
#define REG_BB_L1PEAKTH_AC 0x848
#define REG_BB_FC_AREA_AC 0x860 // fc_area
#define REG_BB_FPGA0_XB_RFINTERFACEOE_AC 0x864
#define REG_BB_FPGA0_XAB_RFINTERFACESW_AC 0x870 // RF Interface Software Control
#define REG_BB_FPGA0_XCD_RFINTERFACESW_AC 0x874
#define REG_BB_FPGA0_XAB_RFPARAMETER_AC 0x878 // RF Parameter
#define REG_BB_FPGA0_XCD_RFPARAMETER_AC 0x87c
#define REG_BB_FPGA0_ANALOGPARAMETER1_AC 0x880 // Crystal cap setting RF-R/W protection for parameter4??
#define REG_BB_FPGA0_ANALOGPARAMETER2_AC 0x884
#define REG_BB_FPGA0_ANALOGPARAMETER3_AC 0x888
#define REG_BB_FPGA0_ADDACLOCKEN_AC 0x888 // enable ad/da clock1 for dual-phy
#define REG_BB_FPGA0_ANALOGPARAMETER4_AC 0x88c
#define REG_BB_EDCCA_AC 0x8a4 // EDCCA
#define REG_BB_RFMOD_AC 0x8ac //RF mode
#define REG_BB_HSSIREAD_AC 0x8b0 // RF read addr
#define REG_BB_FC_ENABL_VHT_AC 0x8c0
#define REG_BB_VHTLEN_USE_LSIG_AC 0x8c3 // Use LSIG for VHT length
#define REG_BB_ADC_BUF_CLK_AC 0x8c4
/**** page 9 ****/
#define REG_BB_SINGLETONE_CONTTX_AC 0x914
#define REG_BB_AGC_TABLE_AC_V2 0x958
#define REG_BB_TX_PATH_SEL_1 0x93c
#define REG_BB_TX_PATH_SEL_2 0x940
/**** page a ****/
#define REG_BB_CCK_SYSTEM_AC 0xa00 // for cck sideband
#define REG_BB_CCK_RX_AC 0xa04 // for cck rx path selection
#define REG_BB_CCK_CCA_AC 0xa08 // cca threshold
// CCK TX scaling
#define REG_BB_CCK_TXFILTER1_AC 0xa20
#define REG_BB_CCK_TXFILTER2_AC 0xa24
#define REG_BB_CCK_TXFILTER3_MSK_AC 0xa28
#define REG_BB_CCK_FALSEALARM_AC 0xa5c // counter for cck false alarm
/**** page b ****/
// RSSI Dump
#define REG_BB_A_RSSIDUMP_AC 0xBF0
#define REG_BB_B_RSSIDUMP_AC 0xBF1
#define REG_BB_S1_RXEVMDUMP_AC 0xBF4
#define REG_BB_S2_RXEVMDUMP_AC 0xBF5
#define REG_BB_A_RXSNRDUMP_AC 0xBF6
#define REG_BB_B_RXSNRDUMP_AC 0xBF7
#define REG_BB_A_CFOSHORTDUMP_AC 0xBF8
#define REG_BB_B_CFOSHORTDUMP_AC 0xBFA
#define REG_BB_A_CFOLONGDUMP_AC 0xBEC
#define REG_BB_B_CFOLONGDUMP_AC 0xBEE
// YN: mask the following register definition temporarily
//#define REG_BB_PDP_ANTA_AC 0xb00
//#define REG_BB_PDP_ANTA_4_AC 0xb04
//#define REG_BB_CONFIG_PMPD_ANTA_AC 0xb28
//#define REG_BB_CONFIG_ANTA_AC 0xb68
//#define REG_BB_CONFIG_ANTB_AC 0xb6c
//#define REG_BB_PDP_ANTB_AC 0xb70
//#define REG_BB_PDP_ANTB_4_AC 0xb74
//#define REG_BB_CONFIG_PMPD_ANTB_AC 0xb98
//#define REG_BB_APK_AC 0xbd8
/**** page c ****/
#define REG_BB_A_RXIQC_AB_AC 0xc10 //RxIQ imblance matrix coeff. A & B
#define REG_BB_A_RXIQC_CD_AC 0xc14 //RxIQ imblance matrix coeff. C & D
#define REG_BB_AGC_TABLE_AC_V1 0xc1c
// TX AGC
#define REG_BB_TXAGC_A_CCK11_CCK1_AC 0xc20
#define REG_BB_TXAGC_A_OFDM18_OFDM6_AC 0xc24
#define REG_BB_TXAGC_A_OFDM54_OFDM24_AC 0xc28
#define REG_BB_TXAGC_A_MCS3_MCS0_AC 0xc2c
#define REG_BB_TXAGC_A_MCS7_MCS4_AC 0xc30
#define REG_BB_TXAGC_A_MCS11_MCS8_AC 0xc34
#define REG_BB_TXAGC_A_MCS15_MCS12_AC 0xc38
#define REG_BB_TXAGC_A_NSS1INDEX3_NSS1INDEX0_AC 0xc3c
#define REG_BB_TXAGC_A_NSS1INDEX7_NSS1INDEX4_AC 0xc40
#define REG_BB_TXAGC_A_NSS2INDEX1_NSS1INDEX8_AC 0xc44
#define REG_BB_TXAGC_A_NSS2INDEX5_NSS2INDEX2_AC 0xc48
#define REG_BB_TXAGC_A_NSS2INDEX9_NSS2INDEX6_AC 0xc4c
// DIG-related
#define REG_BB_A_IGI_AC 0xc50 // Initial Gain for path-A
// AFE-related
#define REG_BB_A_AFEPWR1_AC 0xc60 // dynamic AFE power control
#define REG_BB_A_AFEPWR2_AC 0xc64 // dynamic AFE power control
#define REG_BB_A_RX_WAITCCA_TX_CCKRFON_AC 0xc68
#define REG_BB_A_TX_CCKBBON_OFDMRFON_AC 0xc6c
#define REG_BB_A_TX_OFDMBBON_TX2RX_AC 0xc70
#define REG_BB_A_TX2TX_RXCCK_AC 0xc74
#define REG_BB_A_RX_OFDM_WAITRIFS_AC 0xc78
#define REG_BB_A_RX2RX_BT_AC 0xc7c
#define REG_BB_A_SLEEP_NAV_AC 0xc80
#define REG_BB_A_PMPD_AC 0xc84
#define REG_BB_A_LSSIWRITE_AC 0xc90 // RF write addr
#define REG_BB_A_RFE_PINMUX_AC 0xcb0 // Path_A RFE cotrol pinmux
#define REG_BB_A_RFE_AC 0xcb8 // Path_A RFE cotrol
/**** page d ****/
#define REG_BB_A_PIREAD_AC 0xd04 // RF readback with PI
#define REG_BB_B_PIREAD_AC 0xd44 // RF readback with PI
#define REG_BB_A_SIREAD_AC 0xd08 // RF readback with SI
#define REG_BB_B_SIREAD_AC 0xd48 // RF readback with SI
/**** page e ****/
// RXIQC
#define REG_BB_B_TXSCALE_AC 0xe1c // Path_B TX scaling factor
#define REG_BB_B_RXIQC_AB_AC 0xe10 //RxIQ imblance matrix coeff. A & B
#define REG_BB_B_RXIQC_CD_AC 0xe14 //RxIQ imblance matrix coeff. C & D
// TX AGC
#define REG_BB_TXAGC_B_CCK11_CCK1_AC 0xe20
#define REG_BB_TXAGC_B_OFDM18_OFDM6_AC 0xe24
#define REG_BB_TXAGC_B_OFDM54_OFDM24_AC 0xe28
#define REG_BB_TXAGC_B_MCS3_MCS0_AC 0xe2c
#define REG_BB_TXAGC_B_MCS7_MCS4_AC 0xe30
#define REG_BB_TXAGC_B_MCS11_MCS8_AC 0xe34
#define REG_BB_TXAGC_B_MCS15_MCS12_AC 0xe38
#define REG_BB_TXAGC_B_NSS1INDEX3_NSS1INDEX0_AC 0xe3c
#define REG_BB_TXAGC_B_NSS1INDEX7_NSS1INDEX4_AC 0xe40
#define REG_BB_TXAGC_B_NSS2INDEX1_NSS1INDEX8_AC 0xe44
#define REG_BB_TXAGC_B_NSS2INDEX5_NSS2INDEX2_AC 0xe48
#define REG_BB_TXAGC_B_NSS2INDEX9_NSS2INDEX6_AC 0xe4c
// DIG-related
#define REG_BB_B_IGI_AC 0xe50 // Initial Gain for path-B
#define REG_BB_B_LSSIWRITE_AC 0xe90 // RF write addr
// Misc functions
#define REG_BB_B_RFE_PINMUX_AC 0xeb0 // Path_B RFE control pinmux
#define REG_BB_B_RFE_AC 0xeb8 // Path_B RFE control
/**** page f ****/
// DIG-related
#define REG_BB_OFDM_FALSEALARM1_AC 0xf48 // counter for break
#define REG_BB_OFDM_FALSEALARM2_AC 0xf4c // counter for spoofing
// Report-related
#define REG_BB_OFDM_SHORTCFOAB_AC 0xf60
#define REG_BB_OFDM_LONGCFOAB_AC 0xf64
#define REG_BB_OFDM_ENDCFOAB_AC 0xf70
#define REG_BB_OFDM_AGCREPORT_AC 0xf84
#define REG_BB_OFDM_RXSNR_AC 0xf88
#define REG_BB_OFDM_RXEVMCSI_AC 0xf8c
#define REG_BB_OFDM_SIGREPORT_AC 0xf90
/**** page 19 ****/
//TX BeamForming
#define REG_BB_TXBF_ANT_SET_BF1 0x19ac
#define REG_BB_TXBF_ANT_SET_BF0 0x19b4
//////////////////////////////////////
// RF Register
//
#define REG_RF_AC_AC 0x00
#define REG_RF_RF_TOP_AC 0x07
#define REG_RF_TXLOK_AC 0x08
#define REG_RF_TXAPK_AC 0x0B
#define REG_RF_CHNLBW_AC 0x18 // RF channel and BW switch
#define REG_RF_TXLCTANK_AC 0x54
#define REG_RF_APK_AC 0x63
#define REG_BRF_CHNLBW_MOD_AG_AC 0x70300
#define REG_BRF_CHNLBW_BW_AC 0xc00
#define REG_RF_RCK1_AC 0x1c
#define REG_RF_RCK2_AC 0x1d
#define REG_RF_RCK3_AC 0x1e
#define REG_RF_LCK_AC 0xB4
#define REG_BB_BRFREGOFFSETMASK_AC 0xfffff
#endif //#if IS_RTL88XX_AC
#if IS_RTL88XX_N
//
// 2. BB Register Page8(0x800)
//
#define REG_BB_FPGA0_RFMOD_N 0x800 //RF mode & CCK TxSC // RF BW Setting??
#define REG_BB_FPGA0_TXINFO_N 0x804 // Status report??
#define REG_BB_FPGA0_PSDFUNCTION_N 0x808
#define REG_BB_FPGA0_TXGAINSTAGE_N 0x80c // Set TX PWR init gain?
#define REG_BB_FPGA0_RFTIMING1_N 0x810 // Useless now
#define REG_BB_FPGA0_RFTIMING2_N 0x814
#define REG_BB_PRIMESC_N 0x818
#define REG_BB_FPGA0_XA_HSSIPARAMETER1_N 0x820 // RF 3 wire register
#define REG_BB_FPGA0_XA_HSSIPARAMETER2_N 0x824
#define REG_BB_FPGA0_XB_HSSIPARAMETER1_N 0x828
#define REG_BB_FPGA0_XB_HSSIPARAMETER2_N 0x82c
#define REG_BB_TXAGC_B_RATE18_06_N 0x830
#define REG_BB_TXAGC_B_RATE54_24_N 0x834
#define REG_BB_TXAGC_B_CCK5_1_MCS32_N 0x838
#define REG_BB_TXAGC_B_MCS03_MCS00_N 0x83c
#define REG_BB_FPGA0_XA_LSSIPARAMETER_N 0x840
#define REG_BB_FPGA0_XB_LSSIPARAMETER_N 0x844
#define REG_BB_TXAGC_B_MCS07_MCS04_N 0x848
#define REG_BB_TXAGC_B_MCS11_MCS08_N 0x84c
#define REG_BB_FPGA0_RFWAKEUPPARAMETER_N 0x850 // Useless now
#define REG_BB_FPGA0_RFSLEEPUPPARAMETER_N 0x854
#define REG_BB_FPGA0_XAB_SWITCHCONTROL_N 0x858 // RF Channel switch
#define REG_BB_FPGA0_XCD_SWITCHCONTROL_N 0x85c
#define REG_BB_FPGA0_XA_RFINTERFACEOE_N 0x860 // RF Channel switch
#define REG_BB_FPGA0_XB_RFINTERFACEOE_N 0x864
#define REG_BB_TXAGC_B_MCS15_MCS12_N 0x868
#define REG_BB_TXAGC_A_CCK11_2_B_CCK11_N 0x86c
#define REG_BB_FPGA0_XAB_RFINTERFACESW_N 0x870 // RF Interface Software Control
#define REG_BB_FPGA0_XCD_RFINTERFACESW_N 0x874
#define REG_BB_FPGA0_XAB_RFPARAMETER_N 0x878 // RF Parameter
#define REG_BB_FPGA0_XCD_RFPARAMETER_N 0x87c
#define REG_BB_FPGA0_ANALOGPARAMETER1_N 0x880 // Crystal cap setting RF-R/W protection for parameter4??
#define REG_BB_FPGA0_ANALOGPARAMETER2_N 0x884
#define REG_BB_FPGA0_ANALOGPARAMETER3_N 0x888 // Useless now
#define REG_BB_FPGA0_ANALOGPARAMETER4_N 0x88c
#define REG_BB_FPGA0_XA_LSSIREADBACK_N 0x8a0 // Tranceiver LSSI Readback
#define REG_BB_FPGA0_XB_LSSIREADBACK_N 0x8a4
#define REG_BB_FPGA0_PSDREPORT_N 0x8b4 // Useless now
#define REG_BB_TRANSCEIVERA_HSPI_READBACK_N 0x8b8
#define REG_BB_TRANSCEIVERB_HSPI_READBACK_N 0x8bc
#define REG_BB_FPGA0_XAB_RFINTERFACERB_N 0x8e0 // Useless now // RF Interface Readback Value
//
// 3. BB Register Page9(0x900)
//
#define REG_BB_FPGA1_RFMOD_N 0x900 //RF mode & OFDM TxSC // RF BW Setting??
#define REG_BB_FPGA1_TXBLOCK_N 0x904 // Useless now
#define REG_BB_FPGA1_DEBUGSELECT_N 0x908 // Useless now
#define REG_BB_FPGA1_TXINFO_N 0x90c // Useless now // Status report??
//
// 4. BB Register PageA(0xA00)
//
// Set Control channel to upper or lower. These settings are required only for 40MHz
#define REG_BB_CCK0_SYSTEM_N 0xa00
#define REG_BB_CCK0_AFESETTING_N 0xa04 // Disable init gain now // Select RX path by RSSI
#define REG_BB_CCK0_CCA_N 0xa08 // Disable init gain now // Init gain
#define REG_BB_CCK0_RXAGC1_N 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define REG_BB_CCK0_RXAGC2_N 0xa10 //AGC & DAGC
#define REG_BB_CCK0_RXHP_N 0xa14
#define REG_BB_CCK0_DSPPARAMETER1_N 0xa18 //Timing recovery & Channel estimation threshold
#define REG_BB_CCK0_DSPPARAMETER2_N 0xa1c //SQ threshold
#define REG_BB_CCK0_TXFILTER1_N 0xa20
#define REG_BB_CCK0_TXFILTER2_N 0xa24
#define REG_BB_CCK0_DEBUGPORT_N 0xa28 //debug port and Tx filter3
#define REG_BB_CCK0_FALSEALARMREPORT_N 0xa2c //0xa2d useless now 0xa30-a4f channel report
#define REG_BB_CCK0_TRSSIREPORT_N 0xa50
#define REG_BB_CCK0_RXREPORT_N 0xa54 //0xa57
#define REG_BB_CCK0_FACOUNTERLOWER_N 0xa5c //0xa5b
#define REG_BB_CCK0_FACOUNTERUPPER_N 0xa58 //0xa5c
//
// 5. BB Register PageC(0xC00)
//
#define REG_BB_OFDM0_LSTF_N 0xc00
#define REG_BB_OFDM0_TRXPATHENABLE_N 0xc04
#define REG_BB_OFDM0_TRMUXPAR_N 0xc08
#define REG_BB_OFDM0_TRSWISOLATION_N 0xc0c
#define REG_BB_OFDM0_XARXAFE_N 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
#define REG_BB_OFDM0_XARXIQIMBALANCE_N 0xc14 //RxIQ imblance matrix
#define REG_BB_OFDM0_XBRXAFE_N 0xc18
#define REG_BB_OFDM0_XBRXIQIMBALANCE_N 0xc1c
/*
#define REG_BB_OFDM0_XCRXAFE_N 0xc20
#define REG_BB_OFDM0_XCRXIQIMBALANCE_N 0xc24
#define REG_BB_OFDM0_XDRXAFE_N 0xc28
#define REG_BB_OFDM0_XDRXIQIMBALANCE_N 0xc2c
*/
#define REG_BB_OFDM0_RXDETECTOR1_N 0xc30 //PD,BW & SBD // DM tune init gain
#define REG_BB_OFDM0_RXDETECTOR2_N 0xc34 //SBD & Fame Sync.
#define REG_BB_OFDM0_RXDETECTOR3_N 0xc38 //Frame Sync.
#define REG_BB_OFDM0_RXDETECTOR4_N 0xc3c //PD, SBD, Frame Sync & Short-GI
#define REG_BB_OFDM0_RXDSP_N 0xc40 //Rx Sync Path
#define REG_BB_OFDM0_CFOANDDAGC_N 0xc44 //CFO & DAGC
#define REG_BB_OFDM0_CCADROPTHRESHOLD_N 0xc48 //CCA Drop threshold
#define REG_BB_OFDM0_ECCATHRESHOLD_N 0xc4c // energy CCA
#define REG_BB_OFDM0_XAAGCCORE1_N 0xc50 // DIG
#define REG_BB_OFDM0_XAAGCCORE2_N 0xc54
#define REG_BB_OFDM0_XBAGCCORE1_N 0xc58
#define REG_BB_OFDM0_XBAGCCORE2_N 0xc5c
/*
#define REG_BB_OFDM0_XCAGCCORE1_N 0xc60
#define REG_BB_OFDM0_XCAGCCORE2_N 0xc64
#define REG_BB_OFDM0_XDAGCCORE1_N 0xc68
#define REG_BB_OFDM0_XDAGCCORE2_N 0xc6c
*/
#define REG_BB_OFDM0_AGCPARAMETER1_N 0xc70
#define REG_BB_OFDM0_AGCPARAMETER2_N 0xc74
#define REG_BB_OFDM0_AGCRSSITABLE_N 0xc78
#define REG_BB_OFDM0_HTSTFAGC_N 0xc7c
#define REG_BB_OFDM0_XATXIQIMBALANC_N 0xc80 // TX PWR TRACK and DIG
#define REG_BB_OFDM0_XATXAFE_N 0xc84
#define REG_BB_OFDM0_XBTXIQIMBALANCE_N 0xc88
#define REG_BB_OFDM0_XBTXAFE_N 0xc8c
#define REG_BB_OFDM0_XCTXIQIMBALANCE_N 0xc90
#define REG_BB_OFDM0_XCTXAFE_N 0xc94
#define REG_BB_OFDM0_XDTXIQIMBALANCE_N 0xc98
#define REG_BB_OFDM0_XDTXAFE_N 0xc9c
#define REG_BB_OFDM0_RXIQEXTANTA_N 0xca0
#define REG_BB_OFDM0_RXHPPARAMETER_N 0xce0
#define REG_BB_OFDM0_TXPSEUDONOISEWGT_N 0xce4
#define REG_BB_OFDM0_FRAMESYNC_N 0xcf0
#define REG_BB_OFDM0_DFSREPORT_N 0xcf4
#define REG_BB_OFDM0_TXCOEFF1_N 0xca4
#define REG_BB_OFDM0_TXCOEFF2_N 0xca8
#define REG_BB_OFDM0_TXCOEFF3_N 0xcac
#define REG_BB_OFDM0_TXCOEFF4_N 0xcb0
#define REG_BB_OFDM0_TXCOEFF5_N 0xcb4
#define REG_BB_OFDM0_TXCOEFF6_N 0xcb8
//
// 6. BB Register PageD(0xD00)
//
#define REG_BB_OFDM1_LSTF_N 0xd00
#define REG_BB_OFDM1_TRXPATHENABLE_N 0xd04
#define REG_BB_OFDM1_CFO_N 0xd08 // No setting now
#define REG_BB_OFDM1_CSI1_N 0xd10
#define REG_BB_OFDM1_SBD_N 0xd14
#define REG_BB_OFDM1_CSI2_N 0xd18
#define REG_BB_OFDM1_CFOTRACKING_N 0xd2c
#define REG_BB_OFDM1_TRXMESAURE1_N 0xd34
#define REG_BB_OFDM1_INTFDET_N 0xd3c
#define REG_BB_OFDM1_PSEUDONOISESTATEAB_N 0xd50
#define REG_BB_OFDM1_PSEUDONOISESTATECD_N 0xd54
#define REG_BB_OFDM1_RXPSEUDONOISEWGT_N 0xd58
#define REG_BB_OFDM_PHYCOUNTER1_N 0xda0 //cca, parity fail
#define REG_BB_OFDM_PHYCOUNTER2_N 0xda4 //rate illegal, crc8 fail
#define REG_BB_OFDM_PHYCOUNTER3_N 0xda8 //MCS not support
#define REG_BB_OFDM_SHORTCFOAB_N 0xdac // No setting now
#define REG_BB_OFDM_SHORTCFOCD_N 0xdb0
#define REG_BB_OFDM_LONGCFOAB_N 0xdb4
#define REG_BB_OFDM_LONGCFOCD_N 0xdb8
#define REG_BB_OFDM_TAILCFOAB_N 0xdbc
#define REG_BB_OFDM_TAILCFOCD_N 0xdc0
#define REG_BB_OFDM_PWMEASURE1_N 0xdc4
#define REG_BB_OFDM_PWMEASURE2_N 0xdc8
#define REG_BB_OFDM_BWREPORT_N 0xdcc
#define REG_BB_OFDM_AGCREPORT_N 0xdd0
#define REG_BB_OFDM_RXSNR_N 0xdd4
#define REG_BB_OFDM_RXEVMCSI_N 0xdd8
#define REG_BB_OFDM_SIGREPORT_N 0xddc
//
// 6. BB Register PageE(0xE00)
//
#define REG_BB_TXAGC_A_RATE18_06_N 0xe00
#define REG_BB_TXAGC_A_RATE54_24_N 0xe04
#define REG_BB_TXAGC_A_CCK1_MCS32_N 0xe08
#define REG_BB_TXAGC_A_MCS03_MCS00_N 0xe10
#define REG_BB_TXAGC_A_MCS07_MCS04_N 0xe14
#define REG_BB_TXAGC_A_MCS11_MCS08_N 0xe18
#define REG_BB_TXAGC_A_MCS15_MCS12_N 0xe1c
//
// 7. RF Register 0x00-0x2E
//
//Zebra1
#define REG_RF_ZEBRA1_HSSIENABLE_N 0x0 // Useless now
#define REG_RF_ZEBRA1_TRXENABLE1_N 0x1
#define REG_RF_ZEBRA1_TRXENABLE2_N 0x2
#define REG_RF_ZEBRA1_AGC_N 0x4
#define REG_RF_ZEBRA1_CHARGEPUMP_N 0x5
#define REG_RF_ZEBRA1_CHANNEL_N 0x7 // RF channel switch
#define REG_RF_ZEBRA1_TXGAIN_N 0x8 // Useless now
#define REG_RF_ZEBRA1_TXLPF_N 0x9
#define REG_RF_ZEBRA1_RXLPF_N 0xb
#define REG_RF_ZEBRA1_RXHPFCORNER_N 0xc
#define REG_RF_RFCHANNEL_N 0x18 // RF channel switch For T65 RF 0222d
#define REG_RF_CSI_MASK_N 0x42
//Zebra4
#define REG_RF_GLOBALCTRL_N 0 // Useless now
#define REG_RF_RTL8256_TXLPF_N 19
#define REG_RF_RTL8256_RXLPF_N 11
//RTL8258
#define REG_RF_RTL8258_RSSILPF_N 0xa
#define REG_RF_RTL8258_TXLPF_N 0x11 // Useless now
#define REG_RF_RTL8258_RXLPF_N 0x13
#endif //#if IS_RTL88XX_N
#endif //#ifndef __INC_HALCOMPHYREG_BB_H

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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/HalHeader/HalComRXDesc.h Executable file
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#ifndef __HAL_COM_RXDESC_H__
#define __HAL_COM_RXDESC_H__
/*-------------------------Modification Log-----------------------------------
-------------------------Modification Log-----------------------------------*/
/*--------------------------Include File--------------------------------------*/
#include "HalHWCfg.h"
/*--------------------------Include File--------------------------------------*/
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
//3 RX Buffer Descriptor
//RXBD Desc bit Mask & Shift
//Dword 0 MSK
#define RXBD_DW0_RXBUFSIZE_MSK 0x3FFF
#define RXBD_DW0_LS_MSK 0x1
#define RXBD_DW0_FS_MSK 0x1
#define RXBD_DW0_TOTALRXPKTSIZE_MSK 0xFFFF
//Dword 0 SHIFT
#define RXBD_DW0_RXBUFSIZE_SH 0
#define RXBD_DW0_LS_SH 14
#define RXBD_DW0_FS_SH 15
#define RXBD_DW0_TOTALRXPKTSIZE_SH 16
//Dword 1 MSK
#define RXBD_DW1_PHYADDR_LOW_MSK 0xFFFFFFFF
//Dword 1 SHIFT
#define RXBD_DW1_PHYADDR_LOW_SH 0
//Dword 2 MSK
#define RXBD_DW2_PHYADDR_HIGH_MSK 0xFFFFFFFF
//Dword 2 SHIFT
#define RXBD_DW2_PHYADDR_HIGH_SH 0
//Dword 3 MSK
#define RXBD_DW3_PHYADDR_RSVD_MSK 0xFFFFFFFF
//Dword 3 SHIFT
#define RXBD_DW3_PHYADDR_RSVD_SH 0
//3 RX WiFi Info
//======RX Desc bit Mask & Shift=======
//Dword0
#define RX_DW0_PKT_LEN_MSK 0x3FFF
#define RX_DW0_CRC32_MSK 0x1
#define RX_DW0_ICVERR_MSK 0x1
#define RX_DW0_DRV_INFO_SIZE_MSK 0xF
#define RX_DW0_SECURITY_MSK 0x7
#define RX_DW0_QOS_MSK 0x1
#define RX_DW0_SHIFT_MSK 0x3
#define RX_DW0_PHYST_MSK 0x1
#define RX_DW0_SWDEC_MSK 0x1
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW0_RSVD28_29_MSK 0x3
#endif
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW0_PHYPKTIDC_MSK 0x1
#define RX_DW0_RSVD_29_MSK 0x1
#endif
#define RX_DW0_EOR_MSK 0x1
#define RX_DW0_OWN_MSK 0x1
//Dword0
#define RX_DW0_PKT_LEN_SH 0
#define RX_DW0_CRC32_SH 14
#define RX_DW0_ICVERR_SH 15
#define RX_DW0_DRV_INFO_SIZE_SH 16
#define RX_DW0_SECURITY_SH 20
#define RX_DW0_QOS_SH 23
#define RX_DW0_SHIFT_SH 24
#define RX_DW0_PHYST_SH 26
#define RX_DW0_SWDEC_SH 27
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW0_RSVD28_29_SH 28
#endif
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW0_PHYPKTIDC_SH 28
#define RX_DW0_RSVD29_SH 29
#endif
#define RX_DW0_EOR_SH 30
#define RX_DW0_RSVD31_SH 31
//Dword1
#define RX_DW1_MACID_MSK 0x7F
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW1_RSVD7_MSK 0x1
#endif
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW1_EXT_SECTYPE_MSK 0x1
#endif
#define RX_DW1_TID_MSK 0xF
#define RX_DW1_MACID_VLD_MSK 0x1
#define RX_DW1_AMSDU_MSK 0x1
#define RX_DW1_RXID_MATCH_MSK 0x1
#define RX_DW1_PAGGR_MSK 0x1
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW1_A1_FIT_MSK 0xF
#endif
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW1_RSVD_16_19_MSK 0xF
#endif
#define RX_DW1_CHKERR_MSK 0x1
#define RX_DW1_RX_IPV_MSK 0x1
#define RX_DW1_RX_IS_TCP_UDP_MSK 0x1
#define RX_DW1_CHK_VLD_MSK 0x1
#define RX_DW1_PAM_MSK 0x1
#define RX_DW1_PWR_MSK 0x1
#define RX_DW1_MD_MSK 0x1
#define RX_DW1_MF_MSK 0x1
#define RX_DW1_TYPE_MSK 0x3
#define RX_DW1_MC_MSK 0x1
#define RX_DW1_BC_MSK 0x1
//Dword1
#define RX_DW1_MACID_SH 0
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW1_RSVD7_SH 7
#endif
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW1_EXT_SECTYPE_SH 7
#endif
#define RX_DW1_TID_SH 8
#define RX_DW1_MACID_VLD_SH 12
#define RX_DW1_AMSDU_SH 13
#define RX_DW1_RXID_MATCH_SH 14
#define RX_DW1_PAGGR_SH 15
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW1_A1_FIT_SH 16
#endif
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW1_RSVD_16_19_SH 16
#endif
#define RX_DW1_CHKERR_SH 20
#define RX_DW1_RX_IPV_SH 21
#define RX_DW1_RX_IS_TCP_UDP_SH 22
#define RX_DW1_CHK_VLD_SH 23
#define RX_DW1_PAM_SH 24
#define RX_DW1_PWR_SH 25
#define RX_DW1_MD_SH 26
#define RX_DW1_MF_SH 27
#define RX_DW1_TYPE_SH 28
#define RX_DW1_MC_SH 30
#define RX_DW1_BC_SH 31
//Dword2
#define RX_DW2_SEQ_MSK 0xFFF
#define RX_DW2_FRAG_MSK 0xF
#define RX_DW2_RX_IS_QOS_MSK 0x1
#define RX_DW2_RSVD17_MSK 0x1
#define RX_DW2_WLANHD_IV_LEN_MSK 0x3F
#define RX_DW2_HWRSVD_MSK 0xF
#define RX_DW2_C2HPKT_MSK 0x1
#define RX_DW2_RSVD29_30_MSK 0x3
#define RX_DW2_FCS_OK_MSK 0x1
//Dword2
#define RX_DW2_SEQ_SH 0
#define RX_DW2_FRAG_SH 12
#define RX_DW2_RX_IS_QOS_SH 16
#define RX_DW2_RSVD17_SH 17
#define RX_DW2_WLANHD_IV_LEN_SH 18
#define RX_DW2_HWRSVD_SH 24
#define RX_DW2_C2HPKT_SH 28
#define RX_DW2_RSVD29_30_SH 29
#define RX_DW2_FCS_OK_SH 31
//Dword3
#define RX_DW3_RX_RATE_MSK 0x7F
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW3_RSVD7_9_MSK 0x7
#endif
#define RX_DW3_HTC_MSK 0x1
#define RX_DW3_EOSP_MSK 0x1
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW3_BSSID_FIT_MSK 0x7
#else
#define RX_DW3_BSSID_FIT_MSK 0x3
#endif
#define RX_DW3_RSVD14_15_MSK 0x3
#define RX_DW3_DMA_AGG_NUM_MSK 0xFF
#define RX_DW3_RSVD24_28_MSK 0x1F
#define RX_DW3_PATTERN_MATCH_MSK 0x1
#define RX_DW3_UNICAST_MSK 0x1
#define RX_DW3_MAGIC_WAKE_MSK 0x1
//Dword3
#define RX_DW3_RX_RATE_SH 0
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW3_RSVD7_9_SH 7
#endif
#define RX_DW3_HTC_SH 10
#define RX_DW3_EOSP_SH 11
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW3_BSSID_FIT_SH 7
#else
#define RX_DW3_BSSID_FIT_SH 12
#endif
#define RX_DW3_RSVD14_15_SH 14
#define RX_DW3_DMA_AGG_NUM_SH 16
#define RX_DW3_RSVD24_28_SH 24
#define RX_DW3_PATTERN_MATCH_SH 29
#define RX_DW3_UNICAST_SH 30
#define RX_DW3_MAGIC_WAKE_SH 31
//Dword4
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW4_OFDM_SGI_MSK 0x1
#define RX_DW4_CCK_SPLCP_MSK 0x1
#define RX_DW4_LDPC_MSK 0x1
#define RX_DW4_STBC_MSK 0x1
#define RX_DW4_NOT_SOUNDING_MSK 0x1
#define RX_DW4_BW_MSK 0x3
#define RX_DW4_RSVD6_31_MSK 0x3FFFFFF
#endif //#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW4_PATTERN_IDX_MSK 0xFF
#define RX_DW4_RXEOF_MSK 0x1
#define RX_DW4_RX_SCRMBLER_MSK 0x7F
#define RX_DW4_RX_PRE_NDP_VLD_MSK 0x1
#define RX_DW4_MACID_MSK 0x7F
#define RX_DW4_A1_FIT_MSK 0x1F
#define RX_DW4_RSVD29_31_MSK 0x7
#endif //#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
//Dword4
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define RX_DW4_OFDM_SGI_SH 0
#define RX_DW4_CCK_SPLCP_SH 0
#define RX_DW4_LDPC_SH 1
#define RX_DW4_STBC_SH 2
#define RX_DW4_NOT_SOUNDING_SH 3
#define RX_DW4_BW_SH 4
#define RX_DW4_RSVD6_31_SH 6
#endif //#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define RX_DW4_PATTERN_IDX_SH 0
#define RX_DW4_RXEOF_SH 8
#define RX_DW4_RX_SCRMBLER_SH 9
#define RX_DW4_RX_PRE_NDP_VLD_SH 16
#define RX_DW4_MACID_SH 17
#define RX_DW4_A1_FIT_SH 24
#define RX_DW4_RSVD29_31_SH 29
#endif //#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
//Dword5
#define RX_DW5_TSFL_MSK 0xFFFFFFFF
//Dword5
#define RX_DW5_TSFL_SH 0
#endif //CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#endif //__HAL_COM_RXDESC_H__

1928
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/HalHeader/HalComReg.h Executable file
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/HalHeader/HalComTXDesc.h Executable file
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#ifndef __HAL_COM_TXDESC_H__
#define __HAL_COM_TXDESC_H__
/*-------------------------Modification Log-----------------------------------
-------------------------Modification Log-----------------------------------*/
/*--------------------------Include File--------------------------------------*/
#include "HalHWCfg.h"
/*--------------------------Include File--------------------------------------*/
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E|SUPPORT_CHIP_8814A)
//3 TX Buffer Descriptor
//TXBD Desc bit Mask & Shift
//Dword 0 MSK
#define TXBD_DW0_TXBUFSIZE_MSK 0xFFFF
//---Normal Packet
#define TXBD_DW0_PSLEN_MSK 0xFFFF
//---Beacon Packet
#define TXBD_DW0_BCN_PSLEN_MSK 0x7FFF
#define TXBD_DW0_BCN_OWN_MSK 0x1
#define TXBD_DW0_EXTENDTXBUF_MSK 0x1
//Dword 0 SHIFT
#define TXBD_DW0_TXBUFSIZE_SH 0
//---Normal Packet
#define TXBD_DW0_PSLEN_SH 16
//---Beacon Packet
#define TXBD_DW0_BCN_PSLEN_SH 16
#define TXBD_DW0_BCN_OWN_SH 31
#define TXBD_DW0_EXTENDTXBUF_SH 31
//Dword 1 MSK
#define TXBD_DW1_PHYADDR_LOW_MSK 0xFFFFFFFF
//Dword 1 SHIFT
#define TXBD_DW1_PHYADDR_LOW_SH 0
//Dword 2 MSK
#define TXBD_DW2_PHYADDR_HIGH_MSK 0xFFFFFFFF
//Dword 2 SHIFT
#define TXBD_DW2_PHYADDR_HIGH_SH 0
//Dword 3 MSK
#define TXBD_DW3_PHYADDR_RSVD_MSK 0xFFFFFFFF
//Dword 3 SHIFT
#define TXBD_DW3_PHYADDR_RSVD_SH 0
//3 TX WiFI Info
//TX Desc bit Mask & Shift
//Dword 0
#define TX_DW0_TXPKSIZE_MSK 0xFFFF
#define TX_DW0_OFFSET_MSK 0xFF
#define TX_DW0_BMC_MSK 0x1
#define TX_DW0_HTC_MSK 0x1
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW0_LS_MSK 0x1
#define TX_DW0_AMSDU_PAD_EN_MSK 0x1
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW0_RSVD_26_MSK 0x1
#define TX_DW0_RSVD_27_MSK 0x1
#endif
#define TX_DW0_LINIP_MSK 0x1
#define TX_DW0_NOACM_MSK 0x1
#define TX_DW0_GF_MSK 0x1
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW0_DISQSELSEQ_MSK 0x1
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW0_RSVD_31_MSK 0x1
#endif
//Dword 0
#define TX_DW0_TXPKSIZE_SH 0
#define TX_DW0_OFFSET_SH 16
#define TX_DW0_BMC_SH 24
#define TX_DW0_HTC_SH 25
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW0_LS_SH 26
#define TX_DW0_AMSDU_PAD_EN_SH 27
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW0_RSVD_26_SH 26
#define TX_DW0_RSVD_27_SH 27
#endif
#define TX_DW0_LINIP_SH 28
#define TX_DW0_NOACM_SH 29
#define TX_DW0_GF_SH 30
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW0_DISQSELSEQ_SH 31
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW0_RSVD_31_SH 31
#endif
//Dword 1
#define TX_DW1_MACID_MSK 0x7F
#define TX_DW1_RSVD_7_MSK 0x1
#define TX_DW1_QSEL_MSK 0x1F
#define TX_DW1_RDG_NAV_EXT_MSK 0x1
#define TX_DW1_LSIG_TXOP_EN_MSK 0x1
#define TX_DW1_PIFS_MSK 0x1
#define TX_DW1_RATE_ID_MSK 0x1F
#define TX_DW1_EN_DESC_ID_MSK 0x1
#define TX_DW1_SECTYPE_MSK 0x3
#define TX_DW1_PKT_OFFSET_MSK 0x1F
#define TX_DW1_MOREDATA_MSK 0x1
#define TX_DW1_TXOP_PS_CAP_MSK 0x1
#define TX_DW1_TXOP_PS_MODE_MSK 0x1
//Dword 1
#define TX_DW1_MACID_SH 0
#define TX_DW1_RSVD_7_SH 7
#define TX_DW1_QSEL_SH 8
#define TX_DW1_RDG_NAV_EXT_SH 13
#define TX_DW1_LSIG_TXOP_EN_SH 14
#define TX_DW1_PIFS_SH 15
#define TX_DW1_RATE_ID_SH 16
#define TX_DW1_EN_DESC_ID_SH 21
#define TX_DW1_SECTYPE_SH 22
#define TX_DW1_PKT_OFFSET_SH 24
#define TX_DW1_MOREDATA_SH 29
#define TX_DW1_TXOP_PS_CAP_SH 30
#define TX_DW1_TXOP_PS_MODE_SH 31
//Dword 2
#define TX_DW2_P_AID_MSK 0x1FF
#define TX_DW2_RSVD_9_MSK 0x1
#define TX_DW2_CCA_RTS_MSK 0x3
#define TX_DW2_AGG_EN_MSK 0x1
#define TX_DW2_RDG_EN_MSK 0x1
#define TX_DW2_NULL_0_MSK 0x1
#define TX_DW2_NULL_1_MSK 0x1
#define TX_DW2_BK_MSK 0x1
#define TX_DW2_MOREFRAG_MSK 0x1
#define TX_DW2_RAW_MSK 0x1
#define TX_DW2_SPE_RPT_MSK 0x1
#define TX_DW2_AMPDU_DENSITY_MSK 0x7
#define TX_DW2_BT_NULL_MSK 0x1
#define TX_DW2_G_ID_MSK 0x3F
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW2_RSVD_30_MSK 0x1
#define TX_DW2_HW_AES_IV_MSK 0x1
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW2_RSVD30_31_MSK 0x3
#endif
//Dword 2
#define TX_DW2_P_AID_SH 0
#define TX_DW2_RSVD_9_SH 9
#define TX_DW2_CCA_RTS_SH 10
#define TX_DW2_AGG_EN_SH 12
#define TX_DW2_RDG_EN_SH 13
#define TX_DW2_NULL_0_SH 14
#define TX_DW2_NULL_1_SH 15
#define TX_DW2_BK_SH 16
#define TX_DW2_MOREFRAG_SH 17
#define TX_DW2_RAW_SH 18
#define TX_DW2_SPE_RPT_SH 19
#define TX_DW2_AMPDU_DENSITY_SH 20
#define TX_DW2_BT_NULL_SH 23
#define TX_DW2_G_ID_SH 24
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW2_RSVD_30_SH 30
#define TX_DW2_HW_AES_IV_SH 31
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW2_RSVD30_31_SH 30
#endif
//Dword 3
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW3_WHEADER_V1_MSK 0x1F
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW3_WHEADER_MSK 0xF
#define TX_DW3_CHK_EN_MSK 0x1
#endif
#define TX_DW3_EARLY_RATE_MSK 0x1
#define TX_DW3_HW_SSN_SEL_MSK 0x3
#define TX_DW3_USERATE_MSK 0x1
#define TX_DW3_DISRTSFB_MSK 0x1
#define TX_DW3_DISDATAFB_MSK 0x1
#define TX_DW3_CTS2SELF_MSK 0x1
#define TX_DW3_RTSEN_MSK 0x1
#define TX_DW3_HW_RTS_EN_MSK 0x1
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW3_CHK_EN_V1_MSK 0x1
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW3_PORT_ID_MSK 0x1
#endif
#define TX_DW3_NAVUSEHDR_MSK 0x1
#define TX_DW3_USE_MAX_LEN_MSK 0x1
#define TX_DW3_MAX_AGG_NUM_MSK 0x1F
#define TX_DW3_NDPA_MSK 0x3
#define TX_DW3_AMPDU_MAX_TIME_MSK 0xFF
//Dword 3
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW3_WHEADER_V1_SH 0
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW3_WHEADER_SH 0
#define TX_DW3_CHK_EN_SH 4
#endif
#define TX_DW3_EARLY_RATE_SH 5
#define TX_DW3_HW_SSN_SEL_SH 6
#define TX_DW3_USERATE_SH 8
#define TX_DW3_DISRTSFB_SH 9
#define TX_DW3_DISDATAFB_SH 10
#define TX_DW3_CTS2SELF_SH 11
#define TX_DW3_RTSEN_SH 12
#define TX_DW3_HW_RTS_EN_SH 13
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW3_CHK_EN_V1_SH 14
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW3_PORT_ID_SH 14
#endif
#define TX_DW3_NAVUSEHDR_SH 15
#define TX_DW3_USE_MAX_LEN_SH 16
#define TX_DW3_MAX_AGG_NUM_SH 17
#define TX_DW3_NDPA_SH 22
#define TX_DW3_AMPDU_MAX_TIME_SH 24
//Dword 4
#define TX_DW4_DATARATE_MSK 0x7F
#define TX_DW4_TRY_RATE_MSK 0x1
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW4_DATA_RATEFB_LMT_MSK 0x1F
#define TX_DW4_RTS_RATEFB_LMT_MSK 0xF
#endif
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW4_DATA_RTY_LOWEST_RATE_MSK 0x1F
#define TX_DW4_RTS_RTY_LOWEST_RATE_MSK 0xF
#endif
#define TX_DW4_RTY_LMT_EN_MSK 0x1
#define TX_DW4_DATA_RT_LMT_MSK 0x3F
#define TX_DW4_RTSRATE_MSK 0x1F
#define TX_DW4_PCTS_EN_MSK 0x1
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW4_PCTS_MASK_IDX_MSK 0x3
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW4_PCTS_MASK_EN_MSK 0x3
#endif
//Dword 4
#define TX_DW4_DATARATE_SH 0
#define TX_DW4_TRY_RATE_SH 7
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW4_DATA_RATEFB_LMT_SH 8
#define TX_DW4_RTS_RATEFB_LMT_SH 13
#endif
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW4_DATA_RTY_LOWEST_RATE_SH 8
#define TX_DW4_RTS_RTY_LOWEST_RATE_SH 13
#endif
#define TX_DW4_RTY_LMT_EN_SH 17
#define TX_DW4_DATA_RT_LMT_SH 18
#define TX_DW4_RTSRATE_SH 24
#define TX_DW4_PCTS_EN_SH 29
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW4_PCTS_MASK_IDX_SH 30
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW4_PCTS_MASK_EN_SH 30
#endif
//Dword 5
#define TX_DW5_DATA_SC_MSK 0xF
#define TX_DW5_DATA_SHORT_MSK 0x1
#define TX_DW5_DATA_BW_MSK 0x3
#define TX_DW5_DATA_LDPC_MSK 0x1
#define TX_DW5_DATA_STBC_MSK 0x3
#define TX_DW5_VCS_STBC_MSK 0x3
#define TX_DW5_RTS_SHORT_MSK 0x1
#define TX_DW5_RTS_SC_MSK 0xF
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW5_SIGNALING_TA_PKT_MSK 0x3
#define TX_DW5_RSVD19_20_MSK 0x3
#define TX_DW5_PORT_ID_V1_MSK 0x7
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW5_RSVD17_23_MSK 0x7F
#endif
#define TX_DW5_TX_ANT_MSK 0xF
#define TX_DW5_TXPWR_OFSET_MSK 0x7
#define TX_DW5_RSVD31_MSK 0x1
//Dword 5
#define TX_DW5_DATA_SC_SH 0
#define TX_DW5_DATA_SHORT_SH 4
#define TX_DW5_DATA_BW_SH 5
#define TX_DW5_DATA_LDPC_SH 7
#define TX_DW5_DATA_STBC_SH 8
#define TX_DW5_VCS_STBC_SH 10
#define TX_DW5_RTS_SHORT_SH 12
#define TX_DW5_RTS_SC_SH 13
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW5_SIGNALING_TA_PKT_SH 17
#define TX_DW5_RSVD19_20_SH 19
#define TX_DW5_PORT_ID_V1_SH 21
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW5_RSVD17_23_SH 17
#endif
#define TX_DW5_TX_ANT_SH 24
#define TX_DW5_TXPWR_OFSET_SH 28
#define TX_DW5_RSVD31_SH 31
//Dword 6
#define TX_DW6_SW_DEFINE_MSK 0xFFF
#define TX_DW6_MBSSID_MSK 0xF
#define TX_DW6_ANTSEL_A_MSK 0x7
#define TX_DW6_ANTSEL_B_MSK 0x7
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW6_ANT_MAP_A_MSK 0x3
#define TX_DW6_ANT_MAP_B_MSK 0x3
#define TX_DW6_ANT_MAP_C_MSK 0x3
#define TX_DW6_ANT_MAP_D_MSK 0x3
#define TX_DW6_SND_PKT_SEL_MSK 0x3
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW6_ANTSEL_C_MSK 0x7
#define TX_DW6_ANTSEL_D_MSK 0x7
#define TX_DW6_RSVD28_31_MSK 0xF
#endif
//Dword 6
#define TX_DW6_SW_DEFINE_SH 0
#define TX_DW6_MBSSID_SH 12
#define TX_DW6_ANTSEL_A_SH 16
#define TX_DW6_ANTSEL_B_SH 19
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW6_ANT_MAP_A_SH 22
#define TX_DW6_ANT_MAP_B_SH 24
#define TX_DW6_ANT_MAP_C_SH 26
#define TX_DW6_ANT_MAP_D_SH 28
#define TX_DW6_SND_PKT_SEL_SH 30
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW6_ANTSEL_C_SH 22
#define TX_DW6_ANTSEL_D_SH 25
#define TX_DW6_RSVD28_31_SH 28
#endif
//Dword 7
#define TX_DW7_SW_TXBUFF_MSK 0xFFFF
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW7_TSFSEL_MSK 0xF
#define TX_DW7_NTX_MAP_MSK 0xF
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW7_RSVD16_23_MSK 0xFF
#endif
#define TX_DW7_USB_TXAGG_NUM_MSK 0xFF
//Dword 7
#define TX_DW7_SW_TXBUFF_SH 0
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW7_TSFSEL_SH 16
#define TX_DW7_NTX_MAP_SH 20
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW7_RSVD16_23_SH 16
#endif
#define TX_DW7_USB_TXAGG_NUM_SH 24
//Dword 8
#define TX_DW8_RTS_RC_MSK 0x3F
#define TX_DW8_BAR_RTY_TH_MSK 0x3
#define TX_DW8_DATA_RC_MSK 0x3F
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW8_EN_HWEXSEQ_MSK 0x1
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW8_RSVD14_MSK 0x1
#endif
#define TX_DW8_EN_HWSEQ_MSK 0x1
#define TX_DW8_NEXTHEADPAGE_MSK 0xFF
#define TX_DW8_TAILPAGE_MSK 0xFF
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW8_SMH_EN_MSK 0x1
#define TX_DW8_STW_EN_MSK 0x1
#define TX_DW8_STW_ANT_DIS_MSK 0x1
#define TX_DW8_STW_RATE_DIS_MSK 0x1
#define TX_DW8_STW_RB_DIS_MSK 0x1
#define TX_DW8_STW_PKTRE_DIS_MSK 0x1
#define TX_DW8_MAC_CP_MSK 0x1
#define TX_DW8_TXWIFI_CP_MSK 0x1
#endif
//Dword 8
#define TX_DW8_RTS_RC_SH 0
#define TX_DW8_BAR_RTY_TH_SH 6
#define TX_DW8_DATA_RC_SH 8
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW8_EN_HWEXSEQ_SH 14
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW8_RSVD14_SH 14
#endif
#define TX_DW8_EN_HWSEQ_SH 15
#define TX_DW8_NEXTHEADPAGE_SH 16
#define TX_DW8_TAILPAGE_SH 24
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW8_SMH_EN_SH 24
#define TX_DW8_STW_EN_SH 25
#define TX_DW8_STW_ANT_DIS_SH 26
#define TX_DW8_STW_RATE_DIS_SH 27
#define TX_DW8_STW_RB_DIS_SH 28
#define TX_DW8_STW_PKTRE_DIS_SH 29
#define TX_DW8_MAC_CP_SH 30
#define TX_DW8_TXWIFI_CP_SH 31
#endif
//Dword 9
//---Normal Packet
#define TX_DW9_PADDING_LEN_MSK 0x7FF
//---Beacon Packet
#define TX_DW9_GROUPBIT_IE_OFFSET_MSK 0x7F
#define TX_DW9_GROUPBIT_IE_ENABLE_MSK 0x1
#define TX_DW9_TXBFPATH_MSK 0x1
#define TX_DW9_SEQ_MSK 0xFFF
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW9_NEXTHEADPAGE_H_MSK 0xF
#define TX_DW9_TAILPAGE_H_MSK 0xF
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW9_FINAL_DATA_RATE_MSK 0xFF
#endif
//Dword 9
//---Normal Packet
#define TX_DW9_PADDING_LEN_SH 0
//---Beacon Packet
#define TX_DW9_GROUPBIT_IE_OFFSET_SH 0
#define TX_DW9_GROUPBIT_IE_ENABLE_SH 7
#define TX_DW9_TXBFPATH_SH 11
#define TX_DW9_SEQ_SH 12
#if CONFIG_WLANREG_SUPPORT & SUPPORT_CHIP_8814A
#define TX_DW9_NEXTHEADPAGE_H_SH 24
#define TX_DW9_TAILPAGE_H_SH 28
#endif
#if CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E)
#define TX_DW9_FINAL_DATA_RATE_SH 24
#endif
//3 TX Buffer Descriptor Detail
//Dword 0
//3 TX WiFI Info Detail
//Dword 0
//Dword 1
//---QSEL
#define TXDESC_QSEL_TID0 0
#define TXDESC_QSEL_TID1 1
#define TXDESC_QSEL_TID2 2
#define TXDESC_QSEL_TID3 3
#define TXDESC_QSEL_TID4 4
#define TXDESC_QSEL_TID5 5
#define TXDESC_QSEL_TID6 6
#define TXDESC_QSEL_TID7 7
#define TXDESC_QSEL_TID8 8
#define TXDESC_QSEL_TID9 9
#define TXDESC_QSEL_TID10 10
#define TXDESC_QSEL_TID11 11
#define TXDESC_QSEL_TID12 12
#define TXDESC_QSEL_TID13 13
#define TXDESC_QSEL_TID14 14
#define TXDESC_QSEL_TID15 15
#define TXDESC_QSEL_BCN 16
#define TXDESC_QSEL_HIGH 17
#define TXDESC_QSEL_MGT 18
#define TXDESC_QSEL_CMD 19
//Dword 1
#define TXDESC_SECTYPE_NO_ENCRYPTION 0
#define TXDESC_SECTYPE_WEP40_OR_TKIP 1
#define TXDESC_SECTYPE_WAPI 2
#define TXDESC_SECTYPE_AES 3
//Dword 2
//Dword 5
//---DataSC
#define TXDESC_DATASC_DONT_CARE 0
#define TXDESC_DATASC_UPPER 1
#define TXDESC_DATASC_LOWER 2
#define TXDESC_DATASC_DUPLICATE 3
#endif //CONFIG_WLANREG_SUPPORT & (SUPPORT_CHIP_8881A|SUPPORT_CHIP_8192E|SUPPORT_CHIP_8814A)
#endif //__HAL_COM_TXDESC_H__

35
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/WlanHAL/HalHeader/HalHWCfg.h Executable file
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@ -0,0 +1,35 @@
#ifndef __HAL_HW_CFG_H__
#define __HAL_HW_CFG_H__
/*-------------------------Modification Log-----------------------------------
20120416 KaiYuan Add BIT Define
-------------------------Modification Log-----------------------------------*/
/*--------------------------Define -------------------------------------------*/
#ifndef BIT
#define BIT(x) (1 << (x))
#endif
#define SUPPORT_CHIP_8723A BIT1
#define SUPPORT_CHIP_8188E BIT2
#define SUPPORT_CHIP_8881A BIT3
#define SUPPORT_CHIP_8812A BIT4
#define SUPPORT_CHIP_8821A BIT5
#define SUPPORT_CHIP_8723B BIT6
#define SUPPORT_CHIP_8192E BIT7
#define SUPPORT_CHIP_8814A BIT8
//Marco Utility
#define SUPPORT_CHIP_ALL (SUPPORT_CHIP_8723A|SUPPORT_CHIP_8188E| \
SUPPORT_CHIP_8881A|SUPPORT_CHIP_8812A| \
SUPPORT_CHIP_8821A|SUPPORT_CHIP_8723B| \
SUPPORT_CHIP_8192E | SUPPORT_CHIP_8814A)
//Compile Option
#define CONFIG_WLANREG_SUPPORT (SUPPORT_CHIP_8192E|SUPPORT_CHIP_8881A | SUPPORT_CHIP_8814A)
#endif//__HAL_HW_CFG_H__