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T
2024-09-09 08:59:52 +00:00
parent f75098198c
commit 46ba6f09ec
1372 changed files with 1231198 additions and 1184 deletions
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1104
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/Hal8192EReg.h Executable file
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1425
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_BB.c Executable file
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59
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_BB.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8192E_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8192E_H
#define __INC_MP_BB_HW_IMG_8192E_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_AGC_TAB(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_PHY_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_PHY_REG(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_PHY_REG_PG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

6716
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_FW.c Executable file
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72
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_FW.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8192E_SUPPORT == 1)
#ifndef __INC_MP_FW_HW_IMG_8192E_H
#define __INC_MP_FW_HW_IMG_8192E_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8192E_FW_AP(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
/******************************************************************************
* FW_AP_PCIE.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8192E_FW_AP_PCIE(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8192E_FW_NIC(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8192E_FW_WoWLAN(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#endif
#endif // end of HWIMG_SUPPORT

290
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_MAC.c Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8192E_SUPPORT == 1)
static BOOLEAN
CheckPositive(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2,
IN const u4Byte Condition3,
IN const u4Byte Condition4
)
{
u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/
u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4;
u4Byte driver1 = pDM_Odm->CutVersion << 24 |
(pDM_Odm->SupportInterface & 0xF0) << 16 |
pDM_Odm->SupportPlatform << 16 |
pDM_Odm->PackageType << 12 |
(pDM_Odm->SupportInterface & 0x0F) << 8 |
_BoardType;
u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 |
(pDM_Odm->TypeGPA & 0xFF) << 8 |
(pDM_Odm->TypeALNA & 0xFF) << 16 |
(pDM_Odm->TypeAPA & 0xFF) << 24;
u4Byte driver3 = 0;
u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 |
(pDM_Odm->TypeGPA & 0xFF00) |
(pDM_Odm->TypeALNA & 0xFF00) << 8 |
(pDM_Odm->TypeAPA & 0xFF00) << 16;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType));
/*============== Value Defined Check ===============*/
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return FALSE;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return FALSE;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u4Byte bitMask = 0;
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
return TRUE;
if ((cond1 & BIT0) != 0) /*GLNA*/
bitMask |= 0x000000FF;
if ((cond1 & BIT1) != 0) /*GPA*/
bitMask |= 0x0000FF00;
if ((cond1 & BIT2) != 0) /*ALNA*/
bitMask |= 0x00FF0000;
if ((cond1 & BIT3) != 0) /*APA*/
bitMask |= 0xFF000000;
if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/
return TRUE;
else
return FALSE;
} else
return FALSE;
}
static BOOLEAN
CheckNegative(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2
)
{
return TRUE;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u4Byte Array_MP_8192E_MAC_REG[] = {
0x011, 0x000000EB,
0x012, 0x00000007,
0x014, 0x00000075,
0x303, 0x000000A7,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x00000000,
0x446, 0x00000000,
0x447, 0x00000000,
0x448, 0x00000000,
0x449, 0x000000F0,
0x44A, 0x0000000F,
0x44B, 0x0000003E,
0x44C, 0x00000010,
0x44D, 0x00000000,
0x44E, 0x00000000,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x000000F0,
0x452, 0x0000000F,
0x453, 0x00000000,
0x456, 0x0000005E,
0x460, 0x00000066,
0x461, 0x00000066,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x540, 0x00000012,
0x541, 0x00000064,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000050,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000050,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x0000002B,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
void
ODM_ReadAndConfig_MP_8192E_MAC_REG(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte i = 0;
u1Byte cCond;
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
u4Byte ArrayLen = sizeof(Array_MP_8192E_MAC_REG)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8192E_MAC_REG;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_MAC_REG\n"));
while ((i + 1) < ArrayLen) {
v1 = Array[i];
v2 = Array[i + 1];
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
if (v1 & BIT31) {/* positive condition*/
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
if (cCond == COND_ENDIF) {/*end*/
bMatched = TRUE;
bSkipped = FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (cCond == COND_ELSE) { /*else*/
bMatched = bSkipped?FALSE:TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
}
else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT30) { /*negative condition*/
if (bSkipped == FALSE) {
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
bMatched = TRUE;
bSkipped = TRUE;
} else {
bMatched = FALSE;
bSkipped = FALSE;
}
} else
bMatched = FALSE;
}
} else {
if (bMatched)
odm_ConfigMAC_8192E(pDM_Odm, v1, (u1Byte)v2);
}
i = i + 2;
}
}
u4Byte
ODM_GetVersion_MP_8192E_MAC_REG(void)
{
return 51;
}
#endif /* end of HWIMG_SUPPORT*/

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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_MAC.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8192E_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8192E_H
#define __INC_MP_MAC_HW_IMG_8192E_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_MAC_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_MAC_REG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

2210
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_RF.c Executable file
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109
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_RF.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8192E_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8192E_H
#define __INC_MP_RF_HW_IMG_8192E_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_RadioA(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_RadioA(void);
/******************************************************************************
* RadioB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_RadioB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_RadioB(void);
/******************************************************************************
* TxPowerTrack_AP.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_AP(void);
/******************************************************************************
* TxPowerTrack_PCIE.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_PCIE(void);
/******************************************************************************
* TxPowerTrack_SDIO.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_SDIO(void);
/******************************************************************************
* TxPowerTrack_USB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_USB(void);
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TXPWR_LMT(void);
/******************************************************************************
* TXPWR_LMT_8192E_SAR_5mm.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TXPWR_LMT_8192E_SAR_5mm(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TXPWR_LMT_8192E_SAR_5mm(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

3315
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalPhyRf_8192e_AP.c Executable file
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146
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalPhyRf_8192e_AP.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8192E_H__
#define __HAL_PHY_RF_8192E_H__
/*--------------------------Define Parameters-------------------------------*/
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#define IQK_DELAY_TIME_92E 15 //ms
#else
#define IQK_DELAY_TIME_92E 10
#endif
#define index_mapping_NUM_92E 15
#define AVG_THERMAL_NUM_92E 4
#define RF_T_METER_92E 0x42
#include "../HalPhyRf_AP.h"
void ConfigureTxpowerTrack_8192E(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8192E(
IN PVOID pDM_VOID,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
);
void DoIQK_8192E(
PVOID pDM_VOID,
u1Byte DeltaThermalIndex,
u1Byte ThermalValue,
u1Byte Threshold
);
VOID
ODM_TxPwrTrackSetPwr92E(
IN PVOID pDM_VOID,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
);
//1 7. IQK
void
PHY_IQCalibrate_8192E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER Adapter,
#endif
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8192E(
IN PVOID pDM_VOID
);
//
// AP calibrate
//
void
PHY_APCalibrate_8192E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8192E(IN PADAPTER pAdapter);
VOID
_PHY_SaveADDARegisters_92E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn_92E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration_92E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
VOID
_PHY_PathAStandBy(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif /* #ifndef __HAL_PHY_RF_8192E_H__*/

455
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/phydm_RTL8192E.c Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8192E_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_Write_Dynamic_CCA(
IN PDM_ODM_T pDM_Odm,
IN u1Byte CurrentMFstate
)
{
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
if (PrimaryCCA->MF_state != CurrentMFstate){
ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, CurrentMFstate);
}
PrimaryCCA->MF_state = CurrentMFstate;
}
VOID
odm_PrimaryCCA_Check_Init(
IN PDM_ODM_T pDM_Odm)
{
#if((DM_ODM_SUPPORT_TYPE==ODM_WIN) ||(DM_ODM_SUPPORT_TYPE==ODM_AP))
PADAPTER pAdapter = pDM_Odm->Adapter;
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->Monitor_flag = 0;
PrimaryCCA->PriCCA_flag = 0;
PrimaryCCA->CH_offset = 0;
PrimaryCCA->MF_state = 0;
#endif
}
VOID
odm_DynamicPrimaryCCA_Check(
IN PDM_ODM_T pDM_Odm
)
{
if(pDM_Odm->SupportICType != ODM_RTL8192E)
return;
if(!(pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA))
return;
switch (pDM_Odm->SupportPlatform)
{
case ODM_WIN:
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
odm_DynamicPrimaryCCAMP(pDM_Odm);
#endif
break;
case ODM_CE:
#if(DM_ODM_SUPPORT_TYPE==ODM_CE)
#endif
break;
case ODM_AP:
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_DynamicPrimaryCCAAP(pDM_Odm);
#endif
break;
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_DynamicPrimaryCCAMP(
IN PDM_ODM_T pDM_Odm
)
{
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
#else
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
#endif
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
BOOLEAN Is40MHz = FALSE;
u8Byte OFDM_CCA, OFDM_FA, BW_USC_Cnt, BW_LSC_Cnt;
u1Byte SecCHOffset;
u1Byte CurMFstate;
static u1Byte CountDown = Monitor_TIME;
OFDM_CCA = FalseAlmCnt->Cnt_OFDM_CCA;
OFDM_FA = FalseAlmCnt->Cnt_Ofdm_fail;
BW_USC_Cnt = FalseAlmCnt->Cnt_BW_USC;
BW_LSC_Cnt = FalseAlmCnt->Cnt_BW_LSC;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: OFDM CCA=%d\n", OFDM_CCA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: OFDM FA=%d\n", OFDM_FA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: BW_USC=%d\n", BW_USC_Cnt));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: BW_LSC=%d\n", BW_LSC_Cnt));
Is40MHz = *(pDM_Odm->pBandWidth);
SecCHOffset = *(pDM_Odm->pSecChOffset); // NIC: 2: sec is below, 1: sec is above
//DbgPrint("92E: SecCHOffset = %d\n", SecCHOffset);
if(IsAPModeExist(pAdapter)){
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
return;
}
if(!pDM_Odm->bLinked){
return;
}
else{
if(Is40MHz){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Cont Down= %d\n", CountDown));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Primary_CCA_flag=%d\n", PrimaryCCA->PriCCA_flag));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Intf_Type=%d\n", PrimaryCCA->intf_type));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Intf_flag=%d\n", PrimaryCCA->intf_flag ));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Duplicate RTS Flag=%d\n", PrimaryCCA->DupRTS_flag));
//DbgPrint("92E RTS_EN=%d\n", pHalData->RTSEN);
if(PrimaryCCA->PriCCA_flag == 0){
if(SecCHOffset == 2){ // Primary channel is above NOTE: duplicate CTS can remove this condition
if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias))
&& (OFDM_FA>(OFDM_CCA>>1))){
PrimaryCCA->intf_type = 1;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
}
else if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias))
&& (OFDM_FA < (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 2;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
PrimaryCCA->DupRTS_flag = 1;
pHalData->RTSEN = 1;
}
else{
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
}
}
else if (SecCHOffset == 1){
if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt > (BW_LSC_Cnt + BW_Ind_Bias))
&& (OFDM_FA > (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 1;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
}
else if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt>(BW_LSC_Cnt + BW_Ind_Bias))
&& (OFDM_FA < (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 2;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
PrimaryCCA->DupRTS_flag = 1;
pHalData->RTSEN = 1;
}
else{
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
}
}
}
else{ // PrimaryCCA->PriCCA_flag==1
CountDown--;
if(CountDown == 0){
CountDown = Monitor_TIME;
PrimaryCCA->PriCCA_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); // default
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
}
}
}
else{
return;
}
}
}
#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
odm_DynamicPrimaryCCAAP(
IN PDM_ODM_T pDM_Odm
)
{
PADAPTER Adapter = pDM_Odm->Adapter;
prtl8192cd_priv priv = pDM_Odm->priv;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
#else
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
#endif
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte i;
static u4Byte Count_Down = Monitor_TIME;
BOOLEAN STA_BW = FALSE, STA_BW_pre = FALSE, STA_BW_TMP = FALSE;
BOOLEAN bConnected = FALSE;
BOOLEAN Is40MHz = FALSE;
u1Byte SecCHOffset;
u1Byte CurMFstate;
PSTA_INFO_T pstat;
Is40MHz = *(pDM_Odm->pBandWidth);
SecCHOffset = *(pDM_Odm->pSecChOffset); // AP: 1: sec is below, 2: sec is above
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
pstat = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat)){
STA_BW_TMP = pstat->tx_bw;
if(STA_BW_TMP > STA_BW){
STA_BW = STA_BW_TMP;
}
bConnected = TRUE;
}
}
if(Is40MHz){
if(PrimaryCCA->PriCCA_flag == 0){
if(bConnected){
if(STA_BW == 0){ //2 STA BW=20M
PrimaryCCA->PriCCA_flag = 1;
if(SecCHOffset==1){
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
}
else if(SecCHOffset==2){
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
}
}
else{ //2 STA BW=40M
if(PrimaryCCA->intf_flag == 0){
odm_Intf_Detection(pDM_Odm);
}
else{ // intf_flag = 1
if(PrimaryCCA->intf_type == 1){
if(PrimaryCCA->CH_offset == 1){
CurMFstate = MF_USC;
if(SecCHOffset == 1){ // AP, 1: primary is above 2: primary is below
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
}
}
else if(PrimaryCCA->CH_offset == 2){
CurMFstate = MF_LSC;
if(SecCHOffset == 2){
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
}
}
}
else if(PrimaryCCA->intf_type==2){
if(PrimaryCCA->CH_offset==1){
//ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_USC);
pHalData->RTSEN = 1;
}
else if(PrimaryCCA->CH_offset==2){
//ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_LSC);
pHalData->RTSEN = 1;
}
}
}
}
}
else{ // disconnected interference detection
odm_Intf_Detection(pDM_Odm);
}// end of disconnected
}
else{ // PrimaryCCA->PriCCA_flag == 1
if(STA_BW==0){
STA_BW_pre = STA_BW;
return;
}
Count_Down--;
if((Count_Down == 0) || ((STA_BW & STA_BW_pre) != 1)){
Count_Down = Monitor_TIME;
PrimaryCCA->PriCCA_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); // default
pHalData->RTSEN = 0;
}
}
STA_BW_pre = STA_BW;
}
else{
//2 Reset
odm_PrimaryCCA_Check_Init(pDM_Odm);
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
Count_Down = Monitor_TIME;
}
}
VOID
odm_Intf_Detection(
IN PDM_ODM_T pDM_Odm
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
#else
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
#endif
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH)
&&(FalseAlmCnt->Cnt_BW_LSC>(FalseAlmCnt->Cnt_BW_USC+BW_Ind_Bias))){
PrimaryCCA->intf_flag = 1;
PrimaryCCA->CH_offset = 1; // 1:LSC, 2:USC
if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){
PrimaryCCA->intf_type = 1;
}
else{
PrimaryCCA->intf_type = 2;
}
}
else if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH)
&&(FalseAlmCnt->Cnt_BW_USC>(FalseAlmCnt->Cnt_BW_LSC+BW_Ind_Bias))){
PrimaryCCA->intf_flag = 1;
PrimaryCCA->CH_offset = 2; // 1:LSC, 2:USC
if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){
PrimaryCCA->intf_type = 1;
}
else{
PrimaryCCA->intf_type = 2;
}
}
else{
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->CH_offset = 0;
}
}
#endif
#endif
#endif // RTL8192E_SUPPORT == 1

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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/phydm_RTL8192E.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8192E_H__
#define __ODM_RTL8192E_H__
#define OFDMCCA_TH 500
#define BW_Ind_Bias 500
#define MF_USC 2
#define MF_LSC 1
#define MF_USC_LSC 0
#define Monitor_TIME 30
VOID
odm_Write_Dynamic_CCA(
IN PDM_ODM_T pDM_Odm,
IN u1Byte CurrentMFstate
);
VOID
odm_PrimaryCCA_Check_Init(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_DynamicPrimaryCCA_Check(
IN PDM_ODM_T pDM_Odm
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_DynamicPrimaryCCAMP(
IN PDM_ODM_T pDM_Odm
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
odm_DynamicPrimaryCCAAP(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_Intf_Detection(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif

233
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/phydm_RegConfig8192E.c Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8192E_SUPPORT == 1)
void
odm_ConfigRFReg_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
)
{
if(Addr == 0xfe || Addr == 0xffe)
{
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else
{
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
//For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by Ed 20130.
if(Addr == 0xb6)
{
u4Byte getvalue=0;
u1Byte count =0;
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_delay_us(1);
while((getvalue>>8)!=(Data>>8))
{
count++;
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
ODM_delay_us(1);
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
if(count>5)
break;
}
}
if(Addr == 0xb2)
{
u4Byte getvalue=0;
u1Byte count =0;
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_delay_us(1);
while(getvalue!=Data)
{
count++;
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
ODM_delay_us(1);
//Do LCK againg
ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07);
ODM_delay_us(1);
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
if(count>5)
break;
}
}
}
}
void
odm_ConfigRF_RadioA_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
}
void
odm_ConfigRF_RadioB_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigMAC_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
)
{
ODM_Write1Byte(pDM_Odm, Addr, Data);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_AGC_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_PHY_REG_PG_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe || Addr == 0xffe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else
{
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
#endif
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
}
void
odm_ConfigBB_PHY_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (Addr == 0xfd)
ODM_delay_ms(5);
else if (Addr == 0xfc)
ODM_delay_ms(1);
else if (Addr == 0xfb)
ODM_delay_us(50);
else if (Addr == 0xfa)
ODM_delay_us(5);
else if (Addr == 0xf9)
ODM_delay_us(1);
else
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
}
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_TXPWR_LMT_8192E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte Regulation,
IN pu1Byte Band,
IN pu1Byte Bandwidth,
IN pu1Byte RateSection,
IN pu1Byte RfPath,
IN pu1Byte Channel,
IN pu1Byte PowerLimit
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
Bandwidth, RateSection, RfPath, Channel, PowerLimit);
#endif
}
#endif

98
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/phydm_RegConfig8192E.h Executable file
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@ -0,0 +1,98 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8192E
#define __INC_ODM_REGCONFIG_H_8192E
#if (RTL8192E_SUPPORT == 1)
void
odm_ConfigRFReg_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
);
void
odm_ConfigRF_RadioA_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigRF_RadioB_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigMAC_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
);
void
odm_ConfigBB_AGC_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_REG_PG_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_TXPWR_LMT_8192E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte Regulation,
IN pu1Byte Band,
IN pu1Byte Bandwidth,
IN pu1Byte RateSection,
IN pu1Byte RfPath,
IN pu1Byte Channel,
IN pu1Byte PowerLimit
);
#endif
#endif // end of SUPPORT

5
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/version_rtl8192e.h Executable file
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/*RTL8192E PHY Parameters*/
#define SVN_COMMIT_VERSION_8192E 53
#define RELEASE_DATE_8192E 20150617
#define COMMIT_BY_8192E "BB_DINO"
#define RELEASE_VERSION_8192E 51