403 lines
16 KiB
C
403 lines
16 KiB
C
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//------------------------------------------------------------------------------
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// ISC License (ISC)
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//
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// Copyright (c) 2007-2010, The Linux Foundation
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// All rights reserved.
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// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
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//
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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//
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//
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//------------------------------------------------------------------------------
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//==============================================================================
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// AR6K device layer that handles register level I/O
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//
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// Author(s): ="Atheros"
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//==============================================================================
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#ifndef AR6K_H_
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#define AR6K_H_
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#include "hci_transport_api.h"
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#include "../htc_debug.h"
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#define AR6K_MAILBOXES 4
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/* HTC runs over mailbox 0 */
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#define HTC_MAILBOX 0
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#define AR6K_TARGET_DEBUG_INTR_MASK 0x01
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#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
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INT_STATUS_ENABLE_CPU_MASK | \
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INT_STATUS_ENABLE_COUNTER_MASK)
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//#define MBOXHW_UNIT_TEST 1
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#include "athstartpack.h"
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typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
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A_UINT8 host_int_status;
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A_UINT8 cpu_int_status;
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A_UINT8 error_int_status;
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A_UINT8 counter_int_status;
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A_UINT8 mbox_frame;
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A_UINT8 rx_lookahead_valid;
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A_UINT8 host_int_status2;
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A_UINT8 gmbox_rx_avail;
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A_UINT32 rx_lookahead[2];
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A_UINT32 rx_gmbox_lookahead_alias[2];
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} POSTPACK AR6K_IRQ_PROC_REGISTERS;
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#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
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typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS {
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A_UINT8 int_status_enable;
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A_UINT8 cpu_int_status_enable;
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A_UINT8 error_status_enable;
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A_UINT8 counter_int_status_enable;
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} POSTPACK AR6K_IRQ_ENABLE_REGISTERS;
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typedef PREPACK struct _AR6K_GMBOX_CTRL_REGISTERS {
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A_UINT8 int_status_enable;
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} POSTPACK AR6K_GMBOX_CTRL_REGISTERS;
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#include "athendpack.h"
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#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
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#define AR6K_REG_IO_BUFFER_SIZE 32
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#define AR6K_MAX_REG_IO_BUFFERS 8
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#define FROM_DMA_BUFFER TRUE
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#define TO_DMA_BUFFER FALSE
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#define AR6K_SCATTER_ENTRIES_PER_REQ 16
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#define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024
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#define AR6K_SCATTER_REQS 4
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#define AR6K_LEGACY_MAX_WRITE_LENGTH 2048
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#ifndef A_CACHE_LINE_PAD
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#define A_CACHE_LINE_PAD 128
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#endif
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/* buffers for ASYNC I/O */
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typedef struct AR6K_ASYNC_REG_IO_BUFFER {
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HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */
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A_UINT8 _Pad1[A_CACHE_LINE_PAD];
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A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; /* cache-line safe with pads around */
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A_UINT8 _Pad2[A_CACHE_LINE_PAD];
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} AR6K_ASYNC_REG_IO_BUFFER;
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typedef struct _AR6K_GMBOX_INFO {
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void *pProtocolContext;
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A_STATUS (*pMessagePendingCallBack)(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes);
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A_STATUS (*pCreditsPendingCallback)(void *pContext, int NumCredits, A_BOOL CreditIRQEnabled);
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void (*pTargetFailureCallback)(void *pContext, A_STATUS Status);
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void (*pStateDumpCallback)(void *pContext);
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A_BOOL CreditCountIRQEnabled;
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} AR6K_GMBOX_INFO;
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typedef struct _AR6K_DEVICE {
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A_MUTEX_T Lock;
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A_UINT8 _Pad1[A_CACHE_LINE_PAD];
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AR6K_IRQ_PROC_REGISTERS IrqProcRegisters; /* cache-line safe with pads around */
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A_UINT8 _Pad2[A_CACHE_LINE_PAD];
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AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; /* cache-line safe with pads around */
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A_UINT8 _Pad3[A_CACHE_LINE_PAD];
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void *HIFDevice;
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A_UINT32 BlockSize;
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A_UINT32 BlockMask;
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HIF_DEVICE_MBOX_INFO MailBoxInfo;
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HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc;
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void *HTCContext;
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HTC_PACKET_QUEUE RegisterIOList;
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AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
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void (*TargetFailureCallback)(void *Context);
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A_STATUS (*MessagePendingCallback)(void *Context,
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A_UINT32 LookAheads[],
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int NumLookAheads,
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A_BOOL *pAsyncProc,
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int *pNumPktsFetched);
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HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode;
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HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent;
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A_BOOL HifAttached;
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HIF_DEVICE_IRQ_YIELD_PARAMS HifIRQYieldParams;
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A_BOOL DSRCanYield;
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int CurrentDSRRecvCount;
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HIF_DEVICE_SCATTER_SUPPORT_INFO HifScatterInfo;
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DL_LIST ScatterReqHead;
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A_BOOL ScatterIsVirtual;
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int MaxRecvBundleSize;
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int MaxSendBundleSize;
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AR6K_GMBOX_INFO GMboxInfo;
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A_BOOL GMboxEnabled;
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AR6K_GMBOX_CTRL_REGISTERS GMboxControlRegisters;
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int RecheckIRQStatusCnt;
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} AR6K_DEVICE;
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#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock);
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#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock);
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#define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1 /* note: no need to lock this, it only gets set */
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A_STATUS DevSetup(AR6K_DEVICE *pDev);
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void DevCleanup(AR6K_DEVICE *pDev);
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A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev);
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A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev);
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A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
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A_UINT32 *pLookAhead,
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int TimeoutMS);
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A_STATUS DevRWCompletionHandler(void *context, A_STATUS status);
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A_STATUS DevDsrHandler(void *context);
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A_STATUS DevCheckPendingRecvMsgsAsync(void *context);
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void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev);
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void DevDumpRegisters(AR6K_DEVICE *pDev,
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AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs,
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AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
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#define DEV_STOP_RECV_ASYNC TRUE
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#define DEV_STOP_RECV_SYNC FALSE
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#define DEV_ENABLE_RECV_ASYNC TRUE
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#define DEV_ENABLE_RECV_SYNC FALSE
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A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
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A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
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A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
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A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
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A_STATUS DevWaitForPendingRecv(AR6K_DEVICE *pDev,A_UINT32 TimeoutInMs,A_BOOL *pbIsRecvPending);
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#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
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#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
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#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
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static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
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A_UINT32 paddedLength;
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A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
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A_STATUS status;
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/* adjust the length to be a multiple of block size if appropriate */
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paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, SendLength);
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#if 0
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if (paddedLength > pPacket->BufferLength) {
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A_ASSERT(FALSE);
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if (pPacket->Completion != NULL) {
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COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
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return A_OK;
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}
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return A_EINVAL;
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}
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#endif
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AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
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("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
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paddedLength,
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pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
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sync ? "SYNC" : "ASYNC"));
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status = HIFReadWrite(pDev->HIFDevice,
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pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
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pPacket->pBuffer,
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paddedLength, /* the padded length */
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sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
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sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
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if (sync) {
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pPacket->Status = status;
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} else {
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if (status == A_PENDING) {
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status = A_OK;
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}
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}
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return status;
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}
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static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
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A_UINT32 paddedLength;
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A_STATUS status;
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A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
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/* adjust the length to be a multiple of block size if appropriate */
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paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, RecvLength);
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if (paddedLength > pPacket->BufferLength) {
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A_ASSERT(FALSE);
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
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("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
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paddedLength,RecvLength,pPacket->BufferLength));
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if (pPacket->Completion != NULL) {
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COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
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return A_OK;
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}
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return A_EINVAL;
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}
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AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
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("DevRecvPacket (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
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(unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
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paddedLength,
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pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
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sync ? "SYNC" : "ASYNC"));
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status = HIFReadWrite(pDev->HIFDevice,
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pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
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pPacket->pBuffer,
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paddedLength,
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sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
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sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
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if (sync) {
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pPacket->Status = status;
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}
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return status;
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}
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#define DEV_CHECK_RECV_YIELD(pDev) \
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((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount)
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#define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode)
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#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
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/**************************************************/
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/****** Scatter Function and Definitions
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*
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*
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*/
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A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA);
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/* copy any READ data back into scatter list */
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#define DEV_FINISH_SCATTER_OPERATION(pR) \
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if (A_SUCCESS((pR)->CompletionStatus) && \
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!((pR)->Request & HIF_WRITE) && \
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((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) { \
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(pR)->CompletionStatus = DevCopyScatterListToFromDMABuffer((pR),FROM_DMA_BUFFER); \
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}
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/* copy any WRITE data to bounce buffer */
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static INLINE A_STATUS DEV_PREPARE_SCATTER_OPERATION(HIF_SCATTER_REQ *pReq) {
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if ((pReq->Request & HIF_WRITE) && (pReq->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {
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return DevCopyScatterListToFromDMABuffer(pReq,TO_DMA_BUFFER);
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} else {
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return A_OK;
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}
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}
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A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer);
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A_STATUS DevCleanupMsgBundling(AR6K_DEVICE *pDev);
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#define DEV_GET_MAX_MSG_PER_BUNDLE(pDev) (pDev)->HifScatterInfo.MaxScatterEntries
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#define DEV_GET_MAX_BUNDLE_LENGTH(pDev) (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq
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#define DEV_ALLOC_SCATTER_REQ(pDev) \
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(pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice)
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#define DEV_FREE_SCATTER_REQ(pDev,pR) \
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(pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR))
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#define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev) (pDev)->MaxRecvBundleSize
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#define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev) (pDev)->MaxSendBundleSize
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#define DEV_SCATTER_READ TRUE
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#define DEV_SCATTER_WRITE FALSE
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#define DEV_SCATTER_ASYNC TRUE
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#define DEV_SCATTER_SYNC FALSE
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A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async);
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#ifdef MBOXHW_UNIT_TEST
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A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev);
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#endif
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/* completely virtual */
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typedef struct _DEV_SCATTER_DMA_VIRTUAL_INFO {
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A_UINT8 *pVirtDmaBuffer; /* dma-able buffer - CPU accessible address */
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A_UINT8 DataArea[1]; /* start of data area */
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} DEV_SCATTER_DMA_VIRTUAL_INFO;
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void DumpAR6KDevState(AR6K_DEVICE *pDev);
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/**************************************************/
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/****** GMBOX functions and definitions
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*
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*
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*/
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#ifdef ATH_AR6K_ENABLE_GMBOX
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void DevCleanupGMbox(AR6K_DEVICE *pDev);
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A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev);
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A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev);
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void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev);
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#else
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/* compiled out */
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#define DevCleanupGMbox(p)
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#define DevCheckGMboxInterrupts(p) A_OK
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#define DevNotifyGMboxTargetFailure(p)
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static INLINE A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev) {
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pDev->GMboxEnabled = FALSE;
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return A_OK;
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}
|
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#endif
|
||
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|
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#ifdef ATH_AR6K_ENABLE_GMBOX
|
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/* GMBOX protocol modules must expose each of these internal APIs */
|
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HCI_TRANSPORT_HANDLE GMboxAttachProtocol(AR6K_DEVICE *pDev, HCI_TRANSPORT_CONFIG_INFO *pInfo);
|
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A_STATUS GMboxProtocolInstall(AR6K_DEVICE *pDev);
|
||
|
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void GMboxProtocolUninstall(AR6K_DEVICE *pDev);
|
||
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|
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|
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/* API used by GMBOX protocol modules */
|
||
|
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AR6K_DEVICE *HTCGetAR6KDevice(void *HTCHandle);
|
||
|
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#define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \
|
||
|
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{ \
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||
|
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(pDev)->GMboxInfo.pProtocolContext = (context); \
|
||
|
|
(pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback); \
|
||
|
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(pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \
|
||
|
|
(pDev)->GMboxInfo.pTargetFailureCallback = (failure); \
|
||
|
|
(pDev)->GMboxInfo.pStateDumpCallback = (statedump); \
|
||
|
|
}
|
||
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|
||
|
|
#define DEV_GMBOX_GET_PROTOCOL(pDev) (pDev)->GMboxInfo.pProtocolContext
|
||
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|
||
|
|
A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength);
|
||
|
|
A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength);
|
||
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|
||
|
|
#define PROC_IO_ASYNC TRUE
|
||
|
|
#define PROC_IO_SYNC FALSE
|
||
|
|
typedef enum GMBOX_IRQ_ACTION_TYPE {
|
||
|
|
GMBOX_ACTION_NONE = 0,
|
||
|
|
GMBOX_DISABLE_ALL,
|
||
|
|
GMBOX_ERRORS_IRQ_ENABLE,
|
||
|
|
GMBOX_RECV_IRQ_ENABLE,
|
||
|
|
GMBOX_RECV_IRQ_DISABLE,
|
||
|
|
GMBOX_CREDIT_IRQ_ENABLE,
|
||
|
|
GMBOX_CREDIT_IRQ_DISABLE,
|
||
|
|
} GMBOX_IRQ_ACTION_TYPE;
|
||
|
|
|
||
|
|
A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE, A_BOOL AsyncMode);
|
||
|
|
A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits);
|
||
|
|
A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize);
|
||
|
|
A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes);
|
||
|
|
A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int SignalNumber, int AckTimeoutMS);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /*AR6K_H_*/
|