270 lines
8.9 KiB
C
270 lines
8.9 KiB
C
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//------------------------------------------------------------------------------
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// ISC License (ISC)
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//
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// Copyright (c) 2010, The Linux Foundation
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// All rights reserved.
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// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
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//
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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//
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//
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//------------------------------------------------------------------------------
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//==============================================================================
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// common Diagnostic access handling for register-based HIFs
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// This module implements diagnostic accesses on behalf of the diagnostic window module for
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// HIFs that are based on a register access model
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//
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//
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// Author(s): ="Atheros"
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//==============================================================================
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#include "a_config.h"
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#include "athdefs.h"
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#include "a_types.h"
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#include "a_osapi.h"
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#define ATH_MODULE_NAME misc
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#include "a_debug.h"
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#include "targaddrs.h"
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#include "hif.h"
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#include "host_reg_table.h"
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#define CPU_DBG_SEL_ADDRESS 0x00000483
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#define CPU_DBG_ADDRESS 0x00000484
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#ifdef USE_4BYTE_REGISTER_ACCESS
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/* set the window address register (using 4-byte register access ).
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* This mitigates host interconnect issues with non-4byte aligned bus requests, some
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* interconnects use bus adapters that impose strict limitations.
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* Since diag window access is not intended for performance critical operations, the 4byte mode should
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* be satisfactory even though it generates 4X the bus activity. */
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static A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
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{
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A_STATUS status;
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static A_UINT8 addrValue[4];
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A_INT32 i;
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static A_UINT32 address;
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address = Address;
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/* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
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* last to initiate the access cycle */
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for (i = 1; i <= 3; i++) {
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/* fill the buffer with the address byte value we want to hit 4 times*/
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addrValue[0] = ((A_UINT8 *)&Address)[i];
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addrValue[1] = addrValue[0];
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addrValue[2] = addrValue[0];
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addrValue[3] = addrValue[0];
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/* hit each byte of the register address with a 4-byte write operation to the same address,
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* this is a harmless operation */
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status = HIFReadWrite(hifDevice,
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RegisterAddr+i,
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addrValue,
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4,
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HIF_WR_SYNC_BYTE_FIX,
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NULL);
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if (status != A_OK) {
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break;
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}
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}
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
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Address, RegisterAddr));
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return status;
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}
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/* write the address register again, this time write the whole 4-byte value.
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* The effect here is that the LSB write causes the cycle to start, the extra
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* 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
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status = HIFReadWrite(hifDevice,
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RegisterAddr,
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(A_UCHAR *)(&address),
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4,
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HIF_WR_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
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Address, RegisterAddr));
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return status;
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}
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return A_OK;
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}
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#else
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/* set the window address register */
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A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
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{
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A_STATUS status;
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/* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
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* last to initiate the access cycle */
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status = HIFReadWrite(hifDevice,
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RegisterAddr+1, /* write upper 3 bytes */
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((A_UCHAR *)(&Address))+1,
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sizeof(A_UINT32)-1,
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HIF_WR_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
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RegisterAddr, Address));
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return status;
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}
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/* write the LSB of the register, this initiates the operation */
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status = HIFReadWrite(hifDevice,
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RegisterAddr,
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(A_UCHAR *)(&Address),
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sizeof(A_UINT8),
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HIF_WR_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
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RegisterAddr, Address));
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return status;
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}
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return A_OK;
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}
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#endif //USE_4BYTE_REGISTER_ACCESS
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/*
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* Read from the AR6000 through its diagnostic window.
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* No cooperation from the Target is required for this.
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*/
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A_STATUS
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HIFDiagReadAccess(HIF_DEVICE *hifDevice, A_UINT32 address, A_UINT32 *data)
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{
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A_STATUS status;
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static A_UINT32 readvalue;
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/* set window register to start read cycle */
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status = ar6000_SetAddressWindowRegister(hifDevice,
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WINDOW_READ_ADDR_ADDRESS,
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address);
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if (status != A_OK) {
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return status;
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}
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/* read the data */
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status = HIFReadWrite(hifDevice,
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WINDOW_DATA_ADDRESS,
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(A_UCHAR *)&readvalue,
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sizeof(A_UINT32),
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HIF_RD_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
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return status;
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}
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*data = readvalue;
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return status;
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}
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/*
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* Write to the AR6000 through its diagnostic window.
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* No cooperation from the Target is required for this.
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*/
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A_STATUS HIFDiagWriteAccess(HIF_DEVICE *hifDevice, A_UINT32 address, A_UINT32 data)
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{
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A_STATUS status;
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static A_UINT32 writeValue;
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writeValue = data;
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/* set write data */
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status = HIFReadWrite(hifDevice,
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WINDOW_DATA_ADDRESS,
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(A_UCHAR *)&writeValue,
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sizeof(A_UINT32),
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HIF_WR_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", data));
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return status;
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}
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/* set window register, which starts the write cycle */
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return ar6000_SetAddressWindowRegister(hifDevice,
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WINDOW_WRITE_ADDR_ADDRESS,
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address);
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}
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/* TODO .. the following APIs are only available on register-based HIFs where the CPU_DBG_SEL_ADDRESS
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* register is available */
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A_STATUS
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ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval)
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{
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A_STATUS status;
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A_UCHAR vals[4];
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A_UCHAR register_selection[4];
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register_selection[0] = register_selection[1] = register_selection[2] = register_selection[3] = (regsel & 0xff);
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status = HIFReadWrite(hifDevice,
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CPU_DBG_SEL_ADDRESS,
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register_selection,
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4,
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HIF_WR_SYNC_BYTE_FIX,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write CPU_DBG_SEL (%d)\n", regsel));
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return status;
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}
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status = HIFReadWrite(hifDevice,
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CPU_DBG_ADDRESS,
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(A_UCHAR *)vals,
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sizeof(vals),
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HIF_RD_SYNC_BYTE_INC,
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NULL);
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if (status != A_OK) {
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from CPU_DBG_ADDRESS\n"));
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return status;
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}
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*regval = vals[0]<<0 | vals[1]<<8 | vals[2]<<16 | vals[3]<<24;
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return status;
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}
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void
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ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs)
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{
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int i;
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A_UINT32 val;
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for (i=0; i<AR6003_FETCH_TARG_REGS_COUNT; i++) {
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val=0xffffffff;
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(void)ar6k_ReadTargetRegister(hifDevice, i, &val);
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targregs[i] = val;
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}
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}
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