48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
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/*
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* Marvell MBUS common definitions.
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*
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* Copyright (C) 2008 Marvell Semiconductor
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __LINUX_MBUS_H
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#define __LINUX_MBUS_H
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struct mbus_dram_target_info
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{
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/*
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* The 4-bit MBUS target ID of the DRAM controller.
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*/
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u8 mbus_dram_target_id;
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/*
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* The base address, size, and MBUS attribute ID for each
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* of the possible DRAM chip selects. Peripherals are
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* required to support at least 4 decode windows.
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*/
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int num_cs;
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struct mbus_dram_window {
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u8 cs_index;
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u8 mbus_attr;
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u32 base;
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u32 size;
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} cs[4];
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};
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/*
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* The Marvell mbus is to be found only on SOCs from the Orion family
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* at the moment. Provide a dummy stub for other architectures.
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*/
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#ifdef CONFIG_PLAT_ORION
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extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
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#else
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static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
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{
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return NULL;
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}
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#endif
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#endif
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