289 lines
7.4 KiB
C
289 lines
7.4 KiB
C
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/*
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* Header file required by picodlp panel driver
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*
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* Copyright (C) 2009-2011 Texas Instruments
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* Author: Mythri P K <mythripk@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __OMAP2_DISPLAY_PANEL_PICODLP_H
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#define __OMAP2_DISPLAY_PANEL_PICODLP_H
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/* Commands used for configuring picodlp panel */
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#define MAIN_STATUS 0x03
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#define PBC_CONTROL 0x08
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#define INPUT_SOURCE 0x0B
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#define INPUT_RESOLUTION 0x0C
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#define DATA_FORMAT 0x0D
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#define IMG_ROTATION 0x0E
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#define LONG_FLIP 0x0F
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#define SHORT_FLIP 0x10
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#define TEST_PAT_SELECT 0x11
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#define R_DRIVE_CURRENT 0x12
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#define G_DRIVE_CURRENT 0x13
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#define B_DRIVE_CURRENT 0x14
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#define READ_REG_SELECT 0x15
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#define RGB_DRIVER_ENABLE 0x16
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#define CPU_IF_MODE 0x18
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#define FRAME_RATE 0x19
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#define CPU_IF_SYNC_METHOD 0x1A
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#define CPU_IF_SOF 0x1B
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#define CPU_IF_EOF 0x1C
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#define CPU_IF_SLEEP 0x1D
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#define SEQUENCE_MODE 0x1E
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#define SOFT_RESET 0x1F
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#define FRONT_END_RESET 0x21
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#define AUTO_PWR_ENABLE 0x22
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#define VSYNC_LINE_DELAY 0x23
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#define CPU_PI_HORIZ_START 0x24
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#define CPU_PI_VERT_START 0x25
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#define CPU_PI_HORIZ_WIDTH 0x26
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#define CPU_PI_VERT_HEIGHT 0x27
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#define PIXEL_MASK_CROP 0x28
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#define CROP_FIRST_LINE 0x29
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#define CROP_LAST_LINE 0x2A
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#define CROP_FIRST_PIXEL 0x2B
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#define CROP_LAST_PIXEL 0x2C
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#define DMD_PARK_TRIGGER 0x2D
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#define MISC_REG 0x30
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/* AGC registers */
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#define AGC_CTRL 0x50
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#define AGC_CLIPPED_PIXS 0x55
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#define AGC_BRIGHT_PIXS 0x56
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#define AGC_BG_PIXS 0x57
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#define AGC_SAFETY_MARGIN 0x17
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/* Color Coordinate Adjustment registers */
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#define CCA_ENABLE 0x5E
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#define CCA_C1A 0x5F
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#define CCA_C1B 0x60
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#define CCA_C1C 0x61
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#define CCA_C2A 0x62
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#define CCA_C2B 0x63
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#define CCA_C2C 0x64
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#define CCA_C3A 0x65
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#define CCA_C3B 0x66
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#define CCA_C3C 0x67
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#define CCA_C7A 0x71
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#define CCA_C7B 0x72
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#define CCA_C7C 0x73
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/**
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* DLP Pico Processor 2600 comes with flash
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* We can do DMA operations from flash for accessing Look Up Tables
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*/
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#define DMA_STATUS 0x100
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#define FLASH_ADDR_BYTES 0x74
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#define FLASH_DUMMY_BYTES 0x75
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#define FLASH_WRITE_BYTES 0x76
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#define FLASH_READ_BYTES 0x77
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#define FLASH_OPCODE 0x78
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#define FLASH_START_ADDR 0x79
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#define FLASH_DUMMY2 0x7A
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#define FLASH_WRITE_DATA 0x7B
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#define TEMPORAL_DITH_DISABLE 0x7E
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#define SEQ_CONTROL 0x82
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#define SEQ_VECTOR 0x83
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/* DMD is Digital Micromirror Device */
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#define DMD_BLOCK_COUNT 0x84
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#define DMD_VCC_CONTROL 0x86
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#define DMD_PARK_PULSE_COUNT 0x87
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#define DMD_PARK_PULSE_WIDTH 0x88
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#define DMD_PARK_DELAY 0x89
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#define DMD_SHADOW_ENABLE 0x8E
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#define SEQ_STATUS 0x8F
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#define FLASH_CLOCK_CONTROL 0x98
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#define DMD_PARK 0x2D
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#define SDRAM_BIST_ENABLE 0x46
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#define DDR_DRIVER_STRENGTH 0x9A
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#define SDC_ENABLE 0x9D
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#define SDC_BUFF_SWAP_DISABLE 0xA3
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#define CURTAIN_CONTROL 0xA6
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#define DDR_BUS_SWAP_ENABLE 0xA7
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#define DMD_TRC_ENABLE 0xA8
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#define DMD_BUS_SWAP_ENABLE 0xA9
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#define ACTGEN_ENABLE 0xAE
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#define ACTGEN_CONTROL 0xAF
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#define ACTGEN_HORIZ_BP 0xB0
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#define ACTGEN_VERT_BP 0xB1
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/* Look Up Table access */
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#define CMT_SPLASH_LUT_START_ADDR 0xFA
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#define CMT_SPLASH_LUT_DEST_SELECT 0xFB
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#define CMT_SPLASH_LUT_DATA 0xFC
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#define SEQ_RESET_LUT_START_ADDR 0xFD
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#define SEQ_RESET_LUT_DEST_SELECT 0xFE
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#define SEQ_RESET_LUT_DATA 0xFF
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/* Input source definitions */
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#define PARALLEL_RGB 0
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#define INT_TEST_PATTERN 1
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#define SPLASH_SCREEN 2
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#define CPU_INTF 3
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#define BT656 4
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/* Standard input resolution definitions */
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#define QWVGA_LANDSCAPE 3 /* (427h*240v) */
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#define WVGA_864_LANDSCAPE 21 /* (864h*480v) */
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#define WVGA_DMD_OPTICAL_TEST 35 /* (608h*684v) */
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/* Standard data format definitions */
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#define RGB565 0
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#define RGB666 1
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#define RGB888 2
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/* Test Pattern definitions */
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#define TPG_CHECKERBOARD 0
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#define TPG_BLACK 1
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#define TPG_WHITE 2
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#define TPG_RED 3
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#define TPG_BLUE 4
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#define TPG_GREEN 5
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#define TPG_VLINES_BLACK 6
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#define TPG_HLINES_BLACK 7
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#define TPG_VLINES_ALT 8
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#define TPG_HLINES_ALT 9
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#define TPG_DIAG_LINES 10
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#define TPG_GREYRAMP_VERT 11
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#define TPG_GREYRAMP_HORIZ 12
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#define TPG_ANSI_CHECKERBOARD 13
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/* sequence mode definitions */
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#define SEQ_FREE_RUN 0
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#define SEQ_LOCK 1
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/* curtain color definitions */
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#define CURTAIN_BLACK 0
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#define CURTAIN_RED 1
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#define CURTAIN_GREEN 2
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#define CURTAIN_BLUE 3
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#define CURTAIN_YELLOW 4
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#define CURTAIN_MAGENTA 5
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#define CURTAIN_CYAN 6
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#define CURTAIN_WHITE 7
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/* LUT definitions */
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#define CMT_LUT_NONE 0
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#define CMT_LUT_GREEN 1
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#define CMT_LUT_RED 2
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#define CMT_LUT_BLUE 3
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#define CMT_LUT_ALL 4
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#define SPLASH_LUT 5
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#define SEQ_LUT_NONE 0
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#define SEQ_DRC_LUT_0 1
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#define SEQ_DRC_LUT_1 2
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#define SEQ_DRC_LUT_2 3
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#define SEQ_DRC_LUT_3 4
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#define SEQ_SEQ_LUT 5
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#define SEQ_DRC_LUT_ALL 6
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#define WPC_PROGRAM_LUT 7
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#define BITSTREAM_START_ADDR 0x00000000
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#define BITSTREAM_SIZE 0x00040000
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#define WPC_FW_0_START_ADDR 0x00040000
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#define WPC_FW_0_SIZE 0x00000ce8
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#define SEQUENCE_0_START_ADDR 0x00044000
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#define SEQUENCE_0_SIZE 0x00001000
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#define SEQUENCE_1_START_ADDR 0x00045000
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#define SEQUENCE_1_SIZE 0x00000d10
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#define SEQUENCE_2_START_ADDR 0x00046000
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#define SEQUENCE_2_SIZE 0x00000d10
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#define SEQUENCE_3_START_ADDR 0x00047000
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#define SEQUENCE_3_SIZE 0x00000d10
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#define SEQUENCE_4_START_ADDR 0x00048000
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#define SEQUENCE_4_SIZE 0x00000d10
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#define SEQUENCE_5_START_ADDR 0x00049000
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#define SEQUENCE_5_SIZE 0x00000d10
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#define SEQUENCE_6_START_ADDR 0x0004a000
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#define SEQUENCE_6_SIZE 0x00000d10
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#define CMT_LUT_0_START_ADDR 0x0004b200
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#define CMT_LUT_0_SIZE 0x00000600
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#define CMT_LUT_1_START_ADDR 0x0004b800
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#define CMT_LUT_1_SIZE 0x00000600
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#define CMT_LUT_2_START_ADDR 0x0004be00
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#define CMT_LUT_2_SIZE 0x00000600
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#define CMT_LUT_3_START_ADDR 0x0004c400
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#define CMT_LUT_3_SIZE 0x00000600
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#define CMT_LUT_4_START_ADDR 0x0004ca00
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#define CMT_LUT_4_SIZE 0x00000600
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#define CMT_LUT_5_START_ADDR 0x0004d000
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#define CMT_LUT_5_SIZE 0x00000600
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#define CMT_LUT_6_START_ADDR 0x0004d600
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#define CMT_LUT_6_SIZE 0x00000600
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#define DRC_TABLE_0_START_ADDR 0x0004dc00
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#define DRC_TABLE_0_SIZE 0x00000100
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#define SPLASH_0_START_ADDR 0x0004dd00
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#define SPLASH_0_SIZE 0x00032280
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#define SEQUENCE_7_START_ADDR 0x00080000
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#define SEQUENCE_7_SIZE 0x00000d10
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#define SEQUENCE_8_START_ADDR 0x00081800
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#define SEQUENCE_8_SIZE 0x00000d10
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#define SEQUENCE_9_START_ADDR 0x00083000
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#define SEQUENCE_9_SIZE 0x00000d10
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#define CMT_LUT_7_START_ADDR 0x0008e000
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#define CMT_LUT_7_SIZE 0x00000600
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#define CMT_LUT_8_START_ADDR 0x0008e800
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#define CMT_LUT_8_SIZE 0x00000600
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#define CMT_LUT_9_START_ADDR 0x0008f000
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#define CMT_LUT_9_SIZE 0x00000600
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#define SPLASH_1_START_ADDR 0x0009a000
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#define SPLASH_1_SIZE 0x00032280
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#define SPLASH_2_START_ADDR 0x000cd000
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#define SPLASH_2_SIZE 0x00032280
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#define SPLASH_3_START_ADDR 0x00100000
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#define SPLASH_3_SIZE 0x00032280
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#define OPT_SPLASH_0_START_ADDR 0x00134000
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#define OPT_SPLASH_0_SIZE 0x000cb100
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#endif
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