686 lines
16 KiB
C
686 lines
16 KiB
C
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/* Copyright (c) 2008-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clk.h>
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#include <mach/clk.h>
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#include "msm_fb.h"
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#include "mipi_dsi.h"
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#include "hdmi_msm.h"
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#include <mach/msm_iomap.h>
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/* multimedia sub system clock control */
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char *mmss_cc_base = MSM_MMSS_CLK_CTL_BASE;
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/* multimedia sub system sfpb */
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char *mmss_sfpb_base;
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void __iomem *periph_base;
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static struct dsi_clk_desc dsicore_clk;
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static struct dsi_clk_desc dsi_pclk;
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static struct clk *dsi_byte_div_clk;
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static struct clk *dsi_esc_clk;
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static struct clk *dsi_m_pclk;
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static struct clk *dsi_s_pclk;
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static struct clk *amp_pclk;
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int mipi_dsi_clk_on;
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int mipi_dsi_clk_init(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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amp_pclk = clk_get(dev, "arb_clk");
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if (IS_ERR_OR_NULL(amp_pclk)) {
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pr_err("can't find amp_pclk\n");
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amp_pclk = NULL;
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goto mipi_dsi_clk_err;
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}
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dsi_m_pclk = clk_get(dev, "master_iface_clk");
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if (IS_ERR_OR_NULL(dsi_m_pclk)) {
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pr_err("can't find dsi_m_pclk\n");
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dsi_m_pclk = NULL;
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goto mipi_dsi_clk_err;
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}
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dsi_s_pclk = clk_get(dev, "slave_iface_clk");
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if (IS_ERR_OR_NULL(dsi_s_pclk)) {
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pr_err("can't find dsi_s_pclk\n");
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dsi_s_pclk = NULL;
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goto mipi_dsi_clk_err;
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}
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dsi_byte_div_clk = clk_get(dev, "byte_clk");
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if (IS_ERR_OR_NULL(dsi_byte_div_clk)) {
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pr_err("can't find dsi_byte_div_clk\n");
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dsi_byte_div_clk = NULL;
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goto mipi_dsi_clk_err;
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}
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dsi_esc_clk = clk_get(dev, "esc_clk");
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if (IS_ERR_OR_NULL(dsi_esc_clk)) {
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printk(KERN_ERR "can't find dsi_esc_clk\n");
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dsi_esc_clk = NULL;
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goto mipi_dsi_clk_err;
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}
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return 0;
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mipi_dsi_clk_err:
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mipi_dsi_clk_deinit(NULL);
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return -EPERM;
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}
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void mipi_dsi_clk_deinit(struct device *dev)
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{
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if (amp_pclk)
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clk_put(amp_pclk);
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if (dsi_m_pclk)
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clk_put(dsi_m_pclk);
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if (dsi_s_pclk)
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clk_put(dsi_s_pclk);
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if (dsi_byte_div_clk)
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clk_put(dsi_byte_div_clk);
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if (dsi_esc_clk)
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clk_put(dsi_esc_clk);
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}
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static void mipi_dsi_clk_ctrl(struct dsi_clk_desc *clk, int clk_en)
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{
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char *cc, *ns, *md;
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int pmxo_sel = 0;
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char mnd_en = 1, root_en = 1;
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uint32 data, val;
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cc = mmss_cc_base + 0x004c;
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md = mmss_cc_base + 0x0050;
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ns = mmss_cc_base + 0x0054;
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if (clk_en) {
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if (clk->mnd_mode == 0) {
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data = clk->pre_div_func << 14;
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data |= clk->src;
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MIPI_OUTP_SECURE(ns, data);
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MIPI_OUTP_SECURE(cc, ((pmxo_sel << 8)
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| (clk->mnd_mode << 6)
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| (root_en << 2) | clk_en));
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} else {
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val = clk->d * 2;
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data = (~val) & 0x0ff;
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data |= clk->m << 8;
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MIPI_OUTP_SECURE(md, data);
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val = clk->n - clk->m;
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data = (~val) & 0x0ff;
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data <<= 24;
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data |= clk->src;
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MIPI_OUTP_SECURE(ns, data);
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MIPI_OUTP_SECURE(cc, ((pmxo_sel << 8)
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| (clk->mnd_mode << 6)
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| (mnd_en << 5)
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| (root_en << 2) | clk_en));
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}
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} else
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MIPI_OUTP_SECURE(cc, 0);
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wmb();
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}
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static void mipi_dsi_sfpb_cfg(void)
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{
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char *sfpb;
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int data;
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sfpb = mmss_sfpb_base + 0x058;
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data = MIPI_INP(sfpb);
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data |= 0x01800;
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MIPI_OUTP(sfpb, data);
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wmb();
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}
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static void mipi_dsi_pclk_ctrl(struct dsi_clk_desc *clk, int clk_en)
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{
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char *cc, *ns, *md;
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char mnd_en = 1, root_en = 1;
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uint32 data, val;
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cc = mmss_cc_base + 0x0130;
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md = mmss_cc_base + 0x0134;
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ns = mmss_cc_base + 0x0138;
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if (clk_en) {
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if (clk->mnd_mode == 0) {
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data = clk->pre_div_func << 12;
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data |= clk->src;
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MIPI_OUTP_SECURE(ns, data);
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MIPI_OUTP_SECURE(cc, ((clk->mnd_mode << 6)
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| (root_en << 2) | clk_en));
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} else {
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val = clk->d * 2;
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data = (~val) & 0x0ff;
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data |= clk->m << 8;
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MIPI_OUTP_SECURE(md, data);
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val = clk->n - clk->m;
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data = (~val) & 0x0ff;
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data <<= 24;
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data |= clk->src;
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MIPI_OUTP_SECURE(ns, data);
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MIPI_OUTP_SECURE(cc, ((clk->mnd_mode << 6)
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| (mnd_en << 5)
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| (root_en << 2) | clk_en));
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}
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} else
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MIPI_OUTP_SECURE(cc, 0);
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wmb();
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}
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static void mipi_dsi_ahb_en(void)
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{
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char *ahb;
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ahb = mmss_cc_base + 0x08;
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pr_debug("%s: ahb=%x %x\n",
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__func__, (int) ahb, MIPI_INP_SECURE(ahb));
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}
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static void mipi_dsi_calibration(void)
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{
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uint32 data;
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MIPI_OUTP(MIPI_DSI_BASE + 0xf4, 0x0000ff11); /* cal_ctrl */
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MIPI_OUTP(MIPI_DSI_BASE + 0xf0, 0x01); /* cal_hw_trigger */
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while (1) {
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data = MIPI_INP(MIPI_DSI_BASE + 0xfc); /* cal_status */
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if ((data & 0x10000000) == 0)
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break;
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udelay(10);
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}
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}
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#define PREF_DIV_RATIO 27
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struct dsiphy_pll_divider_config pll_divider_config;
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int mipi_dsi_phy_pll_config(u32 clk_rate)
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{
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struct dsiphy_pll_divider_config *dividers;
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u32 fb_divider, tmp;
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dividers = &pll_divider_config;
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/* DSIPHY_PLL_CTRL_x: 1 2 3 8 9 10 */
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/* masks 0xff 0x07 0x3f 0x0f 0xff 0xff */
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/* DSIPHY_PLL_CTRL_1 */
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fb_divider = ((dividers->fb_divider) / 2) - 1;
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MIPI_OUTP(MIPI_DSI_BASE + 0x204, fb_divider & 0xff);
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/* DSIPHY_PLL_CTRL_2 */
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tmp = MIPI_INP(MIPI_DSI_BASE + 0x208);
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tmp &= ~0x07;
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tmp |= (fb_divider >> 8) & 0x07;
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MIPI_OUTP(MIPI_DSI_BASE + 0x208, tmp);
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/* DSIPHY_PLL_CTRL_3 */
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tmp = MIPI_INP(MIPI_DSI_BASE + 0x20c);
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tmp &= ~0x3f;
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tmp |= (dividers->ref_divider_ratio - 1) & 0x3f;
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MIPI_OUTP(MIPI_DSI_BASE + 0x20c, tmp);
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/* DSIPHY_PLL_CTRL_8 */
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tmp = MIPI_INP(MIPI_DSI_BASE + 0x220);
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tmp &= ~0x0f;
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tmp |= (dividers->bit_clk_divider - 1) & 0x0f;
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MIPI_OUTP(MIPI_DSI_BASE + 0x220, tmp);
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/* DSIPHY_PLL_CTRL_9 */
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MIPI_OUTP(MIPI_DSI_BASE + 0x224, (dividers->byte_clk_divider - 1));
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/* DSIPHY_PLL_CTRL_10 */
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MIPI_OUTP(MIPI_DSI_BASE + 0x228, (dividers->dsi_clk_divider - 1));
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return 0;
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}
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int mipi_dsi_clk_div_config(uint8 bpp, uint8 lanes,
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uint32 *expected_dsi_pclk)
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{
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u32 fb_divider, rate, vco;
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u32 div_ratio = 0;
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struct dsi_clk_mnd_table const *mnd_entry = mnd_table;
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if (pll_divider_config.clk_rate == 0)
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pll_divider_config.clk_rate = 454000000;
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rate = pll_divider_config.clk_rate / 1000000; /* In Mhz */
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if (rate < 125) {
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vco = rate * 8;
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div_ratio = 8;
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} else if (rate < 250) {
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vco = rate * 4;
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div_ratio = 4;
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} else if (rate < 500) {
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vco = rate * 2;
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div_ratio = 2;
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} else {
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vco = rate * 1;
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div_ratio = 1;
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}
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/* find the mnd settings from mnd_table entry */
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for (; mnd_entry != mnd_table + ARRAY_SIZE(mnd_table); ++mnd_entry) {
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if (((mnd_entry->lanes) == lanes) &&
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((mnd_entry->bpp) == bpp))
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break;
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}
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if (mnd_entry == mnd_table + ARRAY_SIZE(mnd_table)) {
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pr_err("%s: requested Lanes, %u & BPP, %u, not supported\n",
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__func__, lanes, bpp);
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return -EINVAL;
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}
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fb_divider = ((vco * PREF_DIV_RATIO) / 27);
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pll_divider_config.fb_divider = fb_divider;
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pll_divider_config.ref_divider_ratio = PREF_DIV_RATIO;
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pll_divider_config.bit_clk_divider = div_ratio;
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pll_divider_config.byte_clk_divider =
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pll_divider_config.bit_clk_divider * 8;
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pll_divider_config.dsi_clk_divider =
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(mnd_entry->dsiclk_div) * div_ratio;
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if ((mnd_entry->dsiclk_d == 0)
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|| (mnd_entry->dsiclk_m == 1)) {
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dsicore_clk.mnd_mode = 0;
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dsicore_clk.src = 0x3;
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dsicore_clk.pre_div_func = (mnd_entry->dsiclk_n - 1);
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} else {
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dsicore_clk.mnd_mode = 2;
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dsicore_clk.src = 0x3;
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dsicore_clk.m = mnd_entry->dsiclk_m;
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dsicore_clk.n = mnd_entry->dsiclk_n;
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dsicore_clk.d = mnd_entry->dsiclk_d;
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}
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if ((mnd_entry->pclk_d == 0)
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|| (mnd_entry->pclk_m == 1)) {
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dsi_pclk.mnd_mode = 0;
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dsi_pclk.src = 0x3;
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dsi_pclk.pre_div_func = (mnd_entry->pclk_n - 1);
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*expected_dsi_pclk = ((vco * 1000000) /
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((pll_divider_config.dsi_clk_divider)
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* (mnd_entry->pclk_n)));
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} else {
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dsi_pclk.mnd_mode = 2;
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dsi_pclk.src = 0x3;
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dsi_pclk.m = mnd_entry->pclk_m;
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dsi_pclk.n = mnd_entry->pclk_n;
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dsi_pclk.d = mnd_entry->pclk_d;
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*expected_dsi_pclk = ((vco * 1000000 * dsi_pclk.m) /
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((pll_divider_config.dsi_clk_divider)
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* (mnd_entry->pclk_n)));
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}
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return 0;
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}
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void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
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int target_type)
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{
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struct mipi_dsi_phy_ctrl *pd;
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int i, off;
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|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
|
||
|
|
wmb();
|
||
|
|
usleep(1);
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
|
||
|
|
wmb();
|
||
|
|
usleep(1);
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x2cc, 0x0003);/* regulator_ctrl_0 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x2d0, 0x0001);/* regulator_ctrl_1 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x2d4, 0x0001);/* regulator_ctrl_2 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x2d8, 0x0000);/* regulator_ctrl_3 */
|
||
|
|
#ifdef DSI_POWER
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x2dc, 0x0100);/* regulator_ctrl_4 */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
pd = (panel_info->mipi).dsi_phy_db;
|
||
|
|
|
||
|
|
off = 0x02cc; /* regulator ctrl 0 */
|
||
|
|
for (i = 0; i < 4; i++) {
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
|
||
|
|
wmb();
|
||
|
|
off += 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
off = 0x0260; /* phy timig ctrl 0 */
|
||
|
|
for (i = 0; i < 11; i++) {
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
|
||
|
|
wmb();
|
||
|
|
off += 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
off = 0x0290; /* ctrl 0 */
|
||
|
|
for (i = 0; i < 4; i++) {
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
|
||
|
|
wmb();
|
||
|
|
off += 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
off = 0x02a0; /* strength 0 */
|
||
|
|
for (i = 0; i < 4; i++) {
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
|
||
|
|
wmb();
|
||
|
|
off += 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
mipi_dsi_calibration();
|
||
|
|
|
||
|
|
off = 0x0204; /* pll ctrl 1, skip 0 */
|
||
|
|
for (i = 1; i < 21; i++) {
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
|
||
|
|
wmb();
|
||
|
|
off += 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (panel_info)
|
||
|
|
mipi_dsi_phy_pll_config(panel_info->clk_rate);
|
||
|
|
|
||
|
|
/* pll ctrl 0 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
|
||
|
|
wmb();
|
||
|
|
}
|
||
|
|
|
||
|
|
void cont_splash_clk_ctrl(int enable)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
void mipi_dsi_prepare_clocks(void)
|
||
|
|
{
|
||
|
|
clk_prepare(amp_pclk);
|
||
|
|
clk_prepare(dsi_m_pclk);
|
||
|
|
clk_prepare(dsi_s_pclk);
|
||
|
|
clk_prepare(dsi_byte_div_clk);
|
||
|
|
clk_prepare(dsi_esc_clk);
|
||
|
|
}
|
||
|
|
|
||
|
|
void mipi_dsi_unprepare_clocks(void)
|
||
|
|
{
|
||
|
|
clk_unprepare(dsi_esc_clk);
|
||
|
|
clk_unprepare(dsi_byte_div_clk);
|
||
|
|
clk_unprepare(dsi_m_pclk);
|
||
|
|
clk_unprepare(dsi_s_pclk);
|
||
|
|
clk_unprepare(amp_pclk);
|
||
|
|
}
|
||
|
|
|
||
|
|
void mipi_dsi_ahb_ctrl(u32 enable)
|
||
|
|
{
|
||
|
|
static int ahb_ctrl_done;
|
||
|
|
if (enable) {
|
||
|
|
if (ahb_ctrl_done) {
|
||
|
|
pr_info("%s: ahb clks already ON\n", __func__);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
clk_enable(amp_pclk); /* clock for AHB-master to AXI */
|
||
|
|
clk_enable(dsi_m_pclk);
|
||
|
|
clk_enable(dsi_s_pclk);
|
||
|
|
mipi_dsi_ahb_en();
|
||
|
|
mipi_dsi_sfpb_cfg();
|
||
|
|
ahb_ctrl_done = 1;
|
||
|
|
} else {
|
||
|
|
if (ahb_ctrl_done == 0) {
|
||
|
|
pr_info("%s: ahb clks already OFF\n", __func__);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
clk_disable(dsi_m_pclk);
|
||
|
|
clk_disable(dsi_s_pclk);
|
||
|
|
clk_disable(amp_pclk); /* clock for AHB-master to AXI */
|
||
|
|
ahb_ctrl_done = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void mipi_dsi_clk_enable(void)
|
||
|
|
{
|
||
|
|
u32 pll_ctrl = MIPI_INP(MIPI_DSI_BASE + 0x0200);
|
||
|
|
if (mipi_dsi_clk_on) {
|
||
|
|
pr_info("%s: mipi_dsi_clks already ON\n", __func__);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0200, pll_ctrl | 0x01);
|
||
|
|
mb();
|
||
|
|
|
||
|
|
if (clk_set_rate(dsi_byte_div_clk, 1) < 0) /* divided by 1 */
|
||
|
|
pr_err("%s: clk_set_rate failed\n", __func__);
|
||
|
|
mipi_dsi_pclk_ctrl(&dsi_pclk, 1);
|
||
|
|
mipi_dsi_clk_ctrl(&dsicore_clk, 1);
|
||
|
|
clk_enable(dsi_byte_div_clk);
|
||
|
|
clk_enable(dsi_esc_clk);
|
||
|
|
mipi_dsi_clk_on = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mipi_dsi_clk_disable(void)
|
||
|
|
{
|
||
|
|
if (mipi_dsi_clk_on == 0) {
|
||
|
|
pr_info("%s: mipi_dsi_clks already OFF\n", __func__);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
clk_disable(dsi_esc_clk);
|
||
|
|
clk_disable(dsi_byte_div_clk);
|
||
|
|
|
||
|
|
mipi_dsi_pclk_ctrl(&dsi_pclk, 0);
|
||
|
|
mipi_dsi_clk_ctrl(&dsicore_clk, 0);
|
||
|
|
/* DSIPHY_PLL_CTRL_0, disable dsi pll */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0200, 0x40);
|
||
|
|
mipi_dsi_clk_on = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mipi_dsi_phy_ctrl(int on)
|
||
|
|
{
|
||
|
|
if (on) {
|
||
|
|
/* DSIPHY_PLL_CTRL_5 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0214, 0x050);
|
||
|
|
|
||
|
|
/* DSIPHY_TPA_CTRL_1 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0258, 0x00f);
|
||
|
|
|
||
|
|
/* DSIPHY_TPA_CTRL_2 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x025c, 0x000);
|
||
|
|
} else {
|
||
|
|
/* DSIPHY_PLL_CTRL_5 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0214, 0x05f);
|
||
|
|
|
||
|
|
/* DSIPHY_TPA_CTRL_1 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0258, 0x08f);
|
||
|
|
|
||
|
|
/* DSIPHY_TPA_CTRL_2 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x025c, 0x001);
|
||
|
|
|
||
|
|
/* DSIPHY_REGULATOR_CTRL_0 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x02cc, 0x02);
|
||
|
|
|
||
|
|
/* DSIPHY_CTRL_0 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0290, 0x00);
|
||
|
|
|
||
|
|
/* DSIPHY_CTRL_1 */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0294, 0x7f);
|
||
|
|
|
||
|
|
/* disable dsi clk */
|
||
|
|
MIPI_OUTP(MIPI_DSI_BASE + 0x0118, 0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_FB_MSM_HDMI_COMMON
|
||
|
|
#define SW_RESET BIT(2)
|
||
|
|
void hdmi_phy_reset(void)
|
||
|
|
{
|
||
|
|
unsigned int phy_reset_polarity = 0x0;
|
||
|
|
unsigned int val = HDMI_INP_ND(0x2D4);
|
||
|
|
|
||
|
|
phy_reset_polarity = val >> 3 & 0x1;
|
||
|
|
|
||
|
|
if (phy_reset_polarity == 0)
|
||
|
|
HDMI_OUTP(0x2D4, val | SW_RESET);
|
||
|
|
else
|
||
|
|
HDMI_OUTP(0x2D4, val & (~SW_RESET));
|
||
|
|
|
||
|
|
msleep(100);
|
||
|
|
|
||
|
|
if (phy_reset_polarity == 0)
|
||
|
|
HDMI_OUTP(0x2D4, val & (~SW_RESET));
|
||
|
|
else
|
||
|
|
HDMI_OUTP(0x2D4, val | SW_RESET);
|
||
|
|
}
|
||
|
|
|
||
|
|
void hdmi_msm_reset_core(void)
|
||
|
|
{
|
||
|
|
hdmi_msm_clk(0);
|
||
|
|
udelay(5);
|
||
|
|
hdmi_msm_clk(1);
|
||
|
|
|
||
|
|
clk_reset(hdmi_msm_state->hdmi_app_clk, CLK_RESET_ASSERT);
|
||
|
|
udelay(20);
|
||
|
|
clk_reset(hdmi_msm_state->hdmi_app_clk, CLK_RESET_DEASSERT);
|
||
|
|
}
|
||
|
|
|
||
|
|
void hdmi_msm_init_phy(int video_format)
|
||
|
|
{
|
||
|
|
uint32 offset;
|
||
|
|
/* De-serializer delay D/C for non-lbk mode
|
||
|
|
* PHY REG0 = (DESER_SEL(0) | DESER_DEL_CTRL(3)
|
||
|
|
* | AMUX_OUT_SEL(0))
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0300, 0x0C); /*0b00001100*/
|
||
|
|
|
||
|
|
if (video_format == HDMI_VFRMT_720x480p60_16_9) {
|
||
|
|
/* PHY REG1 = DTEST_MUX_SEL(5) | PLL_GAIN_SEL(0)
|
||
|
|
* | OUTVOL_SWING_CTRL(3)
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0304, 0x53); /*0b01010011*/
|
||
|
|
} else {
|
||
|
|
/* If the freq. is less than 120MHz, use low gain 0
|
||
|
|
* for board with termination
|
||
|
|
* PHY REG1 = DTEST_MUX_SEL(5) | PLL_GAIN_SEL(0)
|
||
|
|
* | OUTVOL_SWING_CTRL(4)
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0304, 0x54); /*0b01010100*/
|
||
|
|
}
|
||
|
|
|
||
|
|
/* No matter what, start from the power down mode
|
||
|
|
* PHY REG2 = PD_PWRGEN | PD_PLL | PD_DRIVE_4 | PD_DRIVE_3
|
||
|
|
* | PD_DRIVE_2 | PD_DRIVE_1 | PD_DESER
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0308, 0x7F); /*0b01111111*/
|
||
|
|
|
||
|
|
/* Turn PowerGen on
|
||
|
|
* PHY REG2 = PD_PLL | PD_DRIVE_4 | PD_DRIVE_3
|
||
|
|
* | PD_DRIVE_2 | PD_DRIVE_1 | PD_DESER
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0308, 0x3F); /*0b00111111*/
|
||
|
|
|
||
|
|
/* Turn PLL power on
|
||
|
|
* PHY REG2 = PD_DRIVE_4 | PD_DRIVE_3
|
||
|
|
* | PD_DRIVE_2 | PD_DRIVE_1 | PD_DESER
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0308, 0x1F); /*0b00011111*/
|
||
|
|
|
||
|
|
/* Write to HIGH after PLL power down de-assert
|
||
|
|
* PHY REG3 = PLL_ENABLE
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x030C, 0x01);
|
||
|
|
/* ASIC power on; PHY REG9 = 0 */
|
||
|
|
HDMI_OUTP_ND(0x0324, 0x00);
|
||
|
|
/* Enable PLL lock detect, PLL lock det will go high after lock
|
||
|
|
* Enable the re-time logic
|
||
|
|
* PHY REG12 = PLL_LOCK_DETECT_EN | RETIMING_ENABLE
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0330, 0x03); /*0b00000011*/
|
||
|
|
|
||
|
|
/* Drivers are on
|
||
|
|
* PHY REG2 = PD_DESER
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0308, 0x01); /*0b00000001*/
|
||
|
|
/* If the RX detector is needed
|
||
|
|
* PHY REG2 = RCV_SENSE_EN | PD_DESER
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0308, 0x81); /*0b10000001*/
|
||
|
|
|
||
|
|
offset = 0x0310;
|
||
|
|
while (offset <= 0x032C) {
|
||
|
|
HDMI_OUTP(offset, 0x0);
|
||
|
|
offset += 0x4;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If we want to use lock enable based on counting
|
||
|
|
* PHY REG12 = FORCE_LOCK | PLL_LOCK_DETECT_EN | RETIMING_ENABLE
|
||
|
|
*/
|
||
|
|
HDMI_OUTP_ND(0x0330, 0x13); /*0b00010011*/
|
||
|
|
}
|
||
|
|
|
||
|
|
void hdmi_msm_powerdown_phy(void)
|
||
|
|
{
|
||
|
|
/* Assert RESET PHY from controller */
|
||
|
|
HDMI_OUTP_ND(0x02D4, 0x4);
|
||
|
|
udelay(10);
|
||
|
|
/* De-assert RESET PHY from controller */
|
||
|
|
HDMI_OUTP_ND(0x02D4, 0x0);
|
||
|
|
/* Turn off Driver */
|
||
|
|
HDMI_OUTP_ND(0x0308, 0x1F);
|
||
|
|
udelay(10);
|
||
|
|
/* Disable PLL */
|
||
|
|
HDMI_OUTP_ND(0x030C, 0x00);
|
||
|
|
/* Power down PHY */
|
||
|
|
HDMI_OUTP_ND(0x0308, 0x7F); /*0b01111111*/
|
||
|
|
}
|
||
|
|
|
||
|
|
void hdmi_frame_ctrl_cfg(const struct hdmi_disp_mode_timing_type *timing)
|
||
|
|
{
|
||
|
|
/* 0x02C8 HDMI_FRAME_CTRL
|
||
|
|
* 31 INTERLACED_EN Interlaced or progressive enable bit
|
||
|
|
* 0: Frame in progressive
|
||
|
|
* 1: Frame is interlaced
|
||
|
|
* 29 HSYNC_HDMI_POL HSYNC polarity fed to HDMI core
|
||
|
|
* 0: Active Hi Hsync, detect the rising edge of hsync
|
||
|
|
* 1: Active lo Hsync, Detect the falling edge of Hsync
|
||
|
|
* 28 VSYNC_HDMI_POL VSYNC polarity fed to HDMI core
|
||
|
|
* 0: Active Hi Vsync, detect the rising edge of vsync
|
||
|
|
* 1: Active Lo Vsync, Detect the falling edge of Vsync
|
||
|
|
* 12 RGB_MUX_SEL ALPHA mdp4 input is RGB, mdp4 input is BGR
|
||
|
|
*/
|
||
|
|
HDMI_OUTP(0x02C8,
|
||
|
|
((timing->interlaced << 31) & 0x80000000)
|
||
|
|
| ((timing->active_low_h << 29) & 0x20000000)
|
||
|
|
| ((timing->active_low_v << 28) & 0x10000000)
|
||
|
|
| (1 << 12));
|
||
|
|
}
|
||
|
|
|
||
|
|
void hdmi_msm_phy_status_poll(void)
|
||
|
|
{
|
||
|
|
unsigned int phy_ready;
|
||
|
|
phy_ready = 0x1 & HDMI_INP_ND(0x33c);
|
||
|
|
if (phy_ready) {
|
||
|
|
pr_debug("HDMI Phy Status bit is set and ready\n");
|
||
|
|
} else {
|
||
|
|
pr_debug("HDMI Phy Status bit is not set,"
|
||
|
|
"waiting for ready status\n");
|
||
|
|
do {
|
||
|
|
phy_ready = 0x1 & HDMI_INP_ND(0x33c);
|
||
|
|
} while (!phy_ready);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|