272 lines
13 KiB
C
272 lines
13 KiB
C
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/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __HDMI_UTIL_H__
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#define __HDMI_UTIL_H__
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#include "mdss_io_util.h"
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#include "video/msm_hdmi_modes.h"
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/* HDMI_TX Registers */
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#define HDMI_CTRL (0x00000000)
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#define HDMI_TEST_PATTERN (0x00000010)
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#define HDMI_RANDOM_PATTERN (0x00000014)
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#define HDMI_PKT_BLK_CTRL (0x00000018)
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#define HDMI_STATUS (0x0000001C)
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#define HDMI_AUDIO_PKT_CTRL (0x00000020)
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#define HDMI_ACR_PKT_CTRL (0x00000024)
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#define HDMI_VBI_PKT_CTRL (0x00000028)
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#define HDMI_INFOFRAME_CTRL0 (0x0000002C)
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#define HDMI_INFOFRAME_CTRL1 (0x00000030)
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#define HDMI_GEN_PKT_CTRL (0x00000034)
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#define HDMI_ACP (0x0000003C)
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#define HDMI_GC (0x00000040)
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#define HDMI_AUDIO_PKT_CTRL2 (0x00000044)
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#define HDMI_ISRC1_0 (0x00000048)
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#define HDMI_ISRC1_1 (0x0000004C)
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#define HDMI_ISRC1_2 (0x00000050)
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#define HDMI_ISRC1_3 (0x00000054)
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#define HDMI_ISRC1_4 (0x00000058)
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#define HDMI_ISRC2_0 (0x0000005C)
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#define HDMI_ISRC2_1 (0x00000060)
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#define HDMI_ISRC2_2 (0x00000064)
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#define HDMI_ISRC2_3 (0x00000068)
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#define HDMI_AVI_INFO0 (0x0000006C)
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#define HDMI_AVI_INFO1 (0x00000070)
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#define HDMI_AVI_INFO2 (0x00000074)
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#define HDMI_AVI_INFO3 (0x00000078)
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#define HDMI_MPEG_INFO0 (0x0000007C)
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#define HDMI_MPEG_INFO1 (0x00000080)
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#define HDMI_GENERIC0_HDR (0x00000084)
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#define HDMI_GENERIC0_0 (0x00000088)
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#define HDMI_GENERIC0_1 (0x0000008C)
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#define HDMI_GENERIC0_2 (0x00000090)
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#define HDMI_GENERIC0_3 (0x00000094)
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#define HDMI_GENERIC0_4 (0x00000098)
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#define HDMI_GENERIC0_5 (0x0000009C)
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#define HDMI_GENERIC0_6 (0x000000A0)
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#define HDMI_GENERIC1_HDR (0x000000A4)
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#define HDMI_GENERIC1_0 (0x000000A8)
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#define HDMI_GENERIC1_1 (0x000000AC)
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#define HDMI_GENERIC1_2 (0x000000B0)
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#define HDMI_GENERIC1_3 (0x000000B4)
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#define HDMI_GENERIC1_4 (0x000000B8)
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#define HDMI_GENERIC1_5 (0x000000BC)
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#define HDMI_GENERIC1_6 (0x000000C0)
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#define HDMI_ACR_32_0 (0x000000C4)
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#define HDMI_ACR_32_1 (0x000000C8)
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#define HDMI_ACR_44_0 (0x000000CC)
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#define HDMI_ACR_44_1 (0x000000D0)
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#define HDMI_ACR_48_0 (0x000000D4)
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#define HDMI_ACR_48_1 (0x000000D8)
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#define HDMI_ACR_STATUS_0 (0x000000DC)
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#define HDMI_ACR_STATUS_1 (0x000000E0)
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#define HDMI_AUDIO_INFO0 (0x000000E4)
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#define HDMI_AUDIO_INFO1 (0x000000E8)
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#define HDMI_CS_60958_0 (0x000000EC)
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#define HDMI_CS_60958_1 (0x000000F0)
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#define HDMI_RAMP_CTRL0 (0x000000F8)
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#define HDMI_RAMP_CTRL1 (0x000000FC)
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#define HDMI_RAMP_CTRL2 (0x00000100)
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#define HDMI_RAMP_CTRL3 (0x00000104)
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#define HDMI_CS_60958_2 (0x00000108)
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#define HDMI_HDCP_CTRL (0x00000110)
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#define HDMI_HDCP_DEBUG_CTRL (0x00000114)
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#define HDMI_HDCP_INT_CTRL (0x00000118)
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#define HDMI_HDCP_LINK0_STATUS (0x0000011C)
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#define HDMI_HDCP_DDC_CTRL_0 (0x00000120)
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#define HDMI_HDCP_DDC_CTRL_1 (0x00000124)
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#define HDMI_HDCP_DDC_STATUS (0x00000128)
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#define HDMI_HDCP_ENTROPY_CTRL0 (0x0000012C)
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#define HDMI_HDCP_RESET (0x00000130)
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#define HDMI_HDCP_RCVPORT_DATA0 (0x00000134)
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#define HDMI_HDCP_RCVPORT_DATA1 (0x00000138)
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#define HDMI_HDCP_RCVPORT_DATA2_0 (0x0000013C)
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#define HDMI_HDCP_RCVPORT_DATA2_1 (0x00000140)
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#define HDMI_HDCP_RCVPORT_DATA3 (0x00000144)
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#define HDMI_HDCP_RCVPORT_DATA4 (0x00000148)
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#define HDMI_HDCP_RCVPORT_DATA5 (0x0000014C)
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#define HDMI_HDCP_RCVPORT_DATA6 (0x00000150)
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#define HDMI_HDCP_RCVPORT_DATA7 (0x00000154)
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#define HDMI_HDCP_RCVPORT_DATA8 (0x00000158)
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#define HDMI_HDCP_RCVPORT_DATA9 (0x0000015C)
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#define HDMI_HDCP_RCVPORT_DATA10 (0x00000160)
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#define HDMI_HDCP_RCVPORT_DATA11 (0x00000164)
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#define HDMI_HDCP_RCVPORT_DATA12 (0x00000168)
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#define HDMI_VENSPEC_INFO0 (0x0000016C)
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#define HDMI_VENSPEC_INFO1 (0x00000170)
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#define HDMI_VENSPEC_INFO2 (0x00000174)
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#define HDMI_VENSPEC_INFO3 (0x00000178)
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#define HDMI_VENSPEC_INFO4 (0x0000017C)
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#define HDMI_VENSPEC_INFO5 (0x00000180)
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#define HDMI_VENSPEC_INFO6 (0x00000184)
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#define HDMI_HDCP_DEBUG (0x00000194)
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#define HDMI_TMDS_CTRL_CHAR (0x0000019C)
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#define HDMI_TMDS_CTRL_SEL (0x000001A4)
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#define HDMI_TMDS_SYNCCHAR01 (0x000001A8)
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#define HDMI_TMDS_SYNCCHAR23 (0x000001AC)
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#define HDMI_TMDS_DEBUG (0x000001B4)
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#define HDMI_TMDS_CTL_BITS (0x000001B8)
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#define HDMI_TMDS_DCBAL_CTRL (0x000001BC)
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#define HDMI_TMDS_DCBAL_CHAR (0x000001C0)
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#define HDMI_TMDS_CTL01_GEN (0x000001C8)
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#define HDMI_TMDS_CTL23_GEN (0x000001CC)
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#define HDMI_AUDIO_CFG (0x000001D0)
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#define HDMI_DEBUG (0x00000204)
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#define HDMI_USEC_REFTIMER (0x00000208)
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#define HDMI_DDC_CTRL (0x0000020C)
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#define HDMI_DDC_ARBITRATION (0x00000210)
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#define HDMI_DDC_INT_CTRL (0x00000214)
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#define HDMI_DDC_SW_STATUS (0x00000218)
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#define HDMI_DDC_HW_STATUS (0x0000021C)
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#define HDMI_DDC_SPEED (0x00000220)
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#define HDMI_DDC_SETUP (0x00000224)
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#define HDMI_DDC_TRANS0 (0x00000228)
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#define HDMI_DDC_TRANS1 (0x0000022C)
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#define HDMI_DDC_TRANS2 (0x00000230)
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#define HDMI_DDC_TRANS3 (0x00000234)
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#define HDMI_DDC_DATA (0x00000238)
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#define HDMI_HDCP_SHA_CTRL (0x0000023C)
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#define HDMI_HDCP_SHA_STATUS (0x00000240)
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#define HDMI_HDCP_SHA_DATA (0x00000244)
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#define HDMI_HDCP_SHA_DBG_M0_0 (0x00000248)
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#define HDMI_HDCP_SHA_DBG_M0_1 (0x0000024C)
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#define HDMI_HPD_INT_STATUS (0x00000250)
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#define HDMI_HPD_INT_CTRL (0x00000254)
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#define HDMI_HPD_CTRL (0x00000258)
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#define HDMI_HDCP_ENTROPY_CTRL1 (0x0000025C)
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#define HDMI_HDCP_SW_UPPER_AN (0x00000260)
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#define HDMI_HDCP_SW_LOWER_AN (0x00000264)
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#define HDMI_CRC_CTRL (0x00000268)
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#define HDMI_VID_CRC (0x0000026C)
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#define HDMI_AUD_CRC (0x00000270)
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#define HDMI_VBI_CRC (0x00000274)
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#define HDMI_DDC_REF (0x0000027C)
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#define HDMI_HDCP_SW_UPPER_AKSV (0x00000284)
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#define HDMI_HDCP_SW_LOWER_AKSV (0x00000288)
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#define HDMI_CEC_CTRL (0x0000028C)
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#define HDMI_CEC_WR_DATA (0x00000290)
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#define HDMI_CEC_RETRANSMIT (0x00000294)
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#define HDMI_CEC_STATUS (0x00000298)
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#define HDMI_CEC_INT (0x0000029C)
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#define HDMI_CEC_ADDR (0x000002A0)
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#define HDMI_CEC_TIME (0x000002A4)
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#define HDMI_CEC_REFTIMER (0x000002A8)
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#define HDMI_CEC_RD_DATA (0x000002AC)
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#define HDMI_CEC_RD_FILTER (0x000002B0)
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#define HDMI_ACTIVE_H (0x000002B4)
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#define HDMI_ACTIVE_V (0x000002B8)
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#define HDMI_ACTIVE_V_F2 (0x000002BC)
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#define HDMI_TOTAL (0x000002C0)
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#define HDMI_V_TOTAL_F2 (0x000002C4)
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#define HDMI_FRAME_CTRL (0x000002C8)
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#define HDMI_AUD_INT (0x000002CC)
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#define HDMI_DEBUG_BUS_CTRL (0x000002D0)
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#define HDMI_PHY_CTRL (0x000002D4)
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#define HDMI_CEC_WR_RANGE (0x000002DC)
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#define HDMI_CEC_RD_RANGE (0x000002E0)
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#define HDMI_VERSION (0x000002E4)
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#define HDMI_BIST_ENABLE (0x000002F4)
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#define HDMI_TIMING_ENGINE_EN (0x000002F8)
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#define HDMI_INTF_CONFIG (0x000002FC)
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#define HDMI_HSYNC_CTL (0x00000300)
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#define HDMI_VSYNC_PERIOD_F0 (0x00000304)
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#define HDMI_VSYNC_PERIOD_F1 (0x00000308)
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#define HDMI_VSYNC_PULSE_WIDTH_F0 (0x0000030C)
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#define HDMI_VSYNC_PULSE_WIDTH_F1 (0x00000310)
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#define HDMI_DISPLAY_V_START_F0 (0x00000314)
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#define HDMI_DISPLAY_V_START_F1 (0x00000318)
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#define HDMI_DISPLAY_V_END_F0 (0x0000031C)
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#define HDMI_DISPLAY_V_END_F1 (0x00000320)
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#define HDMI_ACTIVE_V_START_F0 (0x00000324)
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#define HDMI_ACTIVE_V_START_F1 (0x00000328)
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#define HDMI_ACTIVE_V_END_F0 (0x0000032C)
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#define HDMI_ACTIVE_V_END_F1 (0x00000330)
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#define HDMI_DISPLAY_HCTL (0x00000334)
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#define HDMI_ACTIVE_HCTL (0x00000338)
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#define HDMI_HSYNC_SKEW (0x0000033C)
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#define HDMI_POLARITY_CTL (0x00000340)
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#define HDMI_TPG_MAIN_CONTROL (0x00000344)
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#define HDMI_TPG_VIDEO_CONFIG (0x00000348)
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#define HDMI_TPG_COMPONENT_LIMITS (0x0000034C)
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#define HDMI_TPG_RECTANGLE (0x00000350)
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#define HDMI_TPG_INITIAL_VALUE (0x00000354)
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#define HDMI_TPG_BLK_WHT_PATTERN_FRAMES (0x00000358)
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#define HDMI_TPG_RGB_MAPPING (0x0000035C)
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#define HDMI_CEC_COMPL_CTL (0x00000360)
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#define HDMI_CEC_RD_START_RANGE (0x00000364)
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#define HDMI_CEC_RD_TOTAL_RANGE (0x00000368)
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#define HDMI_CEC_RD_ERR_RESP_LO (0x0000036C)
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#define HDMI_CEC_WR_CHECK_CONFIG (0x00000370)
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/* HDMI PHY Registers */
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#define HDMI_PHY_ANA_CFG0 (0x00000000)
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#define HDMI_PHY_ANA_CFG1 (0x00000004)
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#define HDMI_PHY_PD_CTRL0 (0x00000010)
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#define HDMI_PHY_PD_CTRL1 (0x00000014)
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#define HDMI_PHY_BIST_CFG0 (0x00000034)
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#define HDMI_PHY_BIST_PATN0 (0x0000003C)
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#define HDMI_PHY_BIST_PATN1 (0x00000040)
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#define HDMI_PHY_BIST_PATN2 (0x00000044)
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#define HDMI_PHY_BIST_PATN3 (0x00000048)
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/* QFPROM Registers for HDMI/HDCP */
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#define QFPROM_RAW_FEAT_CONFIG_ROW0_LSB (0x000000F8)
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#define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB (0x000000FC)
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#define HDCP_KSV_LSB (0x000060D8)
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#define HDCP_KSV_MSB (0x000060DC)
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#define TOP_AND_BOTTOM 0x10
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#define FRAME_PACKING 0x20
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#define SIDE_BY_SIDE_HALF 0x40
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enum hdmi_tx_feature_type {
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HDMI_TX_FEAT_EDID,
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HDMI_TX_FEAT_HDCP,
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HDMI_TX_FEAT_CEC,
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HDMI_TX_FEAT_MAX,
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};
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struct hdmi_tx_ddc_ctrl {
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struct dss_io_data *io;
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struct completion ddc_sw_done;
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};
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struct hdmi_tx_ddc_data {
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char *what;
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u8 *data_buf;
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u32 data_len;
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u32 dev_addr;
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u32 offset;
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u32 request_len;
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u32 no_align;
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int retry;
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};
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/* video timing related utility routines */
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void hdmi_setup_video_mode_lut(void);
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int hdmi_get_video_id_code(struct msm_hdmi_mode_timing_info *timing_in);
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const struct msm_hdmi_mode_timing_info *hdmi_get_supported_mode(u32 mode);
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void hdmi_del_supported_mode(u32 mode);
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ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf);
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/* todo: Fix this. Right now this is defined in mdss_hdmi_tx.c */
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void *hdmi_get_featuredata_from_sysfs_dev(struct device *device, u32 type);
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/* DDC */
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void hdmi_ddc_config(struct hdmi_tx_ddc_ctrl *);
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int hdmi_ddc_isr(struct hdmi_tx_ddc_ctrl *);
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int hdmi_ddc_write(struct hdmi_tx_ddc_ctrl *, struct hdmi_tx_ddc_data *);
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int hdmi_ddc_read_seg(struct hdmi_tx_ddc_ctrl *, struct hdmi_tx_ddc_data *);
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int hdmi_ddc_read(struct hdmi_tx_ddc_ctrl *, struct hdmi_tx_ddc_data *);
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#endif /* __HDMI_UTIL_H__ */
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