314 lines
8.5 KiB
C
314 lines
8.5 KiB
C
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/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/**
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* This file contains the part of the IOMMUv0 PMU driver that actually touches
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* IOMMU PMU registers.
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*/
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <mach/iommu_hw-v0.h>
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#include <mach/iommu_perfmon.h>
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#include <mach/iommu.h>
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#define PM_RESET_MASK (0xF)
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#define PM_RESET_SHIFT (0x8)
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#define PM_RESET (PM_RESET_MASK << PM_RESET_SHIFT)
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#define PM_ENABLE_MASK (0x1)
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#define PM_ENABLE_SHIFT (0x0)
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#define PM_ENABLE (PM_ENABLE_MASK << PM_ENABLE_SHIFT)
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#define PM_OVFL_FLAG_MASK (0xF)
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#define PM_OVFL_FLAG_SHIFT (0x0)
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#define PM_OVFL_FLAG (PM_OVFL_FLAG_MASK << PM_OVFL_FLAG_SHIFT)
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#define PM_EVENT_TYPE_MASK (0x1F)
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#define PM_EVENT_TYPE_SHIFT (0x2)
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#define PM_EVENT_TYPE (PM_EVENT_TYPE_MASK << PM_EVENT_TYPE_SHIFT)
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#define PM_INT_EN_MASK (0x1)
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#define PM_INT_EN_SHIFT (0x0)
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#define PM_INT_EN (PM_INT_EN_MASK << PM_INT_EN_SHIFT)
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#define PM_INT_POL_MASK (0x1)
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#define PM_INT_POL_SHIFT (0x2)
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#define PM_INT_ACTIVE_HIGH (0x1)
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#define PMEVCNTR_(n) (EMC_N + n*4)
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#define PMEVTYPER_(n) (EMCC_N + n*4)
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/**
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* Translate between SMMUv0 event classes and standard ARM SMMU event classes
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*/
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static int iommu_pm_event_class_translation_table[] = {
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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0x8,
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0x9,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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0x80,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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0x12,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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MSM_IOMMU_PMU_NO_EVENT_CLASS,
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0x10,
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};
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static int iommu_pm_translate_event_class(int event_class)
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{
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const unsigned int TBL_LEN =
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ARRAY_SIZE(iommu_pm_event_class_translation_table);
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unsigned int i;
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if (event_class < 0)
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return event_class;
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for (i = 0; i < TBL_LEN; ++i) {
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if (iommu_pm_event_class_translation_table[i] == event_class)
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return i;
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}
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return MSM_IOMMU_PMU_NO_EVENT_CLASS;
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}
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static unsigned int iommu_pm_is_hw_access_OK(const struct iommu_pmon *pmon)
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{
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/*
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* IOMMUv0 is in always ON domain so we don't care whether we are
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* attached or not. We only care whether the PMU is enabled or
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* not meaning clocks are turned on.
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*/
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return pmon->enabled;
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}
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static void iommu_pm_grp_enable(struct iommu_info *iommu, unsigned int grp_no)
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{
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/* No group concept in v0. */
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}
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static void iommu_pm_grp_disable(struct iommu_info *iommu, unsigned int grp_no)
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{
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/* No group concept in v0. */
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}
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static void iommu_pm_set_int_active_high(const struct iommu_info *iommu)
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{
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unsigned int emmc;
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emmc = readl_relaxed(iommu->base + EMMC);
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emmc |= (PM_INT_ACTIVE_HIGH & PM_INT_POL_MASK) << PM_INT_POL_SHIFT;
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writel_relaxed(emmc, iommu->base + EMMC);
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}
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static void iommu_pm_enable(struct iommu_info *iommu)
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{
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unsigned int emmc;
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emmc = readl_relaxed(iommu->base + EMMC);
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emmc |= PM_ENABLE;
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writel_relaxed(emmc, iommu->base + EMMC);
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}
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static void iommu_pm_disable(struct iommu_info *iommu)
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{
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unsigned int emmc;
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emmc = readl_relaxed(iommu->base + EMMC);
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emmc &= ~PM_ENABLE;
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writel_relaxed(emmc, iommu->base + EMMC);
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}
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static void iommu_pm_reset_counters(const struct iommu_info *iommu)
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{
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unsigned int emmc;
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emmc = readl_relaxed(iommu->base + EMMC);
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emmc |= PM_RESET;
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writel_relaxed(emmc, iommu->base + EMMC);
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}
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static void iommu_pm_check_for_overflow(struct iommu_pmon *pmon)
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{
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struct iommu_pmon_counter *counter;
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struct iommu_info *iommu = &pmon->iommu;
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unsigned int reg_value;
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unsigned int j;
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struct iommu_pmon_cnt_group *cnt_grp = &pmon->cnt_grp[0];
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reg_value = readl_relaxed(iommu->base + EMCS);
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reg_value &= PM_OVFL_FLAG;
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for (j = 0; j < cnt_grp->num_counters; ++j) {
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counter = &cnt_grp->counters[j];
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if (counter->enabled) {
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if (reg_value & (1 << counter->absolute_counter_no))
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counter->overflow_count++;
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}
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}
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/* Clear overflow */
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writel_relaxed(reg_value, iommu->base + EMCS);
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}
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static irqreturn_t iommu_pm_evt_ovfl_int_handler(int irq, void *dev_id)
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{
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struct iommu_pmon *pmon = dev_id;
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struct iommu_info *iommu = &pmon->iommu;
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mutex_lock(&pmon->lock);
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if (!iommu_pm_is_hw_access_OK(pmon)) {
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mutex_unlock(&pmon->lock);
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goto out;
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}
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iommu->ops->iommu_lock_acquire();
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iommu_pm_check_for_overflow(pmon);
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iommu->ops->iommu_lock_release();
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mutex_unlock(&pmon->lock);
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out:
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return IRQ_HANDLED;
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}
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static void iommu_pm_counter_enable(struct iommu_info *iommu,
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struct iommu_pmon_counter *counter)
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{
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unsigned int bit_no = counter->absolute_counter_no;
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unsigned int reg_value;
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/* Clear overflow of counter */
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reg_value = readl_relaxed(iommu->base + EMCS);
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reg_value &= (1 << bit_no);
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writel_relaxed(reg_value, iommu->base + EMCS);
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/* Enable counter */
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counter->enabled = 1;
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}
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static void iommu_pm_counter_disable(struct iommu_info *iommu,
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struct iommu_pmon_counter *counter)
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{
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unsigned int bit_no = counter->absolute_counter_no;
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unsigned int reg_value;
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/* Disable counter */
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counter->enabled = 0;
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/* Clear overflow of counter */
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reg_value = readl_relaxed(iommu->base + EMCS);
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reg_value &= (1 << bit_no);
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writel_relaxed(reg_value, iommu->base + EMCS);
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}
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/*
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* Must be called after iommu_start_access() is called
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*/
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static void iommu_pm_ovfl_int_enable(struct iommu_info *iommu,
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const struct iommu_pmon_counter *counter)
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{
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unsigned int reg_no = counter->absolute_counter_no;
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unsigned int reg_value;
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/* Enable overflow interrupt for counter */
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reg_value = readl_relaxed(iommu->base + PMEVTYPER_(reg_no));
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reg_value |= PM_INT_EN;
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writel_relaxed(reg_value, iommu->base + PMEVTYPER_(reg_no));
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}
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/*
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* Must be called after iommu_start_access() is called
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*/
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static void iommu_pm_ovfl_int_disable(struct iommu_info *iommu,
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const struct iommu_pmon_counter *counter)
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{
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unsigned int reg_no = counter->absolute_counter_no;
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unsigned int reg_value;
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/* Disable overflow interrupt for counter */
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reg_value = readl_relaxed(iommu->base + PMEVTYPER_(reg_no));
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reg_value &= ~PM_INT_EN;
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writel_relaxed(reg_value, iommu->base + PMEVTYPER_(reg_no));
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}
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static void iommu_pm_set_event_class(struct iommu_pmon *pmon,
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unsigned int count_no,
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unsigned int event_class)
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{
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unsigned int reg_no = count_no;
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unsigned int reg_value;
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int event = iommu_pm_translate_event_class(event_class);
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if (event == MSM_IOMMU_PMU_NO_EVENT_CLASS)
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event = 0;
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reg_value = readl_relaxed(pmon->iommu.base + PMEVTYPER_(reg_no));
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reg_value &= ~(PM_EVENT_TYPE_MASK << PM_EVENT_TYPE_SHIFT);
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reg_value |= (event & PM_EVENT_TYPE_MASK) << PM_EVENT_TYPE_SHIFT;
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writel_relaxed(reg_value, pmon->iommu.base + PMEVTYPER_(reg_no));
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}
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static unsigned int iommu_pm_read_counter(struct iommu_pmon_counter *counter)
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{
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struct iommu_pmon *pmon = counter->cnt_group->pmon;
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struct iommu_info *info = &pmon->iommu;
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unsigned int cnt_no = counter->absolute_counter_no;
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return readl_relaxed(info->base + PMEVCNTR_(cnt_no));
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}
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static void iommu_pm_initialize_hw(const struct iommu_pmon *pmon)
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{
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const struct iommu_info *iommu = &pmon->iommu;
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struct msm_iommu_drvdata *iommu_drvdata =
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dev_get_drvdata(iommu->iommu_dev);
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/* This is called during bootup device initialization so no need
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* for locking here.
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*/
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iommu->ops->iommu_power_on(iommu_drvdata);
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iommu->ops->iommu_clk_on(iommu_drvdata);
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iommu_pm_set_int_active_high(iommu);
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iommu->ops->iommu_clk_off(iommu_drvdata);
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iommu->ops->iommu_power_off(iommu_drvdata);
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}
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static struct iommu_pm_hw_ops iommu_pm_hw_ops = {
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.initialize_hw = iommu_pm_initialize_hw,
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.is_hw_access_OK = iommu_pm_is_hw_access_OK,
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.grp_enable = iommu_pm_grp_enable,
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.grp_disable = iommu_pm_grp_disable,
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.enable_pm = iommu_pm_enable,
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.disable_pm = iommu_pm_disable,
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.reset_counters = iommu_pm_reset_counters,
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.check_for_overflow = iommu_pm_check_for_overflow,
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.evt_ovfl_int_handler = iommu_pm_evt_ovfl_int_handler,
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.counter_enable = iommu_pm_counter_enable,
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.counter_disable = iommu_pm_counter_disable,
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.ovfl_int_enable = iommu_pm_ovfl_int_enable,
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.ovfl_int_disable = iommu_pm_ovfl_int_disable,
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.set_event_class = iommu_pm_set_event_class,
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.read_counter = iommu_pm_read_counter,
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};
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struct iommu_pm_hw_ops *iommu_pm_get_hw_ops_v0(void)
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{
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return &iommu_pm_hw_ops;
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}
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EXPORT_SYMBOL(iommu_pm_get_hw_ops_v0);
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