307 lines
11 KiB
C
307 lines
11 KiB
C
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/* Freescale Local Bus Controller
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*
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* Copyright © 2006-2007, 2010 Freescale Semiconductor
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*
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* Authors: Nick Spence <nick.spence@freescale.com>,
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* Scott Wood <scottwood@freescale.com>
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* Jack Lan <jack.lan@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_FSL_LBC_H
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#define __ASM_FSL_LBC_H
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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struct fsl_lbc_bank {
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__be32 br; /**< Base Register */
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#define BR_BA 0xFFFF8000
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#define BR_BA_SHIFT 15
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#define BR_PS 0x00001800
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#define BR_PS_SHIFT 11
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#define BR_PS_8 0x00000800 /* Port Size 8 bit */
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#define BR_PS_16 0x00001000 /* Port Size 16 bit */
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#define BR_PS_32 0x00001800 /* Port Size 32 bit */
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#define BR_DECC 0x00000600
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#define BR_DECC_SHIFT 9
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#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
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#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
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#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
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#define BR_WP 0x00000100
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#define BR_WP_SHIFT 8
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#define BR_MSEL 0x000000E0
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#define BR_MSEL_SHIFT 5
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#define BR_MS_GPCM 0x00000000 /* GPCM */
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#define BR_MS_FCM 0x00000020 /* FCM */
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#define BR_MS_SDRAM 0x00000060 /* SDRAM */
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#define BR_MS_UPMA 0x00000080 /* UPMA */
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#define BR_MS_UPMB 0x000000A0 /* UPMB */
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#define BR_MS_UPMC 0x000000C0 /* UPMC */
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#define BR_V 0x00000001
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#define BR_V_SHIFT 0
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#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
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__be32 or; /**< Base Register */
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#define OR0 0x5004
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#define OR1 0x500C
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#define OR2 0x5014
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#define OR3 0x501C
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#define OR4 0x5024
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#define OR5 0x502C
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#define OR6 0x5034
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#define OR7 0x503C
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#define OR_FCM_AM 0xFFFF8000
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#define OR_FCM_AM_SHIFT 15
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#define OR_FCM_BCTLD 0x00001000
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#define OR_FCM_BCTLD_SHIFT 12
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#define OR_FCM_PGS 0x00000400
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#define OR_FCM_PGS_SHIFT 10
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#define OR_FCM_CSCT 0x00000200
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#define OR_FCM_CSCT_SHIFT 9
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#define OR_FCM_CST 0x00000100
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#define OR_FCM_CST_SHIFT 8
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#define OR_FCM_CHT 0x00000080
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#define OR_FCM_CHT_SHIFT 7
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#define OR_FCM_SCY 0x00000070
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#define OR_FCM_SCY_SHIFT 4
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#define OR_FCM_SCY_1 0x00000010
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#define OR_FCM_SCY_2 0x00000020
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#define OR_FCM_SCY_3 0x00000030
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#define OR_FCM_SCY_4 0x00000040
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#define OR_FCM_SCY_5 0x00000050
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#define OR_FCM_SCY_6 0x00000060
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#define OR_FCM_SCY_7 0x00000070
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#define OR_FCM_RST 0x00000008
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#define OR_FCM_RST_SHIFT 3
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#define OR_FCM_TRLX 0x00000004
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#define OR_FCM_TRLX_SHIFT 2
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#define OR_FCM_EHTR 0x00000002
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#define OR_FCM_EHTR_SHIFT 1
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};
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struct fsl_lbc_regs {
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struct fsl_lbc_bank bank[12];
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u8 res0[0x8];
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__be32 mar; /**< UPM Address Register */
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u8 res1[0x4];
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__be32 mamr; /**< UPMA Mode Register */
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#define MxMR_OP_NO (0 << 28) /**< normal operation */
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#define MxMR_OP_WA (1 << 28) /**< write array */
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#define MxMR_OP_RA (2 << 28) /**< read array */
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#define MxMR_OP_RP (3 << 28) /**< run pattern */
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#define MxMR_MAD 0x3f /**< machine address */
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__be32 mbmr; /**< UPMB Mode Register */
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__be32 mcmr; /**< UPMC Mode Register */
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u8 res2[0x8];
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__be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
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__be32 mdr; /**< UPM Data Register */
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u8 res3[0x4];
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__be32 lsor; /**< Special Operation Initiation Register */
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__be32 lsdmr; /**< SDRAM Mode Register */
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u8 res4[0x8];
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__be32 lurt; /**< UPM Refresh Timer */
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__be32 lsrt; /**< SDRAM Refresh Timer */
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u8 res5[0x8];
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__be32 ltesr; /**< Transfer Error Status Register */
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#define LTESR_BM 0x80000000
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#define LTESR_FCT 0x40000000
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#define LTESR_PAR 0x20000000
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#define LTESR_WP 0x04000000
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#define LTESR_ATMW 0x00800000
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#define LTESR_ATMR 0x00400000
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#define LTESR_CS 0x00080000
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#define LTESR_UPM 0x00000002
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#define LTESR_CC 0x00000001
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#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
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#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
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| LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
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| LTESR_CC)
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#define LTESR_CLEAR 0xFFFFFFFF
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#define LTECCR_CLEAR 0xFFFFFFFF
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#define LTESR_STATUS LTESR_MASK
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#define LTEIR_ENABLE LTESR_MASK
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#define LTEDR_ENABLE 0x00000000
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__be32 ltedr; /**< Transfer Error Disable Register */
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__be32 lteir; /**< Transfer Error Interrupt Register */
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__be32 lteatr; /**< Transfer Error Attributes Register */
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__be32 ltear; /**< Transfer Error Address Register */
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__be32 lteccr; /**< Transfer Error ECC Register */
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u8 res6[0x8];
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__be32 lbcr; /**< Configuration Register */
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#define LBCR_LDIS 0x80000000
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#define LBCR_LDIS_SHIFT 31
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#define LBCR_BCTLC 0x00C00000
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#define LBCR_BCTLC_SHIFT 22
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#define LBCR_AHD 0x00200000
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#define LBCR_LPBSE 0x00020000
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#define LBCR_LPBSE_SHIFT 17
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#define LBCR_EPAR 0x00010000
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#define LBCR_EPAR_SHIFT 16
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#define LBCR_BMT 0x0000FF00
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#define LBCR_BMT_SHIFT 8
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#define LBCR_BMTPS 0x0000000F
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#define LBCR_BMTPS_SHIFT 0
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#define LBCR_INIT 0x00040000
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__be32 lcrr; /**< Clock Ratio Register */
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#define LCRR_DBYP 0x80000000
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#define LCRR_DBYP_SHIFT 31
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#define LCRR_BUFCMDC 0x30000000
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#define LCRR_BUFCMDC_SHIFT 28
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#define LCRR_ECL 0x03000000
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#define LCRR_ECL_SHIFT 24
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#define LCRR_EADC 0x00030000
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#define LCRR_EADC_SHIFT 16
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#define LCRR_CLKDIV 0x0000000F
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#define LCRR_CLKDIV_SHIFT 0
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u8 res7[0x8];
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__be32 fmr; /**< Flash Mode Register */
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#define FMR_CWTO 0x0000F000
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#define FMR_CWTO_SHIFT 12
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#define FMR_BOOT 0x00000800
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#define FMR_ECCM 0x00000100
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#define FMR_AL 0x00000030
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#define FMR_AL_SHIFT 4
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#define FMR_OP 0x00000003
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#define FMR_OP_SHIFT 0
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__be32 fir; /**< Flash Instruction Register */
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#define FIR_OP0 0xF0000000
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#define FIR_OP0_SHIFT 28
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#define FIR_OP1 0x0F000000
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#define FIR_OP1_SHIFT 24
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#define FIR_OP2 0x00F00000
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#define FIR_OP2_SHIFT 20
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#define FIR_OP3 0x000F0000
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#define FIR_OP3_SHIFT 16
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#define FIR_OP4 0x0000F000
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#define FIR_OP4_SHIFT 12
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#define FIR_OP5 0x00000F00
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#define FIR_OP5_SHIFT 8
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#define FIR_OP6 0x000000F0
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#define FIR_OP6_SHIFT 4
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#define FIR_OP7 0x0000000F
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#define FIR_OP7_SHIFT 0
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#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
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#define FIR_OP_CA 0x1 /* Issue current column address */
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#define FIR_OP_PA 0x2 /* Issue current block+page address */
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#define FIR_OP_UA 0x3 /* Issue user defined address */
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#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
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#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
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#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
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#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
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#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
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#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
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#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
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#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
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#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
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#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
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#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
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#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
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__be32 fcr; /**< Flash Command Register */
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#define FCR_CMD0 0xFF000000
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#define FCR_CMD0_SHIFT 24
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#define FCR_CMD1 0x00FF0000
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#define FCR_CMD1_SHIFT 16
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#define FCR_CMD2 0x0000FF00
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#define FCR_CMD2_SHIFT 8
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#define FCR_CMD3 0x000000FF
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#define FCR_CMD3_SHIFT 0
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__be32 fbar; /**< Flash Block Address Register */
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#define FBAR_BLK 0x00FFFFFF
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__be32 fpar; /**< Flash Page Address Register */
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#define FPAR_SP_PI 0x00007C00
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#define FPAR_SP_PI_SHIFT 10
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#define FPAR_SP_MS 0x00000200
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#define FPAR_SP_CI 0x000001FF
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#define FPAR_SP_CI_SHIFT 0
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#define FPAR_LP_PI 0x0003F000
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#define FPAR_LP_PI_SHIFT 12
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#define FPAR_LP_MS 0x00000800
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#define FPAR_LP_CI 0x000007FF
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#define FPAR_LP_CI_SHIFT 0
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__be32 fbcr; /**< Flash Byte Count Register */
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#define FBCR_BC 0x00000FFF
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};
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/*
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* FSL UPM routines
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*/
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struct fsl_upm {
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__be32 __iomem *mxmr;
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int width;
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};
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extern u32 fsl_lbc_addr(phys_addr_t addr_base);
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extern int fsl_lbc_find(phys_addr_t addr_base);
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extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
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/**
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* fsl_upm_start_pattern - start UPM patterns execution
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* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
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* @pat_offset: UPM pattern offset for the command to be executed
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*
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* This routine programmes UPM so the next memory access that hits an UPM
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* will trigger pattern execution, starting at pat_offset.
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*/
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static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
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{
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clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
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}
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/**
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* fsl_upm_end_pattern - end UPM patterns execution
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* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
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*
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* This routine reverts UPM to normal operation mode.
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*/
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static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
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{
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clrbits32(upm->mxmr, MxMR_OP_RP);
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while (in_be32(upm->mxmr) & MxMR_OP_RP)
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cpu_relax();
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}
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/* overview of the fsl lbc controller */
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struct fsl_lbc_ctrl {
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/* device info */
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struct device *dev;
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struct fsl_lbc_regs __iomem *regs;
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int irq;
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wait_queue_head_t irq_wait;
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spinlock_t lock;
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void *nand;
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/* status read from LTESR by irq handler */
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unsigned int irq_status;
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#ifdef CONFIG_SUSPEND
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/* save regs when system go to deep-sleep */
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struct fsl_lbc_regs *saved_regs;
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#endif
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};
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extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
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u32 mar);
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extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
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#endif /* __ASM_FSL_LBC_H */
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