323 lines
7.7 KiB
Plaintext
323 lines
7.7 KiB
Plaintext
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/*
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* MPC8568E MDS Device Tree Source
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*
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* Copyright 2007, 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/mpc8568si-pre.dtsi"
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/ {
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model = "MPC8568EMDS";
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compatible = "MPC8568EMDS", "MPC85xxMDS";
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aliases {
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pci0 = &pci0;
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pci1 = &pci1;
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rapidio0 = &rio;
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x0>;
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};
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lbc: localbus@e0005000 {
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reg = <0x0 0xe0005000 0x0 0x1000>;
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ranges = <0x0 0x0 0xfe000000 0x02000000
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0x1 0x0 0xf8000000 0x00008000
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0x2 0x0 0xf0000000 0x04000000
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0x4 0x0 0xf8008000 0x00008000
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0x5 0x0 0xf8010000 0x00008000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x02000000>;
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bank-width = <2>;
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device-width = <2>;
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};
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bcsr@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8568mds-bcsr";
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reg = <1 0 0x8000>;
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ranges = <0 1 0 0x8000>;
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bcsr5: gpio-controller@11 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8568mds-bcsr-gpio";
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reg = <0x5 0x1>;
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gpio-controller;
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};
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};
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pib@4,0 {
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compatible = "fsl,mpc8568mds-pib";
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reg = <4 0 0x8000>;
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};
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pib@5,0 {
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compatible = "fsl,mpc8568mds-pib";
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reg = <5 0 0x8000>;
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};
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};
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soc: soc8568@e0000000 {
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ranges = <0x0 0x0 0xe0000000 0x100000>;
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i2c-sleep-nexus {
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i2c@3000 {
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <0x68>;
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interrupts = <3 1 0 0>;
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};
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};
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};
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy2>;
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};
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mdio@24520 {
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phy0: ethernet-phy@7 {
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interrupts = <1 1 0 0>;
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reg = <0x7>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupts = <2 1 0 0>;
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupts = <1 1 0 0>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupts = <2 1 0 0>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy3>;
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sleep = <&pmc 0x00000040>;
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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par_io@e0100 {
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num-ports = <7>;
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
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0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
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0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
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0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
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0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
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0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
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0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
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0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
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0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
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0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
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0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
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0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
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0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
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0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
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0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
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0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
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0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
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0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
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0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
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0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
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0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
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0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
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0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
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};
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pio2: ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
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0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
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0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
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0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
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0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
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0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
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0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
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0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
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0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
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0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
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0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
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0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
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0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
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0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
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0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
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0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
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0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
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0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
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0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
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0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
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0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
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0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
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0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
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0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
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0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
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};
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};
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};
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qe: qe@e0080000 {
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ranges = <0x0 0x0 0xe0080000 0x40000>;
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reg = <0x0 0xe0080000 0x0 0x480>;
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spi@4c0 {
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mode = "cpu";
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};
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spi@500 {
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mode = "cpu";
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};
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enet2: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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pio-handle = <&pio1>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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enet3: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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pio-handle = <&pio2>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@2120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2120 0x18>;
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compatible = "fsl,ucc-mdio";
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/* These are the same PHYs as on
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* gianfar's MDIO bus */
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qe_phy0: ethernet-phy@07 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1 0 0>;
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reg = <0x7>;
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device_type = "ethernet-phy";
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};
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qe_phy1: ethernet-phy@01 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1 0 0>;
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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qe_phy2: ethernet-phy@02 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1 0 0>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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qe_phy3: ethernet-phy@03 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1 0 0>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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};
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};
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pci0: pci@e0008000 {
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reg = <0x0 0xe0008000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x12 AD18 */
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0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
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0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
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0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
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0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
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/* IDSEL 0x13 AD19 */
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0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
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0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
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0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
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};
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/* PCI Express */
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pci1: pcie@e000a000 {
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ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
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0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
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reg = <0x0 0xe000a000 0x0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x10000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x800000>;
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};
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};
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rio: rapidio@e00c00000 {
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reg = <0x0 0xe00c0000 0x0 0x20000>;
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port1 {
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ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
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};
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};
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leds {
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compatible = "gpio-leds";
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green {
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gpios = <&bcsr5 1 0>;
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};
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amber {
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gpios = <&bcsr5 2 0>;
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};
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red {
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gpios = <&bcsr5 3 0>;
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};
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};
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};
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/include/ "fsl/mpc8568si-post.dtsi"
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