366 lines
10 KiB
C
366 lines
10 KiB
C
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// include/asm-arm/mach-omap/usb.h
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#ifndef __ASM_ARCH_OMAP_USB_H
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#define __ASM_ARCH_OMAP_USB_H
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#include <linux/io.h>
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#include <linux/usb/musb.h>
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#include <plat/board.h>
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#define OMAP3_HS_USB_PORTS 3
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enum usbhs_omap_port_mode {
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OMAP_USBHS_PORT_MODE_UNUSED,
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OMAP_EHCI_PORT_MODE_PHY,
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OMAP_EHCI_PORT_MODE_TLL,
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OMAP_EHCI_PORT_MODE_HSIC,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
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};
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struct usbhs_omap_board_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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/* have to be valid if phy_reset is true and portx is in phy mode */
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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/* Set this to true for ES2.x silicon */
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unsigned es2_compatibility:1;
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unsigned phy_reset:1;
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/*
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* Regulators for USB PHYs.
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* Each PHY can have a separate regulator.
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*/
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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};
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struct ehci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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unsigned phy_reset:1;
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};
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struct ohci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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unsigned es2_compatibility:1;
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};
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struct usbhs_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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struct ehci_hcd_omap_platform_data *ehci_data;
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struct ohci_hcd_omap_platform_data *ohci_data;
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};
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/*-------------------------------------------------------------------------*/
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#define OMAP1_OTG_BASE 0xfffb0400
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#define OMAP1_UDC_BASE 0xfffb4000
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#define OMAP1_OHCI_BASE 0xfffba000
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#define OMAP2_OHCI_BASE 0x4805e000
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#define OMAP2_UDC_BASE 0x4805e200
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#define OMAP2_OTG_BASE 0x4805e300
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#ifdef CONFIG_ARCH_OMAP1
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#define OTG_BASE OMAP1_OTG_BASE
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#define UDC_BASE OMAP1_UDC_BASE
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#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
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#else
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#define OTG_BASE OMAP2_OTG_BASE
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#define UDC_BASE OMAP2_UDC_BASE
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#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
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struct omap_musb_board_data {
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u8 interface_type;
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u8 mode;
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u16 power;
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unsigned extvbus:1;
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void (*set_phy_power)(u8 on);
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void (*clear_irq)(void);
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void (*set_mode)(u8 mode);
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void (*reset)(void);
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};
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enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
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extern void usb_musb_init(struct omap_musb_board_data *board_data);
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extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
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extern int omap4430_phy_power(struct device *dev, int ID, int on);
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extern int omap4430_phy_set_clk(struct device *dev, int on);
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extern int omap4430_phy_init(struct device *dev);
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extern int omap4430_phy_exit(struct device *dev);
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extern int omap4430_phy_suspend(struct device *dev, int suspend);
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/*
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* NOTE: Please update omap USB drivers to use ioremap + read/write
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*/
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#define OMAP2_L4_IO_OFFSET 0xb2000000
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#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
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static inline u8 omap_readb(u32 pa)
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{
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return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
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}
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static inline u16 omap_readw(u32 pa)
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{
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return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
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}
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static inline u32 omap_readl(u32 pa)
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{
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return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
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}
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static inline void omap_writeb(u8 v, u32 pa)
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{
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__raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
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}
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static inline void omap_writew(u16 v, u32 pa)
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{
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__raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
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}
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static inline void omap_writel(u32 v, u32 pa)
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{
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__raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
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}
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#endif
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extern void am35x_musb_reset(void);
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extern void am35x_musb_phy_power(u8 on);
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extern void am35x_musb_clear_irq(void);
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extern void am35x_set_mode(u8 musb_mode);
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extern void ti81xx_musb_phy_power(u8 on);
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/*
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* FIXME correct answer depends on hmc_mode,
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* as does (on omap1) any nonzero value for config->otg port number
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*/
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#ifdef CONFIG_USB_GADGET_OMAP
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#define is_usb0_device(config) 1
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#else
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#define is_usb0_device(config) 0
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#endif
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void omap_otg_init(struct omap_usb_config *config);
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#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
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void omap1_usb_init(struct omap_usb_config *pdata);
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#else
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static inline void omap1_usb_init(struct omap_usb_config *pdata)
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{
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
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void omap2_usbfs_init(struct omap_usb_config *pdata);
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#else
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static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
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{
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}
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#endif
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/*-------------------------------------------------------------------------*/
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/*
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* OTG and transceiver registers, for OMAPs starting with ARM926
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*/
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#define OTG_REV (OTG_BASE + 0x00)
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#define OTG_SYSCON_1 (OTG_BASE + 0x04)
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# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
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# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
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# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
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# define OTG_IDLE_EN (1 << 15)
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# define HST_IDLE_EN (1 << 14)
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# define DEV_IDLE_EN (1 << 13)
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# define OTG_RESET_DONE (1 << 2)
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# define OTG_SOFT_RESET (1 << 1)
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#define OTG_SYSCON_2 (OTG_BASE + 0x08)
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# define OTG_EN (1 << 31)
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# define USBX_SYNCHRO (1 << 30)
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# define OTG_MST16 (1 << 29)
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# define SRP_GPDATA (1 << 28)
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# define SRP_GPDVBUS (1 << 27)
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# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
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# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
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# define B_ASE_BRST(w) (((w)>>16)&0x07)
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# define SRP_DPW (1 << 14)
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# define SRP_DATA (1 << 13)
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# define SRP_VBUS (1 << 12)
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# define OTG_PADEN (1 << 10)
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# define HMC_PADEN (1 << 9)
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# define UHOST_EN (1 << 8)
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# define HMC_TLLSPEED (1 << 7)
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# define HMC_TLLATTACH (1 << 6)
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# define OTG_HMC(w) (((w)>>0)&0x3f)
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#define OTG_CTRL (OTG_BASE + 0x0c)
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# define OTG_USB2_EN (1 << 29)
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# define OTG_USB2_DP (1 << 28)
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# define OTG_USB2_DM (1 << 27)
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# define OTG_USB1_EN (1 << 26)
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# define OTG_USB1_DP (1 << 25)
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# define OTG_USB1_DM (1 << 24)
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# define OTG_USB0_EN (1 << 23)
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# define OTG_USB0_DP (1 << 22)
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# define OTG_USB0_DM (1 << 21)
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# define OTG_ASESSVLD (1 << 20)
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# define OTG_BSESSEND (1 << 19)
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# define OTG_BSESSVLD (1 << 18)
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# define OTG_VBUSVLD (1 << 17)
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# define OTG_ID (1 << 16)
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# define OTG_DRIVER_SEL (1 << 15)
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# define OTG_A_SETB_HNPEN (1 << 12)
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# define OTG_A_BUSREQ (1 << 11)
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# define OTG_B_HNPEN (1 << 9)
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# define OTG_B_BUSREQ (1 << 8)
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# define OTG_BUSDROP (1 << 7)
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# define OTG_PULLDOWN (1 << 5)
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# define OTG_PULLUP (1 << 4)
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# define OTG_DRV_VBUS (1 << 3)
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# define OTG_PD_VBUS (1 << 2)
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# define OTG_PU_VBUS (1 << 1)
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# define OTG_PU_ID (1 << 0)
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#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
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# define DRIVER_SWITCH (1 << 15)
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# define A_VBUS_ERR (1 << 13)
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# define A_REQ_TMROUT (1 << 12)
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# define A_SRP_DETECT (1 << 11)
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# define B_HNP_FAIL (1 << 10)
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# define B_SRP_TMROUT (1 << 9)
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# define B_SRP_DONE (1 << 8)
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# define B_SRP_STARTED (1 << 7)
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# define OPRT_CHG (1 << 0)
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#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
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// same bits as in IRQ_EN
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#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
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# define OTGVPD (1 << 14)
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# define OTGVPU (1 << 13)
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# define OTGPUID (1 << 12)
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# define USB2VDR (1 << 10)
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# define USB2PDEN (1 << 9)
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# define USB2PUEN (1 << 8)
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# define USB1VDR (1 << 6)
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# define USB1PDEN (1 << 5)
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# define USB1PUEN (1 << 4)
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# define USB0VDR (1 << 2)
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# define USB0PDEN (1 << 1)
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# define USB0PUEN (1 << 0)
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#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
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#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
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/*-------------------------------------------------------------------------*/
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/* OMAP1 */
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#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
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# define CONF_USB2_UNI_R (1 << 8)
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# define CONF_USB1_UNI_R (1 << 7)
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# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
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# define CONF_USB0_ISOLATE_R (1 << 3)
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# define CONF_USB_PWRDN_DM_R (1 << 2)
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# define CONF_USB_PWRDN_DP_R (1 << 1)
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/* OMAP2 */
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# define USB_UNIDIR 0x0
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# define USB_UNIDIR_TLL 0x1
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# define USB_BIDIR 0x2
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# define USB_BIDIR_TLL 0x3
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# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
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# define USBT2TLL5PI (1 << 17)
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# define USB0PUENACTLOI (1 << 16)
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# define USBSTANDBYCTRL (1 << 15)
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/* AM35x */
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/* USB 2.0 PHY Control */
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#define CONF2_PHY_GPIOMODE (1 << 23)
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#define CONF2_OTGMODE (3 << 14)
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#define CONF2_NO_OVERRIDE (0 << 14)
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#define CONF2_FORCE_HOST (1 << 14)
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#define CONF2_FORCE_DEVICE (2 << 14)
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#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
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#define CONF2_SESENDEN (1 << 13)
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#define CONF2_VBDTCTEN (1 << 12)
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#define CONF2_REFFREQ_24MHZ (2 << 8)
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#define CONF2_REFFREQ_26MHZ (7 << 8)
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#define CONF2_REFFREQ_13MHZ (6 << 8)
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#define CONF2_REFFREQ (0xf << 8)
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#define CONF2_PHYCLKGD (1 << 7)
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#define CONF2_VBUSSENSE (1 << 6)
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#define CONF2_PHY_PLLON (1 << 5)
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#define CONF2_RESET (1 << 4)
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#define CONF2_PHYPWRDN (1 << 3)
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#define CONF2_OTGPWRDN (1 << 2)
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#define CONF2_DATPOL (1 << 1)
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/* TI81XX specific definitions */
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#define USBCTRL0 0x620
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#define USBSTAT0 0x624
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/* TI816X PHY controls bits */
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#define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
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#define TI816X_USBPHY_REFCLK_OSC (1 << 8)
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/* TI814X PHY controls bits */
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#define USBPHY_CM_PWRDN (1 << 0)
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#define USBPHY_OTG_PWRDN (1 << 1)
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#define USBPHY_CHGDET_DIS (1 << 2)
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#define USBPHY_CHGDET_RSTRT (1 << 3)
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#define USBPHY_SRCONDM (1 << 4)
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#define USBPHY_SINKONDP (1 << 5)
|
||
|
|
#define USBPHY_CHGISINK_EN (1 << 6)
|
||
|
|
#define USBPHY_CHGVSRC_EN (1 << 7)
|
||
|
|
#define USBPHY_DMPULLUP (1 << 8)
|
||
|
|
#define USBPHY_DPPULLUP (1 << 9)
|
||
|
|
#define USBPHY_CDET_EXTCTL (1 << 10)
|
||
|
|
#define USBPHY_GPIO_MODE (1 << 12)
|
||
|
|
#define USBPHY_DPOPBUFCTL (1 << 13)
|
||
|
|
#define USBPHY_DMOPBUFCTL (1 << 14)
|
||
|
|
#define USBPHY_DPINPUT (1 << 15)
|
||
|
|
#define USBPHY_DMINPUT (1 << 16)
|
||
|
|
#define USBPHY_DPGPIO_PD (1 << 17)
|
||
|
|
#define USBPHY_DMGPIO_PD (1 << 18)
|
||
|
|
#define USBPHY_OTGVDET_EN (1 << 19)
|
||
|
|
#define USBPHY_OTGSESSEND_EN (1 << 20)
|
||
|
|
#define USBPHY_DATA_POLARITY (1 << 23)
|
||
|
|
|
||
|
|
#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
|
||
|
|
u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
|
||
|
|
u32 omap1_usb1_init(unsigned nwires);
|
||
|
|
u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
|
||
|
|
#else
|
||
|
|
static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
static inline u32 omap1_usb1_init(unsigned nwires)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
}
|
||
|
|
static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __ASM_ARCH_OMAP_USB_H */
|