101 lines
2.9 KiB
ArmAsm
101 lines
2.9 KiB
ArmAsm
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/*
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* arch/arm/mach-tegra/include/mach/debug-macro.S
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*
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* Copyright (C) 2010,2011 Google, Inc.
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* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Erik Gilling <konkers@google.com>
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* Doug Anderson <dianders@chromium.org>
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* Stephen Warren <swarren@nvidia.com>
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*
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* Portions based on mach-omap2's debug-macro.S
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* Copyright (C) 1994-1999 Russell King
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/serial_reg.h>
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#include <mach/iomap.h>
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#include <mach/irammap.h>
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.macro addruart, rp, rv, tmp
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adr \rp, 99f @ actual addr of 99f
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ldr \rv, [\rp] @ linked addr is stored there
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sub \rv, \rv, \rp @ offset between the two
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ldr \rp, [\rp, #4] @ linked tegra_uart_config
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sub \tmp, \rp, \rv @ actual tegra_uart_config
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ldr \rp, [\tmp] @ Load tegra_uart_config
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cmp \rp, #1 @ needs intitialization?
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bne 100f @ no; go load the addresses
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mov \rv, #0 @ yes; record init is done
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str \rv, [\tmp]
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mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM
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ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
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movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
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movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
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cmp \rv, \rp @ Cookie present?
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bne 100f @ No, use default UART
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mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM
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ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
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str \rv, [\tmp, #4] @ Store in tegra_uart_phys
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sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address
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add \rv, \rv, #IO_APB_VIRT
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str \rv, [\tmp, #8] @ Store in tegra_uart_virt
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b 100f
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.align
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99: .word .
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.word tegra_uart_config
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.ltorg
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100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
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ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
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.endm
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#define UART_SHIFT 2
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/*
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* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
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* check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
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* We use the fact that all 5 valid UART addresses all have something in the
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* 2nd-to-lowest byte.
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*/
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.macro senduart, rd, rx
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tst \rx, #0x0000ff00
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strneb \rd, [\rx, #UART_TX << UART_SHIFT]
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1001:
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.endm
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.macro busyuart, rd, rx
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tst \rx, #0x0000ff00
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beq 1002f
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1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
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and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
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teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
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bne 1001b
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1002:
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.endm
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.macro waituart, rd, rx
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#ifdef FLOW_CONTROL
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tst \rx, #0x0000ff00
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beq 1002f
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1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
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tst \rd, #UART_MSR_CTS
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beq 1001b
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1002:
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#endif
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.endm
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