226 lines
5.1 KiB
C
226 lines
5.1 KiB
C
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/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ARCH_ARM_MACH_MSM_SPM_H
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#define __ARCH_ARM_MACH_MSM_SPM_H
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enum {
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MSM_SPM_MODE_DISABLED,
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MSM_SPM_MODE_CLOCK_GATING,
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MSM_SPM_MODE_POWER_RETENTION,
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MSM_SPM_MODE_POWER_COLLAPSE,
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MSM_SPM_MODE_NR
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};
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enum {
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MSM_SPM_L2_MODE_DISABLED = MSM_SPM_MODE_DISABLED,
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MSM_SPM_L2_MODE_RETENTION,
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MSM_SPM_L2_MODE_GDHS,
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MSM_SPM_L2_MODE_POWER_COLLAPSE,
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};
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#if defined(CONFIG_MSM_SPM_V1)
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enum {
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MSM_SPM_REG_SAW_AVS_CTL,
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MSM_SPM_REG_SAW_CFG,
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MSM_SPM_REG_SAW_SPM_CTL,
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MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY,
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MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY,
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MSM_SPM_REG_SAW_SLP_CLK_EN,
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MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN,
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MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN,
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MSM_SPM_REG_SAW_SLP_CLMP_EN,
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MSM_SPM_REG_SAW_SLP_RST_EN,
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MSM_SPM_REG_SAW_SPM_MPM_CFG,
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MSM_SPM_REG_NR_INITIALIZE,
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MSM_SPM_REG_SAW_VCTL = MSM_SPM_REG_NR_INITIALIZE,
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MSM_SPM_REG_SAW_STS,
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MSM_SPM_REG_SAW_SPM_PMIC_CTL,
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MSM_SPM_REG_NR
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};
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struct msm_spm_platform_data {
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void __iomem *reg_base_addr;
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uint32_t reg_init_values[MSM_SPM_REG_NR_INITIALIZE];
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uint8_t awake_vlevel;
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uint8_t retention_vlevel;
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uint8_t collapse_vlevel;
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uint8_t retention_mid_vlevel;
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uint8_t collapse_mid_vlevel;
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uint32_t vctl_timeout_us;
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};
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#elif defined(CONFIG_MSM_SPM_V2)
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enum {
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MSM_SPM_REG_SAW2_CFG,
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MSM_SPM_REG_SAW2_AVS_CTL,
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MSM_SPM_REG_SAW2_AVS_HYSTERESIS,
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MSM_SPM_REG_SAW2_SPM_CTL,
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MSM_SPM_REG_SAW2_PMIC_DLY,
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MSM_SPM_REG_SAW2_AVS_LIMIT,
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MSM_SPM_REG_SAW2_AVS_DLY,
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MSM_SPM_REG_SAW2_SPM_DLY,
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MSM_SPM_REG_SAW2_PMIC_DATA_0,
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MSM_SPM_REG_SAW2_PMIC_DATA_1,
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MSM_SPM_REG_SAW2_PMIC_DATA_2,
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MSM_SPM_REG_SAW2_PMIC_DATA_3,
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MSM_SPM_REG_SAW2_PMIC_DATA_4,
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MSM_SPM_REG_SAW2_PMIC_DATA_5,
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MSM_SPM_REG_SAW2_PMIC_DATA_6,
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MSM_SPM_REG_SAW2_PMIC_DATA_7,
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MSM_SPM_REG_SAW2_RST,
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MSM_SPM_REG_NR_INITIALIZE = MSM_SPM_REG_SAW2_RST,
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MSM_SPM_REG_SAW2_ID,
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MSM_SPM_REG_SAW2_SECURE,
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MSM_SPM_REG_SAW2_STS0,
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MSM_SPM_REG_SAW2_STS1,
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MSM_SPM_REG_SAW2_VCTL,
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MSM_SPM_REG_SAW2_SEQ_ENTRY,
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MSM_SPM_REG_SAW2_SPM_STS,
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MSM_SPM_REG_SAW2_AVS_STS,
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MSM_SPM_REG_SAW2_PMIC_STS,
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MSM_SPM_REG_SAW2_VERSION,
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MSM_SPM_REG_NR,
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};
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struct msm_spm_seq_entry {
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uint32_t mode;
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uint8_t *cmd;
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bool notify_rpm;
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};
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struct msm_spm_platform_data {
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void __iomem *reg_base_addr;
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uint32_t reg_init_values[MSM_SPM_REG_NR_INITIALIZE];
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uint32_t ver_reg;
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uint32_t vctl_port;
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uint32_t phase_port;
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uint32_t pfm_port;
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uint8_t awake_vlevel;
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uint32_t vctl_timeout_us;
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uint32_t avs_timeout_us;
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uint32_t num_modes;
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struct msm_spm_seq_entry *modes;
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};
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#endif
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#if defined(CONFIG_MSM_SPM_V1) || defined(CONFIG_MSM_SPM_V2)
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/* Public functions */
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int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm);
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int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel);
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unsigned int msm_spm_get_vdd(unsigned int cpu);
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#if defined(CONFIG_MSM_SPM_V2)
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int msm_spm_turn_on_cpu_rail(unsigned int cpu);
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#else
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static inline int msm_spm_turn_on_cpu_rail(unsigned int cpu)
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{
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return -ENOSYS;
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}
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#endif
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/* Internal low power management specific functions */
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void msm_spm_reinit(void);
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int msm_spm_init(struct msm_spm_platform_data *data, int nr_devs);
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int msm_spm_device_init(void);
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#if defined(CONFIG_MSM_L2_SPM)
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/* Public functions */
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int msm_spm_l2_set_low_power_mode(unsigned int mode, bool notify_rpm);
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int msm_spm_apcs_set_vdd(unsigned int vlevel);
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int msm_spm_apcs_set_phase(unsigned int phase_cnt);
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int msm_spm_enable_fts_lpm(uint32_t mode);
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/* Internal low power management specific functions */
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int msm_spm_l2_init(struct msm_spm_platform_data *data);
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void msm_spm_l2_reinit(void);
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#else
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static inline int msm_spm_l2_set_low_power_mode(unsigned int mode,
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bool notify_rpm)
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{
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return -ENOSYS;
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}
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static inline int msm_spm_l2_init(struct msm_spm_platform_data *data)
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{
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return -ENOSYS;
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}
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static inline void msm_spm_l2_reinit(void)
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{
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/* empty */
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}
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static inline int msm_spm_apcs_set_vdd(unsigned int vlevel)
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{
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return -ENOSYS;
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}
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static inline int msm_spm_apcs_set_phase(unsigned int phase_cnt)
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{
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return -ENOSYS;
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}
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static inline int msm_spm_enable_fts_lpm(uint32_t mode)
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{
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return -ENOSYS;
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}
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#endif /* defined(CONFIG_MSM_L2_SPM) */
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#else /* defined(CONFIG_MSM_SPM_V1) || defined(CONFIG_MSM_SPM_V2) */
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static inline int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm)
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{
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return -ENOSYS;
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}
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static inline int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel)
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{
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return -ENOSYS;
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}
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static inline unsigned int msm_spm_get_vdd(unsigned int cpu)
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{
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return 0;
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}
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static inline void msm_spm_reinit(void)
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{
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/* empty */
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}
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static inline int msm_spm_turn_on_cpu_rail(unsigned int cpu)
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{
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return -ENOSYS;
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}
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static inline int msm_spm_device_init(void)
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{
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return -ENOSYS;
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}
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#endif /*defined(CONFIG_MSM_SPM_V1) || defined (CONFIG_MSM_SPM_V2) */
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#endif /* __ARCH_ARM_MACH_MSM_SPM_H */
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