100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
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/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IRQS_FSM9XXX_H
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#define __ASM_ARCH_MSM_IRQS_FSM9XXX_H
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/* MSM ACPU Interrupt Numbers */
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#define INT_DEBUG_TIMER_EXP 0
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#define INT_GPT0_TIMER_EXP 1
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#define INT_GPT1_TIMER_EXP 2
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#define INT_WDT0_ACCSCSSBARK 3
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#define INT_WDT1_ACCSCSSBARK 4
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#define INT_AVS_SVIC 5
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#define INT_AVS_SVIC_SW_DONE 6
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#define INT_SC_DBG_RX_FULL 7
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#define INT_SC_DBG_TX_EMPTY 8
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#define INT_ARMQC_PERFMON 9
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#define INT_AVS_REQ_DOWN 10
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#define INT_AVS_REQ_UP 11
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#define INT_SC_ACG 12
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/* SCSS_VICFIQSTS0[13:15] are RESERVED */
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#define INT_BPU_CPU 16
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#define INT_L2_SVICDMANSIRPTREQ 17
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#define INT_L2_SVICDMASIRPTREQ 18
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#define INT_L2_SVICSLVIRPTREQ 19
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#define INT_SEAWOLF_IRQ0 20
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#define INT_SEAWOLF_IRQ1 21
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#define INT_SEAWOLF_IRQ2 22
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#define INT_SEAWOLF_IRQ3 23
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#define INT_CARIBE_SUPSS_IRQ 24
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#define INT_ADM_SEC0_IRQ 25
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/* SCSS_VICFIQSTS0[26] is RESERVED */
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#define INT_GMII_PHY 27
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#define INT_SBD_IRQ 28
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#define INT_HH_SUPSS_IRQ 29
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#define INT_EMAC_SBD_IRQ 30
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#define INT_PERPH_SUPSS_IRQ 31
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#define INT_Q6_SW_IRQ_0 (32 + 0)
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#define INT_Q6_SW_IRQ_1 (32 + 1)
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#define INT_Q6_SW_IRQ_2 (32 + 2)
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#define INT_Q6_SW_IRQ_3 (32 + 3)
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#define INT_Q6_SW_IRQ_4 (32 + 4)
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#define INT_Q6_SW_IRQ_5 (32 + 5)
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#define INT_Q6_SW_IRQ_6 (32 + 6)
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#define INT_Q6_SW_IRQ_7 (32 + 7)
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#define INT_IMEM_IRQ (32 + 8)
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#define INT_IMEM_ECC_IRQ (32 + 9)
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#define INT_HSDDRX_IRQ (32 + 10)
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#define INT_BUFMEM_XPU_IRQ (32 + 11)
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#define INT_A9_M2A_0 (32 + 12)
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#define INT_A9_M2A_1 (32 + 13)
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#define INT_A9_M2A_2 (32 + 14)
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#define INT_A9_M2A_3 (32 + 15)
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#define INT_A9_M2A_4 (32 + 16)
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#define INT_A9_M2A_5 (32 + 17)
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#define INT_A9_M2A_6 (32 + 18)
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#define INT_A9_M2A_7 (32 + 19)
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#define INT_SC_PRI_IRQ (32 + 20)
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#define INT_SC_SEC_IRQ (32 + 21)
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#define INT_Q6_WDOG_IRQ (32 + 22)
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#define INT_ADM_SEC3_IRQ (32 + 23)
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#define INT_ARM_WAKE_IRQ (32 + 24)
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#define INT_ARM_WDOG_IRQ (32 + 25)
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#define INT_SUPSS_CFG_XPU_IRQ (32 + 26)
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#define INT_SPB_XPU_IRQ (32 + 27)
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#define INT_FPB_XPU_IRQ (32 + 28)
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#define INT_Q6_XPU_IRQ (32 + 29)
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/* SCSS_VICFIQSTS1[30:31] are RESERVED */
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/* SCSS_VICFIQSTS2[0:31] are RESERVED */
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/* SCSS_VICFIQSTS3[0:31] are RESERVED */
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/* Retrofit universal macro names */
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#define INT_ADM_AARM INT_ADM_SEC3_IRQ
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#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP
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#define INT_ADSP_A11 INT_Q6_SW_IRQ_0
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#define INT_ADSP_A11_SMSM INT_ADSP_A11
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#define INT_SIRC_0 INT_PERPH_SUPSS_IRQ
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#define WDT0_ACCSCSSNBARK_INT INT_WDT0_ACCSCSSBARK
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#define NR_MSM_IRQS 128
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#define NR_GPIO_IRQS 0
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#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS + NR_SIRC_IRQS)
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#define NR_PMIC8058_IRQS 256
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#define NR_BOARD_IRQS (NR_SIRC_IRQS + NR_PMIC8058_IRQS)
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#define NR_MSM_GPIOS 168
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#endif /* __ASM_ARCH_MSM_IRQS_FSM9XXX_H */
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