156 lines
4.2 KiB
C
156 lines
4.2 KiB
C
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/*
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* arch/arm/mach-h720x/include/mach/h7202-regs.h
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*
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* Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
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* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
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* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
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* (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This file contains the hardware definitions of the h720x processors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Do not add implementations specific defines here. This files contains
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* only defines of the onchip peripherals. Add those defines to boards.h,
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* which is included by this file.
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*/
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#define SERIAL2_OFS 0x2d000
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#define SERIAL2_BASE (IO_PHYS + SERIAL2_OFS)
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#define SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS)
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#define SERIAL3_OFS 0x2e000
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#define SERIAL3_BASE (IO_PHYS + SERIAL3_OFS)
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#define SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS)
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/* Matrix Keyboard Controller */
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#define KBD_VIRT (IO_VIRT + 0x22000)
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#define KBD_KBCR 0x00
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#define KBD_KBSC 0x04
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#define KBD_KBTR 0x08
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#define KBD_KBVR0 0x0C
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#define KBD_KBVR1 0x10
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#define KBD_KBSR 0x18
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#define KBD_KBCR_SCANENABLE (1 << 7)
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#define KBD_KBCR_NPOWERDOWN (1 << 2)
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#define KBD_KBCR_CLKSEL_MASK (3)
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#define KBD_KBCR_CLKSEL_PCLK2 0x0
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#define KBD_KBCR_CLKSEL_PCLK128 0x1
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#define KBD_KBCR_CLKSEL_PCLK256 0x2
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#define KBD_KBCR_CLKSEL_PCLK512 0x3
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#define KBD_KBSR_INTR (1 << 0)
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#define KBD_KBSR_WAKEUP (1 << 1)
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/* USB device controller */
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#define USBD_BASE (IO_VIRT + 0x12000)
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#define USBD_LENGTH 0x3C
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#define USBD_GCTRL 0x00
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#define USBD_EPCTRL 0x04
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#define USBD_INTMASK 0x08
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#define USBD_INTSTAT 0x0C
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#define USBD_PWR 0x10
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#define USBD_DMARXTX 0x14
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#define USBD_DEVID 0x18
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#define USBD_DEVCLASS 0x1C
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#define USBD_INTCLASS 0x20
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#define USBD_SETUP0 0x24
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#define USBD_SETUP1 0x28
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#define USBD_ENDP0RD 0x2C
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#define USBD_ENDP0WT 0x30
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#define USBD_ENDP1RD 0x34
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#define USBD_ENDP2WT 0x38
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/* PS/2 port */
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#define PSDATA 0x00
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#define PSSTAT 0x04
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#define PSSTAT_TXEMPTY (1<<0)
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#define PSSTAT_TXBUSY (1<<1)
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#define PSSTAT_RXFULL (1<<2)
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#define PSSTAT_RXBUSY (1<<3)
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#define PSSTAT_CLKIN (1<<4)
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#define PSSTAT_DATAIN (1<<5)
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#define PSSTAT_PARITY (1<<6)
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#define PSCONF 0x08
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#define PSCONF_ENABLE (1<<0)
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#define PSCONF_TXINTEN (1<<2)
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#define PSCONF_RXINTEN (1<<3)
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#define PSCONF_FORCECLKLOW (1<<4)
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#define PSCONF_FORCEDATLOW (1<<5)
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#define PSCONF_LCE (1<<6)
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#define PSINTR 0x0C
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#define PSINTR_TXINT (1<<0)
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#define PSINTR_RXINT (1<<1)
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#define PSINTR_PAR (1<<2)
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#define PSINTR_RXTO (1<<3)
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#define PSINTR_TXTO (1<<4)
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#define PSTDLO 0x10 /* clk low before start transmission */
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#define PSTPRI 0x14 /* PRI clock */
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#define PSTXMT 0x18 /* maximum transmission time */
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#define PSTREC 0x20 /* maximum receive time */
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#define PSPWDN 0x3c
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/* ADC converter */
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#define ADC_BASE (IO_VIRT + 0x29000)
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#define ADC_CR 0x00
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#define ADC_TSCTRL 0x04
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#define ADC_BT_CTRL 0x08
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#define ADC_MC_CTRL 0x0C
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#define ADC_STATUS 0x10
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/* ADC control register bits */
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#define ADC_CR_PW_CTRL 0x80
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#define ADC_CR_DIRECTC 0x04
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#define ADC_CR_CONTIME_NO 0x00
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#define ADC_CR_CONTIME_2 0x04
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#define ADC_CR_CONTIME_4 0x08
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#define ADC_CR_CONTIME_ADE 0x0c
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#define ADC_CR_LONGCALTIME 0x01
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/* ADC touch panel register bits */
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#define ADC_TSCTRL_ENABLE 0x80
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#define ADC_TSCTRL_INTR 0x40
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#define ADC_TSCTRL_SWBYPSS 0x20
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#define ADC_TSCTRL_SWINVT 0x10
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#define ADC_TSCTRL_S400 0x03
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#define ADC_TSCTRL_S200 0x02
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#define ADC_TSCTRL_S100 0x01
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#define ADC_TSCTRL_S50 0x00
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/* ADC Interrupt Status Register bits */
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#define ADC_STATUS_TS_BIT 0x80
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#define ADC_STATUS_MBT_BIT 0x40
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#define ADC_STATUS_BBT_BIT 0x20
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#define ADC_STATUS_MIC_BIT 0x10
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/* Touch data registers */
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#define ADC_TS_X0X1 0x30
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#define ADC_TS_X2X3 0x34
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#define ADC_TS_Y0Y1 0x38
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#define ADC_TS_Y2Y3 0x3c
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#define ADC_TS_X4X5 0x40
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#define ADC_TS_X6X7 0x44
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#define ADC_TS_Y4Y5 0x48
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#define ADC_TS_Y6Y7 0x50
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/* battery data */
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#define ADC_MB_DATA 0x54
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#define ADC_BB_DATA 0x58
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/* Sound data register */
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#define ADC_SD_DAT0 0x60
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#define ADC_SD_DAT1 0x64
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#define ADC_SD_DAT2 0x68
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#define ADC_SD_DAT3 0x6c
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#define ADC_SD_DAT4 0x70
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#define ADC_SD_DAT5 0x74
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#define ADC_SD_DAT6 0x78
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#define ADC_SD_DAT7 0x7c
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