74 lines
3.1 KiB
C
74 lines
3.1 KiB
C
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/*****************************************************************************
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* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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#ifndef CSP_HW_CFG_H
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#define CSP_HW_CFG_H
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/* ---- Include Files ---------------------------------------------------- */
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#include <cfg_global.h>
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#include <mach/csp/cap_inline.h>
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#if defined(__KERNEL__)
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#include <mach/memory_settings.h>
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#else
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#include <hw_cfg.h>
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#endif
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/* Some items that can be defined externally, but will be set to default values */
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/* if they are not defined. */
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/* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */
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/* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
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/* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
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/* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
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/* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
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/* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
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/* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
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#if defined(CFG_GLOBAL_CHIP)
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#if (CFG_GLOBAL_CHIP == FPGA11107)
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#define HW_CFG_BUS_CLK_HZ 5000000
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#define HW_CFG_DDR_CTLR_CLK_HZ 10000000
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#define HW_CFG_DDR_PHY_OMIT
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#define HW_CFG_UART_CLK_HZ 7500000
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#else
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#define HW_CFG_PLL_VCO_HZ 2000000000
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#define HW_CFG_PLL2_VCO_HZ 1800000000
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#define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ
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#define HW_CFG_BUS_CLK_HZ 166666666
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#define HW_CFG_DDR_CTLR_CLK_HZ 333333333
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#define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
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#define HW_CFG_UART_CLK_HZ 142857142
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#define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ
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#endif
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#else
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#define HW_CFG_PLL_VCO_HZ 1800000000
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#define HW_CFG_PLL2_VCO_HZ 1800000000
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#define HW_CFG_ARM_CLK_HZ 450000000
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#define HW_CFG_BUS_CLK_HZ 150000000
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#define HW_CFG_DDR_CTLR_CLK_HZ 300000000
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#define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
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#define HW_CFG_UART_CLK_HZ 150000000
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#define HW_CFG_VPM_CLK_HZ 300000000
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#endif
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/* ---- Public Constants and Types --------------------------------------- */
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/* ---- Public Variable Externs ------------------------------------------ */
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/* ---- Public Function Prototypes --------------------------------------- */
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#endif /* CSP_HW_CFG_H */
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