88 lines
3.5 KiB
Plaintext
88 lines
3.5 KiB
Plaintext
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* Qualcomm MSM IOMMU v1
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Required properties:
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- compatible : one of:
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- "qcom,msm-smmu-v1"
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- reg : offset and length of the register set for the device. Optional
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offset and length for clock register for additional clock that
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needs to be turned on for access to this IOMMU.
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- reg-names: "iommu_base", "clk_base" (optional)
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- label: name of this IOMMU instance.
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Optional properties:
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- qcom,iommu-secure-id : Secure identifier for the IOMMU block
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- qcom,secure-context : boolean indicating that a context is secure and
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programmed by the secure environment.
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- qcom,vdd-supply: Regulator needed to access IOMMU
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- qcom,alt-vdd-supply : Alternative regulator needed to access IOMMU
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configuration registers.
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- interrupts : should contain the performance monitor overflow interrupt number.
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- qcom,iommu-enable-halt : Enable halt of the IOMMU before programming certain 19
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registers
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- qcom,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups.
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- qcom,iommu-pmu-ncounters: Number of PMU counters per group.
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- qcom,iommu-pmu-event-classes: List of event classes supported.
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- Bus scaling properties: See msm_bus.txt
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- List of sub nodes, one for each of the translation context banks supported.
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Each sub node has the following required properties:
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- compatible : "qcom,msm-smmu-v1-ctx"
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- reg : offset and length of the register set for the context bank.
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- interrupts : should contain the context bank interrupt. If this is
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a secure context bank, this should be a list of 2 3-tuples where
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the first is the non-secure interrupt, and the second is the
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secure interrupt.
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- qcom,iommu-ctx-sids : List of stream identifiers associated with this
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translation context.
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- label : Name of the context bank
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- vdd-supply : vdd-supply: phandle to GDSC regulator controlling this IOMMU.
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Optional properties:
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- qcom,needs-alt-core-clk : boolean to enable the secondary core clock for
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access to the IOMMU configuration registers
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- qcom,iommu-bfb-regs : An array of unsigned 32-bit integers corresponding to
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BFB register addresses that need to be configured for performance tuning
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purposes. If this property is present, the qcom,iommu-bfb-data must also be
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present. Register addresses are specified as an offset from the base of the
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IOMMU hardware block. This property may be omitted if no BFB register
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configuration needs to be done for a particular IOMMU hardware instance. The
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registers specified by this property shall fall within the IOMMU
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implementation-defined register region.
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- qcom,iommu-bfb-data : An array of unsigned 32-bit integers representing the
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values to be programmed into the corresponding registers given by the
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qcom,iommu-bfb-regs property. If this property is present, the
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qcom,iommu-bfb-regs property shall also be present, and the lengths of both
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properties shall be the same.
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Example:
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qcom,iommu@fda64000 {
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compatible = "qcom,msm-smmu-v1";
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reg = <0xfda64000 0x10000>;
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reg-names = "iommu_base";
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vdd-supply = <&gdsc_iommu>;
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qcom,iommu-bfb-regs = <0x204c 0x2050>;
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qcom,iommu-bfb-data = <0xffff 0xffce>;
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label = "iommu_0";
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qcom,iommu-pmu-ngroups = <1>;
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qcom,iommu-pmu-ncounters = <8>;
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qcom,iommu-pmu-event-classes = <0x00,
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0x01>;
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qcom,iommu-ctx@fda6c000 {
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compatible = "qcom,msm-smmu-v1-ctx";
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reg = <0xfda6c000 0x1000>;
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interrupts = <0 70 0>;
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qcom,iommu-ctx-sids = <0 2>;
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label = "ctx_0";
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};
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qcom,iommu-ctx@fda6d000 {
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compatible = "qcom,msm-smmu-v1-ctx";
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reg = <0xfda6d000 0x1000>;
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interrupts = <0 71 0>;
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qcom,iommu-ctx-sids = <1>;
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label = "ctx_1";
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};
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};
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