105 lines
4.0 KiB
Plaintext
105 lines
4.0 KiB
Plaintext
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C6X Interrupt Chips
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-------------------
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* C64X+ Core Interrupt Controller
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The core interrupt controller provides 16 prioritized interrupts to the
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C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
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Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
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sources coming from outside the core.
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Required properties:
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--------------------
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- compatible: Should be "ti,c64x+core-pic";
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- #interrupt-cells: <1>
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Interrupt Specifier Definition
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------------------------------
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Single cell specifying the core interrupt priority level (4-15) where
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4 is highest priority and 15 is lowest priority.
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Example
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-------
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core_pic: interrupt-controller@0 {
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "ti,c64x+core-pic";
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};
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* C64x+ Megamodule Interrupt Controller
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The megamodule PIC consists of four interrupt mupliplexers each of which
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combine up to 32 interrupt inputs into a single interrupt output which
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may be cascaded into the core interrupt controller. The megamodule PIC
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has a total of 12 outputs cascading into the core interrupt controller.
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One for each core interrupt priority level. In addition to the combined
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interrupt sources, individual megamodule interrupts may be cascaded to
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the core interrupt controller. When an individual interrupt is cascaded,
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it is no longer handled through a megamodule interrupt combiner and is
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considered to have the core interrupt controller as the parent.
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Required properties:
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--------------------
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- compatible: "ti,c64x+megamod-pic"
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- interrupt-controller
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- #interrupt-cells: <1>
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- reg: base address and size of register area
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- interrupt-parent: must be core interrupt controller
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- interrupts: This should have four cells; one for each interrupt combiner.
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The cells contain the core priority interrupt to which the
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corresponding combiner output is wired.
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Optional properties:
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--------------------
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- ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
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priority interrupts. The first cell corresponds to
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core priority 4 and the last cell corresponds to
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core priority 15. The value of each cell is the
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megamodule interrupt source which is MUXed to
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the core interrupt corresponding to the cell
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position. Allowed values are 4 - 127. Mapping for
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interrupts 0 - 3 (combined interrupt sources) are
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ignored.
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Interrupt Specifier Definition
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------------------------------
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Single cell specifying the megamodule interrupt source (4-127). Note that
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interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
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use the core interrupt controller as their parent and the specifier will
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be the core priority level, not the megamodule interrupt number.
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Examples
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--------
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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interrupts = < 12 13 14 15 >;
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};
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This is a minimal example where all individual interrupts go through a
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combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
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to interrupt 13, etc.
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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interrupts = < 12 13 14 15 >;
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ti,c64x+megamod-pic-mux = < 0 0 0 0
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32 0 0 0
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0 0 0 0 >;
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};
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This the same as the first example except that megamodule interrupt 32 is
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mapped directly to core priority interrupt 8. The node using this interrupt
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must set the core controller as its interrupt parent and use 8 in the
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interrupt specifier value.
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