149 lines
4.7 KiB
C
149 lines
4.7 KiB
C
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/* @file mwifiex_pcie.h
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*
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* @brief This file contains definitions for PCI-E interface.
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* driver.
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*
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* Copyright (C) 2011, Marvell International Ltd.
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*
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* This software file (the "File") is distributed by Marvell International
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* Ltd. under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*/
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#ifndef _MWIFIEX_PCIE_H
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#define _MWIFIEX_PCIE_H
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#include <linux/pci.h>
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#include <linux/pcieport_if.h>
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#include <linux/interrupt.h>
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#include "main.h"
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#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
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/* Constants for Buffer Descriptor (BD) rings */
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#define MWIFIEX_MAX_TXRX_BD 0x20
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#define MWIFIEX_TXBD_MASK 0x3F
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#define MWIFIEX_RXBD_MASK 0x3F
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#define MWIFIEX_MAX_EVT_BD 0x04
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#define MWIFIEX_EVTBD_MASK 0x07
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/* PCIE INTERNAL REGISTERS */
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#define PCIE_SCRATCH_0_REG 0xC10
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#define PCIE_SCRATCH_1_REG 0xC14
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#define PCIE_CPU_INT_EVENT 0xC18
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#define PCIE_CPU_INT_STATUS 0xC1C
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#define PCIE_HOST_INT_STATUS 0xC30
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#define PCIE_HOST_INT_MASK 0xC34
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#define PCIE_HOST_INT_STATUS_MASK 0xC3C
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#define PCIE_SCRATCH_2_REG 0xC40
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#define PCIE_SCRATCH_3_REG 0xC44
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#define PCIE_SCRATCH_4_REG 0xCD0
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#define PCIE_SCRATCH_5_REG 0xCD4
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#define PCIE_SCRATCH_6_REG 0xCD8
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#define PCIE_SCRATCH_7_REG 0xCDC
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#define PCIE_SCRATCH_8_REG 0xCE0
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#define PCIE_SCRATCH_9_REG 0xCE4
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#define PCIE_SCRATCH_10_REG 0xCE8
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#define PCIE_SCRATCH_11_REG 0xCEC
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#define PCIE_SCRATCH_12_REG 0xCF0
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#define CPU_INTR_DNLD_RDY BIT(0)
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#define CPU_INTR_DOOR_BELL BIT(1)
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#define CPU_INTR_SLEEP_CFM_DONE BIT(2)
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#define CPU_INTR_RESET BIT(3)
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#define HOST_INTR_DNLD_DONE BIT(0)
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#define HOST_INTR_UPLD_RDY BIT(1)
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#define HOST_INTR_CMD_DONE BIT(2)
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#define HOST_INTR_EVENT_RDY BIT(3)
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#define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \
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HOST_INTR_UPLD_RDY | \
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HOST_INTR_CMD_DONE | \
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HOST_INTR_EVENT_RDY)
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#define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
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#define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
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#define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
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#define REG_CMD_ADDR_LO PCIE_SCRATCH_0_REG
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#define REG_CMD_ADDR_HI PCIE_SCRATCH_1_REG
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#define REG_CMD_SIZE PCIE_SCRATCH_2_REG
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#define REG_CMDRSP_ADDR_LO PCIE_SCRATCH_4_REG
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#define REG_CMDRSP_ADDR_HI PCIE_SCRATCH_5_REG
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/* TX buffer description read pointer */
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#define REG_TXBD_RDPTR PCIE_SCRATCH_6_REG
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/* TX buffer description write pointer */
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#define REG_TXBD_WRPTR PCIE_SCRATCH_7_REG
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/* RX buffer description read pointer */
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#define REG_RXBD_RDPTR PCIE_SCRATCH_8_REG
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/* RX buffer description write pointer */
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#define REG_RXBD_WRPTR PCIE_SCRATCH_9_REG
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/* Event buffer description read pointer */
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#define REG_EVTBD_RDPTR PCIE_SCRATCH_10_REG
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/* Event buffer description write pointer */
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#define REG_EVTBD_WRPTR PCIE_SCRATCH_11_REG
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/* Driver ready signature write pointer */
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#define REG_DRV_READY PCIE_SCRATCH_12_REG
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/* Max retry number of command write */
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#define MAX_WRITE_IOMEM_RETRY 2
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/* Define PCIE block size for firmware download */
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#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
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/* FW awake cookie after FW ready */
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#define FW_AWAKE_COOKIE (0xAA55AA55)
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struct mwifiex_pcie_buf_desc {
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u64 paddr;
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u16 len;
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u16 flags;
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} __packed;
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struct pcie_service_card {
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struct pci_dev *dev;
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struct mwifiex_adapter *adapter;
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u32 txbd_wrptr;
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u32 txbd_rdptr;
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u32 txbd_ring_size;
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u8 *txbd_ring_vbase;
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phys_addr_t txbd_ring_pbase;
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struct mwifiex_pcie_buf_desc *txbd_ring[MWIFIEX_MAX_TXRX_BD];
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struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
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u32 rxbd_wrptr;
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u32 rxbd_rdptr;
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u32 rxbd_ring_size;
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u8 *rxbd_ring_vbase;
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phys_addr_t rxbd_ring_pbase;
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struct mwifiex_pcie_buf_desc *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
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struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
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u32 evtbd_wrptr;
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u32 evtbd_rdptr;
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u32 evtbd_ring_size;
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u8 *evtbd_ring_vbase;
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phys_addr_t evtbd_ring_pbase;
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struct mwifiex_pcie_buf_desc *evtbd_ring[MWIFIEX_MAX_EVT_BD];
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struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
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struct sk_buff *cmd_buf;
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struct sk_buff *cmdrsp_buf;
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struct sk_buff *sleep_cookie;
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void __iomem *pci_mmap;
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void __iomem *pci_mmap1;
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};
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#endif /* _MWIFIEX_PCIE_H */
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