2024-09-09 08:52:07 +00:00
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#ifndef __MACH_MXC_SDMA_H__
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#define __MACH_MXC_SDMA_H__
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/**
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* struct sdma_script_start_addrs - SDMA script start pointers
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*
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* start addresses of the different functions in the physical
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* address space of the SDMA engine.
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*/
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struct sdma_script_start_addrs {
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s32 ap_2_ap_addr;
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s32 ap_2_bp_addr;
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s32 ap_2_ap_fixed_addr;
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s32 bp_2_ap_addr;
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s32 loopback_on_dsp_side_addr;
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s32 mcu_interrupt_only_addr;
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s32 firi_2_per_addr;
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s32 firi_2_mcu_addr;
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s32 per_2_firi_addr;
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s32 mcu_2_firi_addr;
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s32 uart_2_per_addr;
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s32 uart_2_mcu_addr;
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s32 per_2_app_addr;
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s32 mcu_2_app_addr;
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s32 per_2_per_addr;
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s32 uartsh_2_per_addr;
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s32 uartsh_2_mcu_addr;
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s32 per_2_shp_addr;
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s32 mcu_2_shp_addr;
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s32 ata_2_mcu_addr;
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s32 mcu_2_ata_addr;
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s32 app_2_per_addr;
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s32 app_2_mcu_addr;
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s32 shp_2_per_addr;
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s32 shp_2_mcu_addr;
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s32 mshc_2_mcu_addr;
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s32 mcu_2_mshc_addr;
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s32 spdif_2_mcu_addr;
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s32 mcu_2_spdif_addr;
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s32 asrc_2_mcu_addr;
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s32 ext_mem_2_ipu_addr;
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s32 descrambler_addr;
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s32 dptc_dvfs_addr;
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s32 utra_addr;
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s32 ram_code_start_addr;
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2024-09-09 08:57:42 +00:00
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/* End of v1 array */
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s32 mcu_2_ssish_addr;
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s32 ssish_2_mcu_addr;
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s32 hdmi_dma_addr;
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/* End of v2 array */
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2024-09-09 08:52:07 +00:00
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};
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/**
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* struct sdma_platform_data - platform specific data for SDMA engine
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*
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* @fw_name The firmware name
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* @script_addrs SDMA scripts addresses in SDMA ROM
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*/
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struct sdma_platform_data {
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char *fw_name;
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struct sdma_script_start_addrs *script_addrs;
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};
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#endif /* __MACH_MXC_SDMA_H__ */
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