482 lines
20 KiB
C
482 lines
20 KiB
C
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MSM_CLOCKS_COBALT_H
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#define __MSM_CLOCKS_COBALT_H
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/* clock_rpm controlled clocks */
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#define clk_ce1_clk 0x42229c55
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#define clk_ce1_a_clk 0x44a833fe
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#define clk_cxo_clk_src 0x79e95308
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#define clk_pnoc_clk 0x4325d220
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#define clk_pnoc_a_clk 0x2808c12b
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#define clk_bimc_clk 0x4b80bf00
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#define clk_bimc_a_clk 0x4b25668a
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#define clk_cnoc_clk 0xd5ccb7f4
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#define clk_cnoc_a_clk 0xd8fe2ccc
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#define clk_snoc_clk 0x2c341aa0
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#define clk_snoc_a_clk 0x8fcef2af
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#define clk_ln_bb_clk1 0xb867b147
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#define clk_ln_bb_clk1_ao 0x7f63a93a
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#define clk_ln_bb_clk1_pin 0x6fc5653c
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#define clk_ln_bb_clk1_pin_ao 0x25d625bf
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#define clk_ln_bb_clk2 0xf83e6387
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#define clk_ln_bb_clk2_ao 0x96f09628
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#define clk_ln_bb_clk2_pin 0xa9ebe8d5
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#define clk_ln_bb_clk2_pin_ao 0x89a1226f
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#define clk_ln_bb_clk3 0x4f52a39e
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#define clk_ln_bb_clk3_ao 0xb15eba76
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#define clk_ln_bb_clk3_pin 0xc4de7dad
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#define clk_ln_bb_clk3_pin_ao 0xc01022e8
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#define clk_bimc_msmbus_clk 0xd212feea
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#define clk_bimc_msmbus_a_clk 0x71d1a499
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#define clk_cnoc_msmbus_clk 0x62228b5d
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#define clk_cnoc_msmbus_a_clk 0x67442955
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#define clk_cxo_clk_src_ao 0x64eb6004
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#define clk_cxo_dwc3_clk 0xf79c19f6
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#define clk_cxo_lpm_clk 0x94adbf3d
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#define clk_cxo_otg_clk 0x4eec0bb9
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#define clk_cxo_pil_lpass_clk 0xe17f0ff6
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#define clk_cxo_pil_ssc_clk 0x81832015
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#define clk_cxo_pil_spss_clk 0x5cd71a61
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#define clk_div_clk1 0xaa1157a6
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#define clk_div_clk1_ao 0x6b943d68
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#define clk_div_clk2 0xd454019f
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#define clk_div_clk2_ao 0x53f9e788
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#define clk_div_clk3 0xa9a55a68
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#define clk_div_clk3_ao 0x3d6725a8
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#define clk_ipa_clk 0xfa685cda
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#define clk_ipa_a_clk 0xeeec2919
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#define clk_mcd_ce1_clk 0xbb615d26
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#define clk_mmssnoc_axi_clk 0xdb4b31e6
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#define clk_mmssnoc_axi_a_clk 0xd4970614
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#define clk_pnoc_keepalive_a_clk 0xf8f91f0b
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#define clk_pnoc_msmbus_clk 0x38b95c77
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#define clk_pnoc_msmbus_a_clk 0x8c9b4e93
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#define clk_pnoc_pm_clk 0xd6f7dfb9
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#define clk_pnoc_sps_clk 0xd482ecc7
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#define clk_qcedev_ce1_clk 0x293f97b0
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#define clk_qcrypto_ce1_clk 0xa6ac14df
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#define clk_qdss_clk 0x1492202a
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#define clk_qdss_a_clk 0xdd121669
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#define clk_qseecom_ce1_clk 0xaa858373
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#define clk_rf_clk1 0xaabeea5a
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#define clk_rf_clk1_ao 0x72a10cb8
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#define clk_rf_clk1_pin 0x8f463562
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#define clk_rf_clk1_pin_ao 0x62549ff6
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#define clk_rf_clk2 0x24a30992
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#define clk_rf_clk2_ao 0x944d8bbd
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#define clk_rf_clk2_pin 0xa7c5602a
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#define clk_rf_clk2_pin_ao 0x2d75eb4d
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#define clk_rf_clk3 0xb673936b
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#define clk_rf_clk3_ao 0x038bb968
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#define clk_rf_clk3_pin 0x726f53f5
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#define clk_rf_clk3_pin_ao 0x76f9240f
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#define clk_scm_ce1_clk 0xd8ebcc62
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#define clk_snoc_msmbus_clk 0xe6900bb6
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#define clk_snoc_msmbus_a_clk 0x5d4683bd
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#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01
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#define clk_gcc_ce1_axi_m_clk 0xc174dfba
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#define clk_aggre1_noc_clk 0x049abba8
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#define clk_aggre1_noc_a_clk 0xc12e4220
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#define clk_aggre2_noc_clk 0xaa681404
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#define clk_aggre2_noc_a_clk 0xcab67089
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#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11
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/* clock_gcc controlled clocks*/
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#define clk_debug_mmss_clk 0x977c99b6
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#define clk_debug_rpm_clk 0x8e2b07ca
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#define clk_debug_cpu_clk 0x0e696b2b
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#define clk_gpu_gcc_debug_clk 0x3eb88190
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#define clk_gpll0 0x1ebe3bc4
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#define clk_gpll0_out_main 0xe9374de7
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#define clk_gpll0_ao 0xa1368304
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#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d
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#define clk_gpll4 0xb3b5d85b
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#define clk_gpll4_out_main 0xa9a0ab9d
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#define clk_hmss_ahb_clk_src 0xaec8450f
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#define clk_usb30_master_clk_src 0xc6262f89
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#define clk_pcie_aux_clk_src 0xebc50566
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#define clk_ufs_axi_clk_src 0x297ca380
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#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e
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#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa
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#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79
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#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a
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#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902
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#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f
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#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68
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#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb
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#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804
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#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f
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#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803
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#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4
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#define clk_blsp1_uart1_apps_clk_src 0xf8146114
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#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73
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#define clk_blsp1_uart3_apps_clk_src 0x600497f2
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#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d
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#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365
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#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51
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#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44
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#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c
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#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92
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#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c
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#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1
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#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd
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#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e
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#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151
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#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755
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#define clk_blsp2_uart1_apps_clk_src 0x562c66dc
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#define clk_blsp2_uart2_apps_clk_src 0xdd448080
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#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f
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#define clk_glm_clk_src 0x532bf9ac
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#define clk_gp1_clk_src 0xad85b97a
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#define clk_gp2_clk_src 0xfb1f0065
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#define clk_gp3_clk_src 0x63b693d6
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#define clk_hmss_rbcpr_clk_src 0xedd9a474
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#define clk_pdm2_clk_src 0x31e494fd
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#define clk_sdcc2_apps_clk_src 0xfc46c821
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#define clk_sdcc4_apps_clk_src 0x7aaaaa0c
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#define clk_tsif_ref_clk_src 0x4e9042d1
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#define clk_ufs_ice_core_clk_src 0xda8e7119
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#define clk_ufs_phy_aux_clk_src 0xc6bca085
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#define clk_ufs_unipro_core_clk_src 0x179e80a9
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#define clk_usb30_mock_utmi_clk_src 0xa024a976
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#define clk_usb3_phy_aux_clk_src 0x15eec63c
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#define clk_gcc_pcie_phy_0_reset 0x6bb4df33
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#define clk_gcc_usb3_phy_reset 0x03d559f1
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#define clk_gcc_usb3phy_phy_reset 0xb1a4f885
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#define clk_gcc_aggre1_ufs_axi_clk 0x873459d8
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#define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8
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#define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f
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#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f
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#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9
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#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0
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#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220
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#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f
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#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82
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#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880
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#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f
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#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f
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#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604
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#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7
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#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820
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#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85
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#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90
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#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96
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#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7
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#define clk_gcc_blsp2_ahb_clk 0x8f283c1d
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#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd
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#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc
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#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e
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#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d
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#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170
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#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6
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#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d
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#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93
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#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d
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#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd
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#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4
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#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a
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#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff
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#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3
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#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab
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#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1
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#define clk_gcc_bimc_gfx_clk 0x3edd69ad
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#define clk_gcc_cfg_noc_usb3_axi_clk 0x9ea4c2d9
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#define clk_gcc_glm_ahb_clk 0x9fa410cc
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#define clk_gcc_glm_clk 0x8170c540
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#define clk_gcc_glm_xo_clk 0x3f1df8b2
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#define clk_gcc_gp1_clk 0x057f7b69
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#define clk_gcc_gp2_clk 0x9bf83ffd
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#define clk_gcc_gp3_clk 0xec6539ee
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#define clk_gcc_gpu_snoc_dvm_gfx_clk 0xc9147451
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#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b
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#define clk_gcc_gpu_bimc_gfx_src_clk 0x377cb748
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#define clk_gcc_bimc_hmss_axi_clk 0x84653931
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#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57
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#define clk_gcc_hmss_ahb_clk 0x62818713
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#define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53
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#define clk_gcc_hmss_rbcpr_clk 0x699183be
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#define clk_hmss_gpll0_clk_src 0x17eb05d0
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#define clk_hmss_gpll4_clk_src 0x20456cae
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#define clk_gcc_mmss_qm_ahb_clk 0xc759178c
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#define clk_gcc_mmss_qm_core_clk 0xa3412619
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#define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b
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#define clk_gcc_mss_at_clk 0x1692c5aa
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#define clk_nav_gcc_dbg_clk 0x2221c544
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#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece
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#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3
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#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b
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#define clk_gcc_pcie_0_pipe_clk 0x4f37621e
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#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1
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#define clk_gcc_pcie_phy_aux_clk 0x4746e74f
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#define clk_gcc_pdm2_clk 0x99d55711
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#define clk_gcc_pdm_ahb_clk 0x365664f6
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#define clk_gcc_prng_ahb_clk 0x397e7eaa
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#define clk_gcc_sdcc2_ahb_clk 0x23d5727f
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#define clk_gcc_sdcc2_apps_clk 0x861b20ac
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#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8
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#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8
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#define clk_gcc_tsif_ahb_clk 0x88d2822c
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#define clk_gcc_tsif_ref_clk 0x8f1ed2c2
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#define clk_gcc_ufs_ahb_clk 0x1914bb84
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#define clk_gcc_ufs_axi_clk 0x47c743a7
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#define clk_gcc_ufs_ice_core_clk 0x310b0710
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#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb
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#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c
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#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a
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#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7
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#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd
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#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2
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#define clk_gcc_usb30_master_clk 0xb3b4e2cb
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#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a
|
||
|
|
#define clk_gcc_usb30_sleep_clk 0xd0b65c92
|
||
|
|
#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0
|
||
|
|
#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2
|
||
|
|
#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e
|
||
|
|
#define clk_gcc_wcss_ahb_s0_clk 0x639a01c4
|
||
|
|
#define clk_gcc_wcss_axi_m_clk 0xabc48ebd
|
||
|
|
#define clk_gcc_wcss_ecahb_clk 0xf1815ce9
|
||
|
|
#define clk_gcc_usb3_clkref_clk 0xb6cc8f00
|
||
|
|
#define clk_gcc_hdmi_clkref_clk 0x4d4eec04
|
||
|
|
#define clk_gcc_edp_clkref_clk 0xa8685c3f
|
||
|
|
#define clk_gcc_ufs_clkref_clk 0x92aa126f
|
||
|
|
#define clk_gcc_pcie_clkref_clk 0xa2e247fa
|
||
|
|
#define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d
|
||
|
|
#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25
|
||
|
|
#define clk_gcc_pcie_0_phy_reset 0xdc3201c1
|
||
|
|
#define clk_gcc_pcie_phy_reset 0x9bc3c959
|
||
|
|
#define clk_gcc_pcie_phy_com_reset 0x8bf513e6
|
||
|
|
#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da
|
||
|
|
#define clk_gcc_qusb2phy_prim_reset 0x07550fa1
|
||
|
|
#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0
|
||
|
|
#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99
|
||
|
|
#define clk_gcc_wcss_shdreg_ahb_clk 0x33459c85
|
||
|
|
#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743
|
||
|
|
#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f
|
||
|
|
#define clk_gcc_mss_cfg_ahb_clk 0x111cde81
|
||
|
|
#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62
|
||
|
|
#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f
|
||
|
|
#define clk_gpll0_out_msscc 0x7d794829
|
||
|
|
#define clk_gcc_mss_snoc_axi_clk 0x0e71de85
|
||
|
|
#define clk_gcc_debug_mux 0x8121ac15
|
||
|
|
|
||
|
|
/* clock_mmss controlled clocks */
|
||
|
|
#define clk_mmpll2 0x1190e4d8
|
||
|
|
#define clk_mmpll3 0x18c76899
|
||
|
|
#define clk_mmpll4 0x22c063c1
|
||
|
|
#define clk_mmpll5 0xa41e1936
|
||
|
|
#define clk_mmpll6 0xc56fb440
|
||
|
|
#define clk_mmpll7 0x3ac216af
|
||
|
|
#define clk_mmpll8 0xd06ad45e
|
||
|
|
#define clk_mmpll9 0x1c50684c
|
||
|
|
#define clk_mmpll10 0x2561263b
|
||
|
|
#define clk_mmpll2_out_main 0x1e9e24a8
|
||
|
|
#define clk_mmpll3_out_main 0x6eb6328f
|
||
|
|
#define clk_mmpll4_out_main 0xfb21c2fd
|
||
|
|
#define clk_mmpll5_out_main 0xcc1897bf
|
||
|
|
#define clk_mmpll6_out_main 0xfb1060bd
|
||
|
|
#define clk_mmpll7_out_main 0x767758ed
|
||
|
|
#define clk_mmpll8_out_main 0x75b1f386
|
||
|
|
#define clk_mmpll9_out_main 0x16b74937
|
||
|
|
#define clk_mmpll10_out_main 0x3c5668f3
|
||
|
|
#define clk_csi0_clk_src 0x227e65bc
|
||
|
|
#define clk_vfe0_clk_src 0xa0c2bd8f
|
||
|
|
#define clk_vfe1_clk_src 0x4e357366
|
||
|
|
#define clk_mdp_clk_src 0x6dc1f8f1
|
||
|
|
#define clk_maxi_clk_src 0x52c09777
|
||
|
|
#define clk_cpp_clk_src 0x8382f56d
|
||
|
|
#define clk_jpeg0_clk_src 0x9a0a0ac3
|
||
|
|
#define clk_rot_clk_src 0xce49b56c
|
||
|
|
#define clk_video_core_clk_src 0x8be4c944
|
||
|
|
#define clk_csi1_clk_src 0x6a2a6c36
|
||
|
|
#define clk_csi2_clk_src 0x4113589f
|
||
|
|
#define clk_csi3_clk_src 0xfd934012
|
||
|
|
#define clk_fd_core_clk_src 0xe4799ab7
|
||
|
|
#define clk_dp_crypto_clk_src 0xf8faa811
|
||
|
|
#define clk_dp_pixel_clk_src 0xf5dfbabf
|
||
|
|
#define clk_pclk0_clk_src 0xccac1f35
|
||
|
|
#define clk_pclk1_clk_src 0x090f68ac
|
||
|
|
#define clk_mmsscc_xo 0x05e63704
|
||
|
|
#define clk_mmsscc_gpll0 0xe900c515
|
||
|
|
#define clk_video_subcore0_clk_src 0x88d79636
|
||
|
|
#define clk_video_subcore1_clk_src 0x4966930c
|
||
|
|
#define clk_cci_clk_src 0x822f3d97
|
||
|
|
#define clk_camss_gp0_clk_src 0x43b063e9
|
||
|
|
#define clk_camss_gp1_clk_src 0xa3315f1b
|
||
|
|
#define clk_mclk0_clk_src 0x266b3853
|
||
|
|
#define clk_mclk1_clk_src 0xa73cad0c
|
||
|
|
#define clk_mclk2_clk_src 0x42545468
|
||
|
|
#define clk_mclk3_clk_src 0x2bfbb714
|
||
|
|
#define clk_csi0phytimer_clk_src 0xc8a309be
|
||
|
|
#define clk_csi1phytimer_clk_src 0x7c0fe23a
|
||
|
|
#define clk_csi2phytimer_clk_src 0x62ffea9c
|
||
|
|
#define clk_byte0_clk_src 0x75cc885b
|
||
|
|
#define clk_byte1_clk_src 0x63c2c955
|
||
|
|
#define clk_dp_aux_clk_src 0x2b6e972b
|
||
|
|
#define clk_dp_gtc_clk_src 0xc5a86a42
|
||
|
|
#define clk_dp_link_clk_src 0x370d0626
|
||
|
|
#define clk_esc0_clk_src 0xb41d7c38
|
||
|
|
#define clk_esc1_clk_src 0x3b0afa42
|
||
|
|
#define clk_extpclk_clk_src 0xb2c31abd
|
||
|
|
#define clk_hdmi_clk_src 0xb40aeea9
|
||
|
|
#define clk_vsync_clk_src 0xecb43940
|
||
|
|
#define clk_bimc_smmu_ahb_clk 0x5b71f87d
|
||
|
|
#define clk_bimc_smmu_axi_clk 0x49cfc61c
|
||
|
|
#define clk_snoc_dvm_axi_clk 0x72bbd57a
|
||
|
|
#define clk_bto_ahb_clk 0x3844ec63
|
||
|
|
#define clk_camss_ahb_clk 0xc4ff91d4
|
||
|
|
#define clk_camss_cci_ahb_clk 0x04c4441a
|
||
|
|
#define clk_camss_cci_clk 0xd6cb5eb9
|
||
|
|
#define clk_camss_cpp_ahb_clk 0x12e9a87b
|
||
|
|
#define clk_camss_cpp_clk 0xb82f366b
|
||
|
|
#define clk_camss_cpp_axi_clk 0x5598c804
|
||
|
|
#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4
|
||
|
|
#define clk_camss_cphy_csid0_clk 0x25706297
|
||
|
|
#define clk_camss_csi0_ahb_clk 0x6e29c972
|
||
|
|
#define clk_camss_csi0_clk 0x30862ddb
|
||
|
|
#define clk_camss_csi0pix_clk 0x6946f77b
|
||
|
|
#define clk_camss_csi0rdi_clk 0x83645ef5
|
||
|
|
#define clk_camss_cphy_csid1_clk 0x0404b393
|
||
|
|
#define clk_camss_csi1_ahb_clk 0xccc15f06
|
||
|
|
#define clk_camss_csi1_clk 0xb150f052
|
||
|
|
#define clk_camss_csi1pix_clk 0x58d19bf3
|
||
|
|
#define clk_camss_csi1rdi_clk 0x4d2f3352
|
||
|
|
#define clk_camss_cphy_csid2_clk 0xe9d0fe2f
|
||
|
|
#define clk_camss_csi2_ahb_clk 0x92d02d75
|
||
|
|
#define clk_camss_csi2_clk 0x74fc92e8
|
||
|
|
#define clk_camss_csi2pix_clk 0xf8ed0731
|
||
|
|
#define clk_camss_csi2rdi_clk 0xdc1b2081
|
||
|
|
#define clk_camss_cphy_csid3_clk 0x4eccef6c
|
||
|
|
#define clk_camss_csi3_ahb_clk 0xee5e459c
|
||
|
|
#define clk_camss_csi3_clk 0x39488fdd
|
||
|
|
#define clk_camss_csi3pix_clk 0xd82bd467
|
||
|
|
#define clk_camss_csi3rdi_clk 0xb6750046
|
||
|
|
#define clk_camss_csi_vfe0_clk 0x3023937a
|
||
|
|
#define clk_camss_csi_vfe1_clk 0xe66fa522
|
||
|
|
#define clk_camss_csiphy0_clk 0x6e1782f1
|
||
|
|
#define clk_camss_csiphy1_clk 0x10d2e851
|
||
|
|
#define clk_camss_csiphy2_clk 0x4c54acb5
|
||
|
|
#define clk_fd_ahb_clk 0x868a2c5c
|
||
|
|
#define clk_fd_core_clk 0x3badcae4
|
||
|
|
#define clk_fd_core_uar_clk 0x7e624e15
|
||
|
|
#define clk_camss_gp0_clk 0xcee7e51d
|
||
|
|
#define clk_camss_gp1_clk 0x41f1c2e3
|
||
|
|
#define clk_camss_ispif_ahb_clk 0x9a212c6d
|
||
|
|
#define clk_camss_jpeg0_clk 0x0b0e2db7
|
||
|
|
#define clk_camss_jpeg_ahb_clk 0x1f47fd28
|
||
|
|
#define clk_camss_jpeg_axi_clk 0x9e5545c8
|
||
|
|
#define clk_camss_mclk0_clk 0xcf0c61e0
|
||
|
|
#define clk_camss_mclk1_clk 0xd1410ed4
|
||
|
|
#define clk_camss_mclk2_clk 0x851286f2
|
||
|
|
#define clk_camss_mclk3_clk 0x4db11c45
|
||
|
|
#define clk_camss_micro_ahb_clk 0x33a23277
|
||
|
|
#define clk_camss_csi0phytimer_clk 0xff93b3c8
|
||
|
|
#define clk_camss_csi1phytimer_clk 0x6c399ab6
|
||
|
|
#define clk_camss_csi2phytimer_clk 0x24f47f49
|
||
|
|
#define clk_camss_top_ahb_clk 0x8f8b2d33
|
||
|
|
#define clk_camss_vfe0_ahb_clk 0x4652833c
|
||
|
|
#define clk_camss_vfe0_clk 0x1e9bb8c4
|
||
|
|
#define clk_camss_vfe0_stream_clk 0x22835fa4
|
||
|
|
#define clk_camss_vfe1_ahb_clk 0x6a56abd3
|
||
|
|
#define clk_camss_vfe1_clk 0x5bffa69b
|
||
|
|
#define clk_camss_vfe1_stream_clk 0x92f849b9
|
||
|
|
#define clk_camss_vfe_vbif_ahb_clk 0x69b314cf
|
||
|
|
#define clk_camss_vfe_vbif_axi_clk 0x37390d57
|
||
|
|
#define clk_mdss_ahb_clk 0x684ccb41
|
||
|
|
#define clk_mdss_axi_clk 0xcc07d687
|
||
|
|
#define clk_mdss_byte0_clk 0xf5a03f64
|
||
|
|
#define clk_mdss_byte0_intf_clk 0x78d77f37
|
||
|
|
#define clk_mdss_byte1_clk 0xb8c7067d
|
||
|
|
#define clk_mdss_byte1_intf_clk 0xca7f2082
|
||
|
|
#define clk_mdss_dp_aux_clk 0xac5fd97c
|
||
|
|
#define clk_mdss_dp_crypto_clk 0x3492537d
|
||
|
|
#define clk_mdss_dp_gtc_clk 0x32341887
|
||
|
|
#define clk_mdss_dp_link_clk 0xef31ea17
|
||
|
|
#define clk_mdss_dp_link_intf_clk 0x960e00b8
|
||
|
|
#define clk_mdss_dp_pixel_clk 0x0173b158
|
||
|
|
#define clk_mdss_esc0_clk 0x28cafbe6
|
||
|
|
#define clk_mdss_esc1_clk 0xc22c6883
|
||
|
|
#define clk_mdss_extpclk_clk 0xfa5aadb0
|
||
|
|
#define clk_mdss_hdmi_clk 0x097a6de9
|
||
|
|
#define clk_mdss_hdmi_dp_ahb_clk 0x862fc1ba
|
||
|
|
#define clk_mdss_mdp_clk 0x618336ac
|
||
|
|
#define clk_mdss_pclk0_clk 0x3487234a
|
||
|
|
#define clk_mdss_pclk1_clk 0xd5804246
|
||
|
|
#define clk_mdss_rot_clk 0x954e31b8
|
||
|
|
#define clk_mdss_vsync_clk 0x42a022d3
|
||
|
|
#define clk_misc_ahb_clk 0xdfbd704c
|
||
|
|
#define clk_misc_cxo_clk 0x012c041f
|
||
|
|
#define clk_mnoc_maxi_clk 0x4def770c
|
||
|
|
#define clk_spdm_ahb_clk 0xdfae8ed9
|
||
|
|
#define clk_spdm_axi_clk 0x31ef53a3
|
||
|
|
#define clk_spdm_cpp_clk 0x3f58e5f8
|
||
|
|
#define clk_spdm_csi0_clk 0x5e537bc8
|
||
|
|
#define clk_spdm_debug_clk 0xa850c7fb
|
||
|
|
#define clk_spdm_dp_crypto_clk 0xdb01d21e
|
||
|
|
#define clk_spdm_dp_pixel_clk 0x321dd909
|
||
|
|
#define clk_spdm_jpeg0_clk 0x28f07f34
|
||
|
|
#define clk_spdm_mdp_clk 0xafc15ea1
|
||
|
|
#define clk_spdm_pclk0_clk 0x6d440ee3
|
||
|
|
#define clk_spdm_pclk1_clk 0xb93af2ab
|
||
|
|
#define clk_spdm_rot_clk 0x105c1345
|
||
|
|
#define clk_spdm_vfe0_clk 0x64266893
|
||
|
|
#define clk_spdm_vfe1_clk 0xdb738e6c
|
||
|
|
#define clk_spdm_video_core_clk 0x76baf313
|
||
|
|
#define clk_spdm_rm_axi_clk 0x3bac1b23
|
||
|
|
#define clk_spdm_rm_maxi_clk 0xd5cf2f39
|
||
|
|
#define clk_camss_micro_ahb_slp_stg_clk 0x51441764
|
||
|
|
#define clk_throttle_camss_ahb_clk 0x5c3b3b21
|
||
|
|
#define clk_throttle_camss_axi_clk 0xbaa23c28
|
||
|
|
#define clk_throttle_camss_cxo_clk 0x93e27c3b
|
||
|
|
#define clk_throttle_mdss_ahb_clk 0x8ae6585f
|
||
|
|
#define clk_throttle_mdss_axi_clk 0xc7850107
|
||
|
|
#define clk_throttle_mdss_cxo_clk 0xadb11a10
|
||
|
|
#define clk_throttle_video_ahb_clk 0x5612a745
|
||
|
|
#define clk_throttle_video_axi_clk 0x06c344d6
|
||
|
|
#define clk_throttle_video_cxo_clk 0x808d592e
|
||
|
|
#define clk_video_subcore0_clk 0xb6f63e6c
|
||
|
|
#define clk_video_subcore1_clk 0x26c29cb4
|
||
|
|
#define clk_video_ahb_clk 0x90775cfb
|
||
|
|
#define clk_video_axi_clk 0xe6c16dba
|
||
|
|
#define clk_video_core_clk 0x7e876ec3
|
||
|
|
#define clk_video_maxi_clk 0x97749db6
|
||
|
|
#define clk_vmem_ahb_clk 0xab6223ff
|
||
|
|
#define clk_vmem_maxi_clk 0x15ef32db
|
||
|
|
#define clk_mmss_debug_mux 0xe646ffda
|
||
|
|
|
||
|
|
/* clock_gpu controlled clocks*/
|
||
|
|
#define clk_gpucc_xo 0xc4e1a890
|
||
|
|
#define clk_gpucc_gpll0 0x0db0e37f
|
||
|
|
#define clk_gfx3d_clk_src 0x917f76ef
|
||
|
|
#define clk_rbbmtimer_clk_src 0x17649ecc
|
||
|
|
#define clk_gfx3d_isense_clk_src 0xecc3eafa
|
||
|
|
#define clk_rbcpr_clk_src 0x2c2e9af2
|
||
|
|
#define clk_gpu_debug_div_clk 0x75d6f53f
|
||
|
|
#define clk_gpucc_gfx3d_clk 0x95f01bd5
|
||
|
|
#define clk_gpucc_rbbmtimer_clk 0x58a0a7ca
|
||
|
|
#define clk_gpucc_gfx3d_isense_clk 0xb2678e80
|
||
|
|
#define clk_gpucc_cxo_clk 0x6532dcae
|
||
|
|
#define clk_gpucc_rbcpr_clk 0x7bd750e8
|
||
|
|
#define clk_gpu_pll0_pll 0x0e61ab4d
|
||
|
|
#define clk_gpu_pll0_pll_out_even 0xb0ed5009
|
||
|
|
#define clk_gpu_pll0_pll_out_odd 0x08c5a8a5
|
||
|
|
#define clk_gpu_pll0_postdiv_clk 0x76c19f3c
|
||
|
|
#define clk_gpu_pll1_pll 0x09ac81ef
|
||
|
|
#define clk_gpu_pll1_pll_out_even 0xa503de04
|
||
|
|
#define clk_gpu_pll1_pll_out_odd 0x1c205dfb
|
||
|
|
#define clk_gpu_pll1_postdiv_clk 0xdf546700
|
||
|
|
#define clk_gpucc_mx_clk 0x1edbb879
|
||
|
|
#define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c
|
||
|
|
|
||
|
|
#endif
|