2024-09-09 08:57:42 +00:00
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/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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2024-09-09 08:52:07 +00:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef DSI_HOST_V2_H
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#define DSI_HOST_V2_H
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#include <linux/bitops.h>
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#define DSI_INTR_ERROR_MASK BIT(25)
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#define DSI_INTR_ERROR BIT(24)
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2024-09-09 08:57:42 +00:00
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#define DSI_INTR_BTA_DONE_MASK BIT(21)
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#define DSI_INTR_BTA_DONE BIT(20)
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#define DSI_INTR_VIDEO_DONE_MASK BIT(17)
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#define DSI_INTR_VIDEO_DONE BIT(16)
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#define DSI_INTR_CMD_MDP_DONE_MASK BIT(9)
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#define DSI_INTR_CMD_MDP_DONE BIT(8)
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#define DSI_INTR_CMD_DMA_DONE_MASK BIT(1)
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#define DSI_INTR_CMD_DMA_DONE BIT(0)
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2024-09-09 08:57:42 +00:00
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#define DSI_INTR_ALL_MASK 0x2220202
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#define DSI_BTA_TERM BIT(1)
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2024-09-09 08:52:07 +00:00
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#define DSI_CTRL 0x0000
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#define DSI_STATUS 0x0004
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#define DSI_FIFO_STATUS 0x0008
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#define DSI_VIDEO_MODE_CTRL 0x000C
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#define DSI_VIDEO_MODE_DATA_CTRL 0x001C
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#define DSI_VIDEO_MODE_ACTIVE_H 0x0020
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#define DSI_VIDEO_MODE_ACTIVE_V 0x0024
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#define DSI_VIDEO_MODE_TOTAL 0x0028
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#define DSI_VIDEO_MODE_HSYNC 0x002C
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#define DSI_VIDEO_MODE_VSYNC 0x0030
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#define DSI_VIDEO_MODE_VSYNC_VPOS 0x0034
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#define DSI_COMMAND_MODE_DMA_CTRL 0x0038
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#define DSI_COMMAND_MODE_MDP_CTRL 0x003C
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#define DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL 0x0040
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#define DSI_DMA_CMD_OFFSET 0x0044
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#define DSI_DMA_CMD_LENGTH 0x0048
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#define DSI_DMA_FIFO_CTRL 0x004C
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#define DSI_COMMAND_MODE_MDP_STREAM0_CTRL 0x0054
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#define DSI_COMMAND_MODE_MDP_STREAM0_TOTAL 0x0058
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#define DSI_COMMAND_MODE_MDP_STREAM1_CTRL 0x005C
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#define DSI_COMMAND_MODE_MDP_STREAM1_TOTAL 0x0060
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#define DSI_ACK_ERR_STATUS 0x0064
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#define DSI_RDBK_DATA0 0x0068
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#define DSI_RDBK_DATA1 0x006C
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#define DSI_RDBK_DATA2 0x0070
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#define DSI_RDBK_DATA3 0x0074
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#define DSI_RDBK_DATATYPE0 0x0078
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#define DSI_RDBK_DATATYPE1 0x007C
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#define DSI_TRIG_CTRL 0x0080
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#define DSI_EXT_MUX 0x0084
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#define DSI_EXT_TE_PULSE_DETECT_CTRL 0x0088
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#define DSI_CMD_MODE_DMA_SW_TRIGGER 0x008C
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#define DSI_CMD_MODE_MDP_SW_TRIGGER 0x0090
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#define DSI_CMD_MODE_BTA_SW_TRIGGER 0x0094
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#define DSI_RESET_SW_TRIGGER 0x0098
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#define DSI_LANE_CTRL 0x00A8
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#define DSI_LANE_SWAP_CTRL 0x00AC
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#define DSI_DLN0_PHY_ERR 0x00B0
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#define DSI_TIMEOUT_STATUS 0x00BC
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#define DSI_CLKOUT_TIMING_CTRL 0x00C0
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#define DSI_EOT_PACKET 0x00C4
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#define DSI_EOT_PACKET_CTRL 0x00C8
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#define DSI_ERR_INT_MASK0 0x0108
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#define DSI_INT_CTRL 0x010c
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#define DSI_SOFT_RESET 0x0114
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#define DSI_CLK_CTRL 0x0118
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#define DSI_CLK_STATUS 0x011C
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#define DSI_PHY_SW_RESET 0x0128
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#define DSI_COMMAND_MODE_MDP_IDLE_CTRL 0x0190
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#define DSI_VERSION 0x01F0
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#define DSI_DSIPHY_PLL_CTRL_0 0x0200
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#define DSI_DSIPHY_PLL_CTRL_1 0x0204
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#define DSI_DSIPHY_PLL_CTRL_2 0x0208
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#define DSI_DSIPHY_PLL_CTRL_3 0x020C
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#define DSI_DSIPHY_PLL_CTRL_4 0x0210
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#define DSI_DSIPHY_PLL_CTRL_5 0x0214
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#define DSI_DSIPHY_PLL_CTRL_6 0x0218
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#define DSI_DSIPHY_PLL_CTRL_7 0x021C
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#define DSI_DSIPHY_PLL_CTRL_8 0x0220
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#define DSI_DSIPHY_PLL_CTRL_9 0x0224
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#define DSI_DSIPHY_PLL_CTRL_10 0x0228
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#define DSI_DSIPHY_PLL_CTRL_11 0x022C
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#define DSI_DSIPHY_PLL_CTRL_12 0x0230
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#define DSI_DSIPHY_PLL_CTRL_13 0x0234
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#define DSI_DSIPHY_PLL_CTRL_14 0x0238
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#define DSI_DSIPHY_PLL_CTRL_15 0x023C
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#define DSI_DSIPHY_PLL_CTRL_16 0x0240
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#define DSI_DSIPHY_PLL_CTRL_17 0x0244
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#define DSI_DSIPHY_PLL_CTRL_18 0x0248
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#define DSI_DSIPHY_PLL_CTRL_19 0x024C
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#define DSI_DSIPHY_ANA_CTRL0 0x0260
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#define DSI_DSIPHY_ANA_CTRL1 0x0264
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#define DSI_DSIPHY_ANA_CTRL2 0x0268
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#define DSI_DSIPHY_ANA_CTRL3 0x026C
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#define DSI_DSIPHY_ANA_CTRL4 0x0270
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#define DSI_DSIPHY_ANA_CTRL5 0x0274
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#define DSI_DSIPHY_ANA_CTRL6 0x0278
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#define DSI_DSIPHY_ANA_CTRL7 0x027C
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#define DSI_DSIPHY_PLL_RDY 0x0280
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#define DSI_DSIPHY_PLL_ANA_STATUS0 0x0294
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#define DSI_DSIPHY_PLL_ANA_STATUS1 0x0298
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#define DSI_DSIPHY_PLL_ANA_STATUS2 0x029C
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#define DSI_DSIPHY_LN0_CFG0 0x0300
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#define DSI_DSIPHY_LN0_CFG1 0x0304
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#define DSI_DSIPHY_LN0_CFG2 0x0308
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#define DSI_DSIPHY_LN1_CFG0 0x0340
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#define DSI_DSIPHY_LN1_CFG1 0x0344
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#define DSI_DSIPHY_LN1_CFG2 0x0348
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#define DSI_DSIPHY_LN2_CFG0 0x0380
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#define DSI_DSIPHY_LN2_CFG1 0x0384
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#define DSI_DSIPHY_LN2_CFG2 0x0388
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#define DSI_DSIPHY_LN3_CFG0 0x03C0
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#define DSI_DSIPHY_LN3_CFG1 0x03C4
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#define DSI_DSIPHY_LN3_CFG2 0x03C8
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#define DSI_DSIPHY_LNCK_CFG0 0x0400
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#define DSI_DSIPHY_LNCK_CFG1 0x0404
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#define DSI_DSIPHY_LNCK_CFG2 0x0408
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#define DSI_DSIPHY_TIMING_CTRL_0 0x0440
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#define DSI_DSIPHY_TIMING_CTRL_1 0x0444
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#define DSI_DSIPHY_TIMING_CTRL_2 0x0448
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#define DSI_DSIPHY_TIMING_CTRL_3 0x044C
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#define DSI_DSIPHY_TIMING_CTRL_4 0x0450
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#define DSI_DSIPHY_TIMING_CTRL_5 0x0454
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#define DSI_DSIPHY_TIMING_CTRL_6 0x0458
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#define DSI_DSIPHY_TIMING_CTRL_7 0x045C
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#define DSI_DSIPHY_TIMING_CTRL_8 0x0460
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#define DSI_DSIPHY_TIMING_CTRL_9 0x0464
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#define DSI_DSIPHY_TIMING_CTRL_10 0x0468
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#define DSI_DSIPHY_TIMING_CTRL_11 0x046C
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#define DSI_DSIPHY_CTRL_0 0x0470
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#define DSI_DSIPHY_CTRL_1 0x0474
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#define DSI_DSIPHY_CTRL_2 0x0478
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#define DSI_DSIPHY_CTRL_3 0x047C
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#define DSI_DSIPHY_STRENGTH_CTRL_0 0x0480
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#define DSI_DSIPHY_STRENGTH_CTRL_1 0x0484
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#define DSI_DSIPHY_STRENGTH_CTRL_2 0x0488
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#define DSI_DSIPHY_LDO_CNTRL 0x04B0
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#define DSI_DSIPHY_REGULATOR_CTRL_0 0x0500
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#define DSI_DSIPHY_REGULATOR_CTRL_1 0x0504
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#define DSI_DSIPHY_REGULATOR_CTRL_2 0x0508
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#define DSI_DSIPHY_REGULATOR_CTRL_3 0x050C
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#define DSI_DSIPHY_REGULATOR_CTRL_4 0x0510
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#define DSI_DSIPHY_REGULATOR_TEST 0x0514
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#define DSI_DSIPHY_REGULATOR_CAL_PWR_CFG 0x0518
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#define DSI_DSIPHY_CAL_HW_TRIGGER 0x0528
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#define DSI_DSIPHY_CAL_SW_CFG0 0x052C
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#define DSI_DSIPHY_CAL_SW_CFG1 0x0530
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#define DSI_DSIPHY_CAL_SW_CFG2 0x0534
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#define DSI_DSIPHY_CAL_HW_CFG0 0x0538
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#define DSI_DSIPHY_CAL_HW_CFG1 0x053C
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#define DSI_DSIPHY_CAL_HW_CFG2 0x0540
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#define DSI_DSIPHY_CAL_HW_CFG3 0x0544
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#define DSI_DSIPHY_CAL_HW_CFG4 0x0548
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#define DSI_DSIPHY_REGULATOR_CAL_STATUS0 0x0550
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#define DSI_DSIPHY_BIST_CTRL0 0x048C
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#define DSI_DSIPHY_BIST_CTRL1 0x0490
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#define DSI_DSIPHY_BIST_CTRL2 0x0494
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#define DSI_DSIPHY_BIST_CTRL3 0x0498
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#define DSI_DSIPHY_BIST_CTRL4 0x049C
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#define DSI_DSIPHY_BIST_CTRL5 0x04A0
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2024-09-09 08:57:42 +00:00
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#define DSI_EN BIT(0)
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#define DSI_VIDEO_MODE_EN BIT(1)
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#define DSI_CMD_MODE_EN BIT(2)
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2024-09-09 08:52:07 +00:00
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#endif /* DSI_HOST_V2_H */
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