280 lines
8.2 KiB
C
280 lines
8.2 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL8723E_DEF_H__
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#define __RTL8723E_DEF_H__
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#define HAL_RETRY_LIMIT_INFRA 48
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#define HAL_RETRY_LIMIT_AP_ADHOC 7
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#define RESET_DELAY_8185 20
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#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
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#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
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#define NUM_OF_FIRMWARE_QUEUE 10
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#define NUM_OF_PAGES_IN_FW 0x100
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
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#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
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#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
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#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
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#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
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#define MAX_LINES_HWCONFIG_TXT 1000
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#define MAX_BYTES_LINE_HWCONFIG_TXT 256
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#define SW_THREE_WIRE 0
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#define HW_THREE_WIRE 2
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#define BT_DEMO_BOARD 0
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#define BT_QA_BOARD 1
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#define BT_FPGA 2
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#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
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#define HAL_PRIME_CHNL_OFFSET_LOWER 1
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#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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#define MAX_H2C_QUEUE_NUM 10
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#define RX_MPDU_QUEUE 0
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#define RX_CMD_QUEUE 1
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#define RX_MAX_QUEUE 2
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#define AC2QUEUEID(_AC) (_AC)
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#define C2H_RX_CMD_HDR_LEN 8
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#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
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#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
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#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
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#define GET_C2H_CMD_CONTINUE(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
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#define GET_C2H_CMD_CONTENT(__prxhdr) \
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((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
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#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
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#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
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#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
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#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
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#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
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#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
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#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
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#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
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#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
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#define CHIP_BONDING_92C_1T2R 0x1
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#define CHIP_8723 BIT(0)
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#define NORMAL_CHIP BIT(3)
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#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
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#define RF_TYPE_1T2R BIT(4)
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#define RF_TYPE_2T2R BIT(5)
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#define CHIP_VENDOR_UMC BIT(7)
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#define B_CUT_VERSION BIT(12)
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#define C_CUT_VERSION BIT(13)
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#define D_CUT_VERSION ((BIT(12)|BIT(13)))
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#define E_CUT_VERSION BIT(14)
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#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
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/* MASK */
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#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
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#define CHIP_TYPE_MASK BIT(3)
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#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
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#define MANUFACTUER_MASK BIT(7)
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#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
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#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
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/* Get element */
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#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
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#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
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#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
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#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
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#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
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#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
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#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\
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true : false)
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#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? \
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true : false)
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#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true)
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#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
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? true : false)
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#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
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? true : false)
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#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version)) ? \
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true : false)
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#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version))\
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? ((GET_CVID_CUT_VERSION(version)) ? \
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false : true) : false)
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#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version))\
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? ((GET_CVID_CUT_VERSION(version)) ? \
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false : true) : false)
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#define IS_VENDOR_8723A_B_CUT(version) ((IS_8723_SERIES(version))\
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? ((GET_CVID_CUT_VERSION(version) == \
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B_CUT_VERSION) ? true : false) : false)
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#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version))\
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? ((GET_CVID_CUT_VERSION(version) == \
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B_CUT_VERSION) ? true : false) : false)
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enum rf_optype {
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RF_OP_BY_SW_3WIRE = 0,
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RF_OP_BY_FW,
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RF_OP_MAX
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};
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enum rf_power_state {
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RF_ON,
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RF_OFF,
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RF_SLEEP,
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RF_SHUT_DOWN,
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};
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enum power_save_mode {
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POWER_SAVE_MODE_ACTIVE,
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POWER_SAVE_MODE_SAVE,
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};
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enum power_policy_config {
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POWERCFG_MAX_POWER_SAVINGS,
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POWERCFG_GLOBAL_POWER_SAVINGS,
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POWERCFG_LOCAL_POWER_SAVINGS,
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POWERCFG_LENOVO,
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};
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enum interface_select_pci {
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INTF_SEL1_MINICARD = 0,
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INTF_SEL0_PCIE = 1,
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INTF_SEL2_RSV = 2,
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INTF_SEL3_RSV = 3,
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};
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enum hal_fw_c2h_cmd_id {
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HAL_FW_C2H_CMD_Read_MACREG = 0,
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HAL_FW_C2H_CMD_Read_BBREG = 1,
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HAL_FW_C2H_CMD_Read_RFREG = 2,
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HAL_FW_C2H_CMD_Read_EEPROM = 3,
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HAL_FW_C2H_CMD_Read_EFUSE = 4,
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HAL_FW_C2H_CMD_Read_CAM = 5,
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HAL_FW_C2H_CMD_Get_BasicRate = 6,
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HAL_FW_C2H_CMD_Get_DataRate = 7,
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HAL_FW_C2H_CMD_Survey = 8,
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HAL_FW_C2H_CMD_SurveyDone = 9,
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HAL_FW_C2H_CMD_JoinBss = 10,
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HAL_FW_C2H_CMD_AddSTA = 11,
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HAL_FW_C2H_CMD_DelSTA = 12,
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HAL_FW_C2H_CMD_AtimDone = 13,
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HAL_FW_C2H_CMD_TX_Report = 14,
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HAL_FW_C2H_CMD_CCX_Report = 15,
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HAL_FW_C2H_CMD_DTM_Report = 16,
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HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
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HAL_FW_C2H_CMD_C2HLBK = 18,
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HAL_FW_C2H_CMD_C2HDBG = 19,
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HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
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HAL_FW_C2H_CMD_MAX
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};
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enum rtl_desc_qsel {
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QSLT_BK = 0x2,
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QSLT_BE = 0x0,
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QSLT_VI = 0x5,
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QSLT_VO = 0x7,
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QSLT_BEACON = 0x10,
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QSLT_HIGH = 0x11,
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QSLT_MGNT = 0x12,
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QSLT_CMD = 0x13,
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};
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enum rtl_desc8723e_rate {
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DESC92C_RATE1M = 0x00,
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DESC92C_RATE2M = 0x01,
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DESC92C_RATE5_5M = 0x02,
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DESC92C_RATE11M = 0x03,
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DESC92C_RATE6M = 0x04,
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DESC92C_RATE9M = 0x05,
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DESC92C_RATE12M = 0x06,
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DESC92C_RATE18M = 0x07,
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DESC92C_RATE24M = 0x08,
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DESC92C_RATE36M = 0x09,
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DESC92C_RATE48M = 0x0a,
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DESC92C_RATE54M = 0x0b,
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DESC92C_RATEMCS0 = 0x0c,
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DESC92C_RATEMCS1 = 0x0d,
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DESC92C_RATEMCS2 = 0x0e,
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DESC92C_RATEMCS3 = 0x0f,
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DESC92C_RATEMCS4 = 0x10,
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DESC92C_RATEMCS5 = 0x11,
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DESC92C_RATEMCS6 = 0x12,
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DESC92C_RATEMCS7 = 0x13,
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DESC92C_RATEMCS8 = 0x14,
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DESC92C_RATEMCS9 = 0x15,
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DESC92C_RATEMCS10 = 0x16,
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DESC92C_RATEMCS11 = 0x17,
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DESC92C_RATEMCS12 = 0x18,
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DESC92C_RATEMCS13 = 0x19,
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DESC92C_RATEMCS14 = 0x1a,
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DESC92C_RATEMCS15 = 0x1b,
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DESC92C_RATEMCS15_SG = 0x1c,
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DESC92C_RATEMCS32 = 0x20,
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};
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struct phy_sts_cck_8723e_t {
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u8 adc_pwdb_X[4];
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u8 sq_rpt;
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u8 cck_agc_rpt;
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};
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struct h2c_cmd_8723e {
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u8 element_id;
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u32 cmd_len;
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u8 *p_cmdbuffer;
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};
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#endif
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