tobi/M7350
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
f75098198c
M7350/kernel/drivers/net/wireless/mwifiex/sdio.h

538 lines
14 KiB
C
Raw Normal View History

M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
/*
* Marvell Wireless LAN device driver: SDIO specific definitions
*
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
* Copyright (C) 2011-2014, Marvell International Ltd.
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
*
* This software file (the "File") is distributed by Marvell International
* Ltd. under the terms of the GNU General Public License Version 2, June 1991
* (the "License"). You may use, redistribute and/or modify this File in
* accordance with the terms and conditions of the License, a copy of which
* is available by writing to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
*
* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
* this warranty disclaimer.
*/
#ifndef _MWIFIEX_SDIO_H
#define _MWIFIEX_SDIO_H
#include <linux/mmc/sdio.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/card.h>
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
#include <linux/mmc/host.h>
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
#include "main.h"
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
#define BLOCK_MODE 1
#define BYTE_MODE 0
#define REG_PORT 0
#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
#define SDIO_MPA_ADDR_BASE 0x1000
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
#define CTRL_PORT 0
#define CTRL_PORT_MASK 0x0001
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
#define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
#define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
#define HOST_TERM_CMD53 (0x1U << 2)
#define REG_PORT 0
#define MEM_PORT 0x10000
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
#define CMD53_NEW_MODE (0x1U << 0)
#define CMD_PORT_RD_LEN_EN (0x1U << 2)
#define CMD_PORT_AUTO_EN (0x1U << 0)
#define CMD_PORT_SLCT 0x8000
#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
#define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
#define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
/* Misc. Config Register : Auto Re-enable interrupts */
#define AUTO_RE_ENABLE_INT BIT(4)
/* Host Control Registers : Configuration */
#define CONFIGURATION_REG 0x00
/* Host Control Registers : Host power up */
#define HOST_POWER_UP (0x1U << 1)
/* Host Control Registers : Upload host interrupt mask */
#define UP_LD_HOST_INT_MASK (0x1U)
/* Host Control Registers : Download host interrupt mask */
#define DN_LD_HOST_INT_MASK (0x2U)
/* Host Control Registers : Upload host interrupt status */
#define UP_LD_HOST_INT_STATUS (0x1U)
/* Host Control Registers : Download host interrupt status */
#define DN_LD_HOST_INT_STATUS (0x2U)
/* Host Control Registers : Host interrupt status */
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
#define CARD_INT_STATUS_REG 0x28
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
/* Card Control Registers : Card I/O ready */
#define CARD_IO_READY (0x1U << 3)
/* Card Control Registers : Download card ready */
#define DN_LD_CARD_RDY (0x1U << 0)
/* Max retry number of CMD53 write */
#define MAX_WRITE_IOMEM_RETRY 2
/* SDIO Tx aggregation in progress ? */
#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
/* SDIO Tx aggregation buffer room for next packet ? */
#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
<= a->mpa_tx.buf_size)
/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
payload, pkt_len); \
a->mpa_tx.buf_len += pkt_len; \
if (!a->mpa_tx.pkt_cnt) \
a->mpa_tx.start_port = port; \
if (a->mpa_tx.start_port <= port) \
a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
else \
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
(a->max_ports - \
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
a->mp_end_port))); \
a->mpa_tx.pkt_cnt++; \
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
} while (0)
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
/* SDIO Tx aggregation limit ? */
#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
/* Reset SDIO Tx aggregation buffer parameters */
#define MP_TX_AGGR_BUF_RESET(a) do { \
a->mpa_tx.pkt_cnt = 0; \
a->mpa_tx.buf_len = 0; \
a->mpa_tx.ports = 0; \
a->mpa_tx.start_port = 0; \
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
} while (0)
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
/* SDIO Rx aggregation limit ? */
#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
/* SDIO Rx aggregation in progress ? */
#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
/* SDIO Rx aggregation buffer room for next packet ? */
#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
/* Reset SDIO Rx aggregation buffer parameters */
#define MP_RX_AGGR_BUF_RESET(a) do { \
a->mpa_rx.pkt_cnt = 0; \
a->mpa_rx.buf_len = 0; \
a->mpa_rx.ports = 0; \
a->mpa_rx.start_port = 0; \
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
} while (0)
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
/* data structure for SDIO MPA TX */
struct mwifiex_sdio_mpa_tx {
/* multiport tx aggregation buffer pointer */
u8 *buf;
u32 buf_len;
u32 pkt_cnt;
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
u32 ports;
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
u16 start_port;
u8 enabled;
u32 buf_size;
u32 pkt_aggr_limit;
};
struct mwifiex_sdio_mpa_rx {
u8 *buf;
u32 buf_len;
u32 pkt_cnt;
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
u32 ports;
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
u16 start_port;
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
struct sk_buff **skb_arr;
u32 *len_arr;
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
u8 enabled;
u32 buf_size;
u32 pkt_aggr_limit;
};
int mwifiex_bus_register(void);
void mwifiex_bus_unregister(void);
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
struct mwifiex_sdio_card_reg {
u8 start_rd_port;
u8 start_wr_port;
u8 base_0_reg;
u8 base_1_reg;
u8 poll_reg;
u8 host_int_enable;
u8 host_int_rsr_reg;
u8 host_int_status_reg;
u8 host_int_mask_reg;
u8 status_reg_0;
u8 status_reg_1;
u8 sdio_int_mask;
u32 data_port_mask;
u8 io_port_0_reg;
u8 io_port_1_reg;
u8 io_port_2_reg;
u8 max_mp_regs;
u8 rd_bitmap_l;
u8 rd_bitmap_u;
u8 rd_bitmap_1l;
u8 rd_bitmap_1u;
u8 wr_bitmap_l;
u8 wr_bitmap_u;
u8 wr_bitmap_1l;
u8 wr_bitmap_1u;
u8 rd_len_p0_l;
u8 rd_len_p0_u;
u8 card_misc_cfg_reg;
u8 card_cfg_2_1_reg;
u8 cmd_rd_len_0;
u8 cmd_rd_len_1;
u8 cmd_rd_len_2;
u8 cmd_rd_len_3;
u8 cmd_cfg_0;
u8 cmd_cfg_1;
u8 cmd_cfg_2;
u8 cmd_cfg_3;
u8 fw_dump_ctrl;
u8 fw_dump_start;
u8 fw_dump_end;
};
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
struct sdio_mmc_card {
struct sdio_func *func;
struct mwifiex_adapter *adapter;
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
const char *firmware;
const struct mwifiex_sdio_card_reg *reg;
u8 max_ports;
u8 mp_agg_pkt_limit;
bool supports_sdio_new_mode;
bool has_control_mask;
bool supports_fw_dump;
u16 tx_buf_size;
u32 mp_tx_agg_buf_size;
u32 mp_rx_agg_buf_size;
u32 mp_rd_bitmap;
u32 mp_wr_bitmap;
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
u16 mp_end_port;
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
u32 mp_data_port_mask;
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
u8 curr_rd_port;
u8 curr_wr_port;
u8 *mp_regs;
struct mwifiex_sdio_mpa_tx mpa_tx;
struct mwifiex_sdio_mpa_rx mpa_rx;
};
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
struct mwifiex_sdio_device {
const char *firmware;
const struct mwifiex_sdio_card_reg *reg;
u8 max_ports;
u8 mp_agg_pkt_limit;
bool supports_sdio_new_mode;
bool has_control_mask;
bool supports_fw_dump;
u16 tx_buf_size;
u32 mp_tx_agg_buf_size;
u32 mp_rx_agg_buf_size;
};
static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
.start_rd_port = 1,
.start_wr_port = 1,
.base_0_reg = 0x0040,
.base_1_reg = 0x0041,
.poll_reg = 0x30,
.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
.host_int_rsr_reg = 0x1,
.host_int_mask_reg = 0x02,
.host_int_status_reg = 0x03,
.status_reg_0 = 0x60,
.status_reg_1 = 0x61,
.sdio_int_mask = 0x3f,
.data_port_mask = 0x0000fffe,
.io_port_0_reg = 0x78,
.io_port_1_reg = 0x79,
.io_port_2_reg = 0x7A,
.max_mp_regs = 64,
.rd_bitmap_l = 0x04,
.rd_bitmap_u = 0x05,
.wr_bitmap_l = 0x06,
.wr_bitmap_u = 0x07,
.rd_len_p0_l = 0x08,
.rd_len_p0_u = 0x09,
.card_misc_cfg_reg = 0x6c,
};
static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
.start_rd_port = 0,
.start_wr_port = 0,
.base_0_reg = 0x60,
.base_1_reg = 0x61,
.poll_reg = 0x50,
.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
.host_int_rsr_reg = 0x1,
.host_int_status_reg = 0x03,
.host_int_mask_reg = 0x02,
.status_reg_0 = 0xc0,
.status_reg_1 = 0xc1,
.sdio_int_mask = 0xff,
.data_port_mask = 0xffffffff,
.io_port_0_reg = 0xD8,
.io_port_1_reg = 0xD9,
.io_port_2_reg = 0xDA,
.max_mp_regs = 184,
.rd_bitmap_l = 0x04,
.rd_bitmap_u = 0x05,
.rd_bitmap_1l = 0x06,
.rd_bitmap_1u = 0x07,
.wr_bitmap_l = 0x08,
.wr_bitmap_u = 0x09,
.wr_bitmap_1l = 0x0a,
.wr_bitmap_1u = 0x0b,
.rd_len_p0_l = 0x0c,
.rd_len_p0_u = 0x0d,
.card_misc_cfg_reg = 0xcc,
.card_cfg_2_1_reg = 0xcd,
.cmd_rd_len_0 = 0xb4,
.cmd_rd_len_1 = 0xb5,
.cmd_rd_len_2 = 0xb6,
.cmd_rd_len_3 = 0xb7,
.cmd_cfg_0 = 0xb8,
.cmd_cfg_1 = 0xb9,
.cmd_cfg_2 = 0xba,
.cmd_cfg_3 = 0xbb,
.fw_dump_ctrl = 0xe2,
.fw_dump_start = 0xe3,
.fw_dump_end = 0xea,
};
static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
.start_rd_port = 0,
.start_wr_port = 0,
.base_0_reg = 0x6C,
.base_1_reg = 0x6D,
.poll_reg = 0x5C,
.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
.host_int_rsr_reg = 0x4,
.host_int_status_reg = 0x0C,
.host_int_mask_reg = 0x08,
.status_reg_0 = 0x90,
.status_reg_1 = 0x91,
.sdio_int_mask = 0xff,
.data_port_mask = 0xffffffff,
.io_port_0_reg = 0xE4,
.io_port_1_reg = 0xE5,
.io_port_2_reg = 0xE6,
.max_mp_regs = 196,
.rd_bitmap_l = 0x10,
.rd_bitmap_u = 0x11,
.rd_bitmap_1l = 0x12,
.rd_bitmap_1u = 0x13,
.wr_bitmap_l = 0x14,
.wr_bitmap_u = 0x15,
.wr_bitmap_1l = 0x16,
.wr_bitmap_1u = 0x17,
.rd_len_p0_l = 0x18,
.rd_len_p0_u = 0x19,
.card_misc_cfg_reg = 0xd8,
.card_cfg_2_1_reg = 0xd9,
.cmd_rd_len_0 = 0xc0,
.cmd_rd_len_1 = 0xc1,
.cmd_rd_len_2 = 0xc2,
.cmd_rd_len_3 = 0xc3,
.cmd_cfg_0 = 0xc4,
.cmd_cfg_1 = 0xc5,
.cmd_cfg_2 = 0xc6,
.cmd_cfg_3 = 0xc7,
};
static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
.firmware = SD8786_DEFAULT_FW_NAME,
.reg = &mwifiex_reg_sd87xx,
.max_ports = 16,
.mp_agg_pkt_limit = 8,
.supports_sdio_new_mode = false,
.has_control_mask = true,
.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
.supports_fw_dump = false,
};
static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
.firmware = SD8787_DEFAULT_FW_NAME,
.reg = &mwifiex_reg_sd87xx,
.max_ports = 16,
.mp_agg_pkt_limit = 8,
.supports_sdio_new_mode = false,
.has_control_mask = true,
.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
.supports_fw_dump = false,
};
static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
.firmware = SD8797_DEFAULT_FW_NAME,
.reg = &mwifiex_reg_sd87xx,
.max_ports = 16,
.mp_agg_pkt_limit = 8,
.supports_sdio_new_mode = false,
.has_control_mask = true,
.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
.supports_fw_dump = false,
};
static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
.firmware = SD8897_DEFAULT_FW_NAME,
.reg = &mwifiex_reg_sd8897,
.max_ports = 32,
.mp_agg_pkt_limit = 16,
.supports_sdio_new_mode = true,
.has_control_mask = false,
.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
.supports_fw_dump = true,
};
static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
.firmware = SD8887_DEFAULT_FW_NAME,
.reg = &mwifiex_reg_sd8887,
.max_ports = 32,
.mp_agg_pkt_limit = 16,
.supports_sdio_new_mode = true,
.has_control_mask = false,
.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
.supports_fw_dump = false,
};
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
/*
* .cmdrsp_complete handler
*/
static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
struct sk_buff *skb)
{
dev_kfree_skb_any(skb);
return 0;
}
/*
* .event_complete handler
*/
static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
struct sk_buff *skb)
{
dev_kfree_skb_any(skb);
return 0;
}
M7350v5_en_gpl
2024-09-09 08:57:42 +00:00
static inline bool
mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
{
u8 tmp;
if (card->curr_rd_port < card->mpa_rx.start_port) {
if (card->supports_sdio_new_mode)
tmp = card->mp_end_port >> 1;
else
tmp = card->mp_agg_pkt_limit;
if (((card->max_ports - card->mpa_rx.start_port) +
card->curr_rd_port) >= tmp)
return true;
}
if (!card->supports_sdio_new_mode)
return false;
if ((card->curr_rd_port - card->mpa_rx.start_port) >=
(card->mp_end_port >> 1))
return true;
return false;
}
static inline bool
mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
{
u16 tmp;
if (card->curr_wr_port < card->mpa_tx.start_port) {
if (card->supports_sdio_new_mode)
tmp = card->mp_end_port >> 1;
else
tmp = card->mp_agg_pkt_limit;
if (((card->max_ports - card->mpa_tx.start_port) +
card->curr_wr_port) >= tmp)
return true;
}
if (!card->supports_sdio_new_mode)
return false;
if ((card->curr_wr_port - card->mpa_tx.start_port) >=
(card->mp_end_port >> 1))
return true;
return false;
}
/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
struct sk_buff *skb, u8 port)
{
card->mpa_rx.buf_len += skb->len;
if (!card->mpa_rx.pkt_cnt)
card->mpa_rx.start_port = port;
if (card->supports_sdio_new_mode) {
card->mpa_rx.ports |= (1 << port);
} else {
if (card->mpa_rx.start_port <= port)
card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
else
card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
}
card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
card->mpa_rx.pkt_cnt++;
}
M7350v1_en_gpl
2024-09-09 08:52:07 +00:00
#endif /* _MWIFIEX_SDIO_H */
Reference in New Issue Copy Permalink