2024-09-09 08:52:07 +00:00
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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2024-09-09 08:57:42 +00:00
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Copyright(c) 1999 - 2013 Intel Corporation.
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2024-09-09 08:52:07 +00:00
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _DCB_82598_CONFIG_H_
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#define _DCB_82598_CONFIG_H_
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/* DCB register definitions */
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#define IXGBE_DPMCS_MTSOS_SHIFT 16
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#define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
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#define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */
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#define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */
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#define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
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#define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
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#define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
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#define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
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#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */
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#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */
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#define IXGBE_TDTQ2TCCR_MCL_SHIFT 12
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#define IXGBE_TDTQ2TCCR_BWG_SHIFT 9
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#define IXGBE_TDTQ2TCCR_GSP 0x40000000
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#define IXGBE_TDTQ2TCCR_LSP 0x80000000
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#define IXGBE_TDPT2TCCR_MCL_SHIFT 12
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#define IXGBE_TDPT2TCCR_BWG_SHIFT 9
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#define IXGBE_TDPT2TCCR_GSP 0x40000000
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#define IXGBE_TDPT2TCCR_LSP 0x80000000
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#define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
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#define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */
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#define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
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#define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */
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#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
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#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
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#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
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#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
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#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000
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/* DCB hardware-specific driver APIs */
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/* DCB PFC functions */
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s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8 pfc_en);
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/* DCB hw initialization */
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s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *prio_type);
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s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type);
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s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
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u16 *refill,
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u16 *max,
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u8 *bwg_id,
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u8 *prio_type);
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s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *prio_type);
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#endif /* _DCB_82598_CONFIG_H */
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