215 lines
6.0 KiB
C
215 lines
6.0 KiB
C
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hdmi.h"
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struct hdmi_phy_8x60 {
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struct hdmi_phy base;
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struct hdmi *hdmi;
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};
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#define to_hdmi_phy_8x60(x) container_of(x, struct hdmi_phy_8x60, base)
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static void hdmi_phy_8x60_destroy(struct hdmi_phy *phy)
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{
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struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
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kfree(phy_8x60);
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}
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static void hdmi_phy_8x60_reset(struct hdmi_phy *phy)
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{
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struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
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struct hdmi *hdmi = phy_8x60->hdmi;
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unsigned int val;
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val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
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if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
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/* pull low */
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hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
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val & ~HDMI_PHY_CTRL_SW_RESET);
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} else {
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/* pull high */
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hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
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val | HDMI_PHY_CTRL_SW_RESET);
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}
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msleep(100);
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if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
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/* pull high */
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hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
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val | HDMI_PHY_CTRL_SW_RESET);
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} else {
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/* pull low */
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hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
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val & ~HDMI_PHY_CTRL_SW_RESET);
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}
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}
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static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
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unsigned long int pixclock)
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{
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struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
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struct hdmi *hdmi = phy_8x60->hdmi;
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/* De-serializer delay D/C for non-lbk mode: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG0,
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HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));
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if (pixclock == 27000000) {
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/* video_format == HDMI_VFRMT_720x480p60_16_9 */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG1,
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HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
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HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
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} else {
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG1,
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HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
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HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
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}
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/* No matter what, start from the power down mode: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
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HDMI_8x60_PHY_REG2_PD_PWRGEN |
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HDMI_8x60_PHY_REG2_PD_PLL |
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HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
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HDMI_8x60_PHY_REG2_PD_DESER);
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/* Turn PowerGen on: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
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HDMI_8x60_PHY_REG2_PD_PLL |
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HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
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HDMI_8x60_PHY_REG2_PD_DESER);
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/* Turn PLL power on: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
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HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
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HDMI_8x60_PHY_REG2_PD_DESER);
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/* Write to HIGH after PLL power down de-assert: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG3,
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HDMI_8x60_PHY_REG3_PLL_ENABLE);
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/* ASIC power on; PHY REG9 = 0 */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG9, 0);
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/* Enable PLL lock detect, PLL lock det will go high after lock
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* Enable the re-time logic
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*/
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG12,
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HDMI_8x60_PHY_REG12_RETIMING_EN |
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HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);
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/* Drivers are on: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
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HDMI_8x60_PHY_REG2_PD_DESER);
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/* If the RX detector is needed: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
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HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
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HDMI_8x60_PHY_REG2_PD_DESER);
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG4, 0);
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG5, 0);
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG6, 0);
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG7, 0);
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG8, 0);
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG9, 0);
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG10, 0);
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG11, 0);
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/* If we want to use lock enable based on counting: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG12,
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HDMI_8x60_PHY_REG12_RETIMING_EN |
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HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN |
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HDMI_8x60_PHY_REG12_FORCE_LOCK);
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}
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static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
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{
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struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
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struct hdmi *hdmi = phy_8x60->hdmi;
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/* Assert RESET PHY from controller */
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hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
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HDMI_PHY_CTRL_SW_RESET);
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udelay(10);
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/* De-assert RESET PHY from controller */
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hdmi_write(hdmi, REG_HDMI_PHY_CTRL, 0);
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/* Turn off Driver */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
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HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
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HDMI_8x60_PHY_REG2_PD_DESER);
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udelay(10);
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/* Disable PLL */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG3, 0);
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/* Power down PHY, but keep RX-sense: */
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hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
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HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
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HDMI_8x60_PHY_REG2_PD_PWRGEN |
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HDMI_8x60_PHY_REG2_PD_PLL |
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HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
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HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
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HDMI_8x60_PHY_REG2_PD_DESER);
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}
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static const struct hdmi_phy_funcs hdmi_phy_8x60_funcs = {
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.destroy = hdmi_phy_8x60_destroy,
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.reset = hdmi_phy_8x60_reset,
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.powerup = hdmi_phy_8x60_powerup,
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.powerdown = hdmi_phy_8x60_powerdown,
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};
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struct hdmi_phy *hdmi_phy_8x60_init(struct hdmi *hdmi)
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{
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struct hdmi_phy_8x60 *phy_8x60;
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struct hdmi_phy *phy = NULL;
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int ret;
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phy_8x60 = kzalloc(sizeof(*phy_8x60), GFP_KERNEL);
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if (!phy_8x60) {
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ret = -ENOMEM;
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goto fail;
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}
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phy = &phy_8x60->base;
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phy->funcs = &hdmi_phy_8x60_funcs;
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phy_8x60->hdmi = hdmi;
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return phy;
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fail:
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if (phy)
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hdmi_phy_8x60_destroy(phy);
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return ERR_PTR(ret);
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}
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