2024-09-09 08:52:07 +00:00
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#ifndef __ASM_SH_IRQ_H
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#define __ASM_SH_IRQ_H
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#include <linux/cpumask.h>
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#include <asm/machvec.h>
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/*
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2024-09-09 08:57:42 +00:00
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* Only legacy non-sparseirq platforms have to set a reasonably sane
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* value here. sparseirq platforms allocate their irq_descs on the fly,
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* so will expand automatically based on the number of registered IRQs.
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2024-09-09 08:52:07 +00:00
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*/
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_SPARSE_IRQ
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# define NR_IRQS 8
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#else
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# define NR_IRQS 512
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#endif
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2024-09-09 08:52:07 +00:00
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/*
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* This is a special IRQ number for indicating that no IRQ has been
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* triggered and to simply ignore the IRQ dispatch. This is a special
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* case that can happen with IRQ auto-distribution when multiple CPUs
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* are woken up and signalled in parallel.
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*/
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#define NO_IRQ_IGNORE ((unsigned int)-1)
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/*
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* Simple Mask Register Support
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*/
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extern void make_maskreg_irq(unsigned int irq);
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extern unsigned short *irq_mask_register;
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/*
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* PINT IRQs
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*/
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void init_IRQ_pint(void);
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void make_imask_irq(unsigned int irq);
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static inline int generic_irq_demux(int irq)
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{
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return irq;
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}
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#define irq_demux(irq) sh_mv.mv_irq_demux(irq)
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void init_IRQ(void);
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void migrate_irqs(void);
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asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs);
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#ifdef CONFIG_IRQSTACKS
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extern void irq_ctx_init(int cpu);
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extern void irq_ctx_exit(int cpu);
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# define __ARCH_HAS_DO_SOFTIRQ
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#else
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# define irq_ctx_init(cpu) do { } while (0)
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# define irq_ctx_exit(cpu) do { } while (0)
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#endif
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#ifdef CONFIG_INTC_BALANCING
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extern unsigned int irq_lookup(unsigned int irq);
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extern void irq_finish(unsigned int irq);
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#else
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#define irq_lookup(irq) (irq)
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#define irq_finish(irq) do { } while (0)
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#endif
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#include <asm-generic/irq.h>
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#ifdef CONFIG_CPU_SH5
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#include <cpu/irq.h>
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#endif
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#endif /* __ASM_SH_IRQ_H */
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