329 lines
7.6 KiB
C
329 lines
7.6 KiB
C
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_MPI_DEFS_H__
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#define __CVMX_MPI_DEFS_H__
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#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
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#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
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#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
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#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
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union cvmx_mpi_cfg {
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uint64_t u64;
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struct cvmx_mpi_cfg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t csena3:1;
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uint64_t csena2:1;
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uint64_t csena1:1;
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uint64_t csena0:1;
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uint64_t cslate:1;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t csena:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t csena:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t cslate:1;
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uint64_t csena0:1;
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uint64_t csena1:1;
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uint64_t csena2:1;
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uint64_t csena3:1;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} s;
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struct cvmx_mpi_cfg_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t reserved_12_15:4;
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uint64_t cslate:1;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t csena:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t csena:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t cslate:1;
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uint64_t reserved_12_15:4;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} cn30xx;
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struct cvmx_mpi_cfg_cn31xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t reserved_11_15:5;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t csena:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t csena:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t reserved_11_15:5;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} cn31xx;
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struct cvmx_mpi_cfg_cn30xx cn50xx;
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struct cvmx_mpi_cfg_cn61xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t reserved_14_15:2;
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uint64_t csena1:1;
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uint64_t csena0:1;
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uint64_t cslate:1;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t reserved_6_6:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t reserved_6_6:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t cslate:1;
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uint64_t csena0:1;
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uint64_t csena1:1;
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uint64_t reserved_14_15:2;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} cn61xx;
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struct cvmx_mpi_cfg_cn66xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t csena3:1;
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uint64_t csena2:1;
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uint64_t reserved_12_13:2;
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uint64_t cslate:1;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t reserved_6_6:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t reserved_6_6:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t cslate:1;
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uint64_t reserved_12_13:2;
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uint64_t csena2:1;
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uint64_t csena3:1;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} cn66xx;
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struct cvmx_mpi_cfg_cn61xx cnf71xx;
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};
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union cvmx_mpi_datx {
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uint64_t u64;
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struct cvmx_mpi_datx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_8_63:56;
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uint64_t data:8;
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#else
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uint64_t data:8;
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uint64_t reserved_8_63:56;
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#endif
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} s;
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struct cvmx_mpi_datx_s cn30xx;
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struct cvmx_mpi_datx_s cn31xx;
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struct cvmx_mpi_datx_s cn50xx;
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struct cvmx_mpi_datx_s cn61xx;
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struct cvmx_mpi_datx_s cn66xx;
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struct cvmx_mpi_datx_s cnf71xx;
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};
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union cvmx_mpi_sts {
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uint64_t u64;
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struct cvmx_mpi_sts_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_13_63:51;
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uint64_t rxnum:5;
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uint64_t reserved_1_7:7;
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uint64_t busy:1;
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#else
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uint64_t busy:1;
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uint64_t reserved_1_7:7;
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uint64_t rxnum:5;
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uint64_t reserved_13_63:51;
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#endif
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} s;
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struct cvmx_mpi_sts_s cn30xx;
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struct cvmx_mpi_sts_s cn31xx;
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struct cvmx_mpi_sts_s cn50xx;
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struct cvmx_mpi_sts_s cn61xx;
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struct cvmx_mpi_sts_s cn66xx;
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struct cvmx_mpi_sts_s cnf71xx;
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};
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union cvmx_mpi_tx {
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uint64_t u64;
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struct cvmx_mpi_tx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_22_63:42;
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uint64_t csid:2;
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uint64_t reserved_17_19:3;
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uint64_t leavecs:1;
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uint64_t reserved_13_15:3;
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uint64_t txnum:5;
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uint64_t reserved_5_7:3;
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uint64_t totnum:5;
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#else
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uint64_t totnum:5;
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uint64_t reserved_5_7:3;
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uint64_t txnum:5;
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uint64_t reserved_13_15:3;
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uint64_t leavecs:1;
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uint64_t reserved_17_19:3;
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uint64_t csid:2;
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uint64_t reserved_22_63:42;
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#endif
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} s;
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struct cvmx_mpi_tx_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_17_63:47;
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uint64_t leavecs:1;
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uint64_t reserved_13_15:3;
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uint64_t txnum:5;
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uint64_t reserved_5_7:3;
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uint64_t totnum:5;
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#else
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uint64_t totnum:5;
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uint64_t reserved_5_7:3;
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uint64_t txnum:5;
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uint64_t reserved_13_15:3;
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uint64_t leavecs:1;
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uint64_t reserved_17_63:47;
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#endif
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} cn30xx;
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struct cvmx_mpi_tx_cn30xx cn31xx;
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struct cvmx_mpi_tx_cn30xx cn50xx;
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struct cvmx_mpi_tx_cn61xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_21_63:43;
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uint64_t csid:1;
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uint64_t reserved_17_19:3;
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uint64_t leavecs:1;
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uint64_t reserved_13_15:3;
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uint64_t txnum:5;
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uint64_t reserved_5_7:3;
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uint64_t totnum:5;
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#else
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uint64_t totnum:5;
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uint64_t reserved_5_7:3;
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uint64_t txnum:5;
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uint64_t reserved_13_15:3;
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uint64_t leavecs:1;
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uint64_t reserved_17_19:3;
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uint64_t csid:1;
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uint64_t reserved_21_63:43;
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#endif
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} cn61xx;
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struct cvmx_mpi_tx_s cn66xx;
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struct cvmx_mpi_tx_cn61xx cnf71xx;
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};
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#endif
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