2024-09-09 08:52:07 +00:00
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/*
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* pnx833x.h: Register mappings for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
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* Daniel Laird <daniel.j.laird@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
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#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
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/* All regs are accessed in KSEG1 */
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#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul)
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#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs)))
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/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */
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/* Read access to multibit fields */
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#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field)
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#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field)
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/* Use PNX833X_FIELD to extract a field from val */
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#define PNX_FIELD(cpu, val, reg, field) \
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(((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
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PNX##cpu##_##reg##_##field##_SHIFT)
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#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field)
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#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field)
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#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field)
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/* Use PNX833X_REGFIELD to extract a field from a register */
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#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field)
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#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field)
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#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field)
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#define PNX_WRITEFIELD(cpu, val, reg, field) \
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(PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
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((val) << PNX##cpu##_##reg##_##field##_SHIFT))
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#define PNX833X_WRITEFIELD(val, reg, field) \
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PNX_WRITEFIELD(833X, val, reg, field)
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#define PNX8330_WRITEFIELD(val, reg, field) \
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PNX_WRITEFIELD(8330, val, reg, field)
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#define PNX8335_WRITEFIELD(val, reg, field) \
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PNX_WRITEFIELD(8335, val, reg, field)
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/* Macros to detect CPU type */
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#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC)
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#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000
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#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12
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#define PNX8330_CONFIG_MODULE_MAJREV 4
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#define PNX8335_CONFIG_MODULE_MAJREV 5
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#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
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PNX8330_CONFIG_MODULE_MAJREV)
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#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
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PNX8335_CONFIG_MODULE_MAJREV)
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#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004)
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#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014)
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#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs))
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#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0)
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#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4)
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#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */
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#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3
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#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq))
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#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
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#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */
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#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */
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#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
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#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020)
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#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f
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#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0
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#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004)
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#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */
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#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040)
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#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000
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#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19
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#define PNX833X_PIO_IN PNX833X_REG(0xF000)
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#define PNX833X_PIO_OUT PNX833X_REG(0xF004)
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#define PNX833X_PIO_DIR PNX833X_REG(0xF008)
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#define PNX833X_PIO_SEL PNX833X_REG(0xF014)
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#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020)
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#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024)
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#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028)
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#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0)
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#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4)
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#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8)
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#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C)
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#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060)
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#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064)
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#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068)
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#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000)
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#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF)
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#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000)
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#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF)
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#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000)
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#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF)
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#define PNX833X_CONFIG_USB PNX833X_REG(0x7008)
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#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000)
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#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF)
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#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000)
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#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF)
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#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000)
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#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF)
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#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC)
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#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
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#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16
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#define PNX833X_IDE_MODULE_ID_VALUE 0xA009
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#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004)
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#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008)
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#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C)
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#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010)
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#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014)
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#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018)
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#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C)
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#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020)
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#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14)
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#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
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#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
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#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7
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#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9)
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#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9
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#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000)
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#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3)
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#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3
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#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
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#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2
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#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
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#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1
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#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0)
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#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0
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#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \
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(PNX833X_MIU_CONFIG_SPI = \
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((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \
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((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \
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((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \
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((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT))
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#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000)
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#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF)
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#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC)
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#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
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#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16
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#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902
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/* I/O location(gets remapped)*/
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#define PNX8335_NAND_BASE 0x18000000
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/* I/O location with CLE high */
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#define PNX8335_NAND_CLE_MASK 0x00100000
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/* I/O location with ALE high */
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#define PNX8335_NAND_ALE_MASK 0x00010000
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#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000)
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#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF)
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#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC)
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#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
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#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16
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#define PNX8335_SATA_MODULE_ID_VALUE 0xA099
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#endif
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