2024-09-09 08:52:07 +00:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
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*
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*/
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#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H
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#define __ASM_MACH_IP32_DMA_COHERENCE_H
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#include <asm/ip32/crime.h>
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struct device;
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/*
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* Few notes.
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* 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
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* 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
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* native-endian)
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* 3. All other devices see memory as one big chunk at 0x40000000
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* 4. Non-PCI devices will pass NULL as struct device*
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*
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* Thus we translate differently, depending on device.
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*/
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#define RAM_OFFSET_MASK 0x3fffffffUL
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static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
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size_t size)
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{
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dma_addr_t pa = virt_to_phys(addr) & RAM_OFFSET_MASK;
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if (dev == NULL)
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pa += CRIME_HI_MEM_BASE;
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return pa;
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}
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static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
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struct page *page)
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{
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dma_addr_t pa;
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pa = page_to_phys(page) & RAM_OFFSET_MASK;
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if (dev == NULL)
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pa += CRIME_HI_MEM_BASE;
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return pa;
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}
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2024-09-09 08:57:42 +00:00
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/* This is almost certainly wrong but it's what dma-ip32.c used to use */
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2024-09-09 08:52:07 +00:00
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static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
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dma_addr_t dma_addr)
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{
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unsigned long addr = dma_addr & RAM_OFFSET_MASK;
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if (dma_addr >= 256*1024*1024)
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addr += CRIME_HI_MEM_BASE;
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return addr;
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}
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static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction direction)
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{
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}
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static inline int plat_dma_supported(struct device *dev, u64 mask)
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{
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/*
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* we fall back to GFP_DMA when the mask isn't all 1s,
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* so we can't guarantee allocations that must be
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* within a tighter range than GFP_DMA..
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*/
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if (mask < DMA_BIT_MASK(24))
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return 0;
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return 1;
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}
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static inline int plat_device_is_coherent(struct device *dev)
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{
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return 0; /* IP32 is non-cohernet */
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}
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#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */
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