2024-09-09 08:52:07 +00:00
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/*
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* Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
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* Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
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*
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* Written by Ralf Baechle and Andreas Busse, modified for DECstation
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* support by Paul Antoine and Harald Koerfgen.
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*
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* completly rewritten:
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* Copyright (C) 1998 Harald Koerfgen
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*
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* Rewritten extensively for controller-driven IRQ support
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* by Maciej W. Rozycki.
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*/
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/dec/interrupts.h>
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#include <asm/dec/ioasic_addrs.h>
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#include <asm/dec/ioasic_ints.h>
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#include <asm/dec/kn01.h>
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#include <asm/dec/kn02.h>
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#include <asm/dec/kn02xa.h>
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#include <asm/dec/kn03.h>
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#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
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#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
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#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
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.text
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.set noreorder
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/*
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* plat_irq_dispatch: Interrupt handler for DECstations
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*
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* We follow the model in the Indy interrupt code by David Miller, where he
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* says: a lot of complication here is taken away because:
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*
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* 1) We handle one interrupt and return, sitting in a loop
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* and moving across all the pending IRQ bits in the cause
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* register is _NOT_ the answer, the common case is one
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* pending IRQ so optimize in that direction.
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*
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* 2) We need not check against bits in the status register
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* IRQ mask, that would make this routine slow as hell.
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*
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* 3) Linux only thinks in terms of all IRQs on or all IRQs
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* off, nothing in between like BSD spl() brain-damage.
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*
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* Furthermore, the IRQs on the DECstations look basically (barring
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* software IRQs which we don't use at all) like...
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*
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* DS2100/3100's, aka kn01, aka Pmax:
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*
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* MIPS IRQ Source
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2024-09-09 08:57:42 +00:00
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 SCSI
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* 3 Lance Ethernet
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* 4 DZ11 serial
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* 5 RTC
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* 6 Memory Controller & Video
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* 7 FPU
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2024-09-09 08:52:07 +00:00
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*
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* DS5000/200, aka kn02, aka 3max:
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*
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* MIPS IRQ Source
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2024-09-09 08:57:42 +00:00
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 TurboChannel
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* 3 RTC
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* 4 Reserved
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* 5 Memory Controller
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* 6 Reserved
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* 7 FPU
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2024-09-09 08:52:07 +00:00
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*
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* DS5000/1xx's, aka kn02ba, aka 3min:
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*
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* MIPS IRQ Source
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2024-09-09 08:57:42 +00:00
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 TurboChannel Slot 0
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* 3 TurboChannel Slot 1
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* 4 TurboChannel Slot 2
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* 5 TurboChannel Slot 3 (ASIC)
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* 6 Halt button
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* 7 FPU/R4k timer
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2024-09-09 08:52:07 +00:00
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*
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* DS5000/2x's, aka kn02ca, aka maxine:
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*
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* MIPS IRQ Source
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2024-09-09 08:57:42 +00:00
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 Periodic Interrupt (100usec)
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* 3 RTC
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* 4 I/O write timeout
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* 5 TurboChannel (ASIC)
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* 6 Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER)
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* 7 FPU/R4k timer
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2024-09-09 08:52:07 +00:00
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*
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* DS5000/2xx's, aka kn03, aka 3maxplus:
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*
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* MIPS IRQ Source
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2024-09-09 08:57:42 +00:00
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 System Board (ASIC)
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* 3 RTC
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* 4 Reserved
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* 5 Memory
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* 6 Halt Button
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* 7 FPU/R4k timer
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2024-09-09 08:52:07 +00:00
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*
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* We handle the IRQ according to _our_ priority (see setup.c),
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* then we just return. If multiple IRQs are pending then we will
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* just take another exception, big deal.
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*/
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.align 5
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NESTED(plat_irq_dispatch, PT_SIZE, ra)
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.set noreorder
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/*
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* Get pending Interrupts
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*/
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mfc0 t0,CP0_CAUSE # get pending interrupts
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mfc0 t1,CP0_STATUS
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#ifdef CONFIG_32BIT
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lw t2,cpu_fpu_mask
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#endif
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andi t0,ST0_IM # CAUSE.CE may be non-zero!
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and t0,t1 # isolate allowed ones
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beqz t0,spurious
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#ifdef CONFIG_32BIT
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and t2,t0
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bnez t2,fpu # handle FPU immediately
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#endif
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/*
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* Find irq with highest priority
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*/
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PTR_LA t1,cpu_mask_nr_tbl
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1: lw t2,(t1)
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nop
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and t2,t0
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beqz t2,1b
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addu t1,2*PTRSIZE # delay slot
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/*
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* Do the low-level stuff
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*/
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lw a0,(-PTRSIZE)(t1)
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nop
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bgez a0,handle_it # irq_nr >= 0?
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# irq_nr < 0: it is an address
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nop
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jr a0
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# a trick to save a branch:
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lui t2,(KN03_IOASIC_BASE>>16)&0xffff
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# upper part of IOASIC Address
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/*
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* Handle "IRQ Controller" Interrupts
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* Masked Interrupts are still visible and have to be masked "by hand".
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*/
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FEXPORT(kn02_io_int) # 3max
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lui t0,(KN02_CSR_BASE>>16)&0xffff
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# get interrupt status and mask
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lw t0,(t0)
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nop
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andi t1,t0,KN02_IRQ_ALL
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b 1f
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srl t0,16 # shift interrupt mask
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FEXPORT(kn02xa_io_int) # 3min/maxine
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lui t2,(KN02XA_IOASIC_BASE>>16)&0xffff
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# upper part of IOASIC Address
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FEXPORT(kn03_io_int) # 3max+ (t2 loaded earlier)
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lw t0,IO_REG_SIR(t2) # get status: IOASIC sir
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lw t1,IO_REG_SIMR(t2) # get mask: IOASIC simr
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nop
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1: and t0,t1 # mask out allowed ones
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beqz t0,spurious
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/*
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* Find irq with highest priority
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*/
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PTR_LA t1,asic_mask_nr_tbl
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2: lw t2,(t1)
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nop
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and t2,t0
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beq zero,t2,2b
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addu t1,2*PTRSIZE # delay slot
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/*
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* Do the low-level stuff
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*/
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lw a0,%lo(-PTRSIZE)(t1)
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nop
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bgez a0,handle_it # irq_nr >= 0?
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# irq_nr < 0: it is an address
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nop
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jr a0
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nop # delay slot
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/*
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* Dispatch low-priority interrupts. We reconsider all status
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* bits again, which looks like a lose, but it makes the code
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* simple and O(log n), so it gets compensated.
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*/
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FEXPORT(cpu_all_int) # HALT, timers, software junk
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li a0,DEC_CPU_IRQ_BASE
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srl t0,CAUSEB_IP
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li t1,CAUSEF_IP>>CAUSEB_IP # mask
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b 1f
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li t2,4 # nr of bits / 2
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FEXPORT(kn02_all_int) # impossible ?
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li a0,KN02_IRQ_BASE
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li t1,KN02_IRQ_ALL # mask
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b 1f
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li t2,4 # nr of bits / 2
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FEXPORT(asic_all_int) # various I/O ASIC junk
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li a0,IO_IRQ_BASE
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li t1,IO_IRQ_ALL # mask
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b 1f
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li t2,8 # nr of bits / 2
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/*
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* Dispatch DMA interrupts -- O(log n).
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*/
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FEXPORT(asic_dma_int) # I/O ASIC DMA events
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li a0,IO_IRQ_BASE+IO_INR_DMA
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srl t0,IO_INR_DMA
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li t1,IO_IRQ_DMA>>IO_INR_DMA # mask
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li t2,8 # nr of bits / 2
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/*
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* Find irq with highest priority.
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* Highest irq number takes precedence.
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*/
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1: srlv t3,t1,t2
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2: xor t1,t3
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and t3,t0,t1
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beqz t3,3f
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nop
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move t0,t3
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addu a0,t2
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3: srl t2,1
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bnez t2,2b
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srlv t3,t1,t2
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handle_it:
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j dec_irq_dispatch
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nop
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#ifdef CONFIG_32BIT
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fpu:
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j handle_fpe_int
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nop
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#endif
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spurious:
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j spurious_interrupt
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nop
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END(plat_irq_dispatch)
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/*
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* Generic unimplemented interrupt routines -- cpu_mask_nr_tbl
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* and asic_mask_nr_tbl are initialized to point all interrupts here.
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* The tables are then filled in by machine-specific initialisation
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* in dec_setup().
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*/
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FEXPORT(dec_intr_unimplemented)
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move a1,t0 # cheats way of printing an arg!
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PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%08x");
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FEXPORT(asic_intr_unimplemented)
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move a1,t0 # cheats way of printing an arg!
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PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%08x");
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