113 lines
3.6 KiB
C
113 lines
3.6 KiB
C
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/*
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* mcfmmu.h -- definitions for the ColdFire v4e MMU
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*
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* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#ifndef MCFMMU_H
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#define MCFMMU_H
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/*
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* The MMU support registers are mapped into the address space using
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* the processor MMUBASE register. We used a fixed address for mapping,
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* there doesn't seem any need to make this configurable yet.
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*/
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#define MMUBASE 0xfe000000
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/*
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* The support registers of the MMU. Names are the sames as those
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* used in the Freescale v4e documentation.
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*/
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#define MMUCR (MMUBASE + 0x00) /* Control register */
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#define MMUOR (MMUBASE + 0x04) /* Operation register */
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#define MMUSR (MMUBASE + 0x08) /* Status register */
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#define MMUAR (MMUBASE + 0x10) /* TLB Address register */
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#define MMUTR (MMUBASE + 0x14) /* TLB Tag register */
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#define MMUDR (MMUBASE + 0x18) /* TLB Data register */
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/*
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* MMU Control register bit flags
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*/
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#define MMUCR_EN 0x00000001 /* Virtual mode enable */
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#define MMUCR_ASM 0x00000002 /* Address space mode */
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/*
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* MMU Operation register.
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*/
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#define MMUOR_UAA 0x00000001 /* Update allocatiom address */
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#define MMUOR_ACC 0x00000002 /* TLB access */
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#define MMUOR_RD 0x00000004 /* TLB access read */
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#define MMUOR_WR 0x00000000 /* TLB access write */
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#define MMUOR_ADR 0x00000008 /* TLB address select */
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#define MMUOR_ITLB 0x00000010 /* ITLB operation */
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#define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
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#define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
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#define MMUOR_CA 0x00000080 /* Clear all TLBs */
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#define MMUOR_STLB 0x00000100 /* Search TLBs */
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#define MMUOR_AAN 16 /* TLB allocation address */
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#define MMUOR_AAMASK 0xffff0000 /* AA mask */
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/*
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* MMU Status register.
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*/
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#define MMUSR_HIT 0x00000002 /* Search TLB hit */
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#define MMUSR_WF 0x00000008 /* Write access fault */
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#define MMUSR_RF 0x00000010 /* Read access fault */
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#define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
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/*
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* MMU Read/Write Tag register.
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*/
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#define MMUTR_V 0x00000001 /* Valid */
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#define MMUTR_SG 0x00000002 /* Shared global */
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#define MMUTR_IDN 2 /* Address Space ID */
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#define MMUTR_IDMASK 0x000003fc /* ASID mask */
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#define MMUTR_VAN 10 /* Virtual Address */
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#define MMUTR_VAMASK 0xfffffc00 /* VA mask */
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/*
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* MMU Read/Write Data register.
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*/
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#define MMUDR_LK 0x00000002 /* Lock entry */
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#define MMUDR_X 0x00000004 /* Execute access enable */
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#define MMUDR_W 0x00000008 /* Write access enable */
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#define MMUDR_R 0x00000010 /* Read access enable */
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#define MMUDR_SP 0x00000020 /* Supervisor access enable */
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#define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */
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#define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */
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#define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */
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#define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */
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#define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */
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#define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */
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#define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */
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#define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */
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#define MMUDR_PAN 10 /* Physical address */
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#define MMUDR_PAMASK 0xfffffc00 /* PA mask */
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#ifndef __ASSEMBLY__
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/*
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* Simple access functions for the MMU registers. Nothing fancy
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* currently required, just simple 32bit access.
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*/
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static inline u32 mmu_read(u32 a)
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{
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return *((volatile u32 *) a);
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}
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static inline void mmu_write(u32 a, u32 v)
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{
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*((volatile u32 *) a) = v;
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__asm__ __volatile__ ("nop");
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}
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int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word);
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#endif
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#endif /* MCFMMU_H */
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