565 lines
14 KiB
Plaintext
565 lines
14 KiB
Plaintext
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/*
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* Copyright (C) 2013 STMicroelectronics Limited.
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "st-pincfg.h"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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aliases {
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gpio0 = &PIO0;
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gpio1 = &PIO1;
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gpio2 = &PIO2;
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gpio3 = &PIO3;
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gpio4 = &PIO4;
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gpio5 = &PIO40;
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gpio6 = &PIO5;
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gpio7 = &PIO6;
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gpio8 = &PIO7;
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gpio9 = &PIO8;
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gpio10 = &PIO9;
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gpio11 = &PIO10;
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gpio12 = &PIO11;
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gpio13 = &PIO12;
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gpio14 = &PIO30;
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gpio15 = &PIO31;
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gpio16 = &PIO13;
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gpio17 = &PIO14;
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gpio18 = &PIO15;
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gpio19 = &PIO16;
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gpio20 = &PIO17;
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gpio21 = &PIO18;
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gpio22 = &PIO100;
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gpio23 = &PIO101;
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gpio24 = &PIO102;
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gpio25 = &PIO103;
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gpio26 = &PIO104;
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gpio27 = &PIO105;
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gpio28 = &PIO106;
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gpio29 = &PIO107;
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};
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soc {
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pin-controller-sbc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih416-sbc-pinctrl";
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st,syscfg = <&syscfg_sbc>;
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reg = <0xfe61f080 0x4>;
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reg-names = "irqmux";
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irqmux";
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ranges = <0 0xfe610000 0x6000>;
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PIO0: gpio@fe610000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x100>;
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st,bank-name = "PIO0";
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};
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PIO1: gpio@fe611000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO1";
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};
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PIO2: gpio@fe612000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO2";
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};
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PIO3: gpio@fe613000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO3";
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};
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PIO4: gpio@fe614000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO4";
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};
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PIO40: gpio@fe615000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x100>;
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st,bank-name = "PIO40";
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st,retime-pin-mask = <0x7f>;
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};
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rc{
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pinctrl_ir: ir0 {
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st,pins {
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ir = <&PIO4 0 ALT2 IN>;
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};
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};
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};
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sbc_serial1 {
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pinctrl_sbc_serial1: sbc_serial1 {
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st,pins {
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tx = <&PIO2 6 ALT3 OUT>;
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rx = <&PIO2 7 ALT3 IN>;
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};
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};
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};
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keyscan {
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pinctrl_keyscan: keyscan {
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st,pins {
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keyin0 = <&PIO0 2 ALT2 IN>;
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keyin1 = <&PIO0 3 ALT2 IN>;
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keyin2 = <&PIO0 4 ALT2 IN>;
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keyin3 = <&PIO2 6 ALT2 IN>;
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keyout0 = <&PIO1 6 ALT2 OUT>;
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keyout1 = <&PIO1 7 ALT2 OUT>;
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keyout2 = <&PIO0 6 ALT2 OUT>;
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keyout3 = <&PIO2 7 ALT2 OUT>;
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};
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};
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};
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sbc_i2c0 {
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pinctrl_sbc_i2c0_default: sbc_i2c0-default {
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st,pins {
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sda = <&PIO4 6 ALT1 BIDIR>;
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scl = <&PIO4 5 ALT1 BIDIR>;
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};
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};
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};
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sbc_i2c1 {
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pinctrl_sbc_i2c1_default: sbc_i2c1-default {
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st,pins {
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sda = <&PIO3 2 ALT2 BIDIR>;
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scl = <&PIO3 1 ALT2 BIDIR>;
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};
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};
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};
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gmac1 {
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pinctrl_mii1: mii1 {
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st,pins {
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txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
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col = <&PIO0 7 ALT1 IN BYPASS 1000>;
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mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
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mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
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crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
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mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
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rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
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phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
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};
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};
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pinctrl_rgmii1: rgmii1-0 {
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st,pins {
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txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
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txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
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txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
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txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
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txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
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txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
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mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
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mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
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rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
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rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
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rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
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rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
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rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
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rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
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phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
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clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
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};
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};
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};
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};
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pin-controller-front {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih416-front-pinctrl";
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st,syscfg = <&syscfg_front>;
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reg = <0xfee0f080 0x4>;
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reg-names = "irqmux";
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irqmux";
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ranges = <0 0xfee00000 0x10000>;
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PIO5: gpio@fee00000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x100>;
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st,bank-name = "PIO5";
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};
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PIO6: gpio@fee01000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO6";
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};
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PIO7: gpio@fee02000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO7";
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};
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PIO8: gpio@fee03000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO8";
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};
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PIO9: gpio@fee04000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO9";
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};
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PIO10: gpio@fee05000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x100>;
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st,bank-name = "PIO10";
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};
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PIO11: gpio@fee06000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x6000 0x100>;
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st,bank-name = "PIO11";
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};
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PIO12: gpio@fee07000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x7000 0x100>;
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st,bank-name = "PIO12";
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};
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PIO30: gpio@fee08000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x8000 0x100>;
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st,bank-name = "PIO30";
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};
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PIO31: gpio@fee09000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x9000 0x100>;
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st,bank-name = "PIO31";
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};
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serial2-oe {
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pinctrl_serial2_oe: serial2-1 {
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st,pins {
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output-enable = <&PIO11 3 ALT2 OUT>;
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};
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};
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};
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i2c0 {
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pinctrl_i2c0_default: i2c0-default {
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st,pins {
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sda = <&PIO9 3 ALT1 BIDIR>;
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scl = <&PIO9 2 ALT1 BIDIR>;
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};
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};
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};
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i2c1 {
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pinctrl_i2c1_default: i2c1-default {
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st,pins {
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sda = <&PIO12 1 ALT1 BIDIR>;
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scl = <&PIO12 0 ALT1 BIDIR>;
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};
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};
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};
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fsm {
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pinctrl_fsm: fsm {
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st,pins {
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spi-fsm-clk = <&PIO12 2 ALT1 OUT>;
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spi-fsm-cs = <&PIO12 3 ALT1 OUT>;
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spi-fsm-mosi = <&PIO12 4 ALT1 OUT>;
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spi-fsm-miso = <&PIO12 5 ALT1 IN>;
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spi-fsm-hol = <&PIO12 6 ALT1 OUT>;
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spi-fsm-wp = <&PIO12 7 ALT1 OUT>;
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};
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};
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};
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};
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pin-controller-rear {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih416-rear-pinctrl";
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st,syscfg = <&syscfg_rear>;
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reg = <0xfe82f080 0x4>;
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reg-names = "irqmux";
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irqmux";
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ranges = <0 0xfe820000 0x6000>;
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PIO13: gpio@fe820000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x100>;
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||
|
|
st,bank-name = "PIO13";
|
||
|
|
};
|
||
|
|
PIO14: gpio@fe821000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x1000 0x100>;
|
||
|
|
st,bank-name = "PIO14";
|
||
|
|
};
|
||
|
|
PIO15: gpio@fe822000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x2000 0x100>;
|
||
|
|
st,bank-name = "PIO15";
|
||
|
|
};
|
||
|
|
PIO16: gpio@fe823000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x3000 0x100>;
|
||
|
|
st,bank-name = "PIO16";
|
||
|
|
};
|
||
|
|
PIO17: gpio@fe824000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x4000 0x100>;
|
||
|
|
st,bank-name = "PIO17";
|
||
|
|
};
|
||
|
|
PIO18: gpio@fe825000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x5000 0x100>;
|
||
|
|
st,bank-name = "PIO18";
|
||
|
|
st,retime-pin-mask = <0xf>;
|
||
|
|
};
|
||
|
|
|
||
|
|
serial2 {
|
||
|
|
pinctrl_serial2: serial2-0 {
|
||
|
|
st,pins {
|
||
|
|
tx = <&PIO17 4 ALT2 OUT>;
|
||
|
|
rx = <&PIO17 5 ALT2 IN>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
gmac0 {
|
||
|
|
pinctrl_mii0: mii0 {
|
||
|
|
st,pins {
|
||
|
|
mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
|
||
|
|
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||
|
|
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||
|
|
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||
|
|
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
||
|
|
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
||
|
|
|
||
|
|
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
|
||
|
|
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||
|
|
crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
|
||
|
|
col = <&PIO15 3 ALT2 IN BYPASS 1000>;
|
||
|
|
mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
|
||
|
|
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
|
||
|
|
|
||
|
|
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
|
||
|
|
phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gmii0: gmii0 {
|
||
|
|
st,pins {
|
||
|
|
};
|
||
|
|
};
|
||
|
|
pinctrl_rgmii0: rgmii0 {
|
||
|
|
st,pins {
|
||
|
|
phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
|
||
|
|
txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
|
||
|
|
txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
|
||
|
|
txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
|
||
|
|
txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
|
||
|
|
txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
|
||
|
|
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
|
||
|
|
|
||
|
|
mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
|
||
|
|
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
|
||
|
|
|
||
|
|
rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
|
||
|
|
rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
|
||
|
|
rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
|
||
|
|
rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
|
||
|
|
rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
|
||
|
|
rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
|
||
|
|
|
||
|
|
clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pin-controller-fvdp-fe {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "st,stih416-fvdp-fe-pinctrl";
|
||
|
|
st,syscfg = <&syscfg_fvdp_fe>;
|
||
|
|
reg = <0xfd6bf080 0x4>;
|
||
|
|
reg-names = "irqmux";
|
||
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "irqmux";
|
||
|
|
ranges = <0 0xfd6b0000 0x3000>;
|
||
|
|
|
||
|
|
PIO100: gpio@fd6b0000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0 0x100>;
|
||
|
|
st,bank-name = "PIO100";
|
||
|
|
};
|
||
|
|
PIO101: gpio@fd6b1000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x1000 0x100>;
|
||
|
|
st,bank-name = "PIO101";
|
||
|
|
};
|
||
|
|
PIO102: gpio@fd6b2000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x2000 0x100>;
|
||
|
|
st,bank-name = "PIO102";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pin-controller-fvdp-lite {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "st,stih416-fvdp-lite-pinctrl";
|
||
|
|
st,syscfg = <&syscfg_fvdp_lite>;
|
||
|
|
reg = <0xfd33f080 0x4>;
|
||
|
|
reg-names = "irqmux";
|
||
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "irqmux";
|
||
|
|
ranges = <0 0xfd330000 0x5000>;
|
||
|
|
|
||
|
|
PIO103: gpio@fd330000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0 0x100>;
|
||
|
|
st,bank-name = "PIO103";
|
||
|
|
};
|
||
|
|
PIO104: gpio@fd331000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x1000 0x100>;
|
||
|
|
st,bank-name = "PIO104";
|
||
|
|
};
|
||
|
|
PIO105: gpio@fd332000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x2000 0x100>;
|
||
|
|
st,bank-name = "PIO105";
|
||
|
|
};
|
||
|
|
PIO106: gpio@fd333000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x3000 0x100>;
|
||
|
|
st,bank-name = "PIO106";
|
||
|
|
};
|
||
|
|
|
||
|
|
PIO107: gpio@fd334000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x4000 0x100>;
|
||
|
|
st,bank-name = "PIO107";
|
||
|
|
st,retime-pin-mask = <0xf>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|