239 lines
7.1 KiB
Plaintext
239 lines
7.1 KiB
Plaintext
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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msm_vidc: qcom,vidc@c00000 {
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compatible = "qcom,msm-vidc";
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status = "ok";
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reg = <0xC00000 0xff000>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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qcom,hfi = "venus";
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qcom,hfi-version = "3xx";
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qcom,reg-presets = <0x80010 0xffffffff>,
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<0x80018 0x00001556>,
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<0x8001C 0x00001556>;
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qcom,qdss-presets = <0x08180000 0x2000>,
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<0x08182000 0x2000>,
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<0x08184000 0x2000>,
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<0x08186000 0x2000>,
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<0x08188000 0x2000>,
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<0x0818A000 0x2000>,
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<0x0818C000 0x2000>,
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<0x0818E000 0x2000>;
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qcom,max-hw-load = <2563200>; /* Full 4k @ 60 + 1080p @ 60 */
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qcom,firmware-name = "venus";
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qcom,imem-size = <524288>; /* 512 kB */
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qcom,never-unload-fw;
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qcom,sw-power-collapse;
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qcom,max-secure-instances = <5>;
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qcom,load-freq-tbl =
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/* Encoders */
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<972000 490000000 0x55555555>, /* 4k UHD @ 30 */
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<489600 320000000 0x55555555>, /* 1080p @ 60 */
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<244800 150000000 0x55555555>, /* 1080p @ 30 */
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<108000 75000000 0x55555555>, /* 720p @ 30 */
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/* Decoders */
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<1944000 490000000 0xffffffff>, /* 4k UHD @ 60 */
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< 972000 320000000 0xffffffff>, /* 4k UHD @ 30 */
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< 489600 150000000 0xffffffff>, /* 1080p @ 60 */
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< 244800 75000000 0xffffffff>; /* 1080p @ 30 */
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qcom,dcvs-tbl =
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<972000 972000 19944000 0x3f00000c>, /* UHD 30 */
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<489600 489600 972000 0x3f00000c>, /* 1080p 60 */
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<244800 244800 489600 0x3f00000c>, /* 1080p 30 */
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<829440 489600 972000 0x04000004>; /* DCI 24 */
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qcom,dcvs-limit =
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<32400 30>, /* Encoder UHD */
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<14400 30>; /* Decoder WQHD */
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/* Table lists <video_core_freq imem_ab> pairs.
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* imem_ab value determines the imem clock frequency for the
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* corresponding video core frequency.
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*/
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qcom,imem-ab-tbl =
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<75000000 1500000>, /* imem @ svs2 freq 75 Mhz */
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<150000000 1500000>, /* imem @ svs2 freq 75 Mhz */
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<320000000 2500000>, /* imem @ svs freq 171 Mhz */
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<490000000 6000000>; /* imem @ noimal freq 320 Mhz */
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/* Regulators */
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/* Note: don't change the order of the regulators below as they
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* correspond to the order in which the driver enables them.
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*/
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mmagic-venus-supply = <&gdsc_mmagic_video>;
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venus-supply = <&gdsc_venus>;
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venus-core0-supply = <&gdsc_venus_core0>;
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venus-core1-supply = <&gdsc_venus_core1>;
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/* Clocks */
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clock-names = "smmu_ahb_clk", "smmu_axi_clk",
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"mmagic_video_axi", "core_clk", "iface_clk",
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"bus_clk", "maxi_clk", "core0_clk", "core1_clk";
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clocks = <&clock_mmss clk_smmu_video_ahb_clk>,
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<&clock_mmss clk_smmu_video_axi_clk>,
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<&clock_mmss clk_mmagic_video_axi_clk>,
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<&clock_mmss clk_video_core_clk>,
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<&clock_mmss clk_video_ahb_clk>,
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<&clock_mmss clk_video_axi_clk>,
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<&clock_mmss clk_video_maxi_clk>,
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<&clock_mmss clk_video_subcore0_clk>,
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<&clock_mmss clk_video_subcore1_clk>;
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qcom,clock-configs = <0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x1 0x1>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-vidc,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1 1>;
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};
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venus_bus_ddr {
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compatible = "qcom,msm-vidc,bus";
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label = "venus-ddr";
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qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
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qcom,bus-governor = "msm-vidc-ddr";
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qcom,bus-range-kbps = <1000 3388000>;
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};
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venus_bus_vmem {
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compatible = "qcom,msm-vidc,bus";
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label = "venus-vmem";
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qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0_OCMEM>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VMEM>;
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qcom,bus-governor = "msm-vidc-vmem+";
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qcom,bus-range-kbps = <1000 6776000>;
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};
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arm9_bus_ddr {
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compatible = "qcom,msm-vidc,bus";
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label = "venus-arm9-ddr";
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qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1 1>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_ns";
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iommus = <&venus_smmu 0x00>,
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<&venus_smmu 0x01>,
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<&venus_smmu 0x0a>,
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<&venus_smmu 0x07>,
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<&venus_smmu 0x0e>,
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<&venus_smmu 0x0f>,
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<&venus_smmu 0x08>,
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<&venus_smmu 0x09>,
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<&venus_smmu 0x0b>,
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<&venus_smmu 0x0c>,
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<&venus_smmu 0x0d>,
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<&venus_smmu 0x10>,
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<&venus_smmu 0x11>,
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<&venus_smmu 0x21>,
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<&venus_smmu 0x28>,
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<&venus_smmu 0x29>,
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<&venus_smmu 0x2b>,
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<&venus_smmu 0x2c>,
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<&venus_smmu 0x2d>,
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<&venus_smmu 0x31>;
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x70800000 0x8F800000>;
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};
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firmware_cb {
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compatible = "qcom,msm-vidc,context-bank";
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qcom,fw-context-bank;
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iommus = <&venus_smmu 0x180>,
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<&venus_smmu 0x186>;
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};
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secure_bitstream_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_bitstream";
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iommus = <&venus_smmu 0x100>,
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<&venus_smmu 0x102>,
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<&venus_smmu 0x109>,
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<&venus_smmu 0x10a>,
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<&venus_smmu 0x10b>,
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<&venus_smmu 0x10e>,
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<&venus_smmu 0x126>,
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<&venus_smmu 0x129>,
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<&venus_smmu 0x12b>;
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buffer-types = <0x241>;
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virtual-addr-pool = <0x4b000000 0x25800000>;
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qcom,secure-context-bank;
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};
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venus_secure_pixel_cb: secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_pixel";
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iommus = <&venus_smmu 0x104>,
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<&venus_smmu 0x10c>,
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<&venus_smmu 0x110>,
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<&venus_smmu 0x12c>;
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buffer-types = <0x106>;
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virtual-addr-pool = <0x25800000 0x25800000>;
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qcom,secure-context-bank;
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};
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venus_secure_non_pixel_cb: secure_non_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_non_pixel";
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iommus = <&venus_smmu 0x105>,
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<&venus_smmu 0x107>,
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<&venus_smmu 0x108>,
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<&venus_smmu 0x10d>,
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<&venus_smmu 0x10f>,
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<&venus_smmu 0x125>,
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<&venus_smmu 0x128>,
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<&venus_smmu 0x12d>,
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<&venus_smmu 0x140>;
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buffer-types = <0x480>;
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virtual-addr-pool = <0x1000000 0x24800000>;
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qcom,secure-context-bank;
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};
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};
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vmem: qcom,vmem@880000 {
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compatible = "qcom,msm-vmem";
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interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x880000 0x800>,
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<0x6800000 0x80000>;
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reg-names = "reg-base", "mem-base";
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vdd-supply = <&gdsc_mmagic_video>;
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clocks = <&clock_mmss clk_vmem_ahb_clk>,
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<&clock_mmss clk_vmem_maxi_clk>;
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clock-names = "ahb", "maxi";
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qcom,msm-bus,name = "vmem";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VMEM_CFG 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VMEM_CFG 500 800>;
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qcom,bank-size = <131072>; /* 128 kB */
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};
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};
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