666 lines
14 KiB
Plaintext
666 lines
14 KiB
Plaintext
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* As a general rule, only version-specific property overrides should be placed
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* inside this file. Common device definitions should be placed inside the
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* msm8996.dtsi file.
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*/
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#include "msm8996.dtsi"
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#include "msm8996-coresight-v3.dtsi"
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#include "msm-arm-smmu-impl-defs-8996-v3.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. MSM 8996 v3";
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qcom,msm-id = <246 0x30001>;
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};
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&clock_gcc {
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compatible = "qcom,gcc-8996-v3";
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};
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&clock_debug {
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compatible = "qcom,cc-debug-8996-v3";
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};
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&clock_mmss {
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compatible = "qcom,mmsscc-8996-v3";
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};
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&clock_gpu {
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compatible = "qcom,gpucc-8996-v3";
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qcom,gfx3d_clk_src_v2-opp-handle = <&msm_gpu>;
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qcom,gfxfreq-speedbin0 =
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< 0 0 0 >,
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< 133000000 2 4 >,
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< 214000000 3 4 >,
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< 315000000 4 4 >,
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< 401800000 5 5 >,
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< 510000000 6 5 >,
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< 560000000 7 7 >,
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< 624000000 8 7 >;
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qcom,gfxfreq-mx-speedbin0 =
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< 0 0 >,
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< 133000000 4 >,
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< 214000000 4 >,
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< 315000000 4 >,
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< 401800000 5 >,
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< 510000000 5 >,
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< 560000000 7 >,
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< 624000000 7 >;
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qcom,gfxfreq-speedbin1 =
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< 0 0 0 >,
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< 133000000 2 4 >,
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< 214000000 3 4 >,
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< 315000000 4 4 >,
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< 401800000 5 5 >,
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< 510000000 6 5 >;
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qcom,gfxfreq-mx-speedbin1 =
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< 0 0 >,
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< 133000000 4 >,
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< 214000000 4 >,
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< 315000000 4 >,
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< 401800000 5 >,
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< 510000000 5 >;
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};
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&gdsc_gpu_gx {
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clock-names = "core_clk", "core_root_clk";
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clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>,
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<&clock_gpu clk_gfx3d_clk_src_v2>;
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};
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&pcie0 {
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qcom,pcie-phy-ver = <3>;
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};
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&pcie1 {
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qcom,pcie-phy-ver = <3>;
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};
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&pcie2 {
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qcom,pcie-phy-ver = <3>;
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};
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/* GPU overrides */
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&msm_gpu {
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/* Updated chip ID */
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qcom,chipid = <0x05030002>;
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qcom,initial-pwrlevel = <5>;
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qcom,bus-width = <32>;
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/* Quirks */
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qcom,gpu-quirk-two-pass-use-wfi;
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible="qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <624000000>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <11>;
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qcom,bus-max = <12>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <560000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <9>;
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qcom,bus-max = <12>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <510000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <11>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <401800000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <315000000>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <5>;
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qcom,bus-max = <7>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <214000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <133000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <4>;
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};
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <27000000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <1>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <510000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <401800000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <315000000>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <5>;
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qcom,bus-max = <7>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <214000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <133000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <2>;
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qcom,bus-max = <4>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <27000000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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};
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};
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&soc {
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l2-pmu {
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compatible = "qcom,qcom-l2cache-pmu";
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interrupts = <0 0 1>, <0 8 1>;
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qcom,cpu-affinity = <0>, <2>;
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};
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};
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&soc {
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jtag_mm0: jtagmm@3840000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x3840000 0x1000>;
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reg-names = "etm-base";
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU0>;
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};
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jtag_mm1: jtagmm@3940000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x3940000 0x1000>;
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reg-names = "etm-base";
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU1>;
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};
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jtag_mm2: jtagmm@3a40000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x3a40000 0x1000>;
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reg-names = "etm-base";
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU2>;
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};
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jtag_mm3: jtagmm@3b40000 {
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compatible = "qcom,jtagv8-mm";
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reg = <0x3b40000 0x1000>;
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reg-names = "etm-base";
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clocks = <&clock_gcc clk_qdss_clk>,
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<&clock_gcc clk_qdss_a_clk>;
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clock-names = "core_clk", "core_a_clk";
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qcom,coresight-jtagmm-cpu = <&CPU3>;
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};
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};
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&mdss_hdmi_pll {
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compatible = "qcom,mdss_hdmi_pll_8996_v3";
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};
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&msm_vidc {
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/* Table lists <video_core_freq imem_ab> pairs.
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* imem_ab value determines the imem clock frequency for the
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* corresponding video core frequency.
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*/
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qcom,imem-ab-tbl =
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<75000000 1500000>, /* imem @ svs2 freq 75 Mhz */
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<150000000 1500000>, /* imem @ svs2 freq 75 Mhz */
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<346666667 2500000>, /* imem @ svs freq 171 Mhz */
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<520000000 6000000>; /* imem @ noimal freq 320 Mhz */
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qcom,load-freq-tbl =
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/* Encoders */
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<972000 520000000 0x55555555>, /* 4k UHD @ 30 */
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<489600 346666667 0x55555555>, /* 1080p @ 60 */
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<244800 150000000 0x55555555>, /* 1080p @ 30 */
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<108000 75000000 0x55555555>, /* 720p @ 30 */
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/* Decoders */
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<1944000 520000000 0xffffffff>, /* 4k UHD @ 60 */
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< 972000 346666667 0xffffffff>, /* 4k UHD @ 30 */
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< 489600 150000000 0xffffffff>, /* 1080p @ 60 */
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< 244800 75000000 0xffffffff>; /* 1080p @ 30 */
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qcom,pm-qos-latency-us = <501>;
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};
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&gdsc_venus_core0 {
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qcom,support-hw-trigger;
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};
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&gdsc_venus_core1 {
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qcom,support-hw-trigger;
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};
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&soc {
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ipa_hw: qcom,ipa@680000 {
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compatible = "qcom,ipa";
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reg = <0x680000 0x4effc>,
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<0x684000 0x26934>;
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reg-names = "ipa-base", "bam-base";
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interrupts = <0 333 0>,
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<0 432 0>;
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interrupt-names = "ipa-irq", "bam-irq";
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qcom,ipa-hw-ver = <5>; /* IPA core version = IPAv2.5 */
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qcom,ipa-hw-mode = <0>;
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qcom,ee = <0>;
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qcom,use-ipa-tethering-bridge;
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qcom,ipa-bam-remote-mode;
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qcom,modem-cfg-emb-pipe-flt;
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clocks = <&clock_gcc clk_ipa_clk>;
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clock-names = "core_clk";
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qcom,use-dma-zone;
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qcom,msm-bus,name = "ipa";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<90 512 0 0>, <90 585 0 0>, /* No vote */
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<90 512 80000 640000>, <90 585 80000 640000>, /* SVS */
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<90 512 206000 960000>, <90 585 206000 960000>; /* PERF */
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qcom,bus-vector-names = "MIN", "SVS", "PERF";
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};
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qcom,m4m-hwmon@6530000 {
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compatible = "qcom,m4m-hwmon";
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reg = <0x6530000 0x160>;
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interrupts = <0 19 4>;
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qcom,counter-event-sel = <4 0x8000>,
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<5 0x4000>;
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qcom,target-dev = <&m4m_cache>;
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};
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};
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|
|
|
||
|
|
&clock_cpu {
|
||
|
|
compatible = "qcom,cpu-clock-8996-v3";
|
||
|
|
/* Nominal FMAXes only until characterization completes. */
|
||
|
|
qcom,pwrcl-speedbin0-v0 =
|
||
|
|
< 0 0 >,
|
||
|
|
< 307200000 1 >,
|
||
|
|
< 422400000 2 >,
|
||
|
|
< 480000000 3 >,
|
||
|
|
< 556800000 4 >,
|
||
|
|
< 652800000 5 >,
|
||
|
|
< 729600000 6 >,
|
||
|
|
< 844800000 7 >,
|
||
|
|
< 960000000 8 >,
|
||
|
|
< 1036800000 9 >,
|
||
|
|
< 1113600000 10 >,
|
||
|
|
< 1190400000 11 >,
|
||
|
|
< 1228800000 12 >,
|
||
|
|
< 1324800000 13 >,
|
||
|
|
< 1401600000 14 >,
|
||
|
|
< 1478400000 15 >,
|
||
|
|
< 1593600000 16 >;
|
||
|
|
qcom,pwrcl-speedbin1-v0 =
|
||
|
|
< 0 0 >,
|
||
|
|
< 307200000 1 >,
|
||
|
|
< 422400000 2 >,
|
||
|
|
< 480000000 3 >,
|
||
|
|
< 556800000 4 >,
|
||
|
|
< 652800000 5 >,
|
||
|
|
< 729600000 6 >,
|
||
|
|
< 844800000 7 >,
|
||
|
|
< 960000000 8 >,
|
||
|
|
< 1036800000 9 >,
|
||
|
|
< 1113600000 10 >,
|
||
|
|
< 1190400000 11 >,
|
||
|
|
< 1228800000 12 >,
|
||
|
|
< 1363200000 13 >;
|
||
|
|
qcom,perfcl-speedbin0-v0 =
|
||
|
|
< 0 0 >,
|
||
|
|
< 307200000 1 >,
|
||
|
|
< 403200000 2 >,
|
||
|
|
< 480000000 3 >,
|
||
|
|
< 556800000 4 >,
|
||
|
|
< 652800000 5 >,
|
||
|
|
< 729600000 6 >,
|
||
|
|
< 806400000 7 >,
|
||
|
|
< 883200000 8 >,
|
||
|
|
< 940800000 9 >,
|
||
|
|
< 1036800000 10 >,
|
||
|
|
< 1113600000 11 >,
|
||
|
|
< 1190400000 12 >,
|
||
|
|
< 1248000000 13 >,
|
||
|
|
< 1324800000 14 >,
|
||
|
|
< 1401600000 15 >,
|
||
|
|
< 1478400000 16 >,
|
||
|
|
< 1555200000 17 >,
|
||
|
|
< 1632000000 18 >,
|
||
|
|
< 1708800000 19 >,
|
||
|
|
< 1785600000 20 >,
|
||
|
|
< 1824000000 21 >,
|
||
|
|
< 1920000000 22 >,
|
||
|
|
< 1996800000 23 >,
|
||
|
|
< 2073600000 24 >,
|
||
|
|
< 2150400000 25 >;
|
||
|
|
qcom,perfcl-speedbin1-v0 =
|
||
|
|
< 0 0 >,
|
||
|
|
< 307200000 1 >,
|
||
|
|
< 403200000 2 >,
|
||
|
|
< 480000000 3 >,
|
||
|
|
< 556800000 4 >,
|
||
|
|
< 652800000 5 >,
|
||
|
|
< 729600000 6 >,
|
||
|
|
< 806400000 7 >,
|
||
|
|
< 883200000 8 >,
|
||
|
|
< 940800000 9 >,
|
||
|
|
< 1036800000 10 >,
|
||
|
|
< 1113600000 11 >,
|
||
|
|
< 1190400000 12 >,
|
||
|
|
< 1248000000 13 >,
|
||
|
|
< 1324800000 14 >,
|
||
|
|
< 1401600000 15 >,
|
||
|
|
< 1478400000 16 >,
|
||
|
|
< 1555200000 17 >,
|
||
|
|
< 1632000000 18 >,
|
||
|
|
< 1708800000 19 >,
|
||
|
|
< 1785600000 20 >,
|
||
|
|
< 1804800000 21 >;
|
||
|
|
qcom,cbf-speedbin0-v0 =
|
||
|
|
< 0 0 >,
|
||
|
|
< 307200000 1 >,
|
||
|
|
< 384000000 2 >,
|
||
|
|
< 460800000 3 >,
|
||
|
|
< 537600000 4 >,
|
||
|
|
< 595200000 5 >,
|
||
|
|
< 672000000 6 >,
|
||
|
|
< 748800000 7 >,
|
||
|
|
< 825600000 8 >,
|
||
|
|
< 902400000 9 >,
|
||
|
|
< 979200000 10 >,
|
||
|
|
< 1056000000 11 >,
|
||
|
|
< 1132800000 12 >,
|
||
|
|
< 1190400000 13 >,
|
||
|
|
< 1228800000 14 >,
|
||
|
|
< 1305600000 15 >,
|
||
|
|
< 1382400000 16 >,
|
||
|
|
< 1459200000 17 >,
|
||
|
|
< 1536000000 18 >,
|
||
|
|
< 1593600000 19 >;
|
||
|
|
qcom,cbf-speedbin1-v0 =
|
||
|
|
< 0 0 >,
|
||
|
|
< 307200000 1 >,
|
||
|
|
< 384000000 2 >,
|
||
|
|
< 460800000 3 >,
|
||
|
|
< 537600000 4 >,
|
||
|
|
< 595200000 5 >,
|
||
|
|
< 672000000 6 >,
|
||
|
|
< 748800000 7 >,
|
||
|
|
< 825600000 8 >,
|
||
|
|
< 902400000 9 >,
|
||
|
|
< 979200000 10 >,
|
||
|
|
< 1056000000 11 >,
|
||
|
|
< 1132800000 12 >,
|
||
|
|
< 1190400000 13 >,
|
||
|
|
< 1228800000 14 >,
|
||
|
|
< 1305600000 15 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
&msm_cpufreq {
|
||
|
|
qcom,cpufreq-table-0 =
|
||
|
|
< 307200 >,
|
||
|
|
< 422400 >,
|
||
|
|
< 480000 >,
|
||
|
|
< 556800 >,
|
||
|
|
< 652800 >,
|
||
|
|
< 729600 >,
|
||
|
|
< 844800 >,
|
||
|
|
< 960000 >,
|
||
|
|
< 1036800 >,
|
||
|
|
< 1113600 >,
|
||
|
|
< 1190400 >,
|
||
|
|
< 1228800 >,
|
||
|
|
< 1324800 >,
|
||
|
|
< 1401600 >,
|
||
|
|
< 1478400 >,
|
||
|
|
< 1593600 >;
|
||
|
|
qcom,cpufreq-table-2 =
|
||
|
|
< 307200 >,
|
||
|
|
< 403200 >,
|
||
|
|
< 480000 >,
|
||
|
|
< 556800 >,
|
||
|
|
< 652800 >,
|
||
|
|
< 729600 >,
|
||
|
|
< 806400 >,
|
||
|
|
< 883200 >,
|
||
|
|
< 940800 >,
|
||
|
|
< 1036800 >,
|
||
|
|
< 1113600 >,
|
||
|
|
< 1190400 >,
|
||
|
|
< 1248000 >,
|
||
|
|
< 1324800 >,
|
||
|
|
< 1401600 >,
|
||
|
|
< 1478400 >,
|
||
|
|
< 1555200 >,
|
||
|
|
< 1632000 >,
|
||
|
|
< 1708800 >,
|
||
|
|
< 1785600 >,
|
||
|
|
< 1824000 >,
|
||
|
|
< 1920000 >,
|
||
|
|
< 1996800 >,
|
||
|
|
< 2073600 >,
|
||
|
|
< 2150400 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
&m4m_cache {
|
||
|
|
freq-tbl-khz =
|
||
|
|
< 307200 >,
|
||
|
|
< 384000 >,
|
||
|
|
< 460800 >,
|
||
|
|
< 537600 >,
|
||
|
|
< 595200 >,
|
||
|
|
< 672000 >,
|
||
|
|
< 748800 >,
|
||
|
|
< 825600 >,
|
||
|
|
< 902400 >,
|
||
|
|
< 979200 >,
|
||
|
|
< 1056000 >,
|
||
|
|
< 1132800 >,
|
||
|
|
< 1190400 >,
|
||
|
|
< 1228800 >,
|
||
|
|
< 1305600 >,
|
||
|
|
< 1382400 >,
|
||
|
|
< 1459200 >,
|
||
|
|
< 1536000 >,
|
||
|
|
< 1593600 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
&devfreq_cpufreq {
|
||
|
|
m4m-cpufreq {
|
||
|
|
cpu-to-dev-map-0 =
|
||
|
|
< 307200 307200 >,
|
||
|
|
< 422400 307200 >,
|
||
|
|
< 480000 307200 >,
|
||
|
|
< 556800 307200 >,
|
||
|
|
< 652800 384000 >,
|
||
|
|
< 729600 460800 >,
|
||
|
|
< 844800 537600 >,
|
||
|
|
< 960000 672000 >,
|
||
|
|
< 1036800 672000 >,
|
||
|
|
< 1113600 825600 >,
|
||
|
|
< 1190400 825600 >,
|
||
|
|
< 1228800 902400 >,
|
||
|
|
< 1324800 1056000 >,
|
||
|
|
< 1401600 1132800 >,
|
||
|
|
< 1478400 1190400 >,
|
||
|
|
< 1593600 1382400 >;
|
||
|
|
cpu-to-dev-map-2 =
|
||
|
|
< 480000 307200 >,
|
||
|
|
< 556800 307200 >,
|
||
|
|
< 652800 307200 >,
|
||
|
|
< 729600 307200 >,
|
||
|
|
< 806400 384000 >,
|
||
|
|
< 883200 460800 >,
|
||
|
|
< 940800 537600 >,
|
||
|
|
< 1036800 595200 >,
|
||
|
|
< 1113600 672000 >,
|
||
|
|
< 1190400 672000 >,
|
||
|
|
< 1248000 748800 >,
|
||
|
|
< 1324800 825600 >,
|
||
|
|
< 1401600 902400 >,
|
||
|
|
< 1478400 979200 >,
|
||
|
|
< 1555200 1056000 >,
|
||
|
|
< 1632000 1190400 >,
|
||
|
|
< 1708800 1228800 >,
|
||
|
|
< 1785600 1305600 >,
|
||
|
|
< 1824000 1382400 >,
|
||
|
|
< 1920000 1459200 >,
|
||
|
|
< 1996800 1593600 >,
|
||
|
|
< 2073600 1593600 >,
|
||
|
|
< 2150400 1593600 >;
|
||
|
|
};
|
||
|
|
|
||
|
|
mincpubw-cpufreq {
|
||
|
|
cpu-to-dev-map-0 =
|
||
|
|
< 1593600 1525 >;
|
||
|
|
cpu-to-dev-map-2 =
|
||
|
|
< 2073600 1525 >,
|
||
|
|
< 2150400 5195 >;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&soc {
|
||
|
|
tsens1: tsens@4ad000 {
|
||
|
|
compatible = "qcom,msm8996-tsens";
|
||
|
|
reg = <0x4ac000 0x2000>,
|
||
|
|
<0x75230 0x1000>;
|
||
|
|
reg-names = "tsens_physical", "tsens_eeprom_physical";
|
||
|
|
interrupts = <0 184 0>, <0 430 0>;
|
||
|
|
interrupt-names = "tsens-upper-lower", "tsens-critical";
|
||
|
|
qcom,client-id = <13 14 15 16 17 18 19 20>;
|
||
|
|
qcom,sensor-id = <1 6 7 0 2 3 4 5>;
|
||
|
|
qcom,sensors = <8>;
|
||
|
|
qcom,slope = <2901 2846 3200 3200 3200 3200 3200 3200>;
|
||
|
|
};
|
||
|
|
lmh: qcom,lmh {
|
||
|
|
vdd-apss-supply = <&pm8994_s11>;
|
||
|
|
qcom,lmh-odcm-disable-threshold-mA = <850>;
|
||
|
|
};
|
||
|
|
qcom,msm-thermal {
|
||
|
|
msm_thermal_freq: qcom,vdd-apps-rstr{
|
||
|
|
qcom,max-freq-level = <1190400>;
|
||
|
|
qcom,levels = <1036800 1555200 1555200>;
|
||
|
|
};
|
||
|
|
qcom,vdd-gfx-rstr{
|
||
|
|
qcom,levels = <6 8 8>; /* Nominal, Turbo, Turbo */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
&tsens0 {
|
||
|
|
interrupts = <0 458 0>, <0 445 0>;
|
||
|
|
qcom,sensors = <13>;
|
||
|
|
qcom,slope = <2901 2846 3200 3200 3200 3200 3200 3200 3200
|
||
|
|
3200 3200 3200 3200>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* cpu pmu override */
|
||
|
|
&cpu_pmu {
|
||
|
|
compatible = "qcom,kryo-pmuv3";
|
||
|
|
};
|