271 lines
7.4 KiB
Plaintext
271 lines
7.4 KiB
Plaintext
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/*
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*Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/msm-clocks-titanium.h>
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&soc {
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kgsl_smmu: arm,smmu-kgsl@1c40000 {
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status = "ok";
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compatible = "qcom,smmu-v2";
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qcom,tz-device-id = "GPU";
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reg = <0x1c40000 0x10000>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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interrupts = <0 37 0>, <0 225 0>, <0 232 0>,
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<0 233 0>, <0 234 0>;
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qcom,register-save;
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qcom,skip-init;
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qcom,dynamic;
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qcom,enable-smmu-halt;
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vdd-supply = <&gdsc_oxili_cx>;
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clocks = <&clock_gcc_gfx clk_gcc_oxili_ahb_clk>,
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<&clock_gcc_gfx clk_gcc_bimc_gfx_clk>;
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clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";
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#clock-cells = <1>;
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};
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apps_iommu: qcom,iommu@1e00000 {
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compatible = "qcom,msm-smmu-v2", "qcom,msm-mmu-500";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0x1e00000 0x40000>;
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reg-names = "iommu_base";
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interrupts = <0 41 0>, <0 38 0>;
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interrupt-names = "global_cfg_NS_irq", "global_cfg_S_irq";
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label = "apps_iommu";
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qcom,iommu-secure-id = <17>;
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clocks = <&clock_gcc clk_gcc_smmu_cfg_clk>,
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<&clock_gcc clk_gcc_apss_tcu_async_clk>;
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clock-names = "iface_clk", "core_clk";
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qcom,cb-base-offset = <0x20000>;
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status = "ok";
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adsp_elf: qcom,iommu-ctx@1e20000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e20000 0x1000>;
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qcom,secure-context;
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interrupts = <0 253 0>, <0 253 0>;
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qcom,iommu-ctx-sids = <0x2400>;
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qcom,iommu-sid-mask = <0x3f0>;
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label = "adsp_elf";
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};
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adsp_sec_pixel: qcom,iommu-ctx@1e21000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e21000 0x1000>;
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qcom,secure-context;
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interrupts = <0 254 0>, <0 254 0>;
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qcom,iommu-ctx-sids = <0x2402>;
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qcom,iommu-sid-mask = <0x3f1>;
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label = "adsp_sec_pixel";
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};
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mdp_1: qcom,iommu-ctx@1e22000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e22000 0x1000>;
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qcom,secure-context;
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interrupts = <0 255 0>, <0 255 0>;
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qcom,iommu-ctx-sids = <0xc01>;
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label = "mdp_1";
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};
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venus_fw: qcom,iommu-ctx@1e23000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e23000 0x1000>;
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qcom,secure-context;
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interrupts = <0 53 0>, <0 53 0>;
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qcom,iommu-ctx-sids = <0x980 0x986 0x903>;
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qcom,iommu-sid-mask = <0x200 0x200 0x220>;
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label = "venus_fw";
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qcom,report-error-on-fault;
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};
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venus_sec_non_pixel: qcom,iommu-ctx@1e24000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e24000 0x1000>;
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qcom,secure-context;
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interrupts = <0 54 0>, <0 54 0>;
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qcom,iommu-ctx-sids = <0x908 0x905 0x925 0x928>;
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qcom,iommu-sid-mask = <0x200 0x20a 0x208 0x200>;
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label = "venus_sec_non_pixel";
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qcom,report-error-on-fault;
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};
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venus_sec_bitstream: qcom,iommu-ctx@1e25000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e25000 0x1000>;
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qcom,secure-context;
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interrupts = <0 58 0>, <0 58 0>;
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qcom,iommu-ctx-sids = <0x900 0x902 0x909 0x90e
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0x926 0x929>;
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qcom,iommu-sid-mask = <0x200 0x208 0x202 0x200
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0x200 0x202>;
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label = "venus_sec_bitstream";
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qcom,report-error-on-fault;
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};
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venus_sec_pixel: qcom,iommu-ctx@1e26000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e26000 0x1000>;
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qcom,secure-context;
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interrupts = <0 60 0>, <0 60 0>;
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qcom,iommu-ctx-sids = <0x904 0x910 0x92c>;
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qcom,iommu-sid-mask = <0x208 0x200 0x200>;
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label = "venus_sec_pixel";
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qcom,report-error-on-fault;
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};
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pronto_pil: qcom,iommu-ctx@1e28000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e28000 0x1000>;
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interrupts = <0 76 0>;
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qcom,iommu-ctx-sids = <0x1401 0x1402 0x1404>;
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qcom,iommu-sid-mask = <0x3f2 0x3f0 0x3f0>;
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label = "pronto_pil";
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};
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q6: qcom,iommu-ctx@1e29000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e29000 0x1000>;
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interrupts = <0 77 0>;
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qcom,iommu-ctx-sids = <0x1000>;
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qcom,iommu-sid-mask = <0x3fe>;
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label = "q6";
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};
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periph_rpm: qcom,iommu-ctx@1e2a000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e2a000 0x1000>;
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interrupts = <0 80 0>;
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qcom,iommu-ctx-sids = <0x40>;
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qcom,iommu-sid-mask = <0x3f>;
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label = "periph_rpm";
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};
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lpass: qcom,iommu-ctx@1e2b000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e2b000 0x1000>;
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interrupts = <0 94 0>;
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qcom,iommu-ctx-sids = <0x1c0 0x1ca 0x1cc
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0x1d0 0x1d6 0x1d8 0x1e0
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0x1e4 0x1e8 0x1f0>;
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qcom,iommu-sid-mask = <0x7 0x1 0x3
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0x3 0x1 0x7 0x3
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0x1 0x7 0x1>;
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label = "lpass";
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};
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adsp_io: qcom,iommu-ctx@1e2f000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e2f000 0x1000>;
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interrupts = <0 104 0>;
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qcom,iommu-ctx-sids = <0x2401>;
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qcom,iommu-sid-mask = <0x3f0>;
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label = "adsp_io";
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qcom,virtual-addr-pool = <0x10000000 0x0fffffff>;
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#iommu-cells = <1>;
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};
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adsp_opendsp: qcom,iommu-ctx@1e30000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e30000 0x1000>;
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interrupts = <0 105 0>;
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qcom,iommu-ctx-sids = <0x2404>;
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qcom,iommu-sid-mask = <0x3f0>;
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label = "adsp_opendsp";
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};
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adsp_shared: qcom,iommu-ctx@1e31000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e31000 0x1000>;
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interrupts = <0 106 0>;
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qcom,iommu-ctx-sids = <0x2408>;
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qcom,iommu-sid-mask = <0x3f7>;
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label = "adsp_shared";
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};
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cpp: qcom,iommu-ctx@1e32000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e32000 0x1000>;
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interrupts = <0 109 0>;
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qcom,iommu-ctx-sids = <0x1c00>;
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qcom,iommu-sid-mask = <0x3fc>;
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label = "cpp";
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};
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jpeg_enc0: qcom,iommu-ctx@1e33000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e33000 0x1000>;
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interrupts = <0 110 0>;
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qcom,iommu-ctx-sids = <0x1800>;
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qcom,iommu-sid-mask = <0x3fe>;
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label = "jpeg_enc0";
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};
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vfe: qcom,iommu-ctx@1e34000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e34000 0x1000>;
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interrupts = <0 111 0>;
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qcom,iommu-ctx-sids = <0x400 0x2800>;
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qcom,iommu-sid-mask = <0x3fc 0x3fc>;
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label = "vfe";
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};
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mdp_0: qcom,iommu-ctx@1e35000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e35000 0x1000>;
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interrupts = <0 112 0>;
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qcom,iommu-ctx-sids = <0xc00>;
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qcom,iommu-sid-mask = <0x3fe>;
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label = "mdp_0";
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};
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venus_ns: qcom,iommu-ctx@1e36000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e36000 0x1000>;
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interrupts = <0 113 0>;
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qcom,iommu-ctx-sids = <0x800 0x807 0x808
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0x810 0x828 0x82c
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0x821>;
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qcom,iommu-sid-mask = <0x201 0x200 0x207
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0x201 0x203 0x201
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0x210>;
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label = "venus_ns";
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qcom,report-error-on-fault;
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};
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ipa: qcom,iommu-ctx@1e38000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e38000 0x1000>;
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interrupts = <0 115 0>;
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qcom,iommu-ctx-sids = <0x2000 0x2004>;
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qcom,iommu-sid-mask = <0x3fa 0x3f8>;
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label = "ipa";
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};
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access_control: qcom,iommu-ctx@1e37000 {
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compatible = "qcom,msm-smmu-v2-ctx";
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reg = <0x1e37000 0x1000>;
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interrupts = <0 114 0>;
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qcom,iommu-ctx-sids = <0x1406 0x1408 0x140c
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0x100 0x1d4 0x1e6 0x340>;
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qcom,iommu-sid-mask = <0x3f1 0x3f3 0x3f1
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0x7f 0x1 0x1 0x3f>;
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label = "access_control";
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};
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};
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};
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#include "msm-arm-smmu-impl-defs-titanium.dtsi"
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