427 lines
12 KiB
Plaintext
427 lines
12 KiB
Plaintext
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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aliases {
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &i2c_4;
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spi1 = &spi_1;
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spi2 = &spi_2;
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spi3 = &spi_3;
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spi4 = &spi_4;
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};
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};
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&soc {
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dma_blsp1: qcom,sps-dma@0x7884000{ /* BLSP1 */
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#dma-cells = <4>;
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compatible = "qcom,sps-dma";
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reg = <0x7884000 0x23000>;
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interrupts = <0 238 0>;
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qcom,summing-threshold = <0x10>;
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};
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i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "qup_phys_addr";
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reg = <0x78b5000 0x600>;
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interrupt-names = "qup_irq";
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interrupts = <0 95 0>;
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dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
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<&dma_blsp1 9 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
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<&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_1_active>;
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pinctrl-1 = <&i2c_1_sleep>;
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status = "disabled";
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};
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i2c_2: i2c@78B6000 { /* BLSP1 QUP2 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "qup_phys_addr";
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reg = <0x78B6000 0x600>;
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interrupt-names = "qup_irq";
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interrupts = <0 96 0>;
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dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
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<&dma_blsp1 11 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
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<&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_2_active>;
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pinctrl-1 = <&i2c_2_sleep>;
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status = "disabled";
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};
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i2c_3: i2c@78B7000 { /* BLSP1 QUP3 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "qup_phys_addr";
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reg = <0x78B7000 0x600>;
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interrupt-names = "qup_irq";
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interrupts = <0 97 0>;
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dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
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<&dma_blsp1 13 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
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<&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_3_active>;
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pinctrl-1 = <&i2c_3_sleep>;
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status = "disabled";
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wcd9xxx_codec@d{
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compatible = "qcom,tasha-i2c-pgd";
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reg = <0x0d>;
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interrupt-parent = <&wcd9xxx_intc>;
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interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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17 18 19 20 21 22 23 24 25 26 27 28 29
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30>;
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qcom,cdc-reset-gpio = <&tlmm_pinmux 90 0>;
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clock-names = "wcd_clk";
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clocks = <&clock_audio clk_audio_lpass_mclk>;
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qcom,msm-mbhc-hphl-swh = <0>;
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qcom,msm-mbhc-gnd-swh = <0>;
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cdc-vdd-buck-supply = <&codec_buck_vreg>;
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qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
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qcom,cdc-vdd-buck-current = <650000>;
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cdc-buck-sido-supply = <&codec_buck_vreg>;
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qcom,cdc-buck-sido-voltage = <1800000 1800000>;
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qcom,cdc-buck-sido-current = <200000>;
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cdc-vdd-tx-h-supply = <&pmdcalifornium_l6>;
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qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
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qcom,cdc-vdd-tx-h-current = <25000>;
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cdc-vdd-rx-h-supply = <&pmdcalifornium_l6>;
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qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
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qcom,cdc-vdd-rx-h-current = <25000>;
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cdc-vddpx-1-supply = <&pmdcalifornium_l6>;
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qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
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qcom,cdc-vddpx-1-current = <10000>;
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qcom,cdc-static-supplies = "cdc-vdd-buck",
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"cdc-buck-sido",
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"cdc-vdd-tx-h",
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"cdc-vdd-rx-h",
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"cdc-vddpx-1";
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qcom,cdc-micbias1-mv = <1800>;
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qcom,cdc-micbias2-mv = <1800>;
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qcom,cdc-micbias3-mv = <1800>;
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qcom,cdc-micbias4-mv = <1800>;
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qcom,cdc-mclk-clk-rate = <12288000>;
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qcom,cdc-dmic-sample-rate = <4800000>;
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};
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};
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i2c_4: i2c@78B8000 { /* BLSP1 QUP4 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "qup_phys_addr";
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reg = <0x78B8000 0x600>;
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interrupt-names = "qup_irq";
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interrupts = <0 98 0>;
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dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
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<&dma_blsp1 15 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
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<&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_4_active>;
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pinctrl-1 = <&i2c_4_sleep>;
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status = "disabled";
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};
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spi_1: spi@78B5000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x078B5000 0x600>,
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<0x7884000 0x23000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 95 0>, <0 238 0>;
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spi-max-frequency = <19200000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <8>;
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qcom,bam-producer-pipe-index = <9>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_1_active>;
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pinctrl-1 = <&spi_1_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
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<&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;
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status = "disabled";
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};
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spi_2: spi@78B6000 { /* BLSP1 QUP2 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78B6000 0x600>,
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<0x7884000 0x23000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 96 0>, <0 238 0>;
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spi-max-frequency = <19200000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <10>;
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qcom,bam-producer-pipe-index = <11>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_2_active>;
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pinctrl-1 = <&spi_2_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
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<&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;
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status = "disabled";
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};
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spi_3: spi@78B7000 { /* BLSP1 QUP3 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x078B7000 0x600>,
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<0x7884000 0x23000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 97 0>, <0 238 0>;
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spi-max-frequency = <19200000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <12>;
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qcom,bam-producer-pipe-index = <13>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_3_active>;
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pinctrl-1 = <&spi_3_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
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<&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;
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status = "disabled";
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};
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spi_4: spi@78B8000 { /* BLSP1 QUP4 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x078B8000 0x600>,
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<0x7884000 0x23000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 98 0>, <0 238 0>;
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spi-max-frequency = <19200000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <14>;
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qcom,bam-producer-pipe-index = <15>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_4_active>;
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pinctrl-1 = <&spi_4_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
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<&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>;
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status = "disabled";
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};
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blsp1_uart1_hs: uart@78AF000 { /* BLSP1 UART1 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x78AF000 0x200>,
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<0x7884000 0x23000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart1_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 107 0
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1 &intc 0 238 0
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2 &tlmm_pinmux 1 0>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <0>;
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qcom,bam-rx-ep-pipe-index = <1>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
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<&clock_gcc clk_gcc_blsp1_ahb_clk>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart1_sleep>;
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pinctrl-1 = <&blsp1_uart1_active>;
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qcom,msm-bus,name = "buart1";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<86 512 0 0>,
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<86 512 500 800>;
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status = "disabled";
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};
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blsp1_uart2_hs: uart@78B0000 { /* BLSP1 UART2 */
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compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x78B0000 0x200>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
|
||
|
|
#address-cells = <0>;
|
||
|
|
interrupt-parent = <&blsp1_uart2_hs>;
|
||
|
|
interrupts = <0 1 2>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-map-mask = <0xffffffff>;
|
||
|
|
interrupt-map = <0 &intc 0 108 0
|
||
|
|
1 &intc 0 238 0
|
||
|
|
2 &tlmm_pinmux 5 0>;
|
||
|
|
|
||
|
|
qcom,inject-rx-on-wakeup;
|
||
|
|
qcom,rx-char-to-inject = <0xFD>;
|
||
|
|
|
||
|
|
qcom,bam-tx-ep-pipe-index = <2>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <3>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
|
||
|
|
pinctrl-names = "sleep", "default";
|
||
|
|
pinctrl-0 = <&blsp1_uart2_sleep>;
|
||
|
|
pinctrl-1 = <&blsp1_uart2_active>;
|
||
|
|
|
||
|
|
qcom,msm-bus,name = "buart2";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<86 512 0 0>,
|
||
|
|
<86 512 500 800>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1_uart3_hs: uart@78B1000 { /* BLSP1 UART3 */
|
||
|
|
compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x78B1000 0x200>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
|
||
|
|
#address-cells = <0>;
|
||
|
|
interrupt-parent = <&blsp1_uart3_hs>;
|
||
|
|
interrupts = <0 1 2>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-map-mask = <0xffffffff>;
|
||
|
|
interrupt-map = <0 &intc 0 109 0
|
||
|
|
1 &intc 0 238 0
|
||
|
|
2 &tlmm_pinmux 9 0>;
|
||
|
|
|
||
|
|
qcom,inject-rx-on-wakeup;
|
||
|
|
qcom,rx-char-to-inject = <0xFD>;
|
||
|
|
|
||
|
|
qcom,bam-tx-ep-pipe-index = <4>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <5>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
|
||
|
|
pinctrl-names = "sleep", "default";
|
||
|
|
pinctrl-0 = <&blsp1_uart3_sleep>;
|
||
|
|
pinctrl-1 = <&blsp1_uart3_active>;
|
||
|
|
|
||
|
|
qcom,msm-bus,name = "buart3";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<86 512 0 0>,
|
||
|
|
<86 512 500 800>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1_uart4_hs: uart@78B2000 { /* BLSP1 UART4 */
|
||
|
|
compatible = "qcom,msm-hsuart-v14";
|
||
|
|
reg = <0x78B2000 0x200>,
|
||
|
|
<0x7884000 0x23000>;
|
||
|
|
reg-names = "core_mem", "bam_mem";
|
||
|
|
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
|
||
|
|
#address-cells = <0>;
|
||
|
|
interrupt-parent = <&blsp1_uart4_hs>;
|
||
|
|
interrupts = <0 1 2>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-map-mask = <0xffffffff>;
|
||
|
|
interrupt-map = <0 &intc 0 110 0
|
||
|
|
1 &intc 0 238 0
|
||
|
|
2 &tlmm_pinmux 13 0>;
|
||
|
|
|
||
|
|
qcom,inject-rx-on-wakeup;
|
||
|
|
qcom,rx-char-to-inject = <0xFD>;
|
||
|
|
|
||
|
|
qcom,bam-tx-ep-pipe-index = <6>;
|
||
|
|
qcom,bam-rx-ep-pipe-index = <7>;
|
||
|
|
qcom,master-id = <86>;
|
||
|
|
clock-names = "core_clk", "iface_clk";
|
||
|
|
clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>,
|
||
|
|
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
|
||
|
|
pinctrl-names = "sleep", "default";
|
||
|
|
pinctrl-0 = <&blsp1_uart4_sleep>;
|
||
|
|
pinctrl-1 = <&blsp1_uart4_active>;
|
||
|
|
|
||
|
|
qcom,msm-bus,name = "buart4";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<86 512 0 0>,
|
||
|
|
<86 512 500 800>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|