67 lines
1.9 KiB
Plaintext
67 lines
1.9 KiB
Plaintext
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Renesas AHB to PCI bridge
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-------------------------
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This is the bridge used internally to connect the USB controllers to the
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AHB. There is one bridge instance per USB port connected to the internal
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OHCI and EHCI controllers.
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Required properties:
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- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
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"renesas,pci-r8a7791" for the R8A7791 SoC.
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- reg: A list of physical regions to access the device: the first is
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the operational registers for the OHCI/EHCI controllers and the
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second is for the bridge configuration and control registers.
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- interrupts: interrupt for the device.
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- clocks: The reference to the device clock.
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- bus-range: The PCI bus number range; as this is a single bus, the range
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should be specified as the same value twice.
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- #address-cells: must be 3.
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- #size-cells: must be 2.
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- #interrupt-cells: must be 1.
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- interrupt-map: standard property used to define the mapping of the PCI
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interrupts to the GIC interrupts.
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- interrupt-map-mask: standard property that helps to define the interrupt
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mapping.
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Example SoC configuration:
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pci0: pci@ee090000 {
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compatible = "renesas,pci-r8a7790";
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clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
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reg = <0x0 0xee090000 0x0 0xc00>,
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<0x0 0xee080000 0x0 0x1100>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xff00 0 0 0x7>;
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interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
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0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
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0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
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pci@0,1 {
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reg = <0x800 0 0 0 0>;
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device_type = "pci";
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phys = <&usbphy 0 0>;
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phy-names = "usb";
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};
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pci@0,2 {
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reg = <0x1000 0 0 0 0>;
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device_type = "pci";
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phys = <&usbphy 0 0>;
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phy-names = "usb";
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};
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};
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Example board setup:
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&pci0 {
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status = "okay";
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pinctrl-0 = <&usb0_pins>;
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pinctrl-names = "default";
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};
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