114 lines
4.1 KiB
Plaintext
114 lines
4.1 KiB
Plaintext
|
MSM PCI express endpoint
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible: should be "qcom,pcie-ep".
|
||
|
|
- reg: should contain PCIe register maps.
|
||
|
|
- reg-names: indicates various resources passed to driver by name.
|
||
|
|
Should be "msi", "dm_core", "elbi", "parf", "phy", "mmio".
|
||
|
|
These correspond to different modules within the PCIe domain.
|
||
|
|
- #address-cells: Should provide a value of 0.
|
||
|
|
- interrupt-parent: Should be the PCIe device node itself here.
|
||
|
|
- interrupts: Should be in the format <0 1 2> and it is an index to the
|
||
|
|
interrupt-map that contains PCIe related interrupts.
|
||
|
|
- #interrupt-cells: Should provide a value of 1.
|
||
|
|
- #interrupt-map-mask: should provide a value of 0xffffffff.
|
||
|
|
- interrupt-map: Must create mapping for the number of interrupts
|
||
|
|
that are defined in above interrupts property.
|
||
|
|
For PCIe device node, it should define 6 mappings for
|
||
|
|
the corresponding PCIe interrupts supporting the
|
||
|
|
specification.
|
||
|
|
- interrupt-names: indicates interrupts passed to driver by name.
|
||
|
|
Should be "int_pm_turnoff", "int_dstate_change",
|
||
|
|
"int_l1sub_timeout", "int_link_up",
|
||
|
|
"int_link_down", "int_bridge_flush_n".
|
||
|
|
- perst-gpio: PERST GPIO specified by PCIe spec.
|
||
|
|
- wake-gpio: WAKE GPIO specified by PCIe spec.
|
||
|
|
- clkreq-gpio: CLKREQ GPIO specified by PCIe spec.
|
||
|
|
- <supply-name>-supply: phandle to the regulator device tree node.
|
||
|
|
Refer to the schematics for the corresponding voltage regulators.
|
||
|
|
vreg-1.8-supply: phandle to the analog supply for the PCIe controller.
|
||
|
|
vreg-0.9-supply: phandle to the analog supply for the PCIe controller.
|
||
|
|
|
||
|
|
Optional Properties:
|
||
|
|
- qcom,<supply-name>-voltage-level: specifies voltage levels for supply.
|
||
|
|
Should be specified in pairs (max, min, optimal), units uV.
|
||
|
|
- clock-names: list of names of clock inputs.
|
||
|
|
Should be "pcie_0_pipe_clk",
|
||
|
|
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
|
||
|
|
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
|
||
|
|
"pcie_0_ldo";
|
||
|
|
- max-clock-frequency-hz: list of the maximum operating frequencies stored
|
||
|
|
in the same order of clock names;
|
||
|
|
- qcom,pcie-phy-ver: version of PCIe PHY.
|
||
|
|
- qcom,pcie-link-speed: generation of PCIe link speed. The value could be
|
||
|
|
1, 2 or 3.
|
||
|
|
- qcom,pcie-active-config: boolean type; active configuration of PCIe
|
||
|
|
addressing.
|
||
|
|
- qcom,pcie-aggregated-irq: boolean type; interrupts are aggregated.
|
||
|
|
- mdm2apstatus-gpio: GPIO used by PCIe endpoint side to notify the host side.
|
||
|
|
- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
|
||
|
|
below optional properties:
|
||
|
|
- qcom,msm-bus,name
|
||
|
|
- qcom,msm-bus,num-cases
|
||
|
|
- qcom,msm-bus,num-paths
|
||
|
|
- qcom,msm-bus,vectors-KBps
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
pcie_ep: qcom,pcie@bfffd000 {
|
||
|
|
compatible = "qcom,pcie-ep";
|
||
|
|
|
||
|
|
reg = <0xbfffd000 0x1000>,
|
||
|
|
<0xbfffe000 0x1000>,
|
||
|
|
<0xbffff000 0x1000>,
|
||
|
|
<0xfc520000 0x2000>,
|
||
|
|
<0xfc526000 0x1000>,
|
||
|
|
<0xfc527000 0x1000>;
|
||
|
|
reg-names = "msi", "dm_core", "elbi", "parf", "phy", "mmio";
|
||
|
|
|
||
|
|
#address-cells = <0>;
|
||
|
|
interrupt-parent = <&pcie_ep>;
|
||
|
|
interrupts = <0 1 2 3 4 5>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-map-mask = <0xffffffff>;
|
||
|
|
interrupt-map = <0 &intc 0 44 0
|
||
|
|
1 &intc 0 46 0
|
||
|
|
2 &intc 0 47 0
|
||
|
|
3 &intc 0 50 0
|
||
|
|
4 &intc 0 51 0
|
||
|
|
5 &intc 0 52 0>;
|
||
|
|
interrupt-names = "int_pm_turnoff", "int_dstate_change",
|
||
|
|
"int_l1sub_timeout", "int_link_up",
|
||
|
|
"int_link_down", "int_bridge_flush_n";
|
||
|
|
|
||
|
|
perst-gpio = <&msmgpio 65 0>;
|
||
|
|
wake-gpio = <&msmgpio 61 0>;
|
||
|
|
clkreq-gpio = <&msmgpio 64 0>;
|
||
|
|
mdm2apstatus-gpio = <&tlmm_pinmux 16 0>;
|
||
|
|
|
||
|
|
gdsc-vdd-supply = <&gdsc_pcie_0>;
|
||
|
|
vreg-1.8-supply = <&pmd9635_l8>;
|
||
|
|
vreg-0.9-supply = <&pmd9635_l4>;
|
||
|
|
|
||
|
|
qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
|
||
|
|
qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
|
||
|
|
|
||
|
|
clock-names = "pcie_0_pipe_clk",
|
||
|
|
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
|
||
|
|
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
|
||
|
|
"pcie_0_ldo";
|
||
|
|
max-clock-frequency-hz = <62500000>, <1000000>,
|
||
|
|
<0>, <0>, <0>, <0>;
|
||
|
|
|
||
|
|
qcom,msm-bus,name = "pcie-ep";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<45 512 0 0>,
|
||
|
|
<45 512 500 800>;
|
||
|
|
|
||
|
|
qcom,pcie-link-speed = <1>;
|
||
|
|
qcom,pcie-active-config;
|
||
|
|
qcom,pcie-aggregated-irq;
|
||
|
|
};
|