29 lines
1.1 KiB
Plaintext
29 lines
1.1 KiB
Plaintext
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* Synopsys Designware PCIe interface
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Required properties:
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- compatible: should contain "snps,dw-pcie" to identify the core.
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- reg: Should contain the configuration address space.
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- reg-names: Must be "config" for the PCIe configuration space.
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(The old way of getting the configuration address space from "ranges"
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is deprecated and should be avoided.)
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt
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numbers.
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- num-lanes: number of lanes to use
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "pcie"
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- "pcie_bus"
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Optional properties:
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- reset-gpio: gpio pin number of power good signal
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- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
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specify this property, to keep backwards compatibility a range of 0x00-0xff
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is assumed if not present)
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