143 lines
6.5 KiB
Plaintext
143 lines
6.5 KiB
Plaintext
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Qualcomm MSM Ethernet Controller (EMAC)
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Required properties:
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- cell-index : EMAC controller instance number.
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- compatible : Should be "qcom,mdm9607-emac" for mdm9607 based EMAC driver
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Should be "qcom,emac" for other targets based EMAC driver
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- reg : Offset and length of the register regions for the device
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- reg-names : Register region names referenced in 'reg' above.
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Required register resource entries are:
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"emac" : EMAC controller register block.
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"emac_csr" : EMAC wrapper register block.
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Optional register resource entries are:
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"emac_1588" : EMAC 1588 (PTP) register block.
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Required if 'qcom,emac-tstamp-en' is present.
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"emac_sgmii" : EMAC SGMII PHY register block.
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Required if 'phy-mode' is "sgmii".
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- interrupts : Interrupt numbers used by this controller
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- interrupt-names : Interrupt resource names referenced in 'interrupts' above.
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Required interrupt resource entries are:
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"emac_core0_irq" : EMAC core0 interrupt.
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"emac_core1_irq" : EMAC core1 interrupt.
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"emac_core2_irq" : EMAC core2 interrupt.
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"emac_core3_irq" : EMAC core3 interrupt.
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Optional interrupt resource entries are:
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"emac_sgmii_irq" : EMAC SGMII interrupt.
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Required if 'phy-mode' is "sgmii".
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"emac_wol_irq" : EMAC Wake-On-LAN (WOL) interrupt.
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Required if WOL is supported.
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- qcom,emac-gpio-mdc : GPIO pin number of the MDC line of MDIO bus.
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- qcom,emac-gpio-mdio : GPIO pin number of the MDIO line of MDIO bus.
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- phy-mode: String, operation mode of the PHY interface. See ethernet.txt in the
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same directory.
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- phy-addr : Specifies phy address on MDIO bus.
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Required if the optional property "qcom,no-external-phy"
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is not specified.
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- phy-channel : Phy address for internal phy in ACPI mode.
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- phy-mode : Specifies PHY type being used (eg., "sgmii", "rgmii", "gmii" etc).
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For "sgmii", the "emac_sgmii" register base and
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"emac_sgmii_irq" interrupt must be specified.
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Optional properties:
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- qcom,emac-tstamp-en : Enables the PTP (1588) timestamping feature.
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Include this only if PTP (1588) timestamping
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feature is needed. If included, "emac_1588" register
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base should be specified.
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- local-mac-address : The 6-byte MAC address.
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This field is optional. If present, it is only a
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placeholder for the MAC address. The correct MAC
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address is populated in device tree during platform
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initialization.
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- mac-address : 6- bytes MAC address in ACPI mode.
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This field is optional. If present, it is only a placeholder
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for the MAC address. The correct MAC address is populated in
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device tree during platform initialization.
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- qcom,no-external-phy : Indicates there is no external PHY connected to EMAC.
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Include this only if the EMAC is directly connected to
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the peer end without EPHY.
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- qcom,emac-ptp-grandmaster : Enable the PTP (1588) grandmaster mode.
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Include this only if PTP (1588) is configured as
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grandmaster.
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- qcom,emac-ptp-frac-ns-adj : The vector table to adjust the fractional ns per
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RTC clock cycle.
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Include this only if there is accuracy loss of
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fractional ns per RTC clock cycle. For individual
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table entry, the first field indicates the RTC
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reference clock rate. The second field indicates
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the number of adjustment in 2 ^ -26 ns.
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- no-ephy : Specifies in case there is no external phy present in ACPI mode.
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- tstamp-eble : Enables the PTP (1588) timestamping feature in ACPI mode.
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- <supply-name>-supply: phandle to the regulator device tree node
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Required "supply-name" are "emac_vreg*"
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- qcom,vdd-voltage-level: This property must be a list of five integer
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values (max voltage value for supply 1/2/3/4/5) where each value
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represents a voltage in microvolts.
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Example1:
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emac0: qcom,emac@feb20000 {
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cell-index = <0>;
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compatible = "qcom,emac";
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reg-names = "emac", "emac_csr", "emac_1588", "emac_sgmii";
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reg = <0xfeb20000 0x10000>,
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<0xfeb36000 0x1000>,
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<0xfeb3c000 0x4000>,
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<0xfeb13800 0x400>;
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interrupts = <0 76 0>, <0 77 0>, <0 78 0>, <0 79 0>;
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interrupt-names = "emac_core0_irq", "emac_core1_irq",
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"emac_core2_irq", "emac_core3_irq";
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qcom,emac-gpio-mdc = <&msmgpio 123 0>;
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qcom,emac-gpio-mdio = <&msmgpio 124 0>;
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qcom,emac-tstamp-en;
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phy-mode = "sgmii";
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phy-addr = <0>;
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};
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Example2:
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emac0: qcom,emac@7c40000 {
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cell-index = <0>;
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compatible = "qcom,mdm9607-emac";
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reg-names = "emac", "emac_csr", "emac_1588", "emac_sgmii";
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reg = <0x7c40000 0x10000>,
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<0x7c56000 0x1000>,
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<0x7c5C000 0x4000>,
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<0x7c58000 0x400>;
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#address-cells = <0>;
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interrupt-parent = <&emac0>;
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#interrupt-cells = <1>;
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interrupts = <0 1 2>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 76 0
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1 &intc 0 80 0
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2 &tlmm_pinmux 30 0x8>;
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interrupt-names = "emac_core0_irq",
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"emac_sgmii_irq",
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"emac_wol_irq";
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emac_vreg1-supply = <&mdm9607_l1>;
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emac_vreg2-supply = <&mdm9607_l3>;
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emac_vreg3-supply = <&mdm9607_l5>;
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emac_vreg4-supply = <&mdm9607_l11>;
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emac_vreg5-supply = <&emac_lan_vreg>;
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qcom,vdd-voltage-level = <1250000 1800000 2850000 1800000 0>;
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clocks = <&clock_gcc clk_gcc_emac_0_axi_clk>,
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<&clock_gcc clk_gcc_emac_0_ahb_clk>,
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<&clock_gcc clk_gcc_emac_0_125m_clk>,
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<&clock_gcc clk_gcc_emac_0_sys_25m_clk>,
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<&clock_gcc clk_gcc_emac_0_tx_clk>,
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<&clock_gcc clk_gcc_emac_0_rx_clk>,
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<&clock_gcc clk_gcc_emac_0_sys_clk>;
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clock-names = "axi_clk", "cfg_ahb_clk", "125m_clk",
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"25m_clk", "tx_clk", "rx_clk", "sys_clk";
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pinctrl-names = "emac_mdio_active", "emac_mdio_sleep",
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"emac_ephy_active", "emac_ephy_sleep";
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pinctrl-0 = <&emac0_mdio_active>;
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pinctrl-1 = <&emac0_mdio_sleep>;
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pinctrl-2 = <&emac0_ephy_active>;
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pinctrl-3 = <&emac0_ephy_sleep>;
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qcom,emac-tstamp-en;
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qcom,emac-ptp-frac-ns-adj = <125000000 1>;
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phy-mode = "sgmii";
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phy-addr = <0>;
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status = "disable";
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};
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