63 lines
2.5 KiB
Plaintext
63 lines
2.5 KiB
Plaintext
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* Qualcomm Technologies Inc. MSM JPEG DMA
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Jpeg dma hardware block.
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Jpeg dma can replicate and downscale yuv frames.
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Supported formats: Monochrome, NV12 and NV21.
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Required properties:
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- compatible : "qcom,jpegdma".
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- reg : offset and length of the register set of jpeg dma device and
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vbif device for the jpeg dma operating in compatible mode.
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- reg-names : should specify relevant names to each reg property defined.
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- interrupts : should contain the jpeg interrupt.
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- interrupt-names : should specify relevant names to each interrupts
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property defined.
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- mmagic-vdd-supply: phandle to GDSC regulator controlling mmagic.
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- camss-vdd-supply: phandle to GDSC regulator controlling camss.
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- clock-names : names of clocks required for the device.
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- clocks : clocks required for the device.
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- qcom,clock-rates: should specify clock rates in Hz to each clocks
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property defined.
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Optional properties:
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- qcom,qos-regs: relative address offsets of QoS registers.
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- qcom,qos-settings: QoS values to be written to QoS registers.
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- qcom,vbif-regs: relative address offsets of VBIF registers.
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- qcom,vbif-settings: VBIF values to be written to VBIF registers.
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- qcom,prefetch-regs: relative address offsets of MMU prefetch registers.
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- qcom,prefetch-settings: values to be written to MMU Prefetch registers.
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Example:
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qcom,jpegdma@aa0000 {
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compatible = "qcom,jpegdma";
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reg = <0xaa0000 0x4000>,
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<0xa60000 0x3000>;
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reg-names = "jpegdma_core", "jpeg_vbif";
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interrupts = <0 304 0>;
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interrupt-names = "jpeg";
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mmagic-vdd-supply = <&gdsc_mmagic_camss>;
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camss-vdd-supply = <&gdsc_camss_top>;
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vdd-supply = <&gdsc_jpeg>;
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qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
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clock-names = "core_clk", "iface_clk", "bus_clk0",
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"camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",
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"mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",
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"mmagic_camss_axi_clk";
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clocks = <&clock_mmss clk_camss_jpeg_dma_clk>,
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<&clock_mmss clk_camss_jpeg_ahb_clk>,
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<&clock_mmss clk_camss_jpeg_axi_clk>,
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<&clock_mmss clk_camss_top_ahb_clk>,
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<&clock_mmss clk_camss_ahb_clk>,
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<&clock_mmss clk_smmu_jpeg_axi_clk>,
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<&clock_mmss clk_mmss_mmagic_ahb_clk>,
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<&clock_gcc clk_mmssnoc_axi_clk>,
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<&clock_mmss clk_mmagic_camss_axi_clk>;
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qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>,
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<400000000 0 0 0 0 0 0 0 0>;
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qcom,vbif-regs = <0x4 0xDC 0x124 0x160>;
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qcom,vbif-settings = <0x1 0x7 0x1 0x22222222>;
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qcom,prefetch-regs = <0x18C 0x1A0 0x1B0>;
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qcom,prefetch-settings = <0x11 0x31 0x31>;
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status = "ok";
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};
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