166 lines
7.6 KiB
Plaintext
166 lines
7.6 KiB
Plaintext
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* ARM System MMU Architecture Implementation
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ARM SoCs may contain an implementation of the ARM System Memory
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Management Unit Architecture, which can be used to provide 1 or 2 stages
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of address translation to bus masters external to the CPU.
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The SMMU may also raise interrupts in response to various fault
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conditions.
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** System MMU required properties:
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- compatible : Should be one of:
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"arm,smmu-v1"
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"arm,smmu-v2"
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"arm,mmu-400"
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"arm,mmu-401"
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"arm,mmu-500"
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"qcom,smmu-v2"
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depending on the particular implementation and/or the
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version of the architecture implemented.
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- reg : Base address and size of the SMMU.
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- #global-interrupts : The number of global interrupts exposed by the
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device.
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- interrupts : Interrupt list, with the first #global-irqs entries
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corresponding to the global interrupts and any
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following entries corresponding to context interrupts,
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specified in order of their indexing by the SMMU.
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For SMMUv2 implementations, there must be exactly one
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interrupt per context bank. In the case of a single,
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combined interrupt, it must be listed multiple times.
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- mmu-masters : A list of phandles to device nodes representing bus
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masters for which the SMMU can provide a translation
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and their corresponding StreamIDs (see example below).
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Each device node linked from this list must have a
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"#stream-id-cells" property, indicating the number of
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StreamIDs associated with it.
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** System MMU optional properties:
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- calxeda,smmu-secure-config-access : Enable proper handling of buggy
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implementations that always use secure access to
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SMMU configuration registers. In this case non-secure
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aliases of secure registers have to be used during
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SMMU configuration.
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- qcom,smmu-invalidate-on-map : Enable proper handling of buggy
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implementations that require a TLB invalidate
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operation to occur at map time.
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- qcom,halt-and-tlb-on-atos : Enable proper handling of buffy
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implementations that require a halt and TLB invalidate
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before performing ATOS operations.
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- qcom,register-save : Enable register saving awareness. This causes the
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driver to assume that configuration registers will retain
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their values across gdsc power gating.
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- qcom,skip-init : Disable resetting configuration for all context banks
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during device reset. This is useful for targets where
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some context banks are dedicated to other execution
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environments outside of Linux and those other EEs are
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programming their own stream match tables, SCTLR, etc.
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Without setting this option we will trample on their
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configuration.
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- qcom,errata-ctx-fault-hang : Enable workaround for a context fault hang
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hardware errata.
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- qcom,fatal-asf : Enable BUG_ON for address size faults. Some hardware
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requires special fixups to recover from address size
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faults. Rather than applying the fixups just BUG since
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address size faults are due to a fundamental programming
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error from which we don't care about recovering anyways.
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- qcom,tz-device-id : A string indicating the device ID for this SMMU known
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to TZ. See msm_tz_smmu.c for a full list of mappings.
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- qcom,errata-tz-atos : Enable workaround for an ATOS hardware errata on
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Thulium v1. You *must* also set qcom,tz-device-id for
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this to work.
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- qcom,no-mmu-enable : When attaching to this SMMU, program everything as
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usual (stream matching table, etc) but leave the SCTLR.M
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bit disabled, so that the SMMU doesn't actually perform
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translations. This is needed in cases where the stream
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matching table needs to be set up without turning on SMMU
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translations (for example, when nested translations are
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used with a hypervisor controlling stage-2). This mode of
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operation is described in the ARM SMMU spec as "stage 1
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and stage 2 contexts are valid, but the SMMU is not
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enabled for stage 1 translation" (Section 2.1: "Overview
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of SMMU operation").
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- qcom,no-smr-check : Usually when an SMMU probes we do a sanity check on
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the SMR registers to make sure they can fully support all
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of the mask bits. This check can cause problems for use
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cases where the SMMU is already in use when the SMMU
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probes. For example, for continuous splash screen
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support, the stream matching table is programmed before
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control is even turned over to Linux.
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- qcom,dynamic : Allow dynamic domains to be attached. This is only
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useful if the upstream hardware is capable of switching
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between multiple domains within a single context bank.
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- qcom,enable-smmu-halt : Before SMMU is powered down, SMMU needs to be in
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idle state prior to power collapse. When 'halt' is received by
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SMMU, it ensures that no new requests enters and all
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outstanding requests are completed and generates an
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acknowledgment for halt request. So add an option to register
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a call back notifier on regulators in whcih SMMU can be halted
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or resumed when regulator is powered down/up.
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- clocks : List of clocks to be used during SMMU register access. See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for information about the format. For each clock specified
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here, there must be a corresponding entery in clock-names
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(see below).
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- clock-names : List of clock names corresponding to the clocks specified in
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the "clocks" property (above). See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for more info.
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- vdd-supply : Phandle of the regulator that should be powered on during
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SMMU register access.
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- attach-impl-defs : global registers to program at device attach
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time. This should be a list of 2-tuples of the format:
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<offset reg_value>.
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- qcom,bus-master-id : The master ID of the bus, if a bus vote is needed.
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See include/dt-bindings/msm/msm-bus-ids.h.
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Example:
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smmu {
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compatible = "arm,smmu-v1";
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reg = <0xba5e0000 0x10000>;
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#global-interrupts = <2>;
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interrupts = <0 32 4>,
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<0 33 4>,
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<0 34 4>, /* This is the first context interrupt */
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<0 35 4>,
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<0 36 4>,
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<0 37 4>;
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/*
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* Two DMA controllers, the first with two StreamIDs (0xd01d
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* and 0xd01e) and the second with only one (0xd11c).
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*/
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mmu-masters = <&dma0 0xd01d 0xd01e>,
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<&dma1 0xd11c>;
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attach-impl-defs = <0x124 0x3>,
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<0x128 0xa5>,
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<0x12c 0x1>;
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};
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