87 lines
2.9 KiB
Plaintext
87 lines
2.9 KiB
Plaintext
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GPIO-based I2C Arbitration Using a Challenge & Response Mechanism
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=================================================================
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This uses GPIO lines and a challenge & response mechanism to arbitrate who is
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the master of an I2C bus in a multimaster situation.
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In many cases using GPIOs to arbitrate is not needed and a design can use
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the standard I2C multi-master rules. Using GPIOs is generally useful in
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the case where there is a device on the bus that has errata and/or bugs
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that makes standard multimaster mode not feasible.
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Note that this scheme works well enough but has some downsides:
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* It is nonstandard (not using standard I2C multimaster)
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* Having two masters on a bus in general makes it relatively hard to debug
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problems (hard to tell if i2c issues were caused by one master, another, or
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some device on the bus).
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Algorithm:
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All masters on the bus have a 'bus claim' line which is an output that the
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others can see. These are all active low with pull-ups enabled. We'll
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describe these lines as:
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- OUR_CLAIM: output from us signaling to other hosts that we want the bus
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- THEIR_CLAIMS: output from others signaling that they want the bus
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The basic algorithm is to assert your line when you want the bus, then make
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sure that the other side doesn't want it also. A detailed explanation is best
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done with an example.
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Let's say we want to claim the bus. We:
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1. Assert OUR_CLAIM.
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2. Waits a little bit for the other sides to notice (slew time, say 10
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microseconds).
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3. Check THEIR_CLAIMS. If none are asserted then the we have the bus and we are
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done.
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4. Otherwise, wait for a few milliseconds and see if THEIR_CLAIMS are released.
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5. If not, back off, release the claim and wait for a few more milliseconds.
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6. Go back to 1 (until retry time has expired).
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Required properties:
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- compatible: i2c-arb-gpio-challenge
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- our-claim-gpio: The GPIO that we use to claim the bus.
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- their-claim-gpios: The GPIOs that the other sides use to claim the bus.
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Note that some implementations may only support a single other master.
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- Standard I2C mux properties. See mux.txt in this directory.
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- Single I2C child bus node at reg 0. See mux.txt in this directory.
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Optional properties:
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- slew-delay-us: microseconds to wait for a GPIO to go high. Default is 10 us.
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- wait-retry-us: we'll attempt another claim after this many microseconds.
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Default is 3000 us.
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- wait-free-us: we'll give up after this many microseconds. Default is 50000 us.
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Example:
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i2c@12CA0000 {
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compatible = "acme,some-i2c-device";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c-arbitrator {
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compatible = "i2c-arb-gpio-challenge";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&{/i2c@12CA0000}>;
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our-claim-gpio = <&gpf0 3 1>;
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their-claim-gpios = <&gpe0 4 1>;
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slew-delay-us = <10>;
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wait-retry-us = <3000>;
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wait-free-us = <50000>;
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i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@52 {
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// Normal I2C device
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};
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};
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};
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