50 lines
1.5 KiB
Plaintext
50 lines
1.5 KiB
Plaintext
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* General Purpose Input Output (GPIO) bus.
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Properties:
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- compatible: "cavium,octeon-3860-gpio"
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Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
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- reg: The base address of the GPIO unit's register bank.
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- gpio-controller: This is a GPIO controller.
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- #gpio-cells: Must be <2>. The first cell is the GPIO pin.
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- interrupt-controller: The GPIO controller is also an interrupt
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controller, many of its pins may be configured as an interrupt
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source.
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- #interrupt-cells: Must be <2>. The first cell is the GPIO pin
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connected to the interrupt source. The second cell is the interrupt
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triggering protocol and may have one of four values:
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1 - edge triggered on the rising edge.
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2 - edge triggered on the falling edge
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4 - level triggered active high.
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8 - level triggered active low.
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- interrupts: Interrupt routing for each pin.
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Example:
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gpio-controller@1070000000800 {
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#gpio-cells = <2>;
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compatible = "cavium,octeon-3860-gpio";
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reg = <0x10700 0x00000800 0x0 0x100>;
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gpio-controller;
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/* Interrupts are specified by two parts:
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* 1) GPIO pin number (0..15)
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* 2) Triggering (1 - edge rising
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* 2 - edge falling
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* 4 - level active high
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* 8 - level active low)
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*/
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interrupt-controller;
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#interrupt-cells = <2>;
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/* The GPIO pin connect to 16 consecutive CUI bits */
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interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
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<0 20>, <0 21>, <0 22>, <0 23>,
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<0 24>, <0 25>, <0 26>, <0 27>,
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<0 28>, <0 29>, <0 30>, <0 31>;
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};
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