34 lines
1.0 KiB
Plaintext
34 lines
1.0 KiB
Plaintext
|
* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
|
||
|
|
|
||
|
|
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
|
||
|
|
and several fixed ratio dividers.
|
||
|
|
|
||
|
|
Required Properties:
|
||
|
|
|
||
|
|
- compatible: Must be one of
|
||
|
|
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
|
||
|
|
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
|
||
|
|
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
|
||
|
|
- "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
|
||
|
|
|
||
|
|
- reg: Base address and length of the memory resource used by the CPG
|
||
|
|
|
||
|
|
- clocks: Reference to the parent clock
|
||
|
|
- #clock-cells: Must be 1
|
||
|
|
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
||
|
|
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
|
||
|
|
|
||
|
|
|
||
|
|
Example
|
||
|
|
-------
|
||
|
|
|
||
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
||
|
|
compatible = "renesas,r8a7790-cpg-clocks",
|
||
|
|
"renesas,rcar-gen2-cpg-clocks";
|
||
|
|
reg = <0 0xe6150000 0 0x1000>;
|
||
|
|
clocks = <&extal_clk>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-output-names = "main", "pll0, "pll1", "pll3",
|
||
|
|
"lb", "qspi", "sdh", "sd0", "sd1", "z";
|
||
|
|
};
|